HCPL-4506#560E [AGILENT]
IC Output Optocoupler, 1-Element;
| 型号： | HCPL-4506#560E |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | IC Output Optocoupler, 1-Element |
| 文件： | 总21页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intelligent Power Module
and Gate Drive Interface
Optocouplers
HCPL-4506
HCPL-J456
HCPL-0466
HCNW4506
Technical Data
Features
CSA Approved
IEC/EN/DIN EN 60747-5-2
Approved
-VIORM = 560 Vpeak for
HCPL-0466 Option 060
-VIORM = 630 Vpeak for
HCPL-4506 Option 060
-VIORM = 891 Vpeak for
HCPL-J456
Applications
• IPM Isolation
• Isolated IGBT/MOSFET Gate
Drive
• AC and Brushless DC Motor
Drives
• Performance Specified for
Common IPM Applications
over Industrial Temperature
Range: -40°C to 100°C
• Fast Maximum Propagation
Delays
tPHL = 480 ns
tPLH = 550 ns
• Minimized Pulse Width
Distortion
• Industrial Inverters
-VIORM = 1414 Vpeak for
HCNW4506
PWD = 450 ns
• 15 kV/µs Minimum Common
Mode Transient Immunity
at VCM = 1500 V
• CTR > 44% at IF = 10 mA
• Safety Approval
UL Recognized
Functional Diagram
Truth Table
-3750 V rms / 1 min. for
HCPL-4506/0466/J456
-5000 V rms / 1 min. for
HCPL-4506 Option 020
and HCNW4506
LED
ON
VO
L
OFF
H
NC
1
2
8
7
V
V
CC
L
20 kΩ
ANODE
3
4
6
5
CATHODE
NC
V
O
GND
SHIELD
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
2
Description
shorting output pins 6 and 7, thus
eliminating the need for an
external pull-up resistor in
common IPM applications.
Specifications and performance
plots are given for typical IPM
applications.
difference between devices makes
these optocouplers excellent
solutions for improving inverter
efficiency through reduced
switching dead time.
The HCPL-4506 and HCPL-0466
contain a GaAsP LED while the
HCPL-J456 and the HCNW4506
contain an AlGaAs LED. The LED
is optically coupled to an inte-
grated high gain photo detector.
Minimized propagation delay
An on chip 20 kΩ output pull-up
resistor can be enabled by
Selection Guide
Standard
White Mold
Package
Type
8-Pin DIP
(300 Mil)
8-Pin DIP
(300 Mil)
Small Outline
SO8
Widebody
(400 Mil)
Hermetic*
Part
Number
HCPL-4506
HCPL-J456
HCPL-0466
HCNW4506
HCPL-5300
HCPL-5301
IEC/EN/DIN VIORM = 630 Vpeak VIORM = 891 Vpeak VIORM = 560 Vpeak VIORM = 1414 Vpeak
—
EN 60747-
5-2
(Option 060)
(Option 060)
Approval
*Technical data for these products are on separate Agilent publications.
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-4506#XXXX
020 = UL 5000 V rms/1 minute Option** for HCPL-4506 Only.
060 = IEC/EN/DIN EN 60747-5-2 Option** for HCPL-4506/0466.
300 = Gull Wing Lead Option for HCPL-4506/J456, HCNW4506.
500 = Tape and Reel Packaging Option
XXXE = Lead Free Option
Option data sheets are available. Contact Agilent sales representative or authorized distributor
for information.
**Combination of Option 020 and Option 060 is not available.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July
2001 and lead free option will use “-”
3
Package Outline Drawings
HCPL-4506 Outline Drawing
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
1
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
3.56 ± 0.13
(0.140 ± 0.005)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
* MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
2.54 ± 0.25
(0.100 ± 0.010)
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
HCPL-4506 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
1.016 (0.040)
9.65 ± 0.25
(0.380 ± 0.010)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2.0 (0.080)
2
3
4
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
3.56 ± 0.13
(0.140 ± 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
4
Package Outline Drawings
HCPL-J456 Outline Drawing
7.62 ± 0.25
(0.300 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010)
8
1
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
3.56 ± 0.13
(0.140 ± 0.005)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
* MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
2.54 ± 0.25
(0.100 ± 0.010)
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
HCPL-J456 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
9.80 ± 0.25
1.016 (0.040)
(0.386 ± 0.010)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2.0 (0.080)
2
3
4
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
3.56 ± 0.13
(0.140 ± 0.005)
+ 0.003)
- 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
5
HCPL-0466 Outline Drawing (8-Pin Small Outline Package)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
3
PIN ONE
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
0.432
(0.017)
*
7°
5.080 ± 0.127
(0.200 ± 0.005)
45° X
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
HCNW4506 Outline Drawing (8-Pin Widebody Package)
11.00
MAX.
11.15 ± 0.15
(0.442 ± 0.006)
(0.433)
9.00 ± 0.15
(0.354 ± 0.006)
7
6
5
8
TYPE NUMBER
DATE CODE
A
HCNWXXXX
YYWW
1
3
2
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
- 0.0051
0.254
+ 0.003)
- 0.002)
(0.010
5.10
(0.201)
MAX.
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
6
HCNW4506 Gull Wing Surface Mount Option 300 Outline Drawing
11.15 ± 0.15
(0.442 ± 0.006)
LAND PATTERN RECOMMENDATION
7
6
5
8
9.00 ± 0.15
(0.354 ± 0.006)
13.56
(0.534)
1
3
2
4
2.29
1.3
(0.09)
(0.051)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00
MAX.
(0.433)
4.00
MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
1.00 ± 0.15
(0.039 ± 0.006)
0.75 ± 0.25
(0.030 ± 0.010)
+ 0.076
- 0.0051
2.54
(0.100)
BSC
0.254
+ 0.003)
- 0.002)
(0.010
DIMENSIONS IN MILLIMETERS (INCHES).
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
7
Solder Reflow Temperature Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5°C ± 0.5°C/SEC.
SOLDERING
TIME
200°C
30
160°C
150°C
140°C
SEC.
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
200
250
TIME (SECONDS)
Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
t
p
15 SEC.
260 +0/-5 °C
T
T
p
217 °C
L
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
150 - 200 °C
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, T = 150 °C
T
smax
smin
8
Regulatory Information
The devices contained in this data sheet have been approved by the following agencies:
Agency/Standard
HCPL-4506 HCPL-J456 HCPL-0466 HCNW4506
Underwriters Laboratories (UL)
UL 1577
Recognized under UL 1577, Component
Recognized Program, Category FPQU2,
File E55361
✔
✔
✔
✔
✔
Canadian Standards
Association (CSA)
File CA88324
Verband Deutscher
Electrotechniker (VDE)
Component
Acceptance
Notice #5
DIN VDE 0884
(June 1992)
✔
✔
✔
✔
✔
✔
✔
✔
✔
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
✔
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
Insulation and Safety Related Specifications
Value
Parameter
Symbol HCPL-4506 HCPL-J456 HCPL-0466 HCNW4506 Units
Conditions
Minimum External L(101)
Air Gap (External
Clearance)
7.1
7.4
8.0
0.5
4.9
9.6
10.0
1.0
mm Measured from input
terminals to output
terminals, shortest
distance through air.
Minimum External L(102)
Tracking (External
Creepage)
7.4
4.8
mm Measured from input
terminals to output
terminals, shortest
distance path along body.
Minimum Internal
Plastic Gap
(Internal Clearance)
0.08
0.08
mm Through insulation
distance, conductor to
conductor, usually the
direct distance between
the photoemitter and
photodetector inside the
optocoupler cavity.
Minimum Internal
Tracking (Internal
Creepage)
NA
NA
NA
4.0
mm Measured from input
terminals to output
terminals, along internal
cavity.
Tracking Resistance CTI
(Comparative
Tracing Index)
≥ 175
≥ 175
≥ 175
≥ 200
Volts DIN IEC 112/VDE 0303
Part 1
Isolation Group
IIIa
IIIa
IIIa
IIIa
Material Group (DIN
VDE 0110, 1/89, Table 1)
All Agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equipment designer when determining the circuit insulation require-
ments. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be
met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a
printed circuit board between the solder fillets of the input and output leads must be considered. There are recom-
mended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage
and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and
insulation level.
9
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
HCPL-0466 HCPL-4506
Symbol Option 060 Option 060 HCPL-J456 HCNW4506 Unit
Description
Installation classification per
DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 V rms
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
for rated mains voltage ≤ 600 V rms
for rated mains voltage ≤ 1000 V rms
I-IV
I-III
I-IV
I-IV
I-III
I-IV
I-IV
I-III
I-III
I-IV
I-IV
I-IV
I-IV
I-III
Climatic Classification
Pollution Degree
55/100/21
2
55/100/21
2
55/100/21
2
55/100/21
2
(DIN VDE 0110/1.89)
Maximum Working
Insulation Voltage
VIORM
560
630
891
1414
Vpeak
Input to Output Test Voltage,
Method b* VIORM x 1.875 = VPR,
100% Production Test with tm =
1 sec, Partial Discharge < 5pC
VPR
1050
1181
1670
2652
Vpeak
Input to Output Test Voltage,
Method a* VIORM x 1.5 = VPR,
Type and Sample Test, tm = 60 sec,
Partial Discharge < 5pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
VPR
840
945
1336
6000
2121
8000
Vpeak
Vpeak
VIOTM
4000
6000
Safety Limiting Values – maximum
values allowed in the event of a fail-
ure, also see Thermal Derating curve.
Case Temperature
Input Current
Output Power
Insulation Resistance at TS,
VIO = 500 V
TS
IS INPUT
PS OUTPUT
150
150
600
≥ 109
175
230
600
≥ 109
175
400
600
≥ 109
150
400
700
≥ 109
°C
mA
mW
RS
Ω
*Refer to the optocoupler section of the Designer's Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed
description of Method a and Method b partial discharge test profiles.
Note: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data
shall be ensured by means of protective circuits.
Note: Insulation Characteristics are per IEC/EN/DIN EN 60747-5-2.
Note: Surface mount classification is Class A in accordance with CECC 00802.
10
Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
TS
Min.
-55
Max.
125
100
25
Units
°C
Operating Temperature
Average Input Current[1]
Peak Input Current[2] (50% duty cycle, ≤ 1 ms pulse width)
TA
-40
°C
IF(avg)
IF(peak)
IF(tran)
VR
mA
mA
A
50
Peak Transient Input Current (<1 µs pulse width, 300 pps)
1.0
5
Reverse Input Voltage (Pin 3-2)
HCPL-4506, HCPL-0466
HCPL-J456, HCNW4506
Volts
3
Average Output Current (Pin 6)
Resistor Voltage (Pin 7)
IO(avg)
V7
15
mA
Volts
Volts
Volts
mW
-0.5
-0.5
-0.5
VCC
30
Output Voltage (Pin 6-5)
Supply Voltage (Pin 8-5)
Output Power Dissipation[3]
Total Power Dissipation[4]
VO
VCC
PO
30
100
145
PT
mW
Lead Solder Temperature (HCPL-4506, HCPL-J456)
Lead Solder Temperature (HCNW4506)
260°C for 10 s, 1.6 mm below seating plane
260°C for 10 s
(up to seating plane)
Infrared and Vapor Phase Reflow Temperature
(HCPL-0466 and Option 300)
See Package Outline Drawings Section
Recommended Operating Conditions
Parameter
Symbol
VCC
Min.
4.5
0
10
-5
Max.
30
Units
Power Supply Voltage
Output Voltage
Input Current (ON)
Input Voltage (OFF)
Operating Temperature
Volts
Volts
mA
V
VO
IF(on)
30
20
0.8
100
VF(off)
*
TA
-40
°C
*Recommended VF(OFF) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
11
Electrical Specifications
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol Device
Min. Typ.* Max. Units Test Conditions Fig. Note
Current Transfer Ratio
CTR
44
90
%
IF = 10 mA,
VO = 0.6 V
5
Low Level Output Current
IOL
4.4
9.0
mA IF = 10 mA,
VO = 0.6 V
1, 2
1
Low Level Output Voltage
Input Threshold Current
VOL
0.3
1.5
0.6
5
V
IO = 2.4 mA
ITH
HCPL-4506
HCPL-0466
HCNW4506
mA VO = 0.8 V,
IO = 0.75 mA
16
HCPL-J456
0.6
5
High Level Output Current
High Level Supply Current
IOH
50
µA VF = 0.8 V
3
ICCH
0.6
1.3
mA VF = 0.8 V,
VO = Open
16
16
Low Level Supply Current
Input Forward Voltage
ICCL
VF
0.6
1.5
1.3
1.8
mA IF = 10 mA,
VO = Open
HCPL-4506
HCPL-0466
V
IF = 10 mA
4
5
HCPL-J456 1.2
HCNW4506
1.6 1.95
1.6 1.85
-1.6 mV/°C IF = 10 mA
Temperature Coefficient
of Forward Voltage
∆VF/∆TA HCPL-4506
HCPL-0466
HCPL-J456
HCNW4506
-1.3
Input Reverse Breakdown
Voltage
BVR HCPL-4506
HCPL-0466
5
3
V
IR = 10 µA
HCPL-J456
HCNW4506
IR = 100 µA
Input Capacitance
CIN
HCPL-4506
HCPL-0466
60
72
pF f = 1 MHz,
VF = 0 V
HCPL-J456
HCNW4506
Internal Pull-up Resistor
RL
14
20
25
kΩ TA = 25°C
kΩ/°C
12, 13
Internal Pull-up Resistor
Temperature Coefficient
∆RL/∆TA
0.014
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
12
Switching Specifications (RL= 20 kΩ External)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol Min. Typ.* Max. Units
Test Conditions
Fig. Note
Propagation Delay
Time to Logic HCPL-J456
Low at Output
TPHL
30 200
400 ns
480
CL = 100 pF IF(on) = 10 mA, 6, 8,
11,
14,
16
VF(off) = 0.8 V,
10-
13
100
CL = 10 pF VCC = 15.0 V,
Propagation Delay
Time to High
Output Level
TPLH 270 400
130
550 ns
CL = 100 pF VTHLH = 2.0 V,
VTHHL = 1.5 V
CL = 10 pF
Pulse Width
Distortion
Propagation Delay
Difference Between
Any 2 Parts
PWD
200
450 ns
450 ns
CL = 100 pF
20
17
tPLH-tPHL -150 200
Output High Level
Common Mode
Transient Immunity
Output Low Level
Common Mode
|CMH| 15
|CML| 15
30
30
kV/µs IF = 0 mA,
VCC = 15.0 V,
VO > 3.0 V CL = 100 pF,
VCM = 1500 Vp-p
7
18
19
kV/µs IF = 10 mA TA = 25°C
VO < 1.0 V
Transient Immunity
Switching Specifications (RL= Internal Pull-up)
Over recommended operating conditions unless otherwise specified:
TA = -40°C to +100°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V†
Parameter
Symbol Min. Typ.* Max. Units
Test Conditions
Fig. Note
Propagation Delay
Time to Logic HCPL-J456
Low at Output
Propagation Delay Time
to High Output Level
Pulse Width
Distortion
Propagation Delay
Difference Between
Any 2 Parts
tPHL
20 200 400 ns IF(on) = 10 mA, VF(off) = 0.8 V, 6, 9 11-14,
485
220 450 650 ns
250 500 ns
VCC = 15.0 V, CL = 100 pF,
VTHLH = 2.0 V, VTHHL = 1.5 V
16
tPLH
PWD
20
17
tPLH-tPHL -150 250 500 ns
Output High Level
Common Mode
Transient Immunity
Output Low Level
Common Mode
Transient Immunity
|CMH|
|CML|
PSR
30
30
kV/µs IF = 0 mA, VCC = 15.0 V,
VO > 3.0 V CL = 100 pF,
VCM = 1500 Vp-p
7
18
19
16
,
kV/µs IF = 16 mA, TA = 25°C
VO < 1.0 V
Power Supply
Rejection
1.0
Vp-p Square Wave, tRISE, tFALL
> 5 ns, no bypass capacitors
*All typical values at 25°C, VCC = 15 V.
†VF(off) = -3 V to 0.8 V for HCPL-J456, HCNW4506.
13
Package Characteristics
Over recommended temperature (TA = -40°C to 100°C) unless otherwise specified.
Parameter Sym. Device Min. Typ.* Max. Units Test Conditions Fig. Note
Input-Output Momentary VISO HCPL-4506 3750
V rms RH < 50%
t = 1 min.
6,7,10
Withstand Voltage†
HCPL-0466
HCPL-J456 3750
TA = 25°C
6,8,10
HCPL-4506 5000
Option020
6,9,
15
HCNW4506 5000
RI-O HCPL-4506
6,9,10
6
Resistance
1012
VI-O = 500 Vdc
(Input-Output)
HCPL-J456
HCPL-0466
Ω
HCNW4506 1012 1013
Capacitance
CI-O HCPL-4506
0.6
pF
f = 1 MHz
6
(Input-Output)
HCPL-0466
HCPL-J456
HCNW4506
0.8
0.5
*All typical values at 25°C, VCC = 15 V.
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
Table (if applicable), your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output
Endurance Voltage,” publication number 5963-2203E.
Notes:
1. Derate linearly above 90°C free-air
temperature at a rate of 0.8 mA/°C.
2. Derate linearly above 90°C free-air
temperature at a rate of 1.6 mA/°C.
3. Derate linearly above 90°C free-air
temperature at a rate of 3.0 mW/°C.
4. Derate linearly above 90°C free-air
temperature at a rate of 4.2 mW/°C.
5. CURRENT TRANSFER RATIO in
percent is defined as the ratio of
output collector current (IO) to the
forward LED input current (IF) times
100.
6. Device considered a two-terminal
device: Pins 1, 2, 3, and 4 shorted
together and Pins 5, 6, 7, and 8
shorted together.
7. In accordance with UL 1577, each
optocoupler is proof tested by
16. Use of a 0.1 µF bypass capacitor
connected between pins 5 and 8 can
improve performance by filtering
power supply line noise.
17. The difference between tPLH and tPHL
between any two devices under the
same test condition. (See IPM Dead
Time and Propagation Delay
9. In accordance with UL 1577, each
optocoupler is proof tested by
applying an insulation test voltage ≥
6000 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
10. This test is performed before the
100% Production test shown in the
IEC/EN/DIN EN 60747-5-2 Insulation
Related Characteristics Table, if
applicable.
Specifications section.)
18. Common mode transient immunity in
a Logic High level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic High
state (i.e., VO > 3.0 V).
19. Common mode transient immunity in
a Logic Low level is the maximum
tolerable dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic Low
state(i.e., VO < 1.0 V).
11. Pulse: f = 20 kHz, Duty Cycle = 10%.
12. The internal 20 kΩ resistor can be
used by shorting pins 6 and 7
together.
13. Due to tolerance of the internal
resistor, and since propagation delay
is dependent on the load resistor
value, performance can be improved
by using an external 20 kΩ 1% load
resistor. For more information on
how propagation delay varies with
load resistance, see Figure 8.
14. The RL = 20 kΩ, CL = 100 pF load
represents a typical IPM (Intelligent
Power Module) load.
applying an insulation test voltage
≥ 4500 V rms for 1 second (leakage
detection current limit, II-O ≤ 5 µA).
8. In accordance with UL 1577, each
optocoupler is proof tested by
20. Pulse Width Distortion (PWD) is
defined as |tPHL - tPLH| for any given
device.
applying an insulation test voltage ≥
4500 V rms for 1 second (leakage
detection current limit, Ii-o ≤ 5 µA).
15. See Option 020 data sheet for more
information.
14
10
1.05
1.00
0.95
0.90
20.0
V
V
= 0.8 V
F
= V = 4.5 V OR 30 V
CC
O
8
6
4
15.0
10.0
5.0
0
4.5 V
30 V
I
V
= 10 mA
F
V
= 0.6 V
O
= 0.6 V
O
2
0
0.85
0.80
100 °C
25 °C
-40 °C
20
– TEMPERATURE – °C
20
T – TEMPERATURE – °C
A
0
5
10
15
20
-40 -20
0
40
60 80 100
-40 -20
0
40
60 80 100
I
– FORWARD LED CURRENT – mA
T
F
A
Figure 1. Typical Transfer
Characteristics.
Figure 2. Normalized Output Current
vs. Temperature.
Figure 3. High Level Output
Current vs. Temperature.
HCPL-4506/0466
1000
HCPL-J456/HCNW4506
100
T
= 25°C
A
T
= 25 °C
A
100
10
10
1
I
F
I
F
+
V
+
F
V
–
F
–
1.0
0.1
0.1
0.01
0.01
0.001
0.001
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.10 1.20
1.30
1.40
1.50
1.60
V
– INPUT FORWARD VOLTAGE – V
V
– FORWARD VOLTAGE – VOLTS
F
F
Figure 4. HCPL-4506 and HCPL-0466
Input Current vs. Forward Voltage.
Figure 5. HCPL-J456 and HCNW4506
Input Current vs. Forward Voltage.
1
8
7
20 k
Ω
0.1 µF
20 kΩ
I
=10 mA
5 V
F(ON)
+
+
2
3
4
I
–
f
V
= 15 V
t
t
r
CC
f
V
–
O
6
5
V
OUT
90%
10%
90%
10%
C *
L
V
V
THHL
THLH
SHIELD
*TOTAL LOAD CAPACITANCE
t
t
PLH
PHL
Figure 6. Propagation Delay Test Circuit.
15
V
CM
1
2
8
7
0.1 µF
V
20 kΩ
δV
δt
CM
∆t
20 kΩ
I
=
F
+
OV
V
= 15 V
CC
–
A
B
∆t
3
4
6
5
V
OUT
100 pF*
V
O
V
V
CC
+
–
SWITCH AT A: I = 0 mA
SHIELD
F
V
FF
*100 pF TOTAL
CAPACITANCE
V
O
OL
SWITCH AT B: I = 10 mA
F
+
V
= 1500 V
CM
Figure 7. CMR Test Circuit. Typical CMR Waveform.
500
400
300
200
100
600
500
400
300
800
I
V
= 10 mA
= 15 V
F
CC
t
t
PLH
PHL
I
V
= 10 mA
= 15 V
F
CL = 100 pF
RL = 20 kΩ
(INTERNAL)
CC
CL = 100 pF
= 25 °C
600
400
200
T
A
t
t
PLH
PHL
I
V
= 10 mA
= 15 V
CL = 100 pF
RL = 20 kΩ (EXTERNAL)
F
CC
t
t
PLH
PHL
200
100
20
– TEMPERATURE – °C
20
-40 -20
0
40
60 80 100
20
– TEMPERATURE – °C
0
10
30
40
50
-40 -20
0
40
60 80 100
T
RL – LOAD RESISTANCE – kΩ
T
A
A
Figure 8. Propagation Delay with
External 20 kΩ RL vs. Temperature.
Figure 9. Propagation Delay with
Internal 20 kΩ RL vs. Temperature.
Figure 10. Propagation Delay vs. Load
Resistance.
1400
500
1400
I
V
= 10 mA
= 15 V
I
= 10 mA
F
CC
F
t
t
PLH
PHL
CL = 100 pF
RL = 20 kΩ
T
1200
1000
800
RL = 20 kΩ
= 25°C
1200
1000
800
T
= 25°C
A
A
400
300
200
100
t
t
t
t
PLH
PHL
PLH
PHL
V
= 15 V
CC
CL = 100 pF
RL = 20 kΩ
600
600
T
= 25°C
A
400
400
200
0
200
0
0
100
200
300
400
500
5
10
15
20
25
30
0
5
10
15
20
CL – LOAD CAPACITANCE – pF
V
– SUPPLY VOLTAGE – V
I
– FORWARD LED CURRENT – mA
CC
F
Figure 11. Propagation Delay vs. Load
Capacitance.
Figure 12. Propagation Delay vs.
Supply Voltage.
Figure 13. Propagation Delay vs. Input
Current.
16
HCPL-0466 OPTION 060/HCNW4506
HCPL-4506 OPTION 060/HCPL-J456
1000
800
700
600
500
400
300
P
(mW) FOR HCNW4506
(mA) FOR HCNW4506
S
P
(mW)
S
900
800
700
600
500
400
300
I
S
I
(mA) FOR HCPL-4506
S
P
(mW) FOR HCPL-0466
OPTION 060
S
OPTION 060
(mA) FOR HCPL-0466
I
(mA) FOR HCPL-J456
S
I
S
OPTION 060
(230)
200
200
(150)
100
100
0
0
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
0
25
50 75 100 125 150 175
T
T – CASE TEMPERATURE – °C
S
S
Figure 14. Thermal Derating Curve, Dependence of Safety Limiting Value with
Case Temperature per IEC/EN/DIN EN 60747-5-2.
1
2
8
7
1
2
8
7
20 kΩ
0.1 µF
20 kΩ
20 kΩ
C
LEDP
+
+5 V
310 Ω
CMOS
V
= 15 V
–
CC
3
4
6
5
3
4
6
5
V
OUT
C
LEDN
100 pF
SHIELD
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 15. Recommended LED Drive Circuit.
Figure 16. Optocoupler Input to
Output Capacitance Model for
Unshielded Optocouplers.
1
2
8
7
1
8
7
+5 V
20 kΩ
20 kΩ
0.1 µF
20 kΩ
C
LEDP
+
C
2
3
4
LED02
V
= 15 V
–
CC
310 Ω
C
LED01
3
4
6
5
6
5
V
OUT
C
LEDN
CMOS
100 pF
SHIELD
SHIELD
*100 pF TOTAL
CAPACITANCE
Figure 17. Optocoupler Input to
Output Capacitance Model for
Shielded Optocouplers.
Figure 18. LED Drive Circuit with Resistor Connected to LED Anode (Not
Recommended).
17
1
2
8
7
1
2
8
7
20
20
20 kΩ
I
I
TOTAL*
CLEDP
kΩ
kΩ
C
20 kΩ
LEDP
C
C
LED02
LED02
C
I
LEDP
F
310 Ω
C
C
LED01
LED01
I
CLED01
310 Ω
V
OUT
V
C
LEDN
OUT
3
4
6
5
3
4
6
5
C
LEDN
I
CLEDN*
100 pF
100 pF
+ V ** –
R
SHIELD
SHIELD
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV /dt TRANSIENTS.
FLOW FOR +dV /dt TRANSIENTS.
CM
CM
** OPTIONAL CLAMPING DIODE FOR IMPROVED CMH
+
PERFORMANCE.
V
< V
DURING +dV /dt.
R
F (OFF)
CM
V
CM
+
V
CM
Figure 19. AC Equivalent Circuit for Figure 18 During
Common Mode Transients.
Figure 20. AC Equivalent Circuit for Figure 15 During
Common Mode Transients.
1
2
8
7
20
kΩ
C
20 kΩ
LEDP
C
LED02
1
2
8
7
C
LED01
+5 V
20 kΩ
V
C
Q1
OUT
LEDN
3
4
6
5
I
CLEDN*
100 pF
3
4
6
5
SHIELD
Q1
* THE ARROWS INDICATE THE DIRECTION OF CURRENT
FLOW FOR +dV /dt TRANSIENTS.
CM
SHIELD
+
V
CM
Figure 21. Not Recommended Open
Collector LED Drive Circuit.
Figure 22. AC Equivalent Circuit for Figure 21 During
Common Mode Transients.
1
8
7
+5 V
20 kΩ
2
3
6
5
4
SHIELD
Figure 23. Recommended LED Drive
Circuit for Ultra High CMR.
18
HCPL-4506
1
2
8
7
V
CC1
0.1 µF
20 kΩ
IPM
I
LED1
20 kΩ
+5 V
+HV
V
310 Ω
CMOS
OUT1
3
4
6
5
Q1
Q2
M
SHIELD
HCPL-4506
HCPL-4506
1
2
8
7
V
CC2
-HV
0.1 µF
20 kΩ
HCPL-4506
HCPL-4506
HCPL-4506
HCPL-4506
I
LED2
20 kΩ
+5 V
310 Ω
CMOS
V
OUT2
3
4
6
5
SHIELD
Figure 24. Typical Application Circuit.
I
LED1
Q1 OFF
Q2 ON
Q1 ON
Q2 OFF
V
V
OUT1
OUT2
I
LED1
I
LED2
t
PLH
MIN.
Q1 OFF
Q2 ON
t
Q1 ON
PLH
V
V
OUT1
OUT2
MAX.
Q2 OFF
t
PHL
PDD*
MAX.
MIN.
t
PHL
MAX.
I
LED2
MAX.
DEAD TIME
t
PLH MAX.
t
MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)
PHL
MIN.
= (t
= (t
t
t
) + (t
) - (t
t
)
PLH MAX.
-
-
PLH MIN.
PHL MAX.
-
t
PHL MIN.
)
PLH MAX.
PHL MIN.
PLH MIN.
-
PHL MAX.
PDD* MAX. =
(t
= PDD* MAX. - PDD* MIN.
t
)
t
t
PLH- PHL MAX. = PLH MAX. - PHL MIN.
*PDD = PROPAGATION DELAY DIFFERENCE
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE
PDD ARE TAKEN AT EQUAL TEMPERATURES.
NOTE: THE PROPAGATION DELAYS USED TO CALCULATE THE MAXIMUM
DEAD TIME ARE TAKEN AT EQUAL TEMPERATURES.
Figure 25. Minimum LED Skew for Zero Dead Time.
Figure 26. Waveforms for Dead Time Calculation.
19
LED Drive Circuit
connection of the unused input
package pins, and the value of the
capacitor at the optocoupler
output (CL).
trying to pull the output high
(toward a CMR failure) at the
same time the LED current is
being reduced. For this reason,
the recommended LED drive
circuit (Figure 15) places the
current setting resistor in series
with the LED cathode. Figure 20
is the AC equivalent circuit for
Figure 15 during common mode
transients. In this case, the LED
current is not reduced during a
+dVcm/dt transient because the
current flowing through the
package capacitance is supplied
by the power supply. During a
-dVcm/dt transient, however, the
LED current is reduced by the
amount of current flowing
Considerations for Ultra
High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive coupl-
ing from the input side of the
optocoupler, through the
Techniques to keep the LED in
the proper state and minimize the
effect of the direct coupling are
discussed in the next two
sections.
package, to the detector IC
as shown in Figure 16. The
HCPL-4506 series improve
CMR performance by using a
detector IC with an optically
transparent Faraday shield, which
diverts the capacitively coupled
current away from the sensitive
IC circuitry. However, this shield
does not eliminate the capacitive
coupling between the LED and
the optocoupler output pins and
output ground as shown in Figure
17. This capacitive coupling
causes perturbations in the LED
current during common mode
transients and becomes the
major source of CMR failures
for a shielded optocoupler. The
main design objective of a high
CMR LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 15), can achieve
15 kV/µs CMR while minimizing
component complexity. Note that
a CMOS gate is recommended
in Figure 15 to keep the LED
off when the gate is in the high
state.
CMR with the LED On
(CMRL)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. The recommended
minimum LED current of 10 mA
provides adequate margin over
the maximum ITH of 5.0 mA (see
Figure 1) to achieve 15 kV/µs
CMR. Capacitive coupling is
higher when the internal load
through CLEDN. But, better CMR
performance is achieved since the
current flowing in CLEDO1 during a
negative transient acts to keep the
output low.
Coupling to the LED and output
pins is also affected by the con-
nection of pins 1 and 4. If CMR is
limited by perturbations in the
LED on current, as it is for the
recommended drive circuit
(Figure 15), pins 1 and 4 should
be connected to the input circuit
common. However, if CMR
performance is limited by direct
coupling to the output when the
LED is off, pins 1 and 4 should be
left unconnected.
resistor is used (due to CLEDO2
)
and an IF = 16 mA is required to
obtain 10 kV/µs CMR.
The placement of the LED current
setting resistor effects the ability
of the drive circuit to keep the
LED on during transients and
interacts with the direct coupling
to the optocoupler output. For
example, the LED resistor in
Figure 18 is connected to the
anode. Figure 19 shows the AC
equivalent circuit for Figure 18
during common mode transients.
During a +dVcm/dt in Figure 19,
the current available at the LED
anode (Itotal) is limited by the
series resistor. The LED current
(IF) is reduced from its DC value
by an amount equal to the current
that flows through CLEDP and
CLEDO1. The situation is made
worse because the current
CMR with the LED Off
(CMRH)
A high CMR LED drive circuit
must keep the LED off
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a +dVcm/dt transient in
Figure 20, the current flowing
through CLEDN is supplied by the
parallel combination of the LED
and series resistor. As long as the
voltage developed across the
resistor is less than VF(OFF) the
Another cause of CMR failure for
a shielded optocoupler is direct
coupling to the optocoupler
output pins through CLEDO1 and
CLEDO2 in Figure 17. Many factors
influence the effect and magni-
tude of the direct coupling
including: the use of an internal
or external output pull-up
resistor, the position of the LED
current setting resistor, the
through CLEDO1 has the effect of
20
LED will remain off and no
IPM Dead Time and
Propagation Delay
Specifications
is delayed by (tPLH max - tPHL min)
common mode failure will occur.
Even if the LED momentarily
turns on, the 100 pF capacitor
from pins 6-5 will keep the output
from dipping below the threshold.
The recommended LED drive
circuit (Figure 15) provides about
10 V of margin between the
lowest optocoupler output voltage
and a 3 V IPM threshold during
a 15 kV/µs transient with
VCM = 1500 V. Additional margin
can be obtained by adding a diode
in parallel with the resistor, as
shown by the dashed line con-
nection in Figure 20, to clamp
the voltage across the LED
from the LED1 turn off. Note that
the propagation delays used to
calculate PDD are taken at equal
temperatures since the opto-
couplers under consideration
are typically mounted in close
proximity to each other.
(Specifically, tPLH max and tPHL min
in the previous equation are not
the same as the tPLH max and
tPHL min, over the full operating
temperature range, specified in
the data sheet.) This delay is the
maximum value for the propaga-
tion delay difference specification
which is specified at 450 ns for
the HCPL-4506 series over an
operating temperature range of
-40°C to 100°C.
The HCPL-4506 series include
a Propagation Delay Difference
specification intended to help
designers minimize “dead time”
in their power inverter designs.
Dead time is the time period
during which both the high and
low side power transistors (Q1
and Q2 in Figure 24) are off. Any
overlap in Q1 and Q2 conduction
will result in large currents flow-
ing through the power devices
between the high and low voltage
motor rails.
below VF(OFF)
.
To minimize dead time the
designer must consider the propa-
gation delay characteristics of the
optocoupler as well as the charac-
teristics of the IPM IGBT gate
drive circuit. Considering only the
delay characteristics of the opto-
coupler (the characteristics of the
IPM IGBT gate drive circuit can
be analyzed in the same way) it is
important to know the minimum
and maximum turn-on (tPHL) and
turn-off (tPLH) propagation delay
specifications, preferably over the
desired operating temperature
range.
Since the open collector drive
circuit, shown in Figure 21,
cannot keep the LED off during
a +dVcm/dt transient, it is
not desirable for applications
requiring ultra high CMRH
performance. Figure 22 is the AC
equivalent circuit for Figure 21
during common mode transients.
Essentially all the current flowing
through CLEDN during a +dVcm/dt
transient must be supplied by
the LED. CMRH failures can occur
at dV/dt rates where the current
through the LED and CLEDN
exceeds the input threshold.
Figure 23 is an alternative drive
circuit which does achieve ultra
high CMR performance by
Delaying the LED signal by the
maximum propagation delay dif-
ference ensures that the minimum
dead time is zero, but it does not
tell a designer what the maximum
dead time will be. The maximum
dead time occurs in the highly
unlikely case where one opto-
coupler with the fastest tPLH and
another with the slowest tPHL
are in the same inverter leg. The
maximum dead time in this case
becomes the sum of the spread
in the tPLH and tPHL propagation
delays as shown in Figure 26.
The maximum dead time is also
equivalent to the difference
between the maximum and mini-
mum propagation delay difference
specifications. The maximum
dead time (due to the optocoup-
lers) for the HCPL-4506 series
is 600 ns (= 450 ns - (-150 ns) )
over an operating temperature
range of -40°C to 100°C.
The limiting case of zero dead
time occurs when the input to Q1
turns off at the same time that the
input to Q2 turns on. This case
determines the minimum delay
between LED1 turn-off and LED2
turn-on, which is related to the
worst case optocoupler propaga-
tion delay waveforms, as shown in
Figure 25. A minimum dead time
of zero is achieved in Figure 25
when the signal to turn on LED2
shunting the LED in the off state.
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Data subject to change.
Copyright © 2004 Agilent Technologies, Inc.
Obsoletes 5988-8709EN
January 27, 2004
5989-0307EN
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