HCPL-90XX [AGILENT]
High Speed Digital Isolators; 高速数字隔离器
| 型号： | HCPL-90XX |
| 厂家： | 
AGILENT TECHNOLOGIES, LTD. |
| 描述： | High Speed Digital Isolators |
| 文件： | 总12页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators
Data Sheet
Features
• +3.3V and +5V TTL/CMOS
compatible
• 3 ns max. pulse width distortion
•
6 ns max. propagation delay skew
• 15 ns max. propagation delay
• High speed: 100 MBd
Description
tional (HCPL-900J/-090J), two
channels in one direction and
two channels in opposite direc-
tion (HCPL-901J/-091J), and one
channel in one direction and
three channels in opposite
direction (HCPL-902J/-092J).
These high channel density make
them ideally suited to isolating
data conversion devices, parallel
buses and peripheral interfaces.
The HCPL-90xx and HCPL-09xx
CMOS digital isolators feature
high speed performance and
excellent transient immunity
specifications. The symmetric
magnetic coupling barrier gives
these devices a typical pulse
width distortion of 2 ns, a typical
propagation delay skew of 4 ns
and 100 Mbaud data rate, making
them the industry’s fastest
digital isolators.
• 15 kV/µs min. common mode
rejection
• Tri-state output
(HCPL-9000/-0900)
• 2500V RMS isolation
• UL1577 and IEC 61010-1 approved
Applications
• Digital fieldbus isolation
They are available in 8-pin PDIP,
8-pin Gull Wing, 8-pin SOIC
packages, and 16–pin SOIC
narrow-body and wide-body
packages. They are specified over
the temperature range of -40°C
to +100°C.
The single channel digital isola-
tors (HCPL-9000/-0900) features
an active-low logic output enable.
The dual channel digital isolators
are configured as unidirectional
(HCPL-9030/-0930) and bi-
directional (HCPL-9031/-0931),
operating in full duplex mode
making it ideal for digital
• Multiplexed data transmission
• Computer peripheral interface
• High speed digital systems
• Isolated data interfaces
• Logic level shifting
CAUTION: It is advised that
normal static precautions be
taken in handling and assembly
of this component to prevent
damage and/or degradation,
which may be induced by ESD.
fieldbus applications.
The quad channel digital isola-
tors are configured as unidirec-
Selection Guide
Device Number
Channel Configuration
Package
HCPL-9000
HCPL-0900
HCPL-9030
HCPL-0930
HCPL-9031
HCPL-0931
HCPL-900J
HCPL-090J
HCPL-901J
HCPL-091J
HCPL-902J
HCPL-092J
Single
8-pin DIP (300 Mil)
Single
8-pin Small Outline
Dual
8-pin DIP (300 Mil)
Dual
8-pin Small Outline
Dual, Bi-Directional
Dual, Bi-Directional
Quad
8-pin DIP (300 Mil)
8-pin Small Outline
16-pin Small Outline, Wide Body
16-pin Small Outline, Narrow Body
16-pin Small Outline, Wide Body
16-pin Small Outline, Narrow Body
16-pin Small Outline, Wide Body
16-pin Small Outline, Narrow Body
Quad
Quad, 2/2, Bi-Directional
Quad, 2/2, Bi-Directional
Quad, 1/3, Bi-Directional
Quad, 1/3, Bi-Directional
Ordering Information
Specify Part Number followed by Option Number (if desired).
Examples:
HCPL-90xx-xxx
xxx:
No option = 300 Mil PDIP-8 package, 50 units per tube.
300 = Gull Wing Surface Mount Option, 50 units per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
HCPL-09xx-xxx
xxx:
No option = SO-8 package, 100 units per tube.
500 = Tape and Reel Packaging Option, 1500 units per reel.
HCPL-90xJ-xxx
xxx:
No option = Wide Body SOIC-16 package, 50 units per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
HCPL-09xJ-xxx
xxx:
No option = Narrow Body SOIC-16 package, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
2
Pin Description
Functional Diagrams
Symbol
Description
Single Channel
VDD1
VDD2
INX
Power Supply 1
Truth Table
IN1
8
VDD2
VDD1
1
Power Supply 2
VOE
OUT1
IN1
2
3
4
VOE
7
6
5
Logic Input Signal
Logic Output Signal
Power Supply Ground 1
Power Supply Ground 2
L
L
L
OUTX
GND1
GND2
VOE
OUT1
GND2
NC
H
L
L
H
Z
Z
GND1
H
H
H
Logic Output Enable
(Single Channel), Active Low
HCPL-9000/0900
NC
Not Connected
Dual Channel
8
8
VDD2
OUT1
IN2
VDD2
VDD1
IN1
VDD1
1
2
1
IN1
2
3
4
OUT1
OUT2
GND2
7
6
5
7
6
5
3
4
IN2
OUT2
GND1
GND1
GND2
HCPL-9030/0930
HCPL-9031/0931
Quad Channel
VDD1
GND1
IN1
1
VDD1
GND1
IN1
1
16
VDD1
GND1
IN1
16
1
16
VDD2
VDD2
VDD2
GND2
GND2
15
14
13
12
11
GND2
2
3
4
5
6
7
8
15
14
13
12
11
2
3
4
5
6
7
8
2
3
4
5
6
7
8
15
14
13
12
11
OUT1
OUT2
IN3
OUT1
OUT2
OUT3
OUT1
OUT2
OUT3
IN2
IN2
IN3
IN2
IN3
OUT3
OUT4
NC
OUT4
NC
IN4
NC
IN4
IN4
OUT4
NC
10
9
10
9
10
9
NC
NC
GND1
GND1
GND1
GND2
GND2
GND2
HCPL-901J/-091J
HCPL-902J/-092J
HCPL-900J/-090J
3
Package Outline Drawings
HCPL-9000, HCPL-9030 and HCPL-9031 Standard DIP Packages
8
7
6
5
0.240 (6.096)
0.260 (6.604)
1
2
3
4
0.370 (9.398)
0.400 (10.160)
0.55 (1.397)
0.65 (1.651)
0.290 (7.366)
0.310 (7.874)
0.120 (3.048)
0.150 (3.810)
0.008 (0.203)
0.015 (0.381)
0.015 (0.381)
0.035 (0.889)
3°
8°
0.030 (0.762)
0.045 (1.143)
0.300 (7.620)
0.370 (9.398)
0.090 (2.286)
0.110 (2.794)
0.015 (0.380)
0.023 (0.584)
0.045 (1.143)
0.065 (1.651)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
HCPL-9000, HCPL-9030 and HCPL-9031 Gull Wing Surface Mount Option 300
PAD LOCATION (for reference only)
0.370 (9.400)
0.390 (9.900)
0.040 (1.016)
0.047 (1.194)
8
7
6
5
0.190
(4.826)
TYP.
0.240 (6.100)
0.260 (6.600)
0.370 (9.398)
0.390 (9.906)
1
2
3
4
0.015 (0.381)
0.025 (0.635)
0.047 (1.194)
0.070 (1.778)
0.045 (1.143)
0.370 (9.400)
0.065 (1.651)
0.390 (9.900)
0.030 (0.762)
0.045 (1.143)
0.290 (7.370)
0.310 (7.870)
0.008 (0.203)
0.013 (0.330)
0.120 (3.048)
0.150 (3.810)
0.030 (0.760)
0.056 (1.400)
0.015 (0.385)
0.035 (0.885)
12° NOM.
0.025 (0.632)
0.035 (0.892)
0.100
(2.540)
BSC
MIN
DIMENSIONS INCHES (MILLIMETERS)
MAX
LEAD COPLANARITY = 0.004 INCHES (0.10 mm)
4
HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package
0.189 (4.80)
0.197 (5.00)
8
7
6
5
4
0.228 (5.80)
0.244 (6.20)
0.150 (3.80)
0.157 (4.00)
2
1
3
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
0.020 (0.50)
x 45°
0.008 (0.19)
0.010 (0.25)
0.004 (0.10)
0.010 (0.25)
0.054 (1.37)
0.069 (1.75)
0°
8°
0.040 (1.016)
0.060 (1.524)
0.016 (0.40)
0.050 (1.27)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package
0.397 (10.084)
0.413 (10.490)
Pin 1 indent
8
1
0.394 (10.007)
0.419 (10.643)
0.291 (7.391)
0.299 (7.595)
0.013 (0.330)
0.020 (0.508)
0.092 (2.337)
0.104 (2.642)
0.287 (7.290)
0.297 (7.544)
0.010 (0.254)
0.020 (0.508)
7° TYP
x 45°
7° TYP
0.080 (2.032)
0.100 (2.54)
0° – 8° TYP
0.040 (1.016)
0.060 (1.524)
0.009 (0.229)
0.012 (0.305)
0.016 (0.40)
0.050 (1.27)
0.004 (0.1016)
0.011 (0.279)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
5
HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package
0.386 (9.802)
0.394 (9.999)
Pin 1 indent
8
1
0.228 (5.791)
0.244 (6.197)
0.152 (3.861)
0.157 (3.988)
0.013 (0.330)
0.020 (0.508)
0.054 (1.372)
0.068 (1.727)
0.010 (0.245)
0.020 (0.508)
x 45°
0.008 (0.191)
0.010 (0.249)
0.050 (1.270)
0.060 (1.524)
0° – 8° TYP
0.040 (1.016)
0.060 (1.524)
0.016 (0.406)
0.050 (1.270)
0.004 (0.102)
0.010 (0.249)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
Package Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Capacitance (Input-Output)[1]
Single Channel
CI-O
pF
f = 1 MHz
1.1
2.0
4.0
Dual Channel
Quad Channel
Thermal Resistance
8-Pin PDIP
θJCT
°C/W
Thermocouple located at
center underside of package
150
240
8-Pin SOIC
Package Power Dissipation
8-Pin PDIP
PPD
mW
150
150
8-Pin SOIC
Notes:
1. Single and dual channels device are considered two-terminal devices: pins 1-4 shorted and pins 5-8 shorted. Quad channel devices are considered
two-terminal devices: pins 1-8 shorted and pins 9-16 shorted.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
6
Insulation and Safety Related Specifications
Parameters
Condition
Min.
Typ.
Max.
Units
Barrier Impedance
Ω||pF
Single Channel
Dual Channel
Quad Channel
>1014||3
>1014||3
>1014||7
Creepage Distance (External)
mm
8-Pin PDIP
8-Pin SOIC
16-Pin SOIC Narrow Body
16-Pin SOIC Wide Body
7.036
4.026
4.026
8.077
Leakage Current
240 VRMS
60 Hz
0.2
µA
Absolute Maximum Ratings
Parameters
Symbol
Min.
Max.
Units
Storage Temperature
Ambient Operating Temperature[1]
Supply Voltage
TS
–55
–55
–0.5
–0.5
–0.5
–0.5
175
°C
°C
V
TA
125
VDD1, VDD2
VIN
7
Input Voltage
VDD1 +0.5
VDD2 +0.5
VDD2 +0.5
10
V
Voltage Output Enable (HCPL-9000/-0900)
Output Voltage
VOE
V
VOUT
IOUT
V
Output Current Drive
Lead Solder Temperature (10s)
ESD
mA
°C
260
2 kV Human Body Model
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.
Recommended Operating Conditions
Parameters
Symbol
Min.
Max.
Units
Ambient Operating Temperature
Supply Voltage
TA
–40
3.0
2.4
0
100
5.5
VDD1
0.8
1
°C
V
VDD1, VDD2
VIH
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
V
VIL
V
tIR, tIF
µs
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
7
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Quiescent Supply Current 1
IDD1
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
0.008
0.008
1.5
0.016
3.3
0.01
0.01
2.0
0.02
4.0
1.5
2.0
Quiescent Supply Current 2
IDD2
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
3.3
3.3
1.5
5.5
3.3
3.0
4.0
4.0
2.0
8.0
4.0
6.0
Logic Input Current
IIN
-10
10
µA
V
Logic High Output Voltage
VOH
VDD2 –0.1
VDD2
IOUT = -20 µA, VIN= VIH
IOUT = -4 mA, VIN= VIH
IOUT = 20 µA, VIN= VIL
IOUT = 4 mA, VIN= VIL
0.8 V
*
VDD2 –0.5
V
DD2
Logic Low Output Voltage
VOL
0
0.1
0.8
V
0.5
V
Switching Specifications
Maximum Data Rate
100
110
MBd
MHz
ns
CL = 15 pF
Clock Frequency
fmax
tPHL
50
18
Propagation Delay Time to Logic
Low Output
12
12
Propagation Delay Time toLogic
High Output
tPLH
18
3
ns
Pulse Width
tPW
10
ns
ns
Pulse Width Distortion[1]
|PWD|
2
|tPHL – tPLH
|
Propagation Delay Skew[2]
Output Rise Time (10 – 90%)
Output Fall Time (10 – 90%)
tPSK
tR
4
2
2
6
4
4
ns
ns
ns
tF
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
Low to High Impedance
High Impedance to High
High Impedance to Low
tPHZ
tPLZ
tPZH
tPZL
tCSK
3
3
3
3
2
5
5
5
5
3
ns
ns
ns
ns
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
Common Mode Transient Immunity
(Output Logic High or Logic Low)[3]
|CMH|
|CML|
15
18
kV/µs Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
8
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Quiescent Supply Current 1
IDD1
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
0.012
0.012
2.5
0.024
5.0
0.018
0.018
3.0
0.036
6.0
2.5
3.0
Quiescent Supply Current 2
IDD2
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
5.0
5.0
2.5
8.0
5.0
6.0
6.0
6.0
3.0
12.0
6.0
9.0
Logic Input Current
IIN
-10
10
µA
V
Logic High Output Voltage
VOH
VDD2 – 0.1
VDD2
IOUT= -20 µA, VIN= VIH
IOUT= -4 mA, VIN= VIH
IOUT= 20 µA, VIN= VIL
IOUT= 4 mA, VIN= VIL
0.8 V
*
VDD2 – 0.5
V
DD2
Logic Low Output Voltage
VOL
0
0.1
0.8
V
0.5
V
Switching Specifications
Maximum Data Rate
100
110
MBd
MHz
ns
CL = 15 pF
Clock Frequency
fmax
tPHL
50
15
Propagation Delay Time to Logic
Low Output
10
10
Propagation Delay Time to Logic
High Output
tPLH
15
3
ns
Pulse Width
tPW
10
ns
ns
Pulse Width Distortion[1]
|PWD|
2
|tPHL – tPLH
|
Propagation Delay Skew[2]
Output Rise Time (10 – 90%)
Output Fall Time (10 – 90%)
tPSK
tR
4
1
1
6
3
3
ns
ns
ns
tF
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
Low to High Impedance
High Impedance to High
High Impedance to Low
tPHZ
tPLZ
tPZH
tPZL
tCSK
3
3
3
3
2
5
5
5
5
3
ns
ns
ns
ns
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
Common Mode Transient Immunity
(Output Logic High or Logic Low)[3]
|CMH|
|CML|
15
18
kV/µs Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
9
Applications Information
Signal Status on Start-up and
Shut Down
to be connected directly to the
inputs and outputs. As shown in
Figure 1, the only external
Power Consumption
To minimize power dissipation,
the input signals to the channels
of HCPL-90xx and HCPL-09xx
digital isolators are differenti-
ated and then latched on the
output side of the isolation
barrier to reconstruct the signal.
This could result in an ambigu-
ous output state depending on
power up, shutdown and power
loss sequencing. Therefore, the
designer should consider the
inclusion of an initialization
signal in this start-up circuit.
The HCPL-90xx and HCPL-09xx
CMOS digital isolators achieves
low power consumption from the
manner by which they transmit
data across isolation barrier. By
detecting the edge transitions of
the input logic signal and con-
verting this to a narrow current
pulse, which drives the isolation
barrier, the isolator then latches
the input logic state in the output
latch. Since the current pulses
are narrow, about 2.5 ns wide, the
power consumption is indepen-
dent of mark-to-space ratio and
solely dependent on frequency.
components required for proper
operation are two 47 nF ceramic
capacitors for decoupling the
power supplies. For each capaci-
tor, the total lead length between
both ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 2 illustrates
the recommended printed circuit
board layout for the HCPL-9000
or HCPL-0900. For data rates in
excess of 10MBd, use of ground
planes for both GND1 and GND2 is
highly recommended.
Bypassing and PC Board Layout
The HCPL-90xx and HCPL-09xx
digital isolators are extremely
easy to use. No external interface
circuitry is required because the
isolators use high-speed CMOS IC
technology allowing CMOS logic
The approximate power supply
current per channel is:
I(Input) = 40(f/fmax)(1/4) mA
where f = operating frequency,
fmax = 50 MHz.
VDD1
IN1
VDD2
8
1
C2
C1
2
NC 3
4
7
6
VOE
OUT1
GND2
GND1
5
Note: C1, C2 = 47 nF ceramic capacitors
Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.
VDD1
VDD2
IN1
VOE
C2
C1
OUT1
GND2
GND1
Figure 2. Recommended Printed Circuit Board Layout.
10
Propagation Delay, Pulse Width
Distortion and Propagation Delay Skew the difference between tPHL and
Propagation Delay is a figure of
merit, which describes how
quickly a logic signal propagates
Pulse Width Distortion, PWD, is
If the parallel data is being sent
through channels of the digital
isolators, differences in propaga-
tion delays will cause the data to
arrive at the outputs of the
digital isolators at different
times. If this difference in
tPLH and often determines the
maximum data rate capability of
a transmission system. PWD can
through a system as illustrated in be expressed in percent by
Figure 3.
dividing the PWD (in ns) by the
minimum pulse width (in ns)
propagation delay is large
The propagation delay from low to being transmitted. Typically, PWD enough, it will limit the maxi-
high, tPLH, is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low, tPHL, is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low.
on the order of 20–30% of the
minimum pulse width is tolerable. parallel data can be sent through
the digital isolators.
mum transmission rate at which
Propagation Delay Skew, tPSK
,
and Channel-to-Channel Skew,
tCSK, are critical parameters to
consider in parallel data trans-
mission applications where
synchronization of signals on
parallel data lines is a concern.
tPSK is defined as the difference
between the minimum and
maximum propagation delays,
either tPLH or tPHL, among two or
more devices which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and operat-
ing temperature). tCSK is defined
as the difference between the
minimum and maximum propaga-
5 V CMOS
INPUT
tion delays, either tPLH or tPHL
,
50%
V
IN
among two or more channels
within a single device (applicable
to dual and quad channel de-
vices) which are operating under
the same conditions.
0 V
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
OUT
10%
10%
V
OL
As illustrated in Figure 4, if the
inputs of two or more devices are
switched either ON or OFF at the
same time, tPSK is the difference
between the minimum propaga-
tion delay, either tPLH or tPHL, and
the maximum propagation delay,
Figure 3. Timing Diagrams to Illustrate Propagation Delay, tPLH and tPHL
.
VIN
DATA
50%
INPUTS
either tPLH or tPHL
.
CLOCK
2.5 V
CMOS
VOUT
As mentioned earlier, tPSK, can
determine the maximum parallel
data transmission rate. Figure 5
shows the timing diagram of a
typical parallel data transmission
application with both the clock
and data lines being sent through
the digital isolators. The figure
shows data and clock signals at
the inputs and outputs of the
digital isolators. In this case, the
data is clocked off the rising edge
of the clock.
tPSK
DATA
50%
OUTPUTS
CLOCK
VIN
tPSK
tPSK
2.5 V
CMOS
VOUT
Figure 5. Parallel Data Transmission.
Figure 4. Timing Diagrams to Illustrate
Propagation Delay Skew.
11
Propagation delay skew repre-
sents the uncertainty of where
an edge might be after being sent start to change before the clock
the data outputs have settled, or
some of the data outputs may
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
through a digital isolator. Figure
5 shows that there will be uncer-
tainty in both the data and clock
lines. It is important that these
two areas of uncertainty not
overlap, otherwise the clock
signal might arrive before all of
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be pulse width, rise and fall time,
sent through digital isolators in a and propagation delay enable to
parallel application is twice tPSK
A cautious design should use a
slightly longer pulse width to
Figure 6 shows the minimum
.
output waveforms for HCPL-9000
or HCPL-0900.
50%
VIN
tPZL
90%
90%
tPLZ
50%
tPHZ
VOUT
10%
10%
tPZH
tPW
tF
tR
VOE
tPW
tPLZ
tPZH
Minimum Pulse Width
Propagation Delay, Low to High Impedance
Propagation Delay, High Impedance to High
tPHZ
tPZL
tR
Propagation Delay, High to High Impedance
Propagation Delay, High Impedance to Low
Rise Time
tF
Fall Time
Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to
Output Waveforms for HCPL-9000 or HCPL-0900.
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or
(408) 654-8675
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (+65) 6271 2451
India, Australia, New Zealand: (+65) 6271 2394
Japan: (+81 3) 3335-8152(Domestic/International), or
0120-61-1280(Domestic Only)
Korea: (+65) 6271 2194
Malaysia, Singapore: (+65) 6271 2054
Taiwan: (+65) 6271 2654
Data subject to change.
Copyright © 2002 Agilent Technologies, Inc.
October 31, 2002
5988-5626EN
相关型号：
HCPL-J314-300E
Logic IC Output Optocoupler, 1-Element, 3750V Isolation, 0.300 INCH, SURFACE MOUNT, DIP-8
AGILENT
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