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HFBR-1115T

更新时间：2024-09-18 02:10:02

品牌：AGILENT

描述：Fiber Optic Transmitter and Receiver Data Links for 125 MBd

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概述
规格参数
数据手册

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HFBR-1115T 概述

Fiber Optic Transmitter and Receiver Data Links for 125 MBd 光纤发射器和接收数据的125 MBd的相关链接光纤发送器

HFBR-1115T 规格参数

生命周期：	Transferred	包装说明：	DIP
Reach Compliance Code：	unknown	风险等级：	5.27
Is Samacsys：	N	主体宽度：	12.19 mm
主体高度：	9.8 mm	通信标准：	ATM, FDDI
连接类型：	ST CONNECTOR	发射极/检测器类型：	LED
光纤设备类型：	TRANSMITTER	光纤类型：	MMF
安装特点：	THROUGH HOLE MOUNT	最高工作温度：	70 °C
最低工作温度：		最大工作波长：	1380 nm
最小工作波长：	1270 nm	标称工作波长：	1308 nm
标称光功率输出：	0.009 mW	封装形式：	DIP
子类别：	Fiber Optic Emitters	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	传输类型：	DIGITAL
Base Number Matches：	1

HFBR-1115T 数据手册

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Technical Data

The HFBR-1115/-2115 series of

data links are high-performance,

cost-efficient, transmitter and

receiver modules for serial

optical data communication

applications specified at 100

Mbps for FDDI PMD or 100 Base-

FX Fast Ethernet applications.

These modules are designed for

50 or 62.5 µm core multi-mode

optical fiber and operate at a

nominal wavelength of 1300 nm.

They incorporate our high-

performance, reliable, long-

wavelength, optical devices and

proven circuit technology to give

long life and consistent

preamplifier IC. The PIN-

preamplifier combination is ac-

coupled to a custom quantizer IC

which provides the final pulse

shaping for the logic output and

the Signal Detect function. Both

the Data and Signal Detect

Outputs are differential. Also,

both Data and Signal Detect

Outputs are PECL compatible,

ECL-referenced (shifted) to a

+5 V power supply.

performance.

The transmitter utilizes a

1300 nm surface-emitting

InGaAsP LED, packaged in an

optical subassembly. The LED is

dc-coupled to a custom IC which

converts differential-input, PECL

logic signals, ECL-referenced

(shifted) to a +5 V power supply,

into an analog LED drive current.

The overall package concept for

the Data Links consists of the

following basic elements: two

optical subassemblies, two

electrical subassemblies, and the

outer housings as illustrated in

Figure 1.

The receiver utilizes an InGaAs

PIN photodiode coupled to a

custom silicon transimpedance

*ST is a registered trademark of AT&T Lightguide Cable Connectors.

5965-3481E (8/96)

177

The package outline drawing and

pinout are shown in Figures 2

and 3. The details of this package

outline and pinout are compatible

with other data-link modules from

other vendors.

RECEIVER

PIN PHOTODIODE

DIFFERENTIAL

DATA IN

QUANTIZER

DIFFERENTIAL

SIGNAL

DETECT OUT

PREAMP IC

SIMPLEX ST

ELECTRICAL

SUBASSEMBLIES

OPTICAL

SUBASSEMBLIES RECEPTACLE

TRANSMITTER

DIFFERENTIAL

DATA IN

DRIVER IC

LED

TOP VIEW

THREADS

3/8 – 32 UNEF-2A

HFBR-111X/211XT

DATE CODE (YYWW)

SINGAPORE

12.19

MAX.

8.31

41 MAX.

5.05

0.9

7.01

9.8 MAX.

5.0

2.45

19.72

17.78

(7 x 2.54)

NOTES:

1. MATERIAL ALLOY 194 1/2H – 0.38 THK

FINISH MATTE TIN PLATE 7.6 µm MIN.

2. MATERIAL PHOSPHOR BRONZE WITH

120 MICROINCHES TIN LEAD (90/10)

OVER 50 MICROINCHES NICKEL.

8 x 7.62

3. UNITS = mm

HOUSING PINS 0.38 x 0.5 mm

NOTE 1

PCB PINS

DIA. 0.46 mm

NOTE 2

178

Figure 4 illustrates the predicted

OPB associated with the trans-

mitter and receiver specified in this

data sheet at the Beginning of Life

(BOL). This curve represents the

attenuation and chromatic plus

modal dispersion losses associated

with 62.5/125 µm and 50/125 µm

fiber cables only. The area under

the curve represents the remaining

OPB at any link length, which is

available for overcoming non-fiber

cable related losses.

OPTICAL PORT

NO PIN

GND

NO PIN

GND

DATA

GND

DATA

NO PIN

TRANSMITTER

RECEIVER

62.5/125 µm

The optical subassemblies consist

of a transmitter subassembly in

which the LED resides and a

receiver subassembly housing the

PIN-preamplifier combination.

The Applications Engineering

group of the Optical Communi-

cation Division is available to assist

you with the technical understand-

ing and design tradeoffs associated

with these transmitter and receiver

modules. You can contact them

through your Hewlett-Packard

sales representative.

50/125 µm

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

FIBER OPTIC CABLE LENGTH – km

The electrical subassemblies con-

sist of a multi-layer printed circuit

board on which the IC chips and

various sufrace-mounted, passive

circuit elements are attached.

The following information is

provided to answer some of the

most common questions about the

use of these parts.

Each transmitter and receiver

Hewlett-Packard LED technology

has produced 1300 nm LED

devices with lower aging

characteristics than normally asso-

ciated with these technologies in

the industry. The industry

convention is 1.5 dB aging for

1300 nm LEDs; however, HP 1300

nm LEDs will experience less than

1 dB of aging over normal

commercial equipment mission-life

periods. Contact your Hewlett-

Packard sales representative for

additional details.

package includes an internal shield

for the electrical subassembly to

ensure low EMI emissions and high

immunity to external EMI fields.

The outer housing, including the

ST* port, is molded of filled, non-

conductive plastic to provide

mechanical strength and electrical

isolation. For other port styles,

please contact your Hewlett-

Packard Sales Representative.

The Optical Power Budget (OPB)

is the available optical power for a

fiber-optic link to accommodate

fiber cable losses plus losses due to

in-line connectors, splices, optical

switches, and to provide margin for

link aging and unplanned losses

due to cable plant reconfiguration

or repair.

Each data-link module is attached

to a printed circuit board via the

16-pin DIP interface. Pins 8 and 9

provide mechanical strength for

these plastic-port devices and will

provide port-ground for forthcom-

ing metal-port modules.

Figure 4 was generated with a

Hewlett-Packard fiber-optic link

model containing the current

industry conventions for fiber

179

cable specifications and the FDDI

PMD optical parameters. These

parameters are reflected in the

guaranteed performance of the

transmitter and receiver specifica-

tions in this data sheet. This same

model has been used extensively in

the ANSI and IEEE committees,

including the ANSI X3T9.5

3.0

2.5

The Hewlett-Packard 1300 nm data

link modules are designed to

operate per the system jitter

allocations stated in Table E1 of

Annex E of the FDDI PMD

standard.

2.0

1.5

1.0

0.5

committee, to establish the optical

performance requirements for

various fiber-optic interface

The 1300 nm transmitter will

tolerate the worst-case input

electrical jitter allowed in the table

without violating the worst-case

output jitter requirements of

Section 8.1 Active Output Interface

of the FDDI PMD standard.

25 50 75 100 125 150 175 200

SIGNAL RATE (MBd)

standards. The cable parameters

used come from the ISO/IEC JTC1/

SC 25/WG3 Generic Cabling for

Customer Premises per DIS 11801

document and the EIA/TIA-568-A

Commercial Building Telecom-

munications Cabling Standard per

SP-2840.

CONDITIONS:

1. PRBS 2 -1

2. DATA SAMPLED AT CENTER OF DATA SYMBOL.

3. BER = 10

-6

4. T = 25° C

5. V

= 5 Vdc

6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

The 1300 nm receiver will tolerate

the worst-case input optical jitter

allowed in Section 8.2 Active Input

Interface of the FDDI PMD

standard without violating the

worst-case output electrical jitter

allowed in the Table E1 of the

Annex E.

These data link modules can also

be used for applications which

require different bit-error-ratio

(BER) performance. Figure 6

illustrates the typical trade-off

between link BER and the receiver

input optical power level.

For purposes of definition, the

symbol rate (Baud), also called

signaling rate, is the reciprocal of

the symbol time. Data rate (bits/

sec) is the symbol rate divided by

the encoding factor used to encode

the data (symbols/bit).

The jitter specifications stated in

the following transmitter and

receiver specification table are

derived from the values in Table

E1 of Annex E. They represent the

worst-case jitter contribution that

the transmitter and receiver are

allowed to make to the overall

system jitter without violating the

Annex E allocation example. In

practice, the typical jitter

When used in FDDI, ATM 100

Mbps, and Fast Ethernet

-2

1 x 10

applications, the performance of

Hewlett-Packard’s 1300 nm HFBR-

1115/-2115 data link modules is

guaranteed over the signaling rate

of 10 MBd to 125 MBd to the full

conditions listed in the individual

product specification tables.

-3

1 x 10

CENTER OF

SYMBOL

-4

1 x 10

-5

1 x 10

contribution of the Hewlett-

Packard data link modules is well

below the maximum amounts.

-6

1 x 10

-7

1 x 10

-8

-10

2.5 x 10

1 x 10

-11

-12

The data link modules can be used

for other applications at signaling

rates outside of the 10 MBd to 125

MBd range with some penalty in

the link optical power budget

primarily caused by a reduction of

receiver sensitivity. Figure 5 gives

an indication of the typical

-6

-4

-2

It is advised that normal static

precautions be taken in the

handling and assembly of these

data link modules to prevent

damage which may be induced by

electrostatic discharge (ESD). The

HFBR-1115/-2115 series meets

MIL-STD-883C Method 3015.4

Class 2.

RELATIVE INPUT OPTICAL POWER – dB

CONDITIONS:

1. 125 MBd

2. PRBS 2 -1

3. T = 25° C

4. V

= 5 Vdc

5. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

performance of these 1300 nm

products at different rates.

180

These data link modules are

compatible with either industry

standard wave- or hand-solder

processes.

Care should be taken to avoid

shorting the receiver Data or

Signal Detect Outputs directly to

ground without proper current-

limiting impedance.

It is important to take care in the

layout of your circuit board to

achieve optimum performance

from these data link modules.

Figure 7 provides a good example

of a power supply filter circuit that

works well with these parts. Also,

suggested signal terminations for

the Data, Data-bar, Signal Detect

and Signal Detect-bar lines are

shown. Use of a multilayer,

The data link modules are

packaged in a shipping container

designed to protect it from

mechanical and ESD damage

during shipment or storage.

The transmitter and receiver are

delivered with protective process

caps covering the individual ST*

ports. These process caps protect

the optical subassemblies during

wave solder and aqueous wash

processing and act as dust covers

during shipping.

ground-plane printed circuit board

will provide good high-frequency

GND

10 GND

11 GND

12 GND

13 GND

14 SD

GND

+5 Vdc

GND

0.1

(OPTIONAL)

13 GND

DATA

15 SD

16 NC

130 130

82 130 130

0.1

R11

TERMINATE D, D

AT Tx INPUTS

R10

130

R12

130

TOP VIEWS

TERMINATE D, D, SD, SD AT

INPUTS OF FOLLOW-ON DEVICES

NOTES:

1. RESISTANCE IS IN OHMS. CAPACITANCE IS IN MICROFARADS. INDUCTANCE IS IN MICROHENRIES.

2. TERMINATE TRANSMITTER INPUT DATA AND DATA-BAR AT THE TRANSMITTER INPUT PINS. TERMINATE THE RECEIVER OUTPUT DATA, DATA-BAR, AND SIGNAL DETECT-

BAR AT THE FOLLOW-ON DEVICE INPUT PINS. FOR LOWER POWER DISSIPATION IN THE SIGNAL DETECT TERMINATION CIRCUITRY WITH SMALL COMPROMISE TO THE

SIGNAL QUALITY, EACH SIGNAL DETECT OUTPUT CAN BE LOADED WITH 510 OHMS TO GROUND INSTEAD OF THE TWO RESISTOR, SPLIT-LOAD PECL TERMINATION

SHOWN IN THIS SCHEMATIC.

3. MAKE DIFFERENTIAL SIGNAL PATHS SHORT AND OF SAME LENGTH WITH EQUAL TERMINATION IMPEDANCE.

4. SIGNAL TRACES SHOULD BE 50 OHMS MICROSTRIP OR STRIPLINE TRANSMISSION LINES. USE MULTILAYER, GROUND-PLANE PRINTED CIRCUIT BOARD FOR BEST HIGH-

FREQUENCY PERFORMANCE.

5. USE HIGH-FREQUENCY, MONOLITHIC CERAMIC BYPASS CAPACITORS AND LOW SERIES DC RESISTANCE INDUCTORS. RECOMMEND USE OF SURFACE-MOUNT COIL

INDUCTORS AND CAPACITORS. IN LOW NOISE POWER SUPPLY SYSTEMS, FERRITE BEAD INDUCTORS CAN BE SUBSTITUTED FOR COIL INDUCTORS. LOCATE POWER

SUPPLY FILTER COMPONENTS CLOSE TO THEIR RESPECTIVE POWER SUPPLY PINS. C7 IS AN OPTIONAL BYPASS CAPACITOR FOR IMPROVED, LOW-FREQUENCY NOISE

POWER SUPPLY FILTER PERFORMANCE.

6. DEVICE GROUND PINS SHOULD BE DIRECTLY AND INDIVIDUALLY CONNECTED TO GROUND.

7. CAUTION: DO NOT DIRECTLY CONNECT THE FIBER-OPTIC MODULE PECL OUTPUTS (DATA, DATA-BAR, SIGNAL DETECT, SIGNAL DETECT-BAR, V ) TO GROUND WITHOUT

PROPER CURRENT LIMITING IMPEDANCE.

8. (*) OPTIONAL METAL ST OPTICAL PORT TRANSMITTER AND RECEIVER MODULES WILL HAVE PINS 8 AND 9 ELECTRICALLY CONNECTED TO THE METAL PORT ONLY AND

NOT CONNECTED TO THE INTERNAL SIGNAL GROUND.

181

circuit performance with a low

inductance ground return path. See

additional recommendations noted

in the interface schematic shown in

Figure 7.

into effect on January 1, 1997. AEL

Class 1 LED devices are consid-

ered eye safe. See Application Note

1094, LED Device Classifications

with Respect to AEL Values as

Defined in the IEC 825-1

These data link modules are

intended to enable commercial

system designers to develop

equipment that complies with the

various international regulations

governing certification of Infor-

mation Technology Equipment.

Additional information is available

from your Hewlett-Packard sales

representative.

Standard and the European

EN60825-1 Directive.

The Hewlett-Packard transmitter

and receiver hole pattern is

The material used for the housing

in the HFBR-1115/-2115 series is

Ultem 2100 (GE). Ultem 2100 is

recognized for a UL flammability

rating of 94V-0 (UL File Number

E121562) and the CSA (Canadian

Standards Association) equivalent

(File Number LS88480).

compatible with other data link

modules from other vendors. The

drawing shown in Figure 8 can be

used as a guide in the mechanical

layout of your circuit board.

All HFBR-1115T LED transmitters

are classified as IEC-825-1

Accessible Emission Limit (AEL)

Class 1 based upon the current

proposed draft scheduled to go

0.8 ± 0.1

(16X)

–A–

.032 ± .004

Ø 0.000 M

17.78

.700

2.54

.100

(7X)

7.62

.300

TOP VIEW

UNITS = mm/INCH

182

200

180

160

140

120

100

4.40

1.975

1.25

3.0

4.850

1.5

1.525

0.525

10.0

5.6

1.025

1.00

2.0

2.5

3.5

0.075

0.975

0.90

– TRANSMITTER

OUTPUT OPTICAL

RISE/FALL TIMES – ns

r/f

100% TIME

INTERVAL

3.0

3.5

40 ± 0.7

1280 1300 1320 1340 1360 1380

0.50

0.10

± 0.725

– TRANSMITTER OUTPUT OPTICAL

CENTER WAVELENGTH –nm

HFBR-1115T FDDI TRANSMITTER TEST RESULTS

OF λ , ∆λ AND t ARE CORRELATED AND

0% TIME

INTERVAL

r/f

COMPLY WITH THE ALLOWED SPECTRAL WIDTH

AS A FUNCTION OF CENTER WAVELENGTH FOR

VARIOUS RISE AND FALL TIMES.

0.025

0.0

0.075

-0.025

-0.05

1.525

0.525

4.850

5.6

1.975

4.40

10.0

80 ± 500 ppm

TIME – ns

THE HFBR-1115T OUTPUT OPTICAL PULSE SHAPE FITS WITHIN THE BOUNDARIES

OF THE PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS.

-31.0 dBm

MIN (P + 4.0 dB OR -31.0 dBm)

(P + 1.5 dB

< P < -31.0 dBm)

= MAX (P OR -45.0 dBm)

(P = INPUT POWER FOR BER < 10 )

-10

2.5 x 10 BER

INPUT OPTICAL POWER

4.0 dB STEP DECREASE)

(

1.5 dB STEP INCREASE)

(

-12

1.0 x 10 BER

-45.0 dBm

ANS MAX

–

AS MAX

–

SIGNAL DETECT (ON)

–

-4 -3 -2 -1

SIGNAL DETECT (OFF)

–

EYE SAMPLING TIME POSITION (ns)

CONDITIONS:

1.T = 25° C

TIME

AS MAX — MAXIMUM ACQUISITION TIME (SIGNAL).

2. V

= 5 Vdc

3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

4. INPUT OPTICAL POWER IS NORMALIZED TO

CENTER OF DATA SYMBOL.

–

AS MAX IS THE MAXIMUM SIGNAL DETECT ASSERTION TIME FOR THE STATION.

–

AS MAX SHALL NOT EXCEED 100.0 µs. THE DEFAULT VALUE OF AS MAX IS 100.0 µs.

–

5. NOTE 21 AND 22 APPLY.

ANS MAX — MAXIMUM ACQUISITION TIME (NO SIGNAL).

–

ANS MAX IS THE MAXIMUM SIGNAL DETECT DEASSERTION TIME FOR THE STATION.

–

ANS MAX SHALL NOT EXCEED 350 µs. THE DEFAULT VALUE OF AS MAX IS 350 µs.

–

183

No internal connect, used for mechanical strength only

V Bias output

GND

OMIT

Ground

Note 3

No pin

No internal connect, used for mechanical strength only

Ground

Common supply voltage

Ground

Data input

Inverted Data input

Note 5

Note 3

Note 1

Note 3

Note 4

GND

DATA

No internal connect, used for mechanical strength only

DATA

No internal connect, used for mechanical strength only

Inverted Data input

Data input

Common supply voltage

Ground

Note 4

Note 1

Note 3

Note 5

GND

No internal connect, used for mechanical strength only

OMIT

GND

No pin

Ground

Signal Detect

Inverted Signal Detect

No pin

Note 3

Note 2, 4

OMIT

1. Voltages on V must be from the same power supply (they are connected together internally).

2. Signal Detect is a logic signal that indicates the presence or absence of an input optical signal. A logic-high, V , on Signal Detect

indicates presence of an input optical signal. A logic-low, V , on Signal Detect indicates an absence of input optical signal.

3. All GNDs are connected together internally and to the internal shield.

4. DATA, DATA, SD, SD are open-emitter output circuits.

5. On metal-port modules, these pins are redefined as “Port Connection.”

184

Storage Temperature

Lead Soldering Temperature

Lead Soldering Time

Supply Voltage

-40

100

260

7.0

°C

sec.

SOLD

-0.5

Data Input Voltage

Differential Input Voltage

Output Current

1.4

Note 1

Ambient Operating Temperature

Supply Voltage

4.5

5.5

°C

Data Input Voltage–Low

Data Input Voltage–High

Data and Signal Detect Output Load

Signaling Rate

V - V

-1.810

-1.165

-1.475

-0.880

Ω

- V

125

Note 2

Note 3

MBd

Figure 5

(T = 0°C to 70°C, V = 4.5 V to 5.5 V)

Supply Current

Power Dissipation

Threshold Voltage

Data Input Current–Low

Data Input Current–High

145

0.76

-1.3

185

1.1

-1.24

µA

Note 4

Note 7

Note 5

DISS

- V

-1.42

-350

350

(T = 0°C to 70°C, V = 4.5 V to 5.5 V)

Supply Current

Power Dissipation

Data Output Voltage–Low

Data Output Voltage–High

Data Output Rise Time

Data Output Fall Time

0.3

145

0.5

-1.620

-0.880

2.2

Note 6

Note 7

Note 8

Note 9

Note 8

DISS

- V

-1.840

-1.045

0.35

-1.840

2.2

-1.620

Signal Detect Output

- V

Voltage–Low (De-asserted)

Signal Detect Output

- V

-1.045

-0.880

Note 8

Voltage–High (Asserted)

Signal Detect Output Rise Time

Signal Detect Output Fall Time

0.35

2.2

Note 9

185

(T = 0°C to 70°C, V = 4.5 V to 5.5 V)

Output Optical Power

62.5/125 µm, NA = 0.275 Fiber

Output Optical Power

50/125 µm, NA = 0.20 Fiber

Optical Extinction Ratio

Output Optical Power at Logic “0” State

Center Wavelength

P , BOL

-19

-20

-22.5

-23.5

-16.8

-20.3

-14

0.03

-35

-45

1380

170

3.0

dBm

avg.

dBm

avg.

dBm

avg.

Note 13

Note 14

Note 15

P , EOL

P , BOL

P , EOL

0.001

-50

P (“0”)

1270

1308

137

1.0

Note 16

Figure 9

Note 16

Figure 9

Note 16, 17

Figure 9, 10

Note 16, 17

Figure 9, 10

Spectral Width–FWHM

Optical Rise Time

∆λ

0.6

Optical Fall Time

2.1

3.0

Duty Cycle Distortion Contributed by

the Transmitter

Data Dependent Jitter Contributed by

the Transmitter

Random Jitter Contributed by the

Transmitter

DCD

DDJ

0.02

0.6

ns p-p

Note 18

Figure 10

Note 19

Note 20

0.6

0.69

(T = 0°C to 70°C, V = 4.5 V to 5.5 V)

Input Optical Power

Minimum at Window Edge

(W)

-33.5

-34.5

-11.8

-31

dBm

avg.

Note 21,

Figure 11

IN Min.

Input Optical Power

Minimum at Eye Center

(C)

-31.8

dBm

avg.

Note 22,

Figure 8

IN Min.

Input Optical Power Maximum

Operating Wavelength

-14

1270

dBm

avg.

Note 21

IN Max.

1380

0.4

Duty Cycle Distortion

Contributed by the Receiver

DCD

0.02

0.35

1.0

ns p-p

Note 10

Note 11

Note 12

Data Dependent Jitter

Contributed by the Receiver

DDJ

1.0

2.14

-33

ns p-p

Random Jitter Contributed by the

Receiver

Signal Detect–Asserted

Signal Detect–De-asserted

Signal Detect–Hysteresis

P +1.5 dB

dBm

avg.

Note 23, 24

Figure 9

-45

dBm

avg.

Note 25, 26

Figure 12

P -P

1.5

2.4

Figure 9

Signal Detect Assert Time

(off to on)

AS_Max

100

350

µs

Note 23, 24

Figure 12

Signal Detect De-assert Time

(on to off)

ANS_Max

110

µs

Note 25, 26

Figure 12

186

level is -20 dBm average. See

Application Information–Data Link

Jitter Section for further information.

11. Data Dependent Jitter contributed by

the receiver is specified with the

FDDI DDJ test pattern described in

the FDDI PMD Annex A.5. The input

optical power level is -20 dBm

decibels.

1. This is the maximum voltage that can

be applied across the Differential

Transmitter Data Inputs to prevent

damage to the input ESD protection

circuit.

15. The transmitter provides compliance

with the need for Transmit_Disable

commands from the FDDI SMT layer

by providing an Output Optical

Power level of <-45 dBm average in

response to a logic “0” input. This

specification applies to either 62.5/

125 µm or 50/125 µm fiber cables.

16. This parameter complies with the

FDDI PMD requirements for the

tradeoffs between center wavelength,

spectral width, and rise/fall times

shown in Figure 9.

17. This parameter complies with the

optical pulse envelope from the FDDI

PMD shown in Figure 10. The optical

rise and fall times are measured from

10% to 90% when the transmitter is

driven by the FDDI HALT Line State

(12.5 MHz square-wave) input signal.

18. Duty Cycle Distortion contributed by

the transmitter is measured at a 50%

threshold using an IDLE Line State,

125 MBd (62.5 MHz square-wave),

input signal. See Application

2. The outputs are terminated with 50 Ω

connected to V - 2 V.

3. The specified signaling rate of

10 MBd to 125 MBd guarantees

operation of the transmitter and

receiver link to the full conditions

listed in the FDDI Physical Layer

Medium Dependent standard.

average. See Application

Information–Data Link Jitter Section

for further information.

12. Random Jitter contributed by the

receiver is specified with an IDLE

Line State, 125 MBd (62.5 MHz

square-wave), input signal. The input

optical power level is at the maxi-

Specifically, the link bit-error-ratio

will be equal to or better than 2.5 x

-10

10 for any valid FDDI pattern. The

mum of “P

(W).” See Applica-

IN Min.

transmitter section of the link is

capable of dc to 125 MBd. The

receiver is internally ac-coupled

which limits the lower signaling rate

to 10 MBd. For purposes of

tion Information–Data Link Jitter

Section for further information.

13. These optical power values are

measured with the following

conditions:

definition, the symbol rate (Baud),

also called signaling rate, fs, is the

reciprocal of the symbol time. Data

rate (bits/sec) is the symbol rate

divided by the encoding factor used

to encode the data (symbols/bit).

4. The power supply current needed to

operate the transmitter is provided to

differential ECL circuitry. This

circuitry maintains a nearly constant

current flow from the power supply.

Constant current operation helps to

prevent unwanted electrical noise

from being generated and conducted

or emitted to neighboring circuitry.

5. This value is measured with an output

• The Beginning of Life (BOL) to the

End of Life (EOL) optical power

degradation is typically 1.5 dB per

the industry convention for long

wavelength LEDs. The actual

degradation observed in Hewlett-

Packard’s 1300 nm LED products

is < 1dB, as specified in this data

sheet.

• Over the specified operating

voltage and temperature ranges.

• With HALT Line State, (12.5 MHz

square-wave), input signal.

• At the end of one meter of noted

optical fiber with cladding modes

removed.

The average power value can be

converted to a peak power value by

adding 3 dB. Higher output optical

power transmitters are available on

special request.

Information–Data Link Jitter Per-

formance Section of this data sheet

for further details.

19. Data Dependent Jitter contributed by

the transmitter is specified with the

FDDI test pattern described in FDDI

PMD Annex A.5. See Application

Information–Data Link Jitter

Performance Section of this data

sheet for further details.

20. Random Jitter contributed by the

transmitter is specified with an IDLE

Line State, 125 MBd (62.5 MHz

square-wave), input signal. See

Application Information–Data Link

Jitter Performance Section of this

data sheet for further details.

21. This specification is intended to

indicate the performance of the

receiver when Input Optical Power

signal characteristics are present per

the following definitions. The Input

Optical Power dynamic range from

the minimum level (with a window

time-width) to the maximum level is

the range over which the receiver is

guaranteed to provide output data

load R = 10 kΩ.

6. This value is measured with the out-

puts terminated into 50 Ω connected

to V - 2 V and an Input Optical

Power level of -14 dBm average.

7. The power dissipation value is the

power dissipated in the transmitter

and receiver itself. Power dissipation

is calculated as the sum of the

products of supply voltage and

currents, minus the sum of the

products of the output voltages and

currents.

14. The Extinction Ratio is a measure of

the modulation depth of the optical

signal. The data “0” output optical

power is compared to the data “1”

peak output optical power and

expressed as a percentage. With the

transmitter driven by a HALT Line

State (12.5 MHz square-wave) signal,

the average optical power is

8. This value is measured with respect to

with the output terminated into

measured. The data “1” peak power is

then calculated by adding 3 dB to the

measured average optical power. The

data “0” output optical power is

found by measuring the optical

power when the transmitter is driven

by a logic “0” input. The extinction

ratio is the ratio of the optical power

at the “0” level compared to the

optical power at the “1” level

expressed as a percentage or in

50 Ω connected to V - 2 V.

with a Bit-Error-Ratio (BER) better

than or equal to 2.5 x 10

-10

9. The output rise and fall times are

measured between 20% and 80%

levels with the output connected to

• At the Beginning of Life (BOL).

• Over the specified operating

voltage and temperature ranges.

• Input symbol pattern is the FDDI

test pattern defined in FDDI PMD

Annex A.5 with 4B/5B NRZI

- 2 V through 50 Ω.

10. Duty Cycle Distortion contributed by

the receiver is measured at the 50%

threshold using an IDLE Line State,

125 MBd (62.5 MHz square-wave),

input signal. The input optical power

encoded data that contains a duty-

cycle base-line wander effect of

187

50 kHz. This sequence causes a near

worst-case condition for inter-

symbol interference.

• Receiver data window time-width is

2.13 ns or greater and centered at

mid-symbol. This worst-case

window time-width is the minimum

allowed eye-opening presented to

the FDDI PHY PM_Data indication

input (PHY input) per the example

in FDDI PMD Annex E. This

minimum window time-width of

2.13 ns is based upon the worst-

case FDDI PMD Active Input

Interface optical conditions for

peak-to-peak DCD (1.0 ns), DDJ

(1.2 ns) and RJ(0.76 ns) presented

to the receiver.

To test a receiver with the worst-case

FDDI PMD Active Input jitter

components through their

superposition (DCD and DDJ are

directly additive and RJ components

are rms additive). Specifically, when

a nearly ideal input optical test signal

is used and the maximum receiver

peak-to-peak jitter contributions of

DCD (0.4 ns), DDJ (1.0 ns), and RJ

(2.14 ns) exist, the minimum window

time-width becomes 8.0 ns - 0.4 ns -

1.0 ns - 2.14 ns = 4.46 ns, or

conservatively 4.6 ns. This wider

window time-width of 4.6 ns

has been asserted. See Figure 12 for

more information.

25. This value is measured during the

transition from high to low levels of

input optical power. The maximum

value will occur when the input

optical power is either -45 dBm

average or when the input optical

-2

power yields a BER of 10 or better,

whichever power is higher.

26. Signal Detect output shall be

deasserted, logic-low (V ), within

350 µs after a step decrease in the

Input Optical power from a level

which is the lower of -31 dBm or P

guarantees the FDDI PMD Annex E

minimum window time-width of 2.13

ns under worst-case input jitter

conditions to the Hewlett-Packard

receiver.

+ 4 dB (P is the power level at

which Signal Detect was de-asserted),

to a power level of -45 dBm or less.

This step decrease will have occurred

in less than 8 ns. The receiver output

22. All conditions of Note 21 apply

except that the measurement is made

at the center of the symbol with no

window time-width.

23. This value is measured during the

transition from low to high levels of

input optical power.

condition requires exacting control

over DCD, DDJ, and RJ jitter

-2

will have a BER of 10 or better for a

period of 12 µs or until signal detect

is de-asserted. The input data stream

is the Quiet Line State. Also, Signal

Detect will be de-asserted within a

maximum of 350 µs after the BER of

the receiver output degrades above

components that is difficult to

implement with production test

equipment. The receiver can be

equivalently tested to the worst-case

FDDI PMD input jitter conditions and

meet the minimum output data

window time-width of 2.13 ns. This is

accomplished by using a nearly ideal

input optical signal (no DCD,

insignificant DDJ and RJ) and

measuring for a wider window time-

width of 4.6 ns. This is possible due

to the cumulative effect of jitter

24. The Signal Detect output shall be

asserted, logic-high (V ), within

100 µs after a step increase of the

Input Optical Power. The step will be

from a low Input Optical Power,

≤ -45 dBm, into the range between

-2

10 for an input optical data stream

that decays with a negative ramp

function instead of a step function.

See Figure 12 for more information.

greater than P , and -14 dBm. The

BER of the receiver output will be

-2

10 or better during the time,

LS_Max (15 µs) after Signal Detect

188

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