IFD-53010 [AGILENT]

Silicon Bipolar MMIC 3.5 and 5.5 GHz Divide-by-4 Static Prescalers; 硅双极MMIC 3.5和5.5 GHz的分频-4中的静态预分频器
IFD-53010
型号: IFD-53010
厂家: AGILENT TECHNOLOGIES, LTD.    AGILENT TECHNOLOGIES, LTD.
描述:

Silicon Bipolar MMIC 3.5 and 5.5 GHz Divide-by-4 Static Prescalers
硅双极MMIC 3.5和5.5 GHz的分频-4中的静态预分频器

预分频器 逻辑集成电路 时钟
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Silicon Bipolar MMIC  
3.5 and 5.5 GHz Divide-by-4  
Static Prescalers  
Technical Data  
IFD-53010  
IFD-53110  
Features  
• Wide Operating Frequency  
Range:  
IFD-53010:0.15to5.5GHz  
IFD-53110:0.15to3.5GHz  
• Low Phase Noise:  
-143dBc/Hz@1kHzOffset  
• Output Power: -5 dBm Typ.  
• Single Supply Voltage  
Vcc = 5 V or Vee = -5 V  
• On-Chip Terminations  
Provide Good Input and  
Output VSWRs  
100 mil Stripline Package Description  
Hewlett-Packard'sIFD-53010and  
IFD-53110 are low phase noise  
silicon bipolar static digital  
frequency dividers using two  
scaled Emitter-Coupled-Logic  
(ECL) master-slave D flip-flops  
and buffer amplifiers. They are  
housed in hermetic high reliability  
surface mount packages suitable  
for commercial, industrial, and  
military applications. Typical  
applications include stabilized or  
digitally controlled local oscil-  
lators for GPS, SATCOM or  
Pin Configuration  
V
3
EE  
• Hermetic Gold-Ceramic  
Surface Mount Package  
military receivers, and frequency  
synthesizers and counters in  
instrumentation systems. The  
IFD-53110 is a lower cost selected  
version of the IFD-53010, and is  
distinguished by a reduced  
2
4
RF INPUT  
RF OUTPUT  
1
V
CC  
operating frequency range.  
The IFD series of frequency  
dividers is fabricated using  
Hewlett-Packard's 18 GHz, ft,  
ISOSAT™-2 silicon bipolar  
process which uses nitride self-  
alignment, submicrometer  
lithography, trench isolation, ion-  
implantation, gold metallization  
and polyimide intermetal  
dielectric and scratch protection  
to achieve excellent device  
uniformity, performance, and  
reliability.  
Functional Block Diagram  
1
V
CC  
C
Q
Q
C
C
Q
RF OUTPUT  
RF INPUT  
4
2
C
Q
3
V
EE  
5965-9115E  
7-151  
Absolute Maximum Ratings  
Symbol  
Vcc - Vee  
Pdiss  
Parameter  
Units  
V
AbsoluteMaximum[1]  
Device Voltage  
8
650  
PowerDissipation[2,3]  
RF Input Power  
mW  
dBm  
°C  
P in  
+15  
T j  
Junction Temperature  
Storage Temperature  
200  
TSTG  
°C  
-65to+200  
ThermalResistance[2]:θjc =107°C/W  
Notes:  
1, Operation of this device above any one of these parameters may cause permanent damage.  
2.Tcase =25°C.  
3. Derate at 9.3 mW/°C for TC 130°C.  
GuaranteedElectricalSpecifications,IFD-53010andIFD-53110  
TA =25°C, ZO =50, Vcc -Vee =5.0V  
Symbol  
Parameters and Test Conditions  
IFD-53010:  
Units  
Min. Typ. Max.  
FMAX  
Maximum Clock Frequency  
Pin =-10dBm(200mVpp)  
GHz  
5.5  
6.0  
IFD-53110:  
FMAX  
ICC  
Maximum Clock Frequency  
Pin =-10dBm(200mVpp)  
GHz  
mA  
3.5  
35  
5.0  
43  
IFD-53010andIFD-53110: SupplyCurrent  
50  
Typical Design Information, TA = 25°C, Z0 = 50, Vcc- Vee = 5.0 V, Pin = -10 dBm.  
All values apply to both IFD-53010 and IFD-53110. ftest is 5 GHz for IFD-53010 and 3 GHz for IFD-53110 (unless  
otherwise noted).  
Symbol  
F MIN  
Pin  
Parameters and Test Conditions  
Minimum Clock Frequency[1]  
Units  
Value  
MHz  
150  
Input Sensitivity  
f=ftest  
dBm  
mVpp  
-22  
50  
Pout  
VSWR  
PN  
Output Power  
f=0.15toftest  
dBm  
mVpp  
-5  
355  
Input VSWR  
Output VSWR  
f=0.15toftest  
f=0.15toftest  
2.0:1  
2.5:1  
SSB Phase Noise  
f = 3 GHz, 1 kHz offset dBc/Hz  
f=5GHz, 1kHzoffset(IFD-53010only)  
-143  
-138  
Tr  
Tf  
OutputRiseTime,20%-80%  
OutputFallTime,20%-80%  
f=ftest  
f=ftest  
psec  
psec  
145  
85  
Note:  
1. Minimum clock frequency when driven from a sinusoidal input. Operation to lower frequencies is possible when using input signals  
with faster rise times, such as occurs in the case of a cascade of two or more IFDs.  
7-152  
Typical Performance, TA = 25°C, ZO = 50 , Vcc - Vee = 5.0 V  
Graphs apply to both IFD-53010 and IFD-53110 (unless otherwise noted).  
0
0
0
IFD-53010 &  
IFD-53110  
IFD-53010 &  
IFD-53110  
IFD-53010  
-10  
-10  
-10  
IFD-53010  
-20  
-30  
-20  
-30  
-20  
-30  
-40  
-50  
-40  
-50  
-40  
-50  
-55°C  
25°C  
125°C  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
FREQUENCY (GHz)  
FREQUENCY (GHz)  
FREQUENCY (GHz)  
Figure 1. Input Sensitivity vs. Input  
Frequency and Recommended  
Operating Ranges for Nominal  
Figure 2. Input Sensitivity vs. Input  
Frequency and Recommended  
Operating Ranges for Worst Case  
Operating Conditions (-55°C < T <  
125°C and 4.5 V < Vcc - Vee < 5.5 V.  
Figure 3. Input Sensitivity vs. Input  
Frequency and Temperature  
(Vcc - Vee = 5 V).  
Operating Conditions (T = 25°C , Vcc  
-
Vee = 5 V).  
2
70  
60  
3:1  
0
+ 125°C  
50  
5.5 V  
+ 25°C  
-2  
40  
5.0 V  
OUTPUT  
2:1  
30  
-4  
4.5 V  
20  
INPUT  
- 55°C  
-6  
-8  
10  
0
1:1  
10  
10  
100  
1000  
10000  
0
1
2
3
4
5
6
100  
1000  
10000  
FREQUENCY (MHz)  
V
-V  
FREQUENCY (MHz)  
(V)  
CC EE  
Figure 6. Output Power Level vs. Input  
Figure 5. Input and Output VSWR vs.  
Frequency.  
Figure 4. Device Current vs. Voltage  
and Temperature.  
Frequency and Vcc - Vee  
.
-
60  
80  
+100  
+200  
V
in  
-
-100  
-120  
0
0
5 GHz (IFD-53010)  
-140  
-160  
2 TO 4 GHz  
(IFD-53010 & IFD-53110)  
V
out  
-200  
-100  
200  
1
1kHz  
1MHz  
TIME (psec)  
OFFSET FREQUENCY  
Figure 7. SSB Phase Noise vs. Offset  
Frequency, and Input Frequency.  
Figure 8. IFD-53010 Typical Output Response with 5 GHz Input.  
7-153  
BLOCKING CAPACITORS ARE 1000 pF TYP.  
BYPASS CAPACITORS ARE 47 nF min.  
BLOCKING CAPACITORS MAY BE OMITTED  
IF GENERATOR AND LOAD ARE AT V  
LEVEL.  
CC  
TRANSMISSION LINES ARE 50  
.
V
= -5.0 V  
EE  
3
C
BY  
(47 nF min.)  
C
C
BL  
BL  
2
4
F
F/4  
RF OUTPUT  
(50  
RF INPUT  
(50  
)
)
SWINGS BETWEEN V  
CC  
V
CC  
AND V  
-360 mV  
CC  
PIN:  
1
V
= 0 V  
CC  
Figure 9. Typical ECL Biasing Configuration, IFD-53010 and IFD-53110.  
BLOCKING CAPACITORS ARE 1000 pF TYP.  
BYPASS CAPACITOR SHOULD BE 47 nF min.  
TO ENSURE GOOD SENSITIVITY PERFORMANCE.  
TRANSMISSION LINES ARE 50  
.
V
= 0 V  
EE  
PIN:  
3
C
C
BL  
BL  
2
4
F
F/4  
RF OUTPUT  
(50  
RF INPUT  
(50  
)
)
1
V
= 5.0 V  
CC  
C
BY  
(47 nF min.)  
Figure 10. Typical RF Biasing Configuration, IFD-53010 and IFD-53110.  
LO OUTPUT  
PROGRAMMABLE  
DIV. BY 4  
DIVIDER  
VCO  
PHASE DETECTOR  
LPF  
AFC  
STABLE REFERENCE  
Figure 11. Typical Stabilized LO Configuration, IFD-53010 and IFD-53110.  
7-154  
TEST SYSTEM  
= 50  
Z
PIN: 3  
O
V
= -5.0 V  
EE  
10 dB  
10 dB  
SPECTRUM  
ANALYZER  
2
4
P
Z
= 50  
in  
OUT  
f/4  
GENERATOR OUTPUT:  
FREQUENCY = f  
1
LEVEL = P + 10 dB (INTO 50 LOAD)  
in  
V
= 0 V  
CC  
Figure 12. Sensitivity Test Configuration, IFD-53010 and IFD-53110.  
Package Dimensions  
100 mil Stripline Package  
1.02  
(0.040)  
4
0.51  
(0.20)  
1
3
NOTES: (unless otherwise specified)  
1. DIMENSIONS ARE IN mm (INCHES)  
2. TOLERANCES: in .xxx = ± .005  
mm .xx = ± .13  
2
0.76  
0.10 ± 0.05  
(0.004 ± 0.002)  
(0.030)  
2.54  
(0.100)  
12.57 ± 0.76  
(0.495 ± 0.030)  
O
5
7-155  

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