A24C1024 [AITSEMI]
TWO-WIRE SERIAL EEPROM;
| 型号： | A24C1024 |
| 厂家： | 
AiT Semiconductor |
| 描述： | TWO-WIRE SERIAL EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总17页 (文件大小：593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
DESCRIPTION
FEATURES
The A24C1024 are EEPROM devices that use the
industrial standard 2-wire interface for communications.
Two-Wire Serial Interface, I2CTM Compatible
– Bi-directional data transfer protocol
Wide-voltage Operation – VCC = 1.7V to 5.5V
Speed: 400 KHz (1.7V) and 1 MHz (2.5V~5.5V)
Standby current (max.): 1μA, 1.7V
Read operating current (max.): 1mA, 1.7V
Write operating current (max.): 3mA, 1.7V
Hardware Data Protection
The A24C1024 contains
a
memory array of
1024K-bits(131.072x8), which is organized in
256-byte per page.
The EEPROM can operate in a wide voltage range
from 1.7V to 5.5V which fits most application. This
product can provide a low-power 2-wire EEPROM
solution.
The A24C1024 is compatible with the industrial
standard 2-wire bus protocol. If in case the bus is not
responded, a new sent Op-code command will reset
the bus and the device will respond correctly. The
simple bus consists of the Serial Clock wire (SCL)
and the Serial Data wire (SDA).
– Write Protect Pin
Sequential & Random Read Features
Memory organization: 131,072 x 8 bits
Page Size: 256 bytes
Page write mode
Utilizing such bus protocol, a Master device, such as
a microcontroller, can usually control one or more
Slave devices, alike this A24C1024. The bit stream
over the SDA line includes a series of bytes, which
identifies a particular Slave device, an instruction, an
address within that Slave device, and a series of
data, if appropriate. The A24C1024 also has a Write
Protect pin (WP) to allow blocking any write
operations over specified memory area.
– Up to 256 bytes per page write
Self timed write cycle with auto clear: 5ms (max.)
Filtered inputs for noise suppression
High-reliability
– Endurance: 1 Million cycles
– Data retention: 100 years
Industrial temperature grades
Available in SOP8 and TSSOP8 Packages
Under no circumstance, the device will be hung up. In
order to refrain the state machine entering into a
wrong state during power-up sequence or a power
toggle off-on condition, a power on reset circuit is
embedded. During power-up, the device does not
respond to any instructions until the supply voltage
(VCC) has reached an acceptable stable level above
the reset threshold voltage. Once VCC passes the
power on reset threshold, the device is reset and
enters into the Standby mode. This would also avoid
any inadvertent Write operations during power-up
stage.
During power-down process, the device will enter into
standby mode, once VCC drops below the power on
reset threshold voltage. In addition, the device will be
in standby mode after receiving the Stop command,
provided that no internal write operation is in
progress. Nevertheless, it is illegal to send a
command unless the VCC is within its operating level.
ORDERING INFORMATION
Package Type
SOP8
Part Number
A24C1024M8R
M8
A24C1024M8VR
A24C1024TMX8R
A24C1024TMX8VR
TSSOP8
Note
TMX8
V: Halogen free Package
R: Tape & Reel
AiT provides all RoHS products
Suffix “ V “ means Halogen free Package
The A24C1024 is available in SOP8 and TSSOP8
packages.
REV1.0
- JUN 2014 RELEASED -
- 1 -
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
PIN DESCRIPTION
Top View
Symbol
Top View
Function
Pin #
I/O
1
2
3
4
5
6
7
8
NC
A1
-
Not connected
I
Device Address Input
Device Address Input
Ground
A2
I
GND
SDA
SCL
WP
VCC
-
I/O
Serial Address and Data input and Data out put
Serial Clock Input
I
I
-
Write Protect Input
Power Supply
Pin Descriptions
SCL
This input clock pin is used to synchronize the data transfer to and from the device.
SDA
The SDA is a bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is
an open drain output and can be wired with other open drain or open collector outputs. However, the SDA pin
requires a pull-up resistor connected to the power supply.
A1, A2
The A1 and A2 are the device address inputs.
Typically, the A1, and A2 pins are for hardware addressing and a total of 4 devices can be connected on a
single bus system. When A1 and A2 are left floating, the inputs are defaulted to zero.
WP
WP is the Write Protect pin. While the WP pin is connected to the power supply of A24C1024, the entire array
becomes Write Protected (i.e. the device becomes Read only). When WP is tied to Ground or left floating, the
normal write operations are allowed.
VCC
Supply voltage
GND
Ground of supply voltage
REV1.0
- JUN 2014 RELEASED -
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
ABSOLUTE MAXIMUM RATINGS
VS, Supply Voltage
-0.5V ~ +6.5V
–0.5V ~ VCC+0.5V
–55°C ~ +125°C
–65°C ~ +150°C
5mA
VP, Voltage on Any Pin
TBIAS, Temperature Under Bias
TSTG, Storage Temperature
IOUT, Output Current
Stress beyond above listed “Absolute Maximum Ratings” may lead permanent damage to the device. These are stress ratings only and
operations of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGE
Range
Ambient Temperature (TA)
VCC
Industrial
–40°C to +85°C
1.7V to 5.5V
NOTE: Industrial grade for Commercial applications (0°C to +70°C).
CAPACITANCE
Symbol
CIN
Parameter NOTE1,2
Input Capacitance
Conditions
VIN = 0V
Max.
Unit
6
8
pF
pF
CI/O
Input / Output Capacitance
VI/O = 0V
NOTE1: Tested initially and after any design or process changes that may affect these parameters and not 100% tested.
NOTE2: Test conditions: TA = 25°C, f = 1MHz, VCC = 5.0V.
REV1.0
- JUN 2014 RELEASED -
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
DC ELECTRICAL CHARACTERISTIC
Industrial: TA = –40°C to +85°C, VCC = 1.7V ~ 5.5V
Parameter
Supply Voltage
Symbol
VCC
VIH
VCC
Conditions
Min.
1.7
Max.
Unit
V
5.5
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output Low Voltage
Standby Current
0.7*VCC
-1
VCC+1
V
VIL
0.3* VCC
V
ILI
5V
VIN = VCC max
2
2
μA
μA
V
ILO
5V
VOL1
VOL2
ISB1
ISB2
ISB3
1.7V
3V
IOL = 0.15mA
0.2
0.4
1
IOL = 2.1mA
V
1.7V
2.5V
5V
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
Read at 400 KHz
Read at 1 MHz
Read at 1 MHz
Write at 400 KHz
Write at 1 MHz
Write at 1 MHz
μA
μA
μA
Standby Current
2
Standby Current
3
1.7V
2.5V
5.5V
1.7V
2.5V
5.5V
0.5
1
Read Current
Write Current
ICC1
mA
mA
1
2
ICC2
3
3
NOTE: The parameters are characterized but not 100% tested.
REV1.0
- JUN 2014 RELEASED -
- 4 -
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
AC ELECTRICAL CHARACTERISTIC
Industrial: TA = –40°C to +85°C, VCC = 1.7V to 5.5V
1.7V≤VCC<2.5V 2.5V≤VCC<4.5V 4.5V≤VCC≤5.5V
ParameterNOTE3,4
Symbol
Unit
Min.
Max.
400
Min.
Max.
1000
Min.
Max.
1000
SCK Clock Frequency
Clock Low Period
FSCL
TLOW
KHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
1200
600
400
400
400
400
Clock High Period
THIGH
TR
Rise Time (SCL and SDA)
Fall Time (SCL and SDA)
Start Condition Setup Time
Stop Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
300
300
300
100
300
100
TF
TSU:STA
TSU:STO
THD:STA
TSU:DAT
THD:DAT
600
600
600
100
0
200
200
200
40
200
200
200
40
0
0
Clock to Output Access
time (SCL Low to SDA Data
Out Valid)
TAA
100
100
900
50
50
400
50
50
400
ns
ns
Data Out Hold Time (SCL
Low to SDA Data Out
Change)
TDH
Write Cycle Time
TWR
5
5
5
ms
ns
Bus Free Time Before New
Transmission
TBUF
1000
400
400
WP pin Setup Time
WP pin Hold Time
TSU:WP
THD:WP
T
600
400
400
ns
ns
ns
1200
1200
1200
Noise Suppression Time
100
50
50
NOTE3: The parameters are characterized but not 100% tested.
NOTE4: AC measurement conditions:
RL (connects to VCC): 1.3kΩ (2.5V, 5.0V), 10kΩ (1.7V)
CL = 100 pF
Input pulse voltages: 0.3*VCC to 0.7*VCC
Input rise and fall times: ≤ 50 ns
Timing reference voltages: half VCC level
REV1.0
- JUN 2014 RELEASED -
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
BLOCK DIAGRAM
REV1.0
- JUN 2014 RELEASED -
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
DETAILED INFORMATION
Device Operation
The A24C1024 serial interface supports communications using industrial standard 2-wire bus protocol, such
as I2C.
2-WIRE Bus
The two-wire bus is defined as Serial Data (SDA), and Serial Clock (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers. The bus is
controlled by Master device that generates the SCL, controls the bus access, and generates the Start and
Stop conditions. The A24C1024 is the Slave device.
The Bus Protocol
Data transfer may be initiated only when the bus is not busy. During a data transfer, the SDA line must remain
stable whenever the SCL line is high. Any changes in the SDA line while the SCL line is high will be
interpreted as a Start or Stop condition.
The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the
duration of the High period of the clock signal. The data on the SDA line may be changed during the Low
period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start
condition and terminated by a Stop condition.
Start Condition
The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA
when SCL is high. The EEPROM monitors the SDA and SCL lines and will not respond until the Start
condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition of SDA when SCL is high. All operations must end
with a Stop condition.
Acknowledge
After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging
device pulls down the SDA line.
REV1.0
- JUN 2014 RELEASED -
- 7 -
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
Reset
The A24C1024 contains a reset function in case the 2-wire bus transmission on is accidentally interrupted
(e.g. a power loss), or needs to be terminated mid-stream. The reset is initiated when the Master device
creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while
cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level
on SDA.)
Standby Mode
While in standby mode, the power consumption is minimal. The A24C1024 enters into standby mode during
one of the following conditions: a) After Power-up, while no Op-code is sent; b) After the completion of an
operation and followed by the Stop signal, provided that the previous operation is not Write related; or c) After
the completion of any internal write operations.
Device Addressing
The Master begins a transmission on by sending a Start condition then sends the address of the particular
Slave devices to be communicated. The Slave device address is 8 bits format as shown in Figure.1-5.
The four most significant bits of the Slave address are fixed (1010) for A24C1024.
The next two bits, A1 and A2, of the Slave address are specifically related to EEPROM. Up to four A24C1024
units can be connected to the 2-wire bus.
The seventh bit is the memory page address A [16].
The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit
is set to 1, Read operation is selected. While it is set to 0, Write operation is selected.
After the Master transmits the Start condition and Slave address byte appropriately, the associated 2-wire
Slave device, A24C1024, will respond with ACK on the SDA line. Then A24C1024 will pull down the SDA on
the ninth clock cycle, signaling that it received the eight bits of data.
The A24C1024 then prepares for a Read or Write operation by monitoring the bus.
Write Operation
Access each data in the memory requires a 17-bit address. (The Most significant bit A [16] is in the device
address and the Least Significant Bits A [15]-A [0] are defined in two address bytes). The most significant
word address followed by the least significant word address.
Byte Write
In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with
the R/W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends the byte
REV1.0
- JUN 2014 RELEASED -
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
address that is to be written into the address pointer of the A24C1024. After receiving another ACK from the
Slave, the Master device transmits the data byte to be written into the address memory location. The
A24C1024 acknowledges once more and the Master generates the Stop condition, at which time the device
begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to
any request from the Master device.
Page Write
The A24C1024 is capable of 256-byte Page-Write operation. A Page-Write is initiated in the same manner as
a Byte Write, but instead of terminating the internal Write cycle after the first data byte is transferred, the
Master device can transmit up to 255 more bytes. After the receipt of each data byte, the EEPROM responds
immediately with an ACK on SDA line, and the eight lower order data byte address bits are internally
incremented by one, while the higher order bits of the data byte address remain constant. If a byte address is
incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should
transmit more than 256 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 256 bytes are received and the Stop condition has been
sent by the Master, the internal programming cycle begins. At this point, all received data is written to the
A24C1024 in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of the typical Write cycle time. Once the Stop
condition is issued to indicate the end of the host's Write operation, the A24C1024 initiates the internal Write
cycle. ACK polling can be initiated immediately. This involves issuing the Start condition followed by the Slave
address for a Write operation. If the EEPROM is still busy with the Write operation, no ACK will be returned. If
the A24C1024 has completed the Write operation, an ACK will be returned and the host can then proceed
with the next Read or Write operation.
Read Operation
Read operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave
address is set to “1”. There are three Read operation options: current address read, random address read and
sequential read.
Current Address Read
The A24C1024 contains an internal address counter which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation is either a Read or Write operation addressed to
the address location n, the internal address counter would increment to address location n+1. When the
REV1.0
- JUN 2014 RELEASED -
- 9 -
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an
ACK and transmit the 8-bit data byte stored at address location n+1. The Master should not acknowledge the
transfer but should generate a Stop condition so the A24C1024 discontinues transmission. If 'n' is the last
byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 1-8. Current Address Read
Diagram.)
Random Address Read
Selective Read operations allow the Master device to select at random any memory location for a Read
operation. The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read. After the A24C1024 acknowledges the byte
address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to
one. The EEPROM then responds with its ACK and sends the data requested. Then Master device does not
send an ACK but will generate a Stop condition. (Refer to Figure 1-9. Random Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current Address Read or Random Address Read. After the
A24C1024 sends the initial byte sequence, the Master device now responds with an ACK indicating it requires
additional data from the A24C1024. The EEPROM continues to output data for each ACK received. The
Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data
byte to be read, followed by a Stop condition. The data output is sequential, with the data from address n
followed by the data from address n+1,n+2 ... etc.. The address counter increments by one automatically,
allowing the entire memory contents to be serially read during sequential Read operation. When the memory
address boundary of the array is reached, the address counter “rolls over” to address 0, and the device
continues to output data. (Refer to Figure 1-10. Sequential Read Diagram).
Diagrams
Figure 1-1. Typical System Bus Configuration
REV1.0
- JUN 2014 RELEASED -
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
Figure 1-2. output Acknowledge
Figure 1-3. Start and Stop Conditions
Figure 1-4. Data Validity Protocol
Figure 1-5. Slave Address
REV1.0
- JUN 2014 RELEASED -
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
Figure 1-6. Byte Write
Figure 1-7. Page Write
Figure 1-8. Current Address Read
REV1.0
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
Figure 1-9. Random Address Read
Figure 1-10. Sequential Read
REV1.0
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A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
Timing Diagrams
Figure 1-11. Bus Timing
Figure 1-12. Write Cycle Timing
REV1.0
- JUN 2014 RELEASED -
- 14 -
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
PACKAGE INFORMATION
Dimension in SOP8 (Unit: mm)
Symbol
Min
Max
A
A1
b
1.350
0.100
0.330
4.800
5.800
3.800
1.750
0.250
0.510
5.000
6.200
4.000
D
E
E1
e
1.270 BSC.
L
0.380
1.270
L1
ZD
θ
0.250 BSC.
0.545 REF.
0°
8°
REV1.0
- JUN 2014 RELEASED -
- 15 -
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
Dimension in TSSOP8 Package (Unit: mm)
Symbol
Min
-
Max
A
A1
A2
b
1.200
0.150
1.050
0.300
0.200
3.100
4.500
0.050
0.080
0.190
0.090
2.900
4.300
c
D
E
E1
e
6.400 BSC
0.650 BSC
L
0.450
0.750
θ
0°
8°
REV1.0
- JUN 2014 RELEASED -
- 16 -
A24C1024
TWO-WIRE SERIAL EEPROM
1024K (131.072 X 8)
AiT Semiconductor Inc.
www.ait-ic.com
IMPORTANT NOTICE
AiT Semiconductor Inc. (AiT) reserves the right to make changes to any its product, specifications, to
discontinue any integrated circuit product or service without notice, and advises its customers to obtain the
latest version of relevant information to verify, before placing orders, that the information being relied on is
current.
AiT Semiconductor Inc.'s integrated circuit products are not designed, intended, authorized, or warranted to
be suitable for use in life support applications, devices or systems or other critical applications. Use of AiT
products in such applications is understood to be fully at the risk of the customer. As used herein may involve
potential risks of death, personal injury, or servere property, or environmental damage. In order to minimize
risks associated with the customer's applications, the customer should provide adequate design and
operating safeguards.
AiT Semiconductor Inc. assumes to no liability to customer product design or application support. AiT
warrants the performance of its products of the specifications applicable at the time of sale.
REV1.0
- JUN 2014 RELEASED -
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