A24C256TMX8VU [AITSEMI]
MEMORY EEPROM TWO-WIRE SERIAL;
| 型号： | A24C256TMX8VU |
| 厂家： | 
AiT Semiconductor |
| 描述： | MEMORY EEPROM TWO-WIRE SERIAL 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总21页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
DESCRIPTION
FEATURES
The A24C256 provides 262144 bits of serial
electrically erasable and programmable read-only
memory (EEPROM), organized as 32768 words of
8 bits each.
Compatible with all I2C bidirectional data
transfer protocol
Memory array:
256k bits (32k bytes) of EEPROM
Page size: 64 bytes
The device is optimized for use in many industrial
and commercial applications where low-power and
low-voltage operation are essential.
Additional Write lockable page
Single supply voltage and high speed:
1
MHz (2.5V)
400 kHz (1.7V)
The A24C256 offers an additional page, named the
Identification Page (64 bytes). The Identification
Page can be used to store sensitive application
parameters which can be (later) permanently
locked in Read-only mode.
100 kHz (1.7V)
Random and sequential Read modes
Write:
Byte Write within 5 ms
Page Write within 5 ms
Partial Page Writes Allowed
Write Protect Pin for Hardware Data Protection
Schmitt Trigger, Filtered Inputs for Noise
Suppression
The A24C256 is available in SOP8, TSSOP8,
DFN8, DIP8 and CSP4 packages.
ORDERING INFORMATION
High reliability
Endurance: 1 Million Write Cycles
Data Retention: 100 Years
Enhanced ESD/Latch-up protection
HBM 8000V
Package Type
SOP8
Part Number
A24C256M8R
A24C256M8U
A24C256M8VR
A24C256M8VU
A24C256TMX8R
A24C256TMX8U
A24C256TMX8VR
A24C256TMX8VU
A24C256J8R
A24C256J8VR
A24C256P8U
A24C256P8VU
A24C256G4R
A24C256G4VR
M8
Available in SOP8, TSSOP8, DFN8, DIP8 and
CSP4 Packages
TSSOP8
TMX8
DFN8
DIP8
J8
P8
G4
CSP4
V: Halogen free Package
R: Tape & Reel
U: Tube
Note
AiT provides all RoHS products
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
- 1 -
A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
PIN DESCIPTION
Top View
Top View
Top View
Top View
Pin #
Top View
Functions
Symbol
Type
SOP8
TSSOP8
DFN8
DIP8
CSP4
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
-
-
A0
A1
I
I
Address Input
Address Input
Address Input
Ground
-
A2
I
A2
B2
B1
-
GND
SDA
SCL
WP
VCC
P
I/O
I
Serial Data
Serial Clock Input
Write Protect
Power Supply
I
A1
P
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage
-0.3V ~ +6.5V
GND-0.3V ~ VCC +0.3V
-40℃~ +85℃
Input / Output Voltage
Operating Ambient Temperature
Storage Temperature
-65℃ ~ +150℃
Electrostatic Pulse (Human Body Model)
8000V
Stress beyond above listed “Absolute Maximum Ratings” may lead permanent damage to the device. These are stress ratings only and
operations of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CAPACITANCE
Applicable over recommended operating range from: TA = 25℃, f = 1.0MHz, VCC = +1.7V
Parameter
Symbol
CI/O
Condition
VI/O=0V
VIN=0V
Min.
Typ.
Max.
Unit
pF
Input / Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
-
-
-
-
8
6
CIN
pF
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
DC ELECTRICAL CHARACTERISTICS
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, unless otherwise noted
Parameter
Supply Voltage
Symbol
VCC1
VCC2
VCC3
VCC4
ICC1
ICC2
ISB1
Condition
Min.
Typ.
Max.
5.5
Unit
V
1.7
-
Supply Voltage
2.5
-
5.5
V
Supply Voltage
2.7
-
-
5.5
V
Supply Voltage
4.5
5.5
V
Supply Current VCC = 5.0V
Supply Current VCC = 5.0V
Supply Current VCC = 1.7V
Supply Current VCC = 2.5V
Supply Current VCC = 2.7V
Supply Current VCC = 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
Read at 400kHz
Write at 400kHz
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VIN = VCC or VSS
VOUT = VCC or VSS
VCC = 1.8V to 5.5V
-
0.4
2.0
0.6
1.0
1.0
2.0
0.10
0.05
-
1.0
mA
mA
μA
μA
μA
μA
μA
μA
V
-
3.0
-
1.0
ISB2
-
2.0
ISB3
-
2.0
ISB4
-
5.0
ILI
-
-
3.0
ILO
3.0
VIL1
-0.3
VCC x 0.3
VCC + 0.3
VCC x 0.2
VCC + 0.3
0.4
Input High Level
VIH1
VIL2
VCC = 1.8V to 5.5V VCC x0.7
-
V
Input Low Level
VCC = 1.7V
VCC = 1.7V
IOL = 3.0mA
IOL = 2.1mA
IOL = 0.15mA
-0.3
-
V
Input High Level
VIH2
VOL3
VOL2
VOL1
VCC x0.7
-
V
Output Low Level VCC = 5.0V
Output Low Level VCC = 3.0V
Output Low Level VCC = 1.7V
-
-
-
-
V
-
0.4
V
-
0.2
V
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
- 4 -
A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
AC ELECTRICAL CHARACTERISTICS
Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL
Gate and 100pF, unless otherwise noted
1.7V≤VCC<2.5V
2.5V≤VCC<5.5V
Parameter
Symbol
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time
Clock Low to Data Out Valid
Time the bus must be free before
a new transmission can start
Start Hold Time
fSCL
tLOW
tHIGH
tI
-
-
-
-
-
-
400
-
-
0.6
0.4
-
-
-
-
-
-
1000
kHz
μs
1.2
0.6
-
-
-
-
μs
50
0.9
50
0.9
ns
tAA
0.1
0.05
μs
tBUF
1.2
-
-
0.5
-
-
μs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
0.6
0.6
0
-
-
0.25
0.25
0
-
-
μs
μs
Start Setup Time
-
-
-
-
Data In Hold Time
-
-
-
-
-
-
μs
Data In Setup Time
100
-
-
100
-
-
ns
Inputs Rise TimeNOTE1
Inputs Fall TimeNOTE1
Stop Setup Time
-
-
0.3
300
-
-
-
0.3
300
-
μs
tF
-
-
ns
tSU.STO
tDH
0.6
50
-
-
0.25
50
-
-
μs
Data Out Hold Time
-
-
-
-
ns
Write Cycle Time
tWR
3.3
5
3.3
5
ms
Write
Cycles
5.0V, 25℃, Byte ModeNOTE1
Endurance
1M
-
-
-
-
-
NOTE1: This parameter is characterized and is not 100% tested.
NOTE2: AC measurement conditions: RL(connects to VCC): 1.3kΩ
Input pulse voltages: 0.3 VCC to 0.7VCC
Input rise and fall time: 50ns
Input and output timing reference voltages: 0.5VCC
The value of RL should be concerned according to the actual loading on the user’s system.
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
- 5 -
A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
BLOCK DIAGRAM
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
- 6 -
A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
DETAILED INFORMATION
DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are
hard wire for the A24C256. Eight 256k devices may be addressed on a single bus system (device addressing
is discussed in detail under the Device Addressing section).
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and
may be wire-ORed with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and
negative edge clock data out of each device.
WRITE PROTECT (WP): The A24C256 has a Write Protect pin that provides hardware data protection. The
Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write
Protection pin is connected to VCC, the write protection feature is enabled and operates as shown in the
following Table 1.
Table1: Write Protect
WP Pin Status
At VCC
A24C256
Full (256k) Array
At GND
Normal Read/Write Operations
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
FUNCTIONAL DESCRIPTION
1. Memory Organization
A24C256, 256k SERIAL EEPROM: Internally organized with 256 pages of 64 bytes each, the 256k requires a
15-bit data word address for random word addressing.
2. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (see Figure 1 on page12). Data changes during SCL
high periods will indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede
any other command (see Figure 2 on page12).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence,
the stop command will place the EEPROM in a standby power mode (see Figure 2 on page12).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit
words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the
ninth clock cycle.
STANDBY MODE: The A24C256 features a low-power standby mode which is enabled: (a) upon power-up
and (b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be
reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
- 8 -
A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
3. Device Addressing
The 256k EEPROM devices all require an 8-bit device address word following a start condition to enable the
chip for a read or write operation (see Figure 6 on page13)
The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as
shown. This is common to all the Serial EEPROM devices.
The 256K EEPROM uses A2, A1 and A0 device address bits to allow as much as eight devices on the same
bus. These 3 bits must be compared to their corresponding hardwired input pins. The A2, A1 and A0 pins use
an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit
is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will
return to a standby state.
DATA SECURITY: The A24C256 has a hardware data protection scheme that allows the user to write protect
the entire memory when the WP pin is at VCC.
4. Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in
the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7 on
page13).
PAGE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in
the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the
addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this
time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on
page13).
The data word address lower five bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
same page. If more than 64 data words are transmitted to the EEPROM, the data word address will "roll over"
and previous data will be overwritten.
WRITE IDENTIFICATION PAGE: The Identification Page (64 bytes) is an additional page which can be
written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for
the following differences:
Device type identifier = 1011b
MSB address bits B15/B6 are don't care except for address bit B10 which must be "0".
LSB address bits B5/B0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction
are not acknowledged (NoAck).
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.
5. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select
bit in the device address word is set to “1”. There are three read operations: current address read, random
address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed
during the last read or write operation, incremented by one. This address stays valid between operations as
long as the chip power is maintained. The address “roll over” during read is from the last byte of the last
memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the
current page to the first byte of the same page. Once the device address with the read/write select bit set to
“1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following stop condition (see
Figure 9 on page14).
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address
read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a “0” but does
generate a following stop condition (see Figure 10 on page14).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address
read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the
EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address limit is reached, the data word address will “roll over” and
the sequential read will continue. The sequential read operation is terminated when the microcontroller does
not respond with a “0” but does generate a following stop condition (see Figure 11 on page14)
READ IDENTIFICATION PAGE: The Identification Page (64 bytes) is an additional page which can be written
and (Iater) permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses
the same protocol and format as the Random Address Read (from memory array) with device type identifier
defined as 1011b. The MSB address bits B15/B6 are don't care, the LSB address bits B5/B0 define the byte
address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page
boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less
than or equal to 54, as the ID page boundary is 64 bytes)
LOCK IDENTIFICATION PAGE: The Lock Identification Page instruction (Lock ID) permanently locks the
Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array)
with the following specific conditions:
Device type identifier = 1011b
Address bit B10 must be '1'; all other address bits are don't care
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
REV2.0
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
Figure 1 Data Validity
Figure 2 Start and Stop Definition
Figure 3 Output Acknowledge
REV2.0
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
Figure 4 First Word Address
Figure 5 Second Word Address
Figure 6 Device Address
Figure 7 Byte Write
Figure 8 Page Write
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
Figure 9 Current Address Read
Figure 10 Random Read
Figure 11 Sequential Read
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
BUS TIMING
Figure 12 SCL: Serial Clock, SDA: Serial Data I/O
WRITE CYCLE TIMING
Figure 13 SCL: Serial Clock, SDA: Serial Data I/O
NOTE: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
PACKAGE INFORMATION
Dimension in SOP8 (Unit: mm)
Symbol
Min
1.35
0.10
0.31
0.17
4.80
3.81
5.79
Max
1.75
0.25
0.51
0.25
5.00
3.99
6.20
A
A1
b
c
D
E1
E
e
1.27BSC
L
0.40
0°
1.27
8°
θ
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
Dimension in TSSOP8 Package (Unit: mm)
Symbol
Min
Max
D
E
2.90
3.10
6.40 BSC
E1
A
4.30
-
4.50
1.20
1.05
0.30
A2
b
0.80
0.19
e
0.65 BSC
1.00 REF
L
0.45
0.75
L1
REV2.0
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A24C256
AiT Semiconductor Inc.
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MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
Dimension in DFN8 (Unit: mm)
Symbol
Min
>0.50
0.00
Max
A
A1
A3
D
0.60
0.05
0.15 REF.
1.95
2.95
0.20
0.20
1.25
1.15
2.05
3.05
0.30
0.40
1.50
1.40
E
b
L
D2
E2
e
0.50 BSC
REV2.0
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
Dimension in DIP8 (Unit: inches)
Symbol
Min
Max
A
A2
b
-
0.210
0.195
0.022
0.070
0.045
0.014
0.400
-
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
b2
b3
c
D
D1
E
0.325
0.280
E1
e
0.100 BSC
0.300 BSC
eA
L
0.115
0.150
REV2.0
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
Dimension in CSP4 (Unit: mm)
Symbol
A
Min
Max
0.270
0.045
0.215
0.738
0.310
0.065
0.255
0.778
A1
A2
D
D1
E
0.400 BSC
0.400 BSC
0.668
0.160
0.708
0.200
E1
b
X1
X2
Y1
Y2
0.144 REF
0.144 REF
0.179 REF
0.179 REF
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
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A24C256
AiT Semiconductor Inc.
www.ait-ic.com
MEMORY EEPROM
256k BITS (32768 X 8) TWO-WIRE SERIAL
IMPORTANT NOTICE
AiT Semiconductor Inc. (AiT) reserves the right to make changes to any its product, specifications, to
discontinue any integrated circuit product or service without notice, and advises its customers to obtain the
latest version of relevant information to verify, before placing orders, that the information being relied on is
current.
AiT Semiconductor Inc.'s integrated circuit products are not designed, intended, authorized, or warranted to
be suitable for use in life support applications, devices or systems or other critical applications. Use of AiT
products in such applications is understood to be fully at the risk of the customer.
As used herein may
In order to
involve potential risks of death, personal injury, or serve property, or environmental damage.
minimize risks associated with the customer's applications, the customer should provide adequate design and
operating safeguards.
AiT Semiconductor Inc. assumes to no liability to customer product design or application support. AiT
warrants the performance of its products of the specifications applicable at the time of sale.
REV2.0
- MAY 2009 RELEASED, NOV 2016 UPDATED -
- 21 -
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