A25S40M8VR-X [AITSEMI]
MEMORY 4M BIT SPI NOR FLASH;
| 型号： | A25S40M8VR-X |
| 厂家： | 
AiT Semiconductor |
| 描述： | MEMORY 4M BIT SPI NOR FLASH |
| 文件： | 总52页 (文件大小：2553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A25S40
MEMORY
AiT Semiconductor Inc.
www.ait-ic.com
4M BIT SPI NOR FLASH
DESCRIPTION
FEATURES
The A25S40 is 4M-bit Serial Peripheral
Interface(SPI) Flash memory, and supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial
Data I/O0 (SI), I/O1 (SO), I/O2 (/WP), and I/O3
(/HOLD). The Dual I/O data is transferred with speed
of 216Mbits/s and the Quad I/O & Quad output data
is transferred with speed of 432Mbits/s. The device
uses a single low voltage power supply, ranging from
2.7 Volt to 3.6 Volt.
Serial Peripheral Interface(SPI)
Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD
Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD
Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3
Read
Normal Read (Serial): 50MHz clock rate
Fast Read (Serial): 108MHz clock rate
Dual/Quad (Multi-I/O) Read: 108MHz clock rate
Program
Additionally, the device supports JEDEC standard
manufacturer and device ID and three
Serial-input Page Program up to 256bytes
Program Suspend and Resume
Erase
256-bytes Security Registers.
Block erase (64/32 KB)
The A25S40 is available in SOP8 package.
Sector erase (4 KB)
Chip erase
Erase Suspend and Resume
Program/Erase Speed
ORDERING INFORMATION
Page Program time: 0.7ms typical
Sector Erase time: 60ms typical
Block Erase time: 0.3/0.5s typical
Chip Erase time: 4s typical
Package Type
SOP8
Part Number
A25S40M8R-X
A25S40M8VR-X
M8
Flexible Architecture
Sector of 4K-byte
V: Halogen free Package
X: Pin Configuration
A: 150mil / B: 208mil
R: Tape & Reel
Block of 32/64K-byte
Low Power Consumption
Note
20mA maximum active current
5uA maximum power down current
Software/Hardware Write Protection
3x256-Byte Security Registers with OTP Lock
Enable/Disable protection with WP Pin
Write protect all/portion of memory via software
Top or Bottom, Sector or Block selection
Single Supply Voltage
AiT provides all RoHS products
Suffix “ V “ means Halogen free Package
TYPICAL APPLICATION
Full voltage range: 2.7~3.6V
Temperature Range
Commercial (0℃ to +70℃)
Industrial (-40℃ to +85℃)
Cycling Endurance/Data Retention
Typical 100k Program-Erase cycles on any
sector
Typical 20-year data retention at +55℃
Available in SOP8 Package
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MEMORY
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4M BIT SPI NOR FLASH
PIN DESCRIPTION
Top View
Pin #
1
Symbol
/CS
I/O
I
Function
Chip Select
SO
Serial Output for single bit data Instructions. IO1 for Dual or Quad
Instructions.
2
I/O
(IO1)
Write Protect in single bit or Dual data Instructions. IO2 in Quad mode.
The signal has an internal pull-up resistor and may be left unconnected in
the host system if not used for Quad Instructions.
Ground
/WP
3
I/O
(IO2)
4
5
6
VSS
SI
-
I/O
I
Serial Input for single bit data Instructions. IO0 for Dual or Quad
Instructions.
(IO0)
SCLK
Serial Clock
Hold (pause) serial transfer in single bit or Dual data Instructions. IO3 in
Quad-I/O mode. The signal has an internal pull-up resistor and may be
left unconnected in the host system if not used for Quad Instructions.
Core and I/O Power Supply
/HOLD
(IO3)
7
8
I/O
-
VCC
Signal Description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max)
.
All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, see
Section 8.6, DC Electrical Characteristics on page 7). These signals are described next.
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4M BIT SPI NOR FLASH
Chip Select (/CS)
The chip select signal indicates when a instruction for the device is in process and the other signals are
relevant for the memory device. When the /CS signal is at the logic high state, the device is not selected and
all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or
Write Status Registers embedded operation is in progress, the device will be in the Standby Power mode.
Driving the /CS input to logic low state enables the device, placing it in the Active Power mode. After Power
Up, a falling edge on /CS is required prior to the start of any instruction.
Serial Clock (SCLK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data
input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of SCLK.
Serial Input (SI)/IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data
to be programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions, addresses,
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out
data (on the falling edge of SCK).
Serial Data Output (SO)/IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of
the serial SCK clock signal.
SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions, addresses,
and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out
data (on the falling edge of SCK).
Write Protect (/WP)/IO2
When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status
Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status Registers.
This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area
that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers, are also hardware
protected against data modification while /WP remains Low. The /WP function is not available when the Quad
mode is enabled (QE) in Status Register 2 (SR2[1]=1).
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4M BIT SPI NOR FLASH
The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data
to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the
falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and may be
left unconnected in the host system if not used for Quad mode.
HOLD (/HOLD)/IO3
The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation
of write status register, programming, or erasing in progress.
The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK signal
being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition
ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD operation will not
end until SCLK being low).
The Hold condition starts on the falling edge of the Hold (/HOLD) signal, provided that this coincides with SCK
being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic low
state, the Hold condition starts whenever the SCK signal reaches the logic low state. Taking the /HOLD signal
to the logic low state does not terminate any Write, Program or Erase operation that is currently in progress.
VCC Power Supply
VCC is the supply voltage. is the single voltage used for all device functions including read, program, and
erase.
VSS Ground
VSS is the reference for the VCC supply voltage.
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4M BIT SPI NOR FLASH
ABSOLUTE MAXIMUM RATINGS
VCC , Supply Voltage
–0.5V ~ 4V
–0.5V ~ 4V
VIO, Voltage Applied to Any Pin
VIOT, Transient Voltage on any Pin
TSTG, Storage Temperature
Relative to Ground
<20nS Transient Relative to Ground
–2.0V ~ VCC+2.0V
–65°C ~ +150°C
–2000V ~ +2000V
VESD, Electrostatic Discharge Voltage
Human Body ModelNOTE1
Stress beyond above listed “Absolute Maximum Ratings” may lead permanent damage to the device. These are stress ratings only and
operations of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE1: JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms)
ELECTRICAL CHARACTERISTICS
Operating Ranges
Parameter
Symbol
VCC
Conditions
FR = 108MHz,
fR = 50MHz
Commercial
Industrial
Min.
2.7
Max.
3.6
Unit
V
Supply Voltage
0
+70
+85
Temperature Operating
TA
°C
-40
Data Retention and Endurance
Parameter
Conditions
Min.
Unit
150°C
125°C
-40 to 85°C
10
20
Years
Years
Cycles
Minimum Pattern Data Retention Time
Erase/Program Endurance
100K
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4M BIT SPI NOR FLASH
Latch Up Characteristics
Parameter
Input Voltage Respect To VSS On I/O Pins
VCC Current
Min.
-1.0
-100
Max.
VCC+1.0
100
Unit
V
mA
Power-up Timing
Parameter
Symbol
tVSL
Min.
10
Max.
Unit
VCC(min) To /CS Low
Time Delay From VCC(min) To Write
Instruction
μs
tPUW
VWI
1
10
ms
V
Write Inhibit Voltage VCC(min)
2.5
Figure 1. Power-up Timing and Voltage Levels
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4M BIT SPI NOR FLASH
DC ELECTRICAL CHARACTERISTICS
T= -40℃~85℃, VCC=2.7~3.6V
Parameter
Input Leakage Current
Output Leakage Current
Symbol
ILI
Conditions
Min.
Typ.
Max.
±2
Unit
μA
ILO
±2
μA
/CS=VCC,
Standby Current
ICC1
13
2
25
5
μA
μA
VIN=VCC or VSS
/CS=VCC,
Deep Power-Down Current
ICC2
VIN=VCC or VSS
Current: Read Single/Dual/Quad
1MHz
3/4/5
3.5/5/6
mA
Current: Read Single/Dual/Quad
33MHz
5/11/19
6.5/16/30
10/33/60
7.5/12/19.5 mA
SCLK=0.1VCC/
ICC3
NOTE1
0.9VCC
Current: Read Single/Dual/Quad
50MHz
9.5/17/33
12/35/65
mA
mA
Current: Read Single/Dual/Quad
108MHz
Operating Current(Page Program)
Operating Current(WRSR)
Operating Current(Sector Erase)
Operating Current(Block Erase)
Operating Current (Chip Erase)
Input Low Voltage
ICC4
ICC5
ICC6
ICC7
ICC8
VIL
/CS=VCC
/CS=VCC
/CS=VCC
/CS=VCC
/CS=VCC
15
5
mA
mA
mA
mA
mA
V
20
20
20
-0.5
0.2VCC
VCC +0.4
0.4
Input High Voltage
VIH
0.8VCC
V
Output Low Voltage
VOL
VOH
IOL =100μA
IOH =-100μA
V
Output High Voltage
VCC -0.2
V
NOTE1: ICC3 is measured with ATE loading
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4M BIT SPI NOR FLASH
AC MEASUREMENT CONDITIONS
Parameter
Load Capacitance
Symbol
Min.
Typ.
Max.
30
Unit
pF
ns
V
CL
TR, TF
VIN
Input Rise And Fall time
5
Input Pause Voltage
0.2VCC ~ 0.8VCC
0.3VCC ~ 0.7VCC
0.5VCC
Input Timing Reference Voltage
Output Timing Reference Voltage
IN
V
OUT
V
Figure 2. AC Measurement I/O Waveform
AC ELECTRICAL CHARACTERISTICS
Parameter
Clock frequency for all instructions, except
Read Data(03H)
Symbol
Min.
Typ.
Max.
108
55
Unit
fc
DC.
MHz
Clock freq. Read Data instruction(03H)
Serial Clock High Time
fR
DC.
MHz
ns
tCLH
4
Serial Clock Low Time
tCLL
4
ns
Serial Clock Rise Time (Slew Rate)
Serial Clock Fall Time (Slew Rate)
/CS Active Setup Time
tCLCH
tCHCL
tSLCH
tCHSH
tSHCH
tCHSL
tSHSL
0.1NOTE1
V/ ns
V/ ns
ns
0.1NOTE1
5
5
/CS Active Hold Time
ns
/CS Not Active Setup Time
/CS Not Active Hold Time
/CS High Time（read/write）
5
ns
5
ns
20
ns
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4M BIT SPI NOR FLASH
Parameter
Output Disable Time
Symbol
Min.
Typ.
Max.
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
tSHQZ
tCLQX
tDVCH
tCHDX
tHLCH
tHHCH
tCHHL
tCHHH
tHLQZ
tHHQX
tCLQV
tWHSL
tSHWL
tDP
Output Hold Time
0
2
2
5
5
5
5
Data In Setup Time
Data In Hold Time
/Hold Low Setup Time (relative to Clock)
/Hold High Setup Time (relative to Clock)
/Hold High Hold Time (relative to Clock)
/Hold Low Hold Time (relative to Clock)
/Hold Low To High-Z Output
/Hold Low To Low-Z Output
Clock Low To Output Valid
6
6
7
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
/CS High To Deep Power-Down Mode
/CS High To Standby Mode Without
Electronic Signature Read
20
100
0.1
3
tRES1
tRES2
tSUS
μs
μs
μs
/CS High To Standby Mode With
Electronic Signature Read
1.5
2
/CS High To Next Instruction After
Suspend
Write Status Register Cycle Time
Page Programming Time
tW
tPP
tSE
tBE
tCE
10
0.7
15NOTE2
2.4
ms
ms
ms
s
Sector Erase Time
60
300
Block Erase Time(32K Bytes/64K Bytes)
0.3/0.5
15
0.75/1.5
35
Chip Erase Time
s
NOTE1: Tested with clock frequency lower than 50 MHz.
NOTE2: tW can be up to 45 ms at -40℃ during the characterization of the current design. It will be improved in the future design.
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4M BIT SPI NOR FLASH
Figure 3. Serial Input Timing
Figure 4. Output Timing
Figure 5. Hold Timing
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4M BIT SPI NOR FLASH
BLOCK/SECTOR ADDRESSES
Table 1. Block/Sector Addresses of A25S40
Memory
Density
Block
Block
Sector
Sector No.
Address range
(64k byte)
(32k byte)
Size(KB)
Sector 0
：
4
：
4
000000h-000FFFh
：
Half block 0
Half block 1
Half block 2
Sector 7
Sector 8
：
007000h-007FFFh
008000h-008FFFh
：
Block 0
4
4
Sector 15
Sector 16
：
4
00F000h-00FFFFh
010000h-010FFFh
：
4
：
4
Sector 23
Sector 24
：
017000h-017FFFh
018000h-018FFFh
：
Block 1
：
4
Half block 3
：
：
4
Sector 31
：
01F000h-01FFFFh
：
4Mbit
：
4
Sector 96
：
060000h-060FFFh
：
Half block 12
：
4
Sector 103
Sector 104
：
067000h-067FFFh
068000h-068FFFh
：
Block 6
4
Half block 13
Half block 14
Half block 15
：
4
Sector 111
Sector 112
：
06F000h-06FFFFh
070000h-070FFFh
：
4
：
4
Sector 119
Sector 120
：
077000h-077FFFh
078000h-078FFFh
：
Block 7
4
：
4
Sector 127
07F000h-07FFFFh
NOTES: 1. Block = Uniform Block, and the size is 64K bytes.
2. Half block = Half Uniform Block, and the size is 32K bytes.
3. Sector = Uniform Sector, and the size is 4K bytes.
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4M BIT SPI NOR FLASH
SPI OPERATION
Standard SPI Instructions
The A25S40 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (/CS),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is
latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI Instructions
The A25S40 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”
(3BH and BBH) instructions. These instructions allow data to be transferred to or from the device at two times
the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O
pins: IO0 and IO1.
Quad SPI Instructions
The A25S40 supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read”
(6BH, EBH) instructions. These instructions allow data to be transferred t-o or from the device at four times
the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional
I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3. Quad SPI instructions require the
non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
OPERATION FEATURES
Supply Voltage
1.
Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified
[VCC(min), VCC(max)] range must be applied (see operating ranges of page 5). In order to secure a stable DC
supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10nF to 100nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of
the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
2.
Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select
(/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the
/CS line to VCC via a suitable pull-up resistor.
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In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as
well as level sensitive: after power-up, the device does not become selected until a falling edge has first been
detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low
to start the first operation.
3.
Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset
(POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached
the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined
in operating ranges of page 5).
When VCC has passed the POR threshold, the device is reset.
4.
Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to
below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During
Power-down, the device must be deselected (Chip Select (/CS) should be allowed to follow the voltage
applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress).
Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the
device then goes in to the Standby Power mode, and the device consumption drops to ICC1
.
Hold Condition
The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the
clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial
Data Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be
selected, with Chip Select (/CS) Low. Normally, the device is kept selected, for the whole duration of the Hold
condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the
device, and this mechanism can be used if it is required to reset any processes that had been in progress.
The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock (SCLK)
already being Low (as shown in Figure 6).
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The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C)
already being Low. Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (SCLK) being Low.
Figure 6. Hold condition activation
Status Register
1.
Status Register Table
See Table 2 and Table 3 for detail description of the Status Register bits. Status Register-2 (SR2) and Status
Register-1 (SR1) can be used to provide status on the availability of the Flash memory array, if the device is
write enabled or disabled the state of write protection, Quad SPI setting, Security Register lock status, and
Erase/Program Suspend status.
Table 2. Status Register-2 (SR2)
Default
BIT
Name
Function
Description
Value
Suspend
Status
0 = Erase/Program not suspended
1 = Erase/Program suspended
0 = Normal Protection Map
7
SUS
0
Complement
Protect
6
CMP
0
1 = Inverted Protection Map
5
4
3
2
LB3
LB2
0
0
0
0
Security
OTP Lock Bits 3:1 for Security Registers 3:1
0 = Security Register not protected
1 = Security Register protected
Register
Lock Bits
Reserved
LB1
Reserved
0 = Quad Mode Not Enabled, the /WP pin and /HOLD
are enabled.
Quad
1
QE
0
0
Enable
1 = Quad Mode Enabled, the IO2 and IO3 pins are
enabled, and /WP and /HOLD functions are disabled
0 = SRP0 selects whether /WP input has effect on
protection of the status register
Status
Resister
Protect 1
0
SRP1
1 = SRP0 selects Power Supply Lock Down or OTP
Lock Down mode
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Table 3. Status Register-1 (SR1)
Default
Value
BIT
Name
Function
Description
0 = /WP input has no effect or Power Supply Lock Down
Mode
Status
Resister
Protect 0
7
SRP0
0
1 = /WP input can protect the Status Register or OTP
Lock Down
Sector/Block
Protect
0 = BP2-BP0 protect 64KB blocks
1 = BP2-BP0 protect 4KB sectors
0 = BP2-BP0 protect from the Top down
1 = BP2-BP0 protect from the Bottom up
6
5
SEC
TB
0
0
Top/Bottom
Protect
4
3
2
BP2
BP1
BP0
0
0
0
Block Protect
Bits
000b = No protection
See Table 5 and Table 6 for protection ranges
Write Enable
Latch
0 = Not Write Enabled, no embedded operation can start
1 = Write Enabled, embedded operation can start
1
WEL
0
Write in
Progress
Status
0 = Not Busy, no embedded operation in progress
1 = Busy, embedded operation in progress
0
WIP
0
2.
1.
The Status and Control Bits
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,
when WIP bit sets 0, means the device is not in program/erase/write status register progress.
2.
WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal
Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register,
Program or Erase instruction is accepted.
3.
SEC, TB, BP2, BP1, BP0 bits
The Block Protect (SEC, TB, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. These bits are written with the Write Status
Register instruction. When the Block Protect (SEC, TB, BP2, BP1, BP0) bits are set to 1, the relevant memory
area (as defined in Table 5 and Table 6).becomes protected against Page Program, Sector Erase and Block
Erase instructions. The Block Protect (SEC, TB, BP2, BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
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4.
SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply
lock-down or one time programmable protection.
5.
QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the
Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI
operation if the /WP or /HOLD pins directly to the power supply or ground).
6.
LB3/LB2/LB1 bit
The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect
control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked.
LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s
set to 1, the 256byte Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1.
7.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the
SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory
Protection table for details. The default setting is CMP=0.
8.
SUS bit
The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program
Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well
as a power-down, power-up cycle.
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3.
Status Register Protect Table
Table 4. Status Register protect table
SRP1 SRP0
/WP
X
Status Register
Software
Description
The Status Register can be written to after a Write Enable
instruction, WEL=1.(Factory Default)
0
0
0
1
1
0
1
1
0
1
Protected
Hardware
0
1
/WP=0, the Status Register locked and cannot be written.
Protected
Hardware
/WP=1, the Status Register is unlocked and can be written
to after a Write Enable instruction, WEL=1.
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
Status Register is permanently protected and cannot be
written to.
Unprotected
Power Supply
Lock-DownNOTE1
One Time
X
X
ProgramNOTE2
NOTE1: When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
NOTE2: The One time Program feature is available upon special order. Please contact Berg Microelectronics for details.
4.
1.
Write Protect Features
Software Protection: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
2.
3.
Hardware Protection: /WP going low to protected the BP0~SEC bits and SRP0~1 bits.
Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the Release from
deep Power-Down Mode instruction.
4.
Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program, Sector Erase,
Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction.
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5.
1.
Status Register Memory Protection
Protect Table
Table 5. A25S40 Status Register Memory Protection (CMP=0)
Status Register Content
Memory Content
Addresses Density
SEC
X
0
TB
X
0
0
0
1
1
1
X
0
0
0
0
0
1
1
1
1
1
X
BP2
0
BP1
0
BP0
0
Blocks
Portion
NONE
NONE
NONE
NONE
64KB
128KB
256KB
64KB
128KB
256KB
512KB
4KB
0
0
1
7
070000H-07FFFFH
060000H-07FFFFH
040000H-07FFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
07F000H-07FFFFH
07E000H-07FFFFH
07C000H-07FFFFH
078000H-07FFFFH
078000H-07FFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH
000000H-07FFFFH
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/8
Lower 1/4
Lower 1/2
ALL
0
0
1
0
6 and 7
0
0
1
1
4 to 7
0
0
0
1
0
0
0
1
0
0 and 1
0
0
1
1
0 to 3
0
1
X
0
X
1
0 to 7
1
0
7
Upper 1/128
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/16
Lower 1/128
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/16
ALL
1
0
1
0
7
8KB
1
0
1
1
7
16KB
32KB
32KB
4KB
1
1
0
X
0
7
1
1
1
7
1
0
0
1
0
1
0
1
0
0
8KB
1
0
1
1
0
0
16KB
32KB
32KB
512KB
1
1
0
X
0
1
1
1
0
1
1
1
1
0 to 7
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Table 6. A25S40 Status Register Memory Protection (CMP=1)
Status Register Content
Memory Content
Addresses Density
SEC
X
0
TB
X
0
0
0
1
1
1
X
0
0
0
0
0
1
1
1
1
1
X
BP2
0
BP1
0
BP0
0
Blocks
0 to 7
0 to 6
0 to 5
0 to 3
1 to 7
2 to 7
4 to 7
NONE
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
NONE
Portion
ALL
000000H-07FFFFH
000000H-06FFFFH
000000H-05FFFFH
000000H-03FFFFH
010000H-07FFFFH
020000H-07FFFFH
040000H-07FFFFH
NONE
512KB
448KB
384KB
256KB
448KB
384KB
256KB
NONE
508KB
504KB
496KB
480KB
480KB
508KB
504KB
496KB
480KB
480KB
NONE
0
0
1
Lower 7/8
Lower 3/4
Lower 1/2
Upper 7/8
Upper 3/4
Upper 1/2
NONE
0
0
1
0
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
X
0
X
1
1
0
000000H-07EFFFH
000000H-07DFFFH
000000H-07BFFFH
000000H-077FFFH
000000H-077FFFH
001000H-07FFFFH
002000H-07FFFFH
004000H-07FFFFH
008000H-07FFFFH
008000H-07FFFFH
NONE
Lower 127/128
Lower 63/64
Lower 31/32
Lower 15/16
Lower 15/16
Upper 127/128
Upper 63/64
Upper 31/32
Upper 15/16
Upper 15/16
NONE
1
0
1
0
1
0
1
1
1
1
0
X
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
X
X
1
1
1
0
1
1
1
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DEVICE IDENTIFICATION
Three legacy Instructions are supported to access device identification that can indicate the manufacturer,
device type, and capacity (density). The returned data bytes provide the information as shown in the below
table.
Table 7. A25S40 ID Definition table
Operation Code
M7-M0
E0
ID15-ID8
40
ID7-ID0
15
9FH
90H
ABH
E0
14
14
INSTRUCTIONS DESCRIPTION
All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit
on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in
to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK.
See Table 8, every instruction sequence starts with a one-byte instruction code. Depending on the instruction,
this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after
the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read
Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence
is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being
shifted out.
For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write
Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary,
otherwise the instruction is rejected, and is not executed. That is /CS must driven high when the number of
clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input
byte is not a full byte, nothing will happen and WEL will not be reset.
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Table 8. Instruction Set Table
Instruction Name
Write Enable
Byte 1
06H
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Write Disable
04H
Read Status Register-1
Read Status Register-2
Write Enable for
Volatile Status Register
Write Status Register
Read Data
05H
35H
(S7-S0)
(S15-S8)
50H
01H
03H
0BH
3BH
(S7-S0)
A23-A16
A23-A16
A23-A16
(S15-S8)
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
Next byte
(D7-D0)
Fast Read
Dual Output Fast Read
(D7-D0)NOTE1
Dual I/O Fast Read
Quad Output Fast Read
Quad I/O Fast Read
BBH
6BH
EBH
A23-A8NOTE2
(D7-D0)NOTE1
A7-A0
M7-M0 NOTE2
A15-A8
A23-A16
A23-A0
M7-M0NOTE4
FFH
A23-A16
A23-A16
A23-A16
A23-A16
dummy
(D7-D0)
(D7-D0)NOTE3
Next byte
dummy
(D7-D0)NOTE5
Continuous Read Reset
Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
FFH
02H
20H
52H
D8H
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
C7/60H
Program/Erase
Suspend
75H
Program/Erase
Resume
7AH
B9H
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
ABH
ABH
dummy
dummy
dummy
(ID7-ID0)
(M7-M0)
Manufacturer/ Device
ID
JEDEC ID
Erase Security
RegistersNOTE6
Program Security
RegistersNOTE6
Read Security
RegistersNOTE6
90H
9FH
44H
dummy
dummy
00H
(ID7-ID0)
(M7-M0)
A23-A16
(ID15-ID8)
A15-A8
(ID7-ID0)
A7-A0
42H
48H
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
(D7-D0)
dummy
(D7-D0)
(D7-D0)
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NOTES:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3
3. Quad Output Data
IO0 = (D4, D0,…..)
IO1 = (D5, D1,…..)
IO2 = (D6, D2,…..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Security Registers Address:
Security Register0: A23-A16=00h, A15-A8=00h, A7-A0= Byte Address;
Security Register1: A23-A16=00h, A15-A8=01h, A7-A0= Byte Address;
Security Register2: A23-A16=00h, A15-A8=02h, A7-A0= Byte Address;
Security Register3: A23-A16=00h, A15-A8=03h, A7-A0= Byte Address;
Security Register 0 can be used to store the Flash Discoverable Parameters, The feature is upon special
order, please contact Berg Microelectronics for details.
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Configuration and Status Instructions
1. Write Enable (06H)
See Figure 7, the Write Enable instruction is for setting the Write Enable Latch bit. The Write Enable Latch bit
must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register
instruction. The Write Enable instruction sequence: /CS goes low sending the Write Enable instruction /CS
goes high.
Figure 7. Write Enable Sequence Diagram
2.
Write Disable (04H)
See Figure 8, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write Disable
instruction sequence: /CS goes low Sending the Write Disable instruction /CS goes high.
The WEL bit is reset by following condition: Power-up and upon completion of the Write Status Register, Page
Program, Sector Erase, Block Erase and Chip Erase instructions.
Figure 8. Write Disable Sequence Diagram
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3.
Read Status Register (05H or 35H)
See Figure 9 the Read Status Register (RDSR) instruction is for reading the Status Register. The Status
Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before
sending a new instruction to the device. It is also possible to read the Status Register continuously. For
instruction code “05H”, the SO will output Status Register bits S7~S0. The instruction code “35H”, the SO will
output Status Register bits S15~S8.
Figure 9. Read Status Register Sequence Diagram
4.
Write Status Register (01H)
See Figure 10, the Write Status Register instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable instruction must previously have been executed. After the Write
Enable instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S15, S1 and S0 of the Status Register. /CS must be
driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register
instruction is not executed. If /CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1
bits will be cleared to 0. As soon as /CS is driven high, the self-timed Write Status Register cycle (whose
duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be
read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the
self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write
Enable Latch is reset.
The Write Status Register instruction allows the user to change the values of the Block Protect (SEC, TB, BP2,
BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The
Write Status Register instruction also allows the user to set or reset the Status Register Protect (SRP1 and
SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and SRP0)
bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write
Status Register instruction is not executed once the Hardware Protected Mode is entered.
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Figure 10. Write Status Register Sequence Diagram
5.
Write Enable for Volatile Status Register (50H)
See Figure 11, the non-volatile Status Register bits can also be written to as volatile bits. During power up
reset, the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used
during device operation. This gives more flexibility to change the system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile version of the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to each Write Status Registers (01h) instruction.
Write Enable for Volatile Status Register instruction will not set the Write Enable Latch bit, it is only valid for
the next following Write Status Registers instruction, to change the volatile Status Register bit values.
Figure 11. Write Enable for Volatile Status Register
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Read Instructions
1. Read Data (03H)
See Figure 12, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit
being latched-in during the rising edge of SCLK. Then the memory content, at that address, is shifted out on
SO, each bit being shifted out, at a Max frequency fR, during the falling edge of SCLK. The address is
automatically incremented to the next higher address after each byte of data is shifted out allowing for a
continuous stream of data. This means that the entire memory can be accessed with a single command as
long as the clock continues. The command is completed by driving /CS high. The whole memory can be read
with a single Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Normal read mode running up to 50MHz.
Figure 12. Read Data Bytes Sequence Diagram
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2.
Fast Read (0BH)
See Figure 13, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading data out. It
is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge
of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency fc, during the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure 13. Fast Read Sequence Diagram
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3.
Dual Output Fast Read (3BH)
See Figure 14, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy
byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit
per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Figure 14. Dual Output Fast Read Sequence Diagram
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4.
Quad Output Fast Read (6BH)
See Figure 15, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy
byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 4-bit
per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure 15. Quad Output Fast Read Sequence Diagram
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5.
Dual I/O Fast Read (BBH)
See Figure 16, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but with
the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by SI
and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out
2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure 16. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
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6.
Dual I/O Fast Read with “Continuous Read Mode”
See Figure 17, the Dual I/O Fast Read instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode”
bits (M7-0) =AXH, then the next Dual I/O Fast Read instruction (after /CS is raised and then lowered) does not
require the BBH instruction code. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH,
the next instruction requires the first BBH instruction code, thus returning to normal operation. A “Continuous
Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instruction.
Figure 17. Dual I/O Fast Read Sequence Diagram (M7-0= AXH)
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7.
Quad I/O Fast Read (EBH)
See Figure 18, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read instruction but with the
capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit
per clock by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory
contents are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is
shifted out. The Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast read
instruction.
Figure 18. Quad I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)
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8.
Quad I/O Fast Read with “Continuous Read Mode”
See Figure 19, the Quad I/O Fast Read instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode”
bits (M7-0) =AXH, then the next Quad I/O Fast Read instruction (after /CS is raised and then lowered) does
not require the EBH instruction code. If the “Continuous Read Mode” bits (M7-0) are any value other than
AXH, the next instruction requires the first EBH instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can be used to reset (M7-0) before issuing normal instruction.
Figure 19. Quad I/O Fast Read Sequence Diagram (M7-0= AXH)
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9.
Continuous Read Mode Reset (FFH or FFFFH)
The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O” and “Fast Read Quad
I/O” Instructions to provide the highest random Flash memory access rate with minimum SPI instruction
overhead, thus allowing more efficient XIP (execute in place) with this device family.
The “Continuous Read Mode” bits M7-0 are set by the Dual/Quad I/O Read Instructions. M5-4 are used to
control whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next instruction. When
M5-4 = (1,0), the next instruction will be treated the same as the current Dual/Quad I/O Read instruction
without needing the 8-bit instruction code; when M5-4 do not equal to (1,0), the device returns to normal SPI
instruction mode, in which all instructions can be accepted. M7-6 and M3-0 are reserved bits for future use,
either 0 or 1 values can be used.
See Figure 20, the Continuous Read Mode Reset instruction (FFh or FFFFh) can be used to set M4 = 1, thus
the device will release the Continuous Read Mode and return to normal SPI operation.
To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The instruction is
“FFh”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in
instruction “FFFFh
Figure 20. Continuous Read Mode Reset Sequence Diagram
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10. Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction
can either enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap
Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches
the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning
boundary automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. Wrap bit
W7 and the lower nibble W3-0 are not used.
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any
page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with
Wrap instruction should be issued to set W4=1. The default value of W4 upon power on is 1.
W4 = 0
W4 =1 (DEFAULT)
W6
W5
Wrap Around
Wrap Length
8-byte
Wrap Around
Wrap Length
0
0
1
1
0
1
0
1
Yes
Yes
Yes
Yes
No
No
No
No
N/A
N/A
N/A
N/A
16-byte
32-byte
64-byte
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Figure 21. Set Burst with Wrap Command Sequence
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ID and Security Instructions
1. Read Manufacture ID/ Device ID (90H)
See Figure 22, the Read Manufacturer/Device ID instruction is an alternative to the Release from
Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and the specific
Device ID.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H” followed by a
24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H, the Device ID will be read
first.
Figure 22. Read Manufacture ID/ Device ID Sequence Diagram
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2.
JEDEC ID (9FH)
The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of
device identification. The device identification indicates the memory type in the first byte, and the memory
capacity of the device in the second byte. JEDEC ID instruction while an Erase or Program cycle is in
progress, is not decoded, and has no effect on the cycle that is in progress. The JEDEC ID instruction should
not be issued while the device is in Deep Power-Down Mode.
See Figure 23, he device is first selected by driving /CS to low. Then, the 8-bit instruction code for the
instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted
out on Serial Data Output, each bit being shifted out during the falling edge of Serial Clock. The JEDEC ID
instruction is terminated by driving /CS to high at any time during data output. When /CS is driven high, the
device is put in the Standby Mode. Once in the Standby Mode, the device waits to be selected, so that it can
receive, decode and execute instructions.
Figure 23. JEDEC ID Sequence Diagram
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3.
Deep Power-Down (B9H)
Although the standby current during normal operation is relatively low, standby current can be further reduced
with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down (DPD)
instruction especially useful for battery powered applications (see ICC1 and ICC2). The instruction is initiated by
driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 24.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep Power down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the time
duration of tDP. While in the power-down state only the Release from Deep Power-down / Device ID
instruction, which restores the device to normal operation, will be recognized. All other Instructions are
ignored. This includes the Read Status Register instruction, which is always available during normal operation.
Ignoring all but one instruction also makes the Power Down state a useful condition for securing maximum
write protection. The device always powers-up in the normal operation with the standby current of ICC1
.
Figure 24. Deep Power-Down Sequence Diagram
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4.
Release from Deep Power-Down/Read Device ID (ABH)
The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the Power-Down state or obtain the devices electronic identification (ID) number.
See Figure 25a, to release the device from the Power-Down state, the instruction is issued by driving the /CS
pin low, shifting the instruction code “ABH” and driving /CS high Release from Power-Down will take the time
duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other
instruction are accepted. The /CS pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits
are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 25b.
The Device ID value for the A25S40 is listed in Manufacturer and Device Identification table. The Device ID
can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the Power-Down state and obtain the Device ID, the instruction is the
same as previously described, and shown in Figure 25b, except that after /CS is driven high it must remain
high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume
normal operation and other instruction will be accepted. If the Release from Power-Down/Device ID
instruction is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the instruction is
ignored and will not have any effects on the current cycle.
Figure 25a. Release Power-Down Sequence Diagram
Figure 20b. Release Power-Down/Read Device ID Sequence Diagram
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5.
Read Security Registers (48H)
See Figure 26, the Read Security Registers instruction is similar to Fast Read instruction. The instruction is
followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of
SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max
frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. Once the A9-A0
address reaches the last byte of the register (Byte 3FFH), it will reset to 000H, the instruction is completed by
driving /CS high.
Address
A23-A16
00H
A15-A8
01H
A7-A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00H
02H
00H
03H
Figure 26. Read Security Registers instruction Sequence Diagram
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6.
Erase Security Registers (44H)
The A25S40 provides three 256-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
See Figure 27, the Erase Security Registers instruction is similar to Sector/Block Erase instruction. A Write
Enable instruction must previously have been executed to set the Write Enable Latch bit.
The Erase Security Registers instruction sequence: /CS goes low sending Erase Security Registers
instruction /CS goes high. /CS must be driven high after the eighth bit of the instruction code has been latched
in otherwise the Erase Security Registers instruction is not executed. As soon as /CS is driven high, the
self-timed Erase Security Registers cycle (whose duration is tSE) is initiated. While the Erase Security
Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset. The Security Registers Lock Bit (LB) in the Status Register can be used to OTP protect the security
registers. Once the LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security
Registers instruction will be ignored.
Address
A23-A16
00H
A15-A8
01H
A7-A0
Security Registers 1
Security Registers 2
Security Registers 3
Don’t Care
Don’t Care
Don’t Care
00H
02H
00H
03H
Figure 27. Erase Security Registers instruction Sequence Diagram
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7.
Program Security Registers (42H)
See Figure 28, the Program Security Registers instruction is similar to the Page Program instruction. It allows
from 1 to 256 bytes Security Registers data to be programmed. A Write Enable instruction must previously
have been executed to set the Write Enable Latch bit before sending the Program Security Registers
instruction. The Program Security Registers instruction is entered by driving /CS Low, followed by the
instruction code (42H), 3-byte address and at least one data byte on SI. As soon as /CS is driven high, the
self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program Security
Registers cycle is in progress, the Status Register may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset.
If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers instruction will be ignored.
Address
A23-A16
00H
A15-A8
01H
A7-A0
Security Registers 1
Security Registers 2
Security Registers 3
Byte Address
Byte Address
Byte Address
00H
02H
00H
03H
Figure 28. Program Security Registers instruction Sequence Diagram
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Program and Erase Instructions
1. Page Program (02H)
The Page Program instruction is for programming the memory. A Write Enable instruction must previously
have been executed to set the Write Enable Latch bit before sending the Page Program instruction.
See Figure 29, the Page Program instruction is entered by driving /CS Low, followed by the instruction code,
3-byte address and at least one data byte on SI. If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current page are programmed from the start address of
the same page (from the address whose 8 least significant bits (A7-A0) are all zero). /CS must be driven low
for the entire duration of the sequence. The Page Program instruction sequence: /CS goes low sending Page
Program instruction 3-byte address on SI at least 1 byte data on SI /CS goes high. If more than 256 bytes are
sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be
programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly
programmed at the requested addresses without having any effects on the other bytes of the same page. /CS
must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program
instruction is not executed.
As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While
the Page Program cycle is in progress, the Status Register may be read to check the value of the Write in
Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0
when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch bit is
reset.
A Page Program instruction applied to a page which is protected by the Block Protect (SEC, TB, BP2, BP1,
BP0) is not executed.
Figure 29. Page Program Sequence Diagram
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2.
Sector Erase (20H)
The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit. The Sector Erase instruction is entered by
driving /CS low, followed by the instruction code, and 3-address byte on SI. Any address inside the sector is a
valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the sequence.
See Figure 30, The Sector Erase instruction sequence: /CS goes low sending 64KB Block Erase instruction
3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address byte has
been latched in; otherwise the Sector Erase instruction is not executed. As soon as /CS is driven high, the
self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress,
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch bit is reset. A Sector Erase instruction applied to a
sector which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) bit is not executed.
Figure 30. Sector Erase Sequence Diagram
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3.
32KB Block Erase (52H)
The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction
must previously have been executed to set the Write Enable Latch bit. The 32KB Block Erase instruction is
entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the
block is a valid address for the 32KB Block Erase instruction. /CS must be driven low for the entire duration of
the sequence.
See Figure 31, the 32KB Block Erase instruction sequence: /CS goes low sending 32KB Block Erase
instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address
byte has been latched in; otherwise the 32KB Block Erase instruction is not executed. As soon as /CS is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle
is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 32KB Block Erase
instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) bits (see
Table 5&6) is not executed.
Figure 31. 32KB Block Erase Sequence Diagram
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4.
64KB Block Erase (D8H)
The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable instruction
must previously have been executed to set the Write Enable Latch bit. The 64KB Block Erase instruction is
entered by driving /CS low, followed by the instruction code, and 3-byte address on SI. Any address inside the
block is a valid address for the 64KB Block Erase instruction. /CS must be driven low for the entire duration of
the sequence.
See Figure 32, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB Block Erase
instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the last address
byte has been latched in; otherwise the 64KB Block Erase instruction is not executed. As soon as /CS is
driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle
is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The
Write In Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A 64KB Block Erase
instruction applied to a block which is protected by the Block Protect (SEC, TB, BP2, BP1, BP0) bits (see
Table 5&6) is not executed.
Figure 32. 64KB Block Erase Sequence Diagram
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5.
Chip Erase (60/C7H)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 33.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence
for a time duration of tCE. While the Chip Erase cycle is in progress, the Read Status Register instruction may
still be accessed to check the status of the WIP bit.
The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to
accept other Instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Table 5&6).
Figure 33. Chip Erase Sequence Diagram
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6.
Erase / Program Suspend (75H)
The Erase/Program Suspend instruction allows the system to interrupt a Sector or Block Erase operation,
then read from or program data to any other sector. The Erase/Program Suspend instruction also allows the
system to interrupt a Page Program operation and then read from any other page or erase any other sector or
block. The Erase/Program Suspend instruction sequence is shown in Figure 34.
The Write Status Registers instruction (01h) and Erase instructions (20h, D8h, C7h, 60h, 44h) are not allowed
during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If written
during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status Registers
instruction (01h), and Program instructions (02h, 32h, 42h) are not allowed during Program Suspend.
Program Suspend is valid only during the Page Program operation.
Figure 34. Erase/Program Suspend Command Sequence
7.
Erase / Program Resume (7AH)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation
or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be
accepted by the device only if the SUS bit in the Status Register equals to 1 and the WIP bit equals to 0.
After the Resume instruction is issued the SUS bit will be cleared from 1 to 0 immediately, the WIP bit will be
set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation or the page will
complete the program operation. If the SUS bit equals to 0 or the WIP bit equals to 1, the Resume instruction
“7Ah” will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 35.
Figure 35. Erase/Program Resume Command Sequence
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PACKAGE INFORMATION
Dimension in SOP8 150-mil (Unit: mm)
Symbol
Min
-
Max
A
A1
A2
b
1.750
0.200
1.550
0.510
0.250
5.030
6.200
4.000
0.100
1.350
0.360
0.150
4.770
5.800
3.800
C
D
E
E1
e
1.270 TYP.
L
0.460
0.850
0.410
0
0.860
1.250
0.670
8
L1
S
θ
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Dimension in SOP8 208-mil (Unit: mm)
Symbol
Min
-
Max
A
A1
A2
b
2.160
0.250
1.910
0.510
0.250
5.330
8.100
5.380
0.050
1.700
0.360
0.190
5.130
7.700
5.180
C
D
E
E1
e
1.270 TYP.
L
0.500
1.210
0.620
0
0.800
1.410
0.880
8
L1
S
θ
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IMPORTANT NOTICE
AiT Semiconductor Inc. (AiT) reserves the right to make changes to any its product, specifications, to
discontinue any integrated circuit product or service without notice, and advises its customers to obtain the
latest version of relevant information to verify, before placing orders, that the information being relied on is
current.
AiT Semiconductor Inc.'s integrated circuit products are not designed, intended, authorized, or warranted to
be suitable for use in life support applications, devices or systems or other critical applications. Use of AiT
products in such applications is understood to be fully at the risk of the customer. As used herein may involve
potential risks of death, personal injury, or servere property, or environmental damage. In order to minimize
risks associated with the customer's applications, the customer should provide adequate design and
operating safeguards.
AiT Semiconductor Inc. assumes to no liability to customer product design or application support. AiT
warrants the performance of its products of the specifications applicable at the time of sale.
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