AK4141中文资料_数据手册_规格书

[AK4141]

= Preliminary =

AK4141

NICAM/A2/EIA-J Digital Stereo Decoder

GENERAL DESCRIPTION

The AK4141 is a NICAM/A2/EIA-J stereo decoder, which is optimized for Digital TV application. The

AK4141 achieves no alignment, few external components and high audio performance by digital stereo

decoding architecture. The AK4141 integrates a stereo sample rate converter (SRC) for asynchronous

digital audio sources such as HDMI, digital tuner, digital switches and sound processing functions such as

5-band equalizers. The AK4141 supports major audio data formats (MSB/LSB justified, I²S and TDM) to

interface with DSP, ADC, DAC. Therefore, the AK4141 is suitable for the AV systems such as Digital TV

and DVR.

FEATURES

1. Stereo Decoding

Capable of receiving Sound Intermediate Frequency (SIF) with Selector

and FM Demodulation

Automatic Gain Control (AGC: 100mVpp ~ 1Vpp) for SIF input

Alignment Free Digital Stereo Decoding

EIA-J

NICAM: B/G, L, I, D/K with FM/AM Mono

A2: B/G, D/K1, D/K2, D/K3, M/N

Automatic/Manual Stereo Decoding Standard Selection

Automatic/Manual Audio Mode (Stereo/MONO/two sounds) Selection

Signal Quality Detection for Auto Selection Mode

High FM Deviation Option (max: 540kHz)

I2S sampling rate (fs): 32k/44.1k/48kHz

2. Audio Processing (Two Stereos)

Automatic Level Control (ALC)

Balance

5-band Equalizer

Stereo Separation Emphasis

Digital Volume Control with Soft Mute (+12dB~-115dB, 0.5dB/step)

Audio Data Interface:

I2S input x 5 (2 inputs: SRC available)

I2S output x 3

Master/Slave Mode

Audio Format: 24bit Left justified /Right justified / I²S or TDM

3. Asynchronous Sample Rate Converter (SRC)

Input Sample Rate: 8k~192kHz

fso/fsi: 1/6~6

4. Digital Audio Interface Transmitter (DIT) with Through Mode

5. Integrated X’tal Oscillator

6. Master Clock: 256fs/384fs/512fs/768fs/1024fs

7. I2C-bus Control Interface

8. Power Supply: 1.8V±0.1V, 3.3V±0.3V

9. Ta: -20 ~ 85°C

10. Package: 48pin LQFP

Rev. 0.3-PB

2008/01

- 1 -

[AK4141]

VCOM LFLT1 LFLT2 AVDD2 GND5 AVDD1 GND3 GND4 LRCK SCLK

DVDD GND1 TVDD GND2

VREFH

VREFL

FM Demod &

Stereo Decode

DIT

TXOUT

TXIN

AGC

EIAJ

SIF1

SIF2

Decoder

Prescale

ADC

(SIF)

NICAM

A2

ALC, Vol1

Balance1

Bass/Tre1

3D

SDTO1

SDTO2

SDTO3

SDTI1

SDTI2

SDTI3

Prescale

1/2/3/4

Switch

Matrix

ALC, Vol2

Balance2

Bass/Tre2

3D

LRCK4

SCLK4

SDTI4

SRC

LRCK5

SCLK5

SDTI5

SRC

Prescale

X’tal Osc PLL

Clock Gen

Control

Register

CAD0 CAD1 SCL SDA INT

6M5 4M50 4M51 4M52 MSN IIS

PDN

MCLKI XTI XTO MCKO

Rev. 0.3-PB

2008/01

- 2 -

[AK4141]

■ Ordering Guide

AK4141EQ

AKD4141

-20 ∼ +85°C 48pin LQFP (0.5mm pitch)

Evaluation Board for AK4141

■ Pin Layout

24

23

22

21

20

19

18

17

16

15

14

13

VREFH

VREFL

GND3

SIF2

37

TXOUT

A4M52

SDA

38

39

40

41

42

43

44

45

46

47

48

TVDD

GND2

GND1

DVDD

TXIN

AK4141EQ

VCOM

SIF1

AVDD1

GND4

XTI

Top View

MCLKI

PDN

XTO

GND5

AVDD2

SCL

A4M51

Rev. 0.3-PB

2008/01

- 3 -

[AK4141]

PIN/FUNCTION

No.

1

Pin Name

FILT2

I/O

O

Function

PLL Loop Filter 2 Pin

A 0.68μF capacitor should be connected to GND5 externally.

Hi-Z when PDN Pin = “L”.

Audio Data Format Select Pin. ORed with ODIF bit, ORed with IDIF0 bit.

“L”: 24bit Left justified if IDIF0 bit = “0”(default)

“H”: 24/16 bit IIS

2

IIS

I

3

4

5

6

7

LRCK5

SCLK5

SDTI5

LRCK4

SCLK4

I

Input Channel Clock 5 Pin

Audio Serial Data Clock 5 Pin

Audio Serial Data Input 5 Pin

Input Channel Clock 4 Pin

Audio Serial Data Clock 4 Pin

Audio Serial Data Input 4 Pin

Should be synchronized to LRCK and SCLK when SRC is not used.

Audio Serial Data Input 3 Pin

Audio Serial Data Input 2 Pin

Audio Serial Data Input 1 Pin

8

SDTI4

I

9

10

11

SDTI3

SDTI2

SDTI1

I

Decoder Standard Preference Control 0 Pin for 4.5MHz Carrier

This pin is internally XORed with A4M50 bit (default = “1”).

Decoder Standard Preference Control 1 Pin for 4.5MHz Carrier

This pin is internally XORed with A4M51 bit (default = “1”).

Control Data Clock Pin for I2C bus

12

A4M50

I

13

14

A4M51

SCL

I

Power-Down Mode & Reset Pin

15

PDN

I

When “L”, the AK4141 is powered-down, all registers are reset. And then all

digital output pins go “L”. The AK4141 must be reset once upon power-up.

Master Clock Input Pin

16

17

MCKI

TXIN

I

S/PDIF Input Pin

For through output. No Input Amplifier integrated.

Digital Power Supply Pin, 1.7V~1.9V

Ground Pin, 0V

18

19

20

21

22

DVDD

GND1

GND2

TVDD

SDA

-

Ground Pin, 0V

-

I/O Buffer Power Supply Pin, 1.7V~3.6V

Control Data Pin for I2C bus

I/O

Decoder Standard Preference Control 2 Pin for 4.5MHz Carrier

This pin is internally ORed with A4M52 bit (default = “0”).

S/PDIF Output pin. Outputs “L” when PDN Pin = “L”.

Master Clock Output Pin. Outputs “L” when PDN Pin = “L”.

Audio Serial Data Clock Pin.

23

A4M52

I

24

25

TXOUT

MCKO

O

26

27

SCLK

LRCK

I/O

Outputs “L” when PDN Pin = “L” and MSN Pin = “H”.

Hi-Z when PDN Pin = “L” and MSN Pin = “L”.

Input Channel Clock Pin

Outputs “L” when PDN Pin = “L” and MSN Pin = “H”.

Hi-Z when PDN Pin = “L” and MSN Pin = “L”.

Audio Serial Data Output 3 Pin

Outputs “L” when PDN Pin = “L”.

Audio Serial Data Output 2 Pin

Outputs “L” when PDN Pin = “L”.

Audio Serial Data Output 1 Pin

28

29

30

SDTO3

SDTO2

SDTO1

O

Outputs “L” when PDN Pin = “L”.

Rev. 0.3-PB

2008/01

- 4 -

[AK4141]

PIN/FUNCTION

Interrupt Pin

31

32

INT

O

I

Outputs “L” when PDN Pin = “L”.

Decoder Standard Preference Control for 6.5MHz carrier.

“L”: SECAM L NICAM

“H”: D/K1, D/K2, D/K3 or D/K NICAM

This Pin is internally ORed with A6M5 bit (default = “0”).

Master Mode Select Pin

A6M5

33

MSN

I

“L”: Slave mode if CKS[2:0] bits = “000”(default)

“H”: Master mode of MCLK = 256fs if CKS2 bit = “0”(default)

Chip Address 0 pin

Should match CAD0 bit in I2C first byte.

Chip Address 1 pin

34

35

CAD0

CAD1

I

Should match CAD1 bit in I2C first byte.

PLL Loop Filter 1 Pin

36

37

38

FILT1

VREFH

VREFL

O

A 4.7nF capacitor should be connected to GND3 externally.

Hi-Z when PDN Pin = “L”.

ADC Voltage Reference High Pin

A 0.1μF capacitor should be connected to GND3, and another 0.1μF capacitor

should be connected to VREFL Pin externally. Hi-Z when PDN Pin = “L”.

ADC Voltage Reference Low Pin

A 0.1μF capacitor should be connected to GND3 externally.

Hi-Z when PDN Pin = “L”.

39

40

GND3

SIF2

-

I

Ground Pin, 0V

Sound Intermediate Frequency(SIF) Input 2 Pin

ADC Common Voltage Output Pin.

A 1μF capacitor should be connected to GND3 externally. Hi-Z when PDN Pin =

“L”.

41

VCOM

O

42

43

44

45

SIF1

AVDD1

GND4

XTI

I

-

I

Sound Intermediate Frequency(SIF) Input 1 Pin

Analog Power Supply Pin, 3.0V~3.6V

Ground Pin, 0V

X'tal Input Pin

X'tal Output Pin.

46

XTO

O

Outputs “L” when PDN pin = “L”.

Ground Pin, 0V

Analog Power Supply Pin, 3.0V~3.6V

47

48

GND5

AVDD2

-

Note: All digital input pins should not be left floating.

Rev. 0.3-PB

2008/01

- 5 -

[AK4141]

■ Handling of Unused Pin

The unused I/O pins should be processed appropriately as below.

Classification Pin Name

Setting

These pins should be connected to GND

through 10nF capacitor.

Analog

SIF1, SIF2

TXOUT, MCLKO, SDTO1, SDTO2, SDTO3, INT,

LRCK(master mode), SCLK(master mode)

These pins should be open.

LRCK5, SCLK5, SDTI5, LRCK4, SCLK4, SDTI4,

LRCK(slave mode), SCLK(slave mode), SDTI3,

SDTI2, SDTI1, A4M50, A4M51, A4M52, A6M5,

SCL, MCLKI, TXIN, SDA, IIS, MSN, CAD1, CAD0

These pins should be connected to GND.

Digital

ABSOLUTE MAXIMUM RATINGS

(GND1=GND2=GND3=GND4=GND5=0V; Note 1)

Parameter

Power Supplies

Symbol

AVDD

DVDD

TVDD

IIN

VINA

VIND

Ta

min

-0.3

-

−0.3

−20

−65

max

4.3

2.4

4.3

±10

Units

V

mA

V

°C

Analog

Digital

Digital I/O

Input Current, Any Pin Except Supply

Analog Input Voltage (SIF1, SIF2 pin)

Digital Input Voltage (Note 2)

Ambient Temperature (powered applied)

Storage Temperature

AVDD+0.3

TVDD+0.3

85

Tstg

150

Note 1. All voltages with respect to ground.

Note 2. LRCK5, SCLK5, SDTI5, LRCK4, SCLK4, SDTI4, LRCK(slave mode), SCLK(slave mode), SDTI3, SDTI2,

SDTI1, A4M50, A4M51, A4M52, A6M5, SCL, MCLKI, TXIN, SDA, IIS, MSN, CAD1 and CAD0 pin.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(GND1=GND2=GND3=GND4=GND5=0V; Note 1)

Parameter

Power Supplies

Symbol

AVDD

DVDD

TVDD

min

3.0

1.7

typ

3.3

1.8

3.3

max

3.6

1.9

Units

V

AVDD

DVDD

TVDD

DVDD

3.6

V

WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.

Rev. 0.3-PB

2008/01

- 6 -

[AK4141]

AUDIO CHARACTERISTICS

(Ta=25°C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;

SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=50Hz ∼ 13kHz; unless otherwise specified)

SIF & Demodulator Parameter

min

typ

max

Units

SIF Input Impedance

GSEL bit = 0

GSEL bit = 1

SIF Separation (Note 3)

AGC step width

4.05

5.09

40

4.50

5.66

kohm

dB

0.64

dB

Input Voltage

1 or 2 FM Carriers

GSEL bit = “0”

GSEL bit = “1”

0.1

1.4

1.0

Vpp

1 FM and 1 NICAM Carrier

GSEL bit = “0”

0.1

1.4

1.0

Vpp

GSEL bit = “1”

1 AM and 1 NICAM Carrier

GSEL bit = “0”

0.1

0.8

Vpp

GSEL bit = “1”

1 NICAM Only

GSEL bit = “0”

GSEL bit = “1”

0.05

1.0

Vpp

Max FM-deviation (approx.)

Normal

+/-180

+/-360

+/-540

max

kHz

Units

dB

High deviation

Very High Deviation

NICAM Characteristics

Output level (1kHz, 0dBr)

S/N

min

-1.5

74

typ

+1.5

80

dB

THD+N

0.05

0.15

1

+1

%

NICAM Bit Error Rate (FM+ NICAM, normal condition)

Frequency response (20 ~ 15kHz, -12dB, dual)

NICAM Crosstalk attenuation (dual)

Channel separation (stereo)

FM Characteristics (Note 4)

Output level (1kHz, 0dBr)

S/N

10^-7

dB

-1

80

min

-1.5

67

dB

Units

dB

typ

max

+1.5

73

THD+N

0.1

0.3

+1

%

dB

Units

dB

Frequency response (20 ~ 12kHz, -12dB, dual)

FM Crosstalk attenuation (dual)

Channel separation (stereo)

AM Characteristics

S/N

-1

75

30

min

47

85

40

typ

62

max

THD+N

1.2

3

%

Frequency response (20 ~ 12kHz, -12dB, dual)

-2.5

+1

dB

Note 3. Selected SIF pin is connected to GND through 10nF capacitor.

Note 4. 1 FM-Carrier, 5.5MHz.

Rev. 0.3-PB

2008/01

- 7 -

[AK4141]

AUDIO CHARACTERISTICS (Continued)

(Ta=25°C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;

SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=50Hz ∼ 13kHz; unless otherwise specified)

EIAJ Characteristics

min

typ

max

Units

S/N

Stereo

Sub

54

60

dB

THD+N (1kHz L or R or Sub 100%)

Stereo

0.3

0.9

%

Sub

Frequency response

Stereo (20 ~ 12kHz, 100%EIM)

Sub (20 ~ 12kHz, 100%EIM)

Channel separation (stereo)

-1

30

+1

dB

40

SRC CHARACTERISTICS

(Ta=25°C; AVDD=3.3V, DVDD=1.8V, TVDD=3.3V; GND1=GND2=GND3=GND4=GND5=0V; fs=48kHz;

SCLK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ~ FSO/2; unless otherwise specified)

Parameter

Symbol

min

typ

max

Units

SRC Characteristics:

Resolution

Input Sample Rate

Output Sample Rate

20

216

48

Bits

kHz

FSI

FSO

8

32

THD+N

(Input = 1kHz, 0dBFS, Note 5)

FSO/FSI = 48kHz/8kHz

FSO/FSI = 48kHz/32kHz

FSO/FSI = 48kHz/192kHz

Worst Case (FSO/FSI = 32kHz/176.4kHz)

-

-100

-

dB

TBD

Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 5)

FSO/FSI = 48kHz/8kHz

FSO/FSI = 48kHz/32kHz

FSO/FSI = 48kHz/192kHz

Worst Case (FSO/FSI = 48kHz/32kHz)

Ratio between Input and Output Sample Rate

-

103

-

6

dB

-

TBD

1/6

FSO/FSI

Note 5. Measured by Audio Precision System Two Cascade.

Power Supplies

Parameter

min

typ

max

Units

Power Supply Current

Normal Operation (PDN pin = “H”)

TVDD

AVDD1+AVDD2

DVDD

5

20

70

TBD

mA

Power-Down Mode (PDN pin = “L”; Note: 1)

TVDD

AVDD1+AVDD2

DVDD

10

100

μA

Note: 1. All digital inputs including clock pins are held at DVDD or GND.

Rev. 0.3-PB

2008/01

- 8 -

[AK4141]

SRC FILTER CHARACTERISTICS

(Ta=25°C; AVDD=3.0 ∼ 3.6V, DVDD=1.7V∼ 1.9V, TVDD=1.7 ∼ 3.6V; GND1=GND2=GND3=GND4=GND5=0V)

Parameter

Symbol

min

typ

max

Units

Digital Filter

Passband −0.01dB

0.985 ≤ FSO/FSI ≤ 6.000

0.905 ≤ FSO/FSI < 0.985

0.714 ≤ FSO/FSI < 0.905

0.656 ≤ FSO/FSI < 0.714

0.536 ≤ FSO/FSI < 0.656

0.492 ≤ FSO/FSI < 0.536

0.452 ≤ FSO/FSI < 0.492

0.357 ≤ FSO/FSI < 0.452

0.324 ≤ FSO/FSI < 0.357

0.246 ≤ FSO/FSI < 0.324

0.226 ≤ FSO/FSI < 0.246

0.1667 ≤ FSO/FSI < 0.226

0.985 ≤ FSO/FSI ≤ 6.000

0.905 ≤ FSO/FSI < 0.985

0.714 ≤ FSO/FSI < 0.905

0.656 ≤ FSO/FSI < 0.714

0.536 ≤ FSO/FSI < 0.656

0.492 ≤ FSO/FSI < 0.536

0.452 ≤ FSO/FSI < 0.492

0.357 ≤ FSO/FSI < 0.452

0.324 ≤ FSO/FSI < 0.357

0.246 ≤ FSO/FSI < 0.324

0.226 ≤ FSO/FSI < 0.246

0.1667 ≤ FSO/FSI < 0.226

PB

SB

PR

SA

0

0.4583FSI

0.4167FSI

0.3195FSI

0.2852FSI

0.2182FSI

0.2177FSI

0.1948FSI

0.1458FSI

0.1302FSI

0.0917FSI

0.0826FSI

0.0583FSI

kHz

dB

Stopband

0.5417FSI

0.5021FSI

0.3965FSI

0.3643FSI

0.2974FSI

0.2813FSI

0.2604FSI

0.2116FSI

0.1969FSI

0.1573FSI

0.1471FSI

0.1020FSI

Passband Ripple

Stopband

Attenuation

±0.01

0.985 ≤ FSO/FSI ≤ 6.000

0.905 ≤ FSO/FSI < 0.985

0.714 ≤ FSO/FSI < 0.905

102.2

100.4

99.0

dB

0.656 ≤ FSO/FSI < 0.714

0.536 ≤ FSO/FSI < 0.656

0.492 ≤ FSO/FSI < 0.536

0.452 ≤ FSO/FSI < 0.492

0.357 ≤ FSO/FSI < 0.452

0.324 ≤ FSO/FSI < 0.357

0.246 ≤ FSO/FSI < 0.324

0.226 ≤ FSO/FSI < 0.246

0.1667 ≤ FSO/FSI < 0.226

(Note 6)

SA

GD

101.6

99.5

95.2

96.6

97.0

94.4

95.8

95.0

73.7

-

dB

1/fs

Group Delay

56

-

Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output,

when LRCK for Output data corresponds with LRCK for Input.

Rev. 0.3-PB

2008/01

- 9 -

[AK4141]

DC CHARACTERISTICS

(Ta=25°C; AVDD=3.0 ∼ 3.6V, DVDD=1.7V∼ 1.9V, TVDD=1.7 ∼ 3.6V; GND1=GND2=GND3=GND4=GND5=0V)

Parameter

Symbol

min

typ

max

Units

High-Level Input Voltage

TVDD < 2.7V

VIH

80%TVDD

70%TVDD

-

V

TVDD ≥ 2.7V

Low-Level Input Voltage

TVDD < 2.7V

VIL

-

20%TVDD

30%TVDD

V

TVDD ≥ 2.7V

High-Level Output Voltage ( Iout=-400μA)

Low-Level Output Voltage

VOH

VOL

TVDD-0.4

-

0.4

V

(Iout= -400μA(except SDA pin), 3mA(SDA pin))

Input Leakage Current

Iin

-

±10

μA

SWITCHING CHARACTERISTICS

(Ta=-20∼ 85°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;

C_L=20pF, Cb=400pF(SDA pin))

Parameter

Symbol

min

typ

max

Units

Crystal Resonator Frequency

fs=32kHz

fXTAL

256fs

8.192

11.2896

12.288

MHz

fs=44.1kHz

fs=48kHz

Master Clock Timing

Master Clock

128fs:

Pulse Width Low

Pulse Width High

192fs:

Pulse Width Low

Pulse Width High

256fs:

Pulse Width Low

Pulse Width High

384fs:

Pulse Width Low

Pulse Width High

512fs:

Pulse Width Low

Pulse Width High

768fs:

Pulse Width Low

Pulse Width High

1024fs:

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

4.096

65

6.144

43

8.192

27

12.288

20

16.384

16

24.576

11

6.144

9.216

MHz

ns

MHz

ns

MHz

ns

MHz

ns

MHz

ns

MHz

ns

MHz

ns

12.288

18.432

24.576

36.864

49.152

32.768

8

Pulse Width Low

Pulse Width High

tCLKL

tCLKH

8

Rev. 0.3-PB

2008/01

- 10 -

[AK4141]

SWITCHING CHARACTERISTICS (Continued)

(Ta=-20∼ 85°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;

C_L=20pF, Cb=400pF(SDA pin))

Parameter (Note 8)

Symbol

min

typ

max

Units

LRCK Timing (Slave Mode)

Normal mode (TDM=“0”)

LRCK Frequency

fs

Duty

32

45

48

55

kHz

%

Duty Cycle

TDM256 mode (TDM=“1”)

LRCK Frequency

fs

tLRH

tLRL

32

1/256fs

48

kHz

ns

“H” time

“L” time

SRC Input

LRCK Frequency

Duty Cycle

fs

Duty

8

45

192

55

KHz

%

LRCK Timing (Master Mode)

Normal mode (TDM=“0”)

LRCK Frequency

fs

Duty

32

48

kHz

%

Duty Cycle

TDM256 mode (TDM=“1”)

LRCK Frequency

50

fs

tLRH

kHz

ns

“H” time

(Note 7)

1/8fs

Audio Interface Timing (Slave mode)

Normal mode (TDM=“0”)

SCLK Period

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRS

tBSD

tSDH

tSDS

160

65

30

ns

SCLK Pulse Width Low

Pulse Width High

LRCK Edge to SCLK “↑”

SCLK “↑” to LRCK Edge

(Note 9)

LRCK to SDTO(MSB) (Except I²S mode)

SCLK “↓” to SDTO

35

SDTI Hold Time

SDTI Setup Time

10

TDM256 mode (TDM=“1”)

SCLK Period

SCLK Pulse Width Low

Pulse Width High

LRCK Edge to SCLK “↑”

SCLK “↑” to LRCK Edge

SCLK “↓” to SDTO

TDMIN Hold Time

TDMIN Setup Time

SRC Input (Note 10)

SCLK Period

SCLK Pulse Width Low

Pulse Width High

LRCK Edge to SCLK “↑”

SCLK “↑” to LRCK Edge

SDTI Hold Time

tBCK

tBCKL

tBCKH

tLRB

tBLR

tBSD

81

32

20

ns

(Note 9)

20

tSDH

tSDS

10

tBCK

tBCKL

tBCKH

tLRB

tBLR

tSDH

tSDS

81

32

20

10

ns

(Note 9)

SDTI Setup Time

Rev. 0.3-PB

2008/01

- 11 -

[AK4141]

SWITCHING CHARACTERISTICS (Continued)

(Ta=-20∼ 85°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;

C_L=20pF, Cb=400pF(SDA pin))

Parameter (Note 8)

Symbol

min

typ

max

Units

Audio Interface Timing (Master mode)

Normal mode (TDM=“0”)

SCLK Frequency

fBCK

dBCK

tMBLR

tBSD

64fs

50

Hz

%

ns

SCLK Duty

SCLK “↓” to LRCK

SCLK “↓” to SDTO

−20

−40

20

40

TDM256 mode (TDM=“1”)

SCLK Frequency

SCLK Duty

SCLK “↓” to LRCK

SCLK “↓” to SDTO

TDMIN Hold Time

TDMIN Setup Time

fBCK

dBCK

tMBLR

tBSD

tSDH

tSDS

256fs

50

Hz

%

ns

(Note 11)

−12

−20

10

12

20

10

Power-Down & Reset Timing

PDN Pulse Width

(Note 12)

(Note 13)

tPD

tPDV

150

ns

1/fs

PDN “↑” to SDTO valid

TBD

Note 7. “L” time at I²S format.

Note 8. SCLK= SCLK/SCLK4/SCLK5, LRCK= SCLK/LRCK4/LRCK5 unless otherwise specified.

Note 9. SCLK rising edge must not occur at the same time as LRCK edge.

Note 10. SCLK= SCLK4/SCLK5, LRCK= LRCK4/LRCK5.

Note 11. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.

Note 12. The AK4141 can be reset by bringing the PDN pin = “L”.

Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”.

Parameter

Symbol

min

typ

max

Units

Control Interface Timing (I²C Bus):

SCL Clock Frequency

fSCL

tBUF

tHD:STA

-

1.3

0.6

400

-

kHz

μs

Bus Free Time Between Transmissions

Start Condition Hold Time

(prior to first clock pulse)

Clock Low Time

Clock High Time

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

1.3

0.6

0

0.1

-

0.6

0

-

0.9

-

0.3

-

μs

ns

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling (Note 14)

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

Pulse Width of Spike Noise

Suppressed by Input Filter

tF

tSU:STO

tSP

50

Capacitive load on bus

Cb

0

400

pF

Note 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Note 15. I²C is a registered trademark of Philips Semiconductors.

Rev. 0.3-PB

2008/01

- 12 -

[AK4141]

■ Timing Diagram

1/fCLK

VIH

VIL

MCLK

tCLKH

tCLKL

1/fs

VIH

VIL

LRCK

SCLK

tBCK

VIH

VIL

tBCKH

tBCKL

Figure 1. Clock Timing (TDM bit = “0”)

1/fCLK

VIH

VIL

MCLK

LRCK

SCLK

tCLKH

tCLKL

1/fs

VIH

VIL

tLRH

tLRL

tBCK

VIH

VIL

tBCKH

tBCKL

Figure 2. Clock Timing (TDM bit = “1”)

Rev. 0.3-PB

2008/01

- 13 -

[AK4141]

VIH

VIL

LRCK

tBLR

tLRB

VIH

VIL

SCLK

SDTO

tLRS

tBSD

50%TVDD

Figure 3. Audio Interface Timing (Slave mode, Normal Mode)

VIH

VIL

LRCK

SCLK

SDTO

tBLR

tLRB

VIH

VIL

tBSD

50%TVDD

tSDS

tSDH

VIH

VIL

SDTI

Figure 4. Audio Interface Timing (Slave mode, TDM Mode)

Rev. 0.3-PB

2008/01

- 14 -

[AK4141]

LRCK

SCLK

SDTO

SDTI

50%TVDD

tMBLR

tBSD

50%TVDD

tDXS

tDXH

VIH

VIL

Figure 5. Audio Interface Timing (Master mode, Normal Mode)

LRCK

SCLK

SDTO

50%TVDD

tMBLR

50%TVDD

tBSD

tSDS

tSDH

VIH

VIL

TDMIN

Figure 6. Audio Interface Timing (Master mode, TDM Mode)

VIH

PDN

VIL

tPDV

SDTO

PDN

50%VDD

tPD

VIL

Figure 7. Power Down & Reset Timing

Rev. 0.3-PB

2008/01

- 15 -

[AK4141]

VIH

VIL

SDA

SCL

tLOW tR

tHIGH

tBUF

tF

tSP

VIH

VIL

tHD:STA

Stop Start

tHD:DAT

tSU:DAT tSU:STA

Start

tSU:STO

Stop

Figure 8. I²C Bus mode Timing

Rev. 0.3-PB

2008/01

- 16 -

[AK4141]

PACKAGE

48pin LQFP(Unit:mm)

1.70Max

9.0 ± 0.2

0.13 ± 0.13

7.0

1.40 ± 0.05

36

25

37

24

48

13

1

12

0.5

0.22 ± 0.1

0.10 M

0° ∼ 10°

0.10

0.3~0.75

■ Package & Lead frame material

Package molding compound:

Lead frame material:

Lead frame surface treatment:

Epoxy

Cu

Solder (Pb free) plate

Rev. 0.3-PB

2008/01

- 17 -

[AK4141]

MARKING

AK4141EQ

XXXXXXX

1

XXXXXXX: Date code identifier

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

EMD Corporation (AKEMD) or authorized distributors as to current status of the products.

z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or

use of any information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,

or strategic materials.

z AKEMD products are neither intended nor authorized for use as critical components_Note1)in any safety, life support, or

other hazard related device or system_Note2), and AKEMD assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKEMD. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or

for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform

may reasonably be expected to result in loss of life or in significant injury or damage to person or property.

z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise

places the product with a third party, to notify such third party in advance of the above content and conditions, and the

buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any

and all claims arising from the use of said product in the absence of such notification.

Rev. 0.3-PB

2008/01

- 18 -

[AK4141]

Thank you for your access to AKEMD products information.

More detail product information is available, please contact our

sales office or authorized distributors.

Rev. 0.3-PB

2008/01

- 19 -

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