AK4425A [AKM]
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output; 192kHz的24位立体声DAC ΔΣ具有2Vrms的输出
| 型号： | AK4425A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output |
| 文件： | 总27页 (文件大小：393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK4425A]
AK4425A
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4425A is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4425A delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4425A integrates a combination of
switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock
jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer
audio applications, such as DVD, AV receiver system and set-top boxes. The AK4425A is offered in a
space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz
Soft mute
Digital Attenuator (Linear 256 Step)
Control I/F: 3-wire
Audio I/F format: 24Bit MSB justified, 24/20/16 LSB justified or
I2S compatible
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -91dB
Dynamic Range: 106dB
Automatic Power-on Reset Circuit
Power supply: +4.5 ∼ +5.5V
Ta = -20 to 85°C
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
MS1127-E-01
2011/03
- 1 -
[AK4425A]
MCLK
AVDD
CSN
CCLK
CDTI
Clock
Divider
De-emphasis
Control
Control
Interface
VSS2
8X
ΔΣ
SCF
LPF
AOUTL
LRCK
Modulator
Interpolator
Audio
Data
Interface
BICK
SDTI
8X
ΔΣ
Modulator
SCF
LPF
AOUTR
Interpolator
Charge
Pump
CP
CN VEE
VSS1
VDD
1μ
1μ
Block Diagram
MS1127-E-01
2011/03
- 2 -
[AK4425A]
■ Ordering Guide
AK4425AET
AKD4425A
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4425A
■ Pin Layout
VSS1
CP
VDD
MCLK
BICK
1
2
3
16
15
14
13
12
11
10
9
CN
VEE
SDTI
4
5
6
7
8
AK4425A
Top
AOUTL
VSS2
AVDD
AOUTR
LRCK
CSN
View
CCLK
CDTI
■ Compatibility with the AK4426
Functions
Power Supply
DC Offset
THD+N
DR
AK4426
AK4425A
Å
± 5mV
Å
+4.5 ∼ +5.5V
± 8mV
-91dB
106dB
Å
Å
Å
Å
DEM
SMUTE
Digital ATT
X
X
X
24-bit MSB/ I²S/
24,20,16bitLSB
I²C
ET: -20 ∼ +85°C
VT: -40 ∼ +85°C
I/F Format
Å
Å
Å
Control I/F
Operating Temperature
-: Not available
X: Available
MS1127-E-01
2011/03
- 3 -
[AK4425A]
PIN/FUNCTION
No. Pin Name
I/O
-
Function
1
Digital Circuit and Charge Pump Circuit Power Supply Pin: 4.5V∼5.5V
Master Clock Input Pin
VDD
2
MCLK
I
An external TTL clock must be input on this pin.
3
4
5
6
7
8
Audio Serial Data Clock Pin
BICK
SDTI
LRCK
CSN
I
I
I
I
I
I
Audio Serial Data Input Pin
L/R Clock Pin
Chip Select Pin
Control Clock input Pin
CCLK
CDTI
Control Data Input Pin
Rch Analog Output Pin
9
AOUTR
O
When power down, outputs VSS(0V, typ).
10
11
Analog Block Power Supply Pin: 4.5V∼5.5V
Ground Pin2
AVDD
VSS2
-
-
Lch Analog Output Pin
12
AOUTL
O
When power down, outputs VSS(0V, typ).
Negative Voltage Output Pin
Connect to VSS1 with a 1.0μF capacitor which is low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the
polarity, the positive polarity pin must be connected to the VSS1 pin. Non
polarity capacitors can also be used.
13
VEE
O
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor which is low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity,
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
14
CN
I
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor which is low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity,
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
15
16
CP
I
-
Ground Pin1
VSS1
Note: All input pins except for the CN pin should not be left floating.
MS1127-E-01
2011/03
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[AK4425A]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
CVDD
IIN
VIND
Ta
min
-0.3
-0.3
-
-0.3
-20
-65
max
+6.0
+6.0
Units
V
V
mA
V
°C
°C
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
±10
VDD+0.3
85
150
Tstg
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 1)
Parameter
Power Supply
Symbol
VDD
AVDD
min
+4.5
typ
+5.0
VDD
max
+5.5
Units
V
Note 3. AVDD should be equal to VDD
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1127-E-01
2011/03
- 5 -
[AK4425A]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics (Note 4)
THD+N
fs=44.1kHz, BW=20kHz
fs=96kHz, BW=40kHz
fs=192kHz, BW=40kHz
-91
-91
-91
106
106
100
0
-84
-
-
dB
dB
dB
dB
dB
dB
dB
Dynamic Range (-60dBFS with A-weighted. (Note 5)
S/N (A-weighted. (Note 6)
Interchannel Isolation (1kHz)
Interchannel Gain Mismatch
DC Accuracy
100
100
90
0.5
DC Offset
Gain Drift
Output Voltage (Note 7)
Load Capacitance (Note 8)
Load Resistance
(at output pin)
-5
2.05
5
0
100
2.2
+5
-
2.35
25
mV
ppm/°C
Vrms
pF
kΩ
Power Supplies
Power Supply Current: (Note 9)
24
27
10
36
40
100
mA
mA
μA
Normal Operation (fs≤96kHz)
Normal Operation (fs=192kHz)
Power-Down Mode (Note 10)
Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 5. 98dB for 16bit input data
Note 6. S/N does not depend on input data size.
Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD,
AOUT (typ.@0dB) = 2.2Vrms × VDD/5.
Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 9. The current into VDD and AVDD.
Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS1(VSS2) or VDD(AVDD).
MS1127-E-01
2011/03
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[AK4425A]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V; fs = 44.1 kHz; DEM = OFF; SLOW = “0”)
Parameter
Digital filter
Passband
Symbol
min
typ
max
Units
PB
0
-
24.1
20.0
-
kHz
kHz
kHz
dB
dB
1/fs
±0.05dB (Note 11)
22.05
–6.0dB
Stopband (Note 11)
Passband Ripple
Stopband Attenuation
Group Delay (Note 12)
SB
PR
SA
GD
± 0.02
54
-
19.3
-
Digital Filter + LPF
Frequency Response 20.0kHz fs=44.1kHz
40.0kHz fs=96kHz
FR
FR
FR
-
-
-
-
-
-
dB
dB
dB
± 0.05
± 0.05
± 0.05
80.0kHz fs=192kHz
Note 11. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 12. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data
of both channels to input register to the output of the analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter
Digital Filter
Passband
Symbol
min
typ
max
Units
±0.04dB (Note 13)
-3.0dB
PB
0
-
8.1
-
kHz
kHz
kHz
dB
18.2
Stopband
(Note 13)
SB
PR
SA
GD
39.2
Passband Ripple
Stopband Attenuation
Group Delay
± 0.005
72
-
dB
(Note 12)
19.3
-
1/fs
Digital Filter + LPF
Frequency Response
FR
FR
FR
-
-
-
+0/-5
+0/-4
+0/-5
-
-
-
dB
dB
dB
fs=44.kHz
fs=96kHz
fs=192kHz
20.0kHz
40.0kHz
80.0kHz
Note 13. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.185×fs (@±0.04dB), SB=0.888×fs.
MS1127-E-01
2011/03
- 7 -
[AK4425A]
DC CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
Symbol
VIH
VIL
min
2.2
-
typ
max
-
0.8
Units
V
V
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
-
-
-
Iin
-
± 10
μA
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V)
Parameter
Master Clock Frequency
Symbol
fCLK
dCLK
min
2.048
30
Typ
11.2896
max
36.864
70
Units
MHz
%
Duty Cycle
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
fsn
fsd
8
48
96
kHz
kHz
kHz
%
32
fsq
120
45
192
55
Duty Cycle
Audio Interface Timing
BICK Period
Duty
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 14)
LRCK Edge to BICK “↑” (Note 14)
SDTI Hold Time
30
20
20
20
20
SDTI Setup Time
Control Interface Timing
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCSH
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
MS1127-E-01
2011/03
- 8 -
[AK4425A]
■ Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
VIL
LRCK
BICK
tBCK
VIH
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
LRCK
BICK
SDTI
VIL
tBLR
tLRB
VIH
VIL
tSDS
tSDH
VIH
VIL
Figure 2. Serial Interface Timing
MS1127-E-01
2011/03
- 9 -
[AK4425A]
VIH
VIL
CSN
tCSS
tCCKL tCCKH
VIH
VIL
CCLK
CDTI
tCDS tCDH
C0
VIH
VIL
C1
R/W
A4
Figure 3. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
VIL
CCLK
CDTI
VIH
VIL
D3
D2
D1
D0
Figure 4. WRITE Data Input Timing
MS1127-E-01
2011/03
- 10 -
[AK4425A]
OPERATION OVERVIEW
■ System Clock
The external clocks required to operate the AK4425A are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There
are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the sampling speed is set
by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table 2) When the power
applied, the AK4425A is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is
detected automatically (Table 3), and the internal master clock becomes the appropriate frequency (Table 4), it is not
necessary to set DFS0/1.
The AK4425A is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal
operation mode, and the analog output is forced to 0V(typ). When MCLK, LRCK and BICK are input again, the
AK4425A is powered up. After power-up, the AK4425A is in the power-down mode until MCLK, LRCK and BICK are
input.
DFS1
DFS0
Sampling Rate (fs)
(default)
0
0
1
0
1
0
Normal Speed Mode
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Double Speed Mode
Quad Speed Mode
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
(kHz)
fs
BICK
(MHz)
64fs
Sampling
Speed
MCLK (MHz)
DFS1 DFS0
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
0
0
0
0
0
1
1
0
0
0
1
1
0
0
32.0
44.1
48.0
88.2
96.0
-
-
-
-
-
-
8.1920
12.2880 16.3840 24.5760 36.8640
2.0480
2.8224
3.0720
5.6448
6.1440
11.2896
12.2880
Normal
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
-
-
-
-
-
-
11.2896 16.9344 22.5792 33.8688
12.2880 18.4320 24.5760 36.8640
22.5792 33.8688
24.5760 36.8640
-
-
-
-
-
-
-
-
Double
Quad
176.4
192.0
-
-
-
-
Table 2. System Clock Example
MCLK
1152fs
Sampling Speed
Normal (fs=32kHz only)
512fs
256fs
128fs
768fs
384fs
192fs
Normal
Double
Quad
Table 3. Sampling Speed(Auto Setting Mode: Default)
MS1127-E-01
2011/03
- 11 -
[AK4425A]
LRCK
fs
MCLK (MHz)
Sampling
Speed
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
32.0kHz
44.1kHz
48.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
-
-
-
-
-
-
-
-
-
-
-
-
16.3840
22.5792
24.5760
24.5760 36.8640
Normal
33.8688
36.8640
-
-
8.192
11.2896
12.288
22.5792
24.5760
-
12.288
16.9344
18.432
33.8688
36.8640
-
Double
Quad
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
22.5792
24.5760
33.8688
36.8640
-
-
Table 4. System Clock Example (Auto Setting Mode)
When MCLK= 256fs/384fs, the AK4425A supports sampling rate of 32kHz~96kHz in auto setting mode (Table 4). But,
when the sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=
512fs/768fs.
MCLK
256fs/384fs
512fs/768fs
DR,S/N
103dB
106dB
Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) (Auto Setting Mode)
■ Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF2-0 bit can select within five
serial data modes as shown in Table 6. In all modes the serial data is MSB-first, two’s complement format and it is latched
on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0
SDTI Format
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
0
1
2
3
4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
24bit LSB Justified
Figure 5
Figure 6
Figure 7
Figure 8
Figure 6
(default)
Table 6. Audio Data Format in Serial control mode
MS1127-E-01
2011/03
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[AK4425A]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15 14
6
5
4
3
2
1
0
0
15 14
6
5
4
3
2
1
0
0
15 14
0
1
14
15
16
17
31
0
1
14
15
16
17
31
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15 14
Don’t care
15 14
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 5. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
0
1
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
0
Don’t care
Don’t care
19
0
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23 22 21 20 19
23 22 21 20 19
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 1/4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
23 22
23:MSB, 0:LSB
1
0
Don’t care
23 22
1
0
Don’t care
23 22
Lch Data
Rch Data
Figure 7. Mode 2 Timing
MS1127-E-01
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[AK4425A]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
23:MSB, 0:LSB
Don’t care
23 22
1
0
Don’t care
23
Lch Data
Figure 8. Mode 3 Timing
Rch Data
MS1127-E-01
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[AK4425A]
■ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and it is enabled or disabled
by DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always OFF.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
(default)
48kHz
32kHz
Table 7. De-emphasis Filter Control (Normal Speed Mode)
■ Analog Output Block
The internal negative power supply generation circuit (Figure 9) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4425A to output an audio signal centered at VSS (0V, typ) as shown in Figure 10. The negative
power generation circuit (Figure 9) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS1 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4425A is placed in the reset mode automatically and the
analog outputs settle to VSS (0V, typ).
AK4425
VDD
Charge
Pump
Negative Power
CP
CN
VEE
VSS1
Cb
(+)
1uF
(+)
Ca
1uF
Figure 9. Negative Power Generation Circuit
AK4425
2.2Vrms
0V
AOUTR
(AOUTL)
Figure 10. Audio Signal Output
MS1127-E-01
2011/03
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[AK4425A]
■ Output Volume
The AK4425A includes channel independent digital output volumes (ATT) with 256 levels at linear step including
MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When
changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The
transition time of 1 level and all 256 levels is shown in Table 8.
Transition Time
Sampling Speed
1 Level
4LRCK
8LRCK
255 to 0
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
1020LRCK
2040LRCK
4080LRCK
16LRCK
Table 8. ATT Transition Time
■ Soft Mute Operation
Soft mute operation is performed in digital domain. When the SMUTE bit is set to “1”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 8) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT
level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit
(1)
(1)
ATT Level
Attenuation
(3)
-∞
GD
GD
(2)
AOUT
Notes:
(1) ATT_DATA×ATT transition time (Table 8). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
Figure 11. Soft Mute function
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[AK4425A]
■ System Reset
The AK4425A is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped
up. The AK4425A is in power-down mode until LRCK are input.
tW<20ms
Power Supply0.8xVDD
0.3V
(VDD, AVDD)
(1)
Low
MCLK
20 µs
Reset Release
(3)
Internal
Reset
50ms(max)
(2)
Reset
Audio circuit
Power-up
Power-up
2, 3
LRCK Clocks
(4)
Power down
Charge Pump
Circuit
Time A
(5)
VEE Pin
0V
0V
“0” data
D/A In
(Digital)
D/A Out
(Analog)
Active (D/A Out)
MUTE (D/A Out)
Notes:
(1) The AK4425A includes an internal Power on Reset Circuit which is used reset the digital logic into a default state after
power up. Therefore, the power supply voltage must reach 80% VDD from 0.3V in less than 20msec.
(2) Register writings are valid after 50ms (max).
(3) When internal reset is released, approximately 20us after a MCLK input, the internal analog circuit is powered-up.
(4) The digital circuit and charge pump circuit are powered-up in 2, 3 LRCK cycle when the analog circuit is powered-up.
(5) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/(fs x 16): Normal speed mode
Time A = 1024/(fs x 8): Double speed mode
Time A = 1024/(fs x 4): Quad speed mode
Figure 12. System Reset Diagram
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[AK4425A]
■ Reset Function
When the MCLK, LRCK or BICK stops, the AK4425A is placed in reset mode and its analog outputs are set to VSS (0V,
typ). When the MCLK, LRCK and BICK are restarted, the AK4425A returns to normal operation mode.
Internal
Normal Operation
Reset
Normal Operation
State
D/A In
(Digital)
(1)
GD
(2)
(3)
(4)
(3)
VSS
D/A Out
(Analog)
<Case1:MCLK Stop>
Clock In
MCLK, BICK, LRCK
MCLK Stop
<Case2:LRCK Stop>
Clock In
MCLK, BICK, LRCK
(4)
LRCK Stop
<Case3:BICK Stop>
Clock In
MCLK, BICK, LRCK
(4) BICK Stop
Notes:
(1) Digital data can be stopped. The click noise after MCLK, LRCK and BICK are input again can be reduced by
inputting the “0” data during this period.
(2) The analog output corresponding to a specific digital input has group delay (GD).
(3) No audible click noise occurs under normal conditions.
(4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
Figure 13. Reset Timing Example
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[AK4425A]
■ Mode Control Interface
The function of the AK4425A can be controlled by register settings. The register can be accessed 50msec(max) after
power up the AK4425A. Internal registers may be written to 3-wire µP interface pins, CSN, CCLK and CDTI. The data
on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only),
Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). Address and data are clocked in on the rising
edge of CCLK. For write operations, the data is latched after a low-to-high transition of the 16th CCLK. The clock speed
of CCLK is 5MHz(max).
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (Fixed to “01”)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 14. 3-wire Serial Control I/F Timing
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[AK4425A]
■ Register Map
Addr
00H
Register Name
D7
D0
Control 1
ACKS
RSTN
01H
02H
03H
04H
Control 2
Control 3
Lch ATT
Rch ATT
0
ATT5
ATT4
ATT3
ATT2
ATT1
SMUTE
0
ATT0
ATT0
RRST
ATT7
ATT7
ATT6
Notes:
Do not write any data to the register over 05H directly.
Writing “1” to D7 and D6 of Addr01H and D2 of Addr02H is ignored.
The bits defined as 0 must contain a “0” value.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
Do not write the registers within 50msec after the power supplies are fed.
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[AK4425A]
■ Register Definitions
Addr Register Name
D7
ACKS
1
0
1
0
1
D0
RSTN
1
00H Control 1
default
0
0
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
The click noise, which occurs when MCLK frequency or DFS is changed, can be reduced by RSTN
bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (Table 6)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the settings of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
Register Name
D7
0
0
0
0
0
1
D0
SMUTE
0
01H Control 2
default
0
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft muted
DEM1-0: De-emphasis Response (Table 7)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal Speed Mode
01: Double Speed Mode
10: Quad Speed Mode
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
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[AK4425A]
Addr
Register Name
D7
RRST
0
0
0
D0
0
02H Control 3
default
0
0
0
0
0
INVR: Inverting Lch Output Polarity
0: Normal Output
1: Inverted Output
INVL: Inverting Rch Output Polarity
0: Normal Output
1: Inverted Output
RRST: Register Reset
0: Normal Operation
1: Register Reset (except RRST bit)
Addr
Register Name
D7
D0
03H Lch ATT
04H Rch ATT
ATT7
ATT7
ATT0
ATT0
default
1
1
1
1
1
1
1
1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
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[AK4425A]
SYSTEM DESIGN
Figure 15 shows the system connection diagram. An evaluation board (AKD4425) is available for fast evaluation as well
as suggestions for peripheral circuitry.
Analog
5.0V
+
0.1u
10u
VSS1
CP
VDD
16
15
14
13
1
2
3
4
MCLK
BICK
SDTI
LRCK
CSN
+
Master Clock
CN
1u (1)
1u (1)
64fs
VEE
24bit Audio Data
AK4425A
AOUTL
fs
12
11
10
9
5
6
7
Lch Out
10u
VSS2
AVDD
0.1u
μP
+
CCLK
CDTI
AOUTR
8
Rch Out
Analog Ground
Digital Ground
Note:
Use low ESR (Equivalent Series Resistance) capacitors. When using polarized capacitors, the positive polarity pin
should be connected to the CP and VSS1 pin.
VSS1 and VSS2 should be separated from digital system ground.
Digital input pins should not be allowed to float.
Figure 15. Typical Connection Diagram
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[AK4425A]
1. Grounding and Power Supply Decoupling
VDD and AVDD are supplied from the analog supply and should be separated from the system digital supply.
Decoupling capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD
and AVDD as possible. The VSS1 and VSS2 must be connected to the same analog ground plane. Power-up sequence
between VDD and AVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically
2.2Vrms (typ @AVDD=5V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the
noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1st-order LPF (Figure 16) can
reduce noise beyond the audio passband.
AK4425
470
Analog
Out
AOUT
2.2Vrms (typ)
2.2nF
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 16. External 1st order LPF Circuit Example
MS1127-E-01
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[AK4425A]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
A
8
1
0.65
0.22±0.1
0.17±0.05
M
0.13
Detail A
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Epoxy, Halogen (bromine and chlorine) free
Cu
Lead frame surface treatment:
Solder (Pb free) plate
MS1127-E-01
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[AK4425A]
MARKING
AKM
4425AET
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4425AET
4) Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD) Revision Reason
Page
Contents
09/09/18
11/03/01
00
01
First Edition
Error Correction 24
1. Grounding and Power Supply Decoupling
The description was changed.
MS1127-E-01
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[AK4425A]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS1127-E-01
2011/03
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相关型号：
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