AK4611_技术文档

[AK4611]

AK4611

4/8-Channel Audio CODEC

GENERAL DESCRIPTION

The AK4611 is a single chip audio CODEC that includes four ADC channels and eight DAC channels.

The converters are designed with Enhanced Dual Bit architecture for the ADC’s, and Advanced Multi-Bit

architecture for the DAC, enabling very low noise performance. Fabricated on a low power process, the

AK4611 operates off of a +3.3V analog supply and a +1.8V digital supply. The AK4611 supports both

single-ended and differential inputs and outputs. A wide range of applications can be realized, including

home theater, pro audio and car audio. The AK4611 is available in an 80-pin LQFP package.

FEATURES

1. 4channel 24bit ADC

- 128x Oversampling

- Linear Phase Digital Anti-Alias Filter

- Analog Anti-Alias Filter for Single-Ended Input and Differential Input

- ADC S/(N+D)

92dB: Single-Ended Input

97dB: Differential Input

- ADC DR, S/N

103dB: Single-Ended Input

104dB: Differential Input

- Digital HPF for offset cancellation

- I/F format: MSB justified, I²S or TDM

- Overflow flag

2. 8channel 24bit DAC

- 128x Oversampling

- Linear Phase 24bit 8 times Digital Filter

- Analog Smoothing Filter for Single-Ended Output

- DAC S/(N+D)

94dB: Single-Ended Output

100dB: Differential Output

- DAC DR, S/N

105dB: Single-Ended Output

108dB: Differential Output

- Individual channel digital volume with 256 levels and 0.5dB steps

- Soft mute

- De-emphasis for 32kHz, 44.1kHz and 48kHz

- Zero Detect Function

- I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I²S or TDM

3. Sampling Frequency

- Normal Speed Mode: 32kHz to 48kHz

- Double Speed Mode: 64kHz to 96kHz

- Quad Speed Mode: 128kHz to 192kHz

4. Master / Slave mode

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5. Master clock

- Slave mode: 256fs, 384fs or 512fs (Normal Speed Mode: fs=32kHz ∼ 48kHz)

256fs

128fs

(Double Speed Mode: fs=64kHz ∼ 96kHz)

(Quad Speed Mode: fs=128kHz ∼ 192kHz)

(Normal Speed Mode: fs=32kHz ∼ 48kHz)

(Double Speed Mode: fs=64kHz ∼ 96kHz)

(Quad Speed Mode: fs=128kHz ∼ 192kHz)

- Master mode: 256fs or 512fs

256fs

128fs

6. 4-wire Serial and I²C Bus µP I/F for mode setting

7. Power Supply

- Analog Power Supply: AVDD1, AVDD2 = 3.0 ∼ 3.6V

- Digital Power Supply: DVDD = 1.6 ∼ 2.0V

- I/O Buffer Power Supply: TVDD1, TVDD2 = 1.6 ∼ 3.6V

8. Power Supply Current : 81 mA (fs=48kHz)

9. Ta = -20 ~ 85ºC (AK4611EQ), - 40 ∼ 105ºC (AK4611VQ)

10. Package: 80pin LQFP (0.5mm pitch)

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■ Block Diagram

M/S

LIN1+ / LIN1

LIN1-

ADC1

ADC2

HPF1

HPF2

PDN

DVMPD

RIN1+ / RIN1

RIN1-

XTI / MCKI

LIN2+ / LIN2

LIN2-

X’tal

Oscillation

RIN2+ / RIN2

RIN2-

Audio

I/F

XTO

MCKO

Divider

MCLK

LRCK

BICK

LRCK

BICK

LOUT1+ / LOUT1

LOUT1-

DATT1

DEM1

SCF1

SCF2

DAC1

DAC2

TST1

TST2

TST3

TST4

TST5

SDTO1

ROUT1+ / ROUT1

ROUT1-

DATT1

DEM1

LOUT2+ / LOUT2

LOUT2-

DATT2

DEM2

SDOUT1

SDOUT2

SDTO2

TST6

ROUT2+ / ROUT2

ROUT2-

DATT2

DEM2

SCF2

SCF3

SCF4

DAC2

DAC3

LOUT3+ / LOUT3

LOUT3-

DATT3

DEM3

OVF1 / DZF1

OVF2 / DZF2

VCOM

ROUT3+ / ROUT3

ROUT3-

DATT3

DEM3

SDTI1

SDTI2

SDTI3

SDIN1

SDIN2

SDIN3

SDIN4

LOUT4+ / LOUT4

LOUT4-

DATT4

DEM4

DAC4

ROUT4+ / ROUT4

ROUT4-

DATT4

DEM4

SDTI4

TST7

SCF4

TST8

CAD0

CAD1

uP I/F

I2C

CSN

CCLK / SCL

CDTI / SDA

CDTO

VREFH1

VREFH2

AVDD1 VSS1 AVDD2 VSS2 DVDD

VSS3 TVDD1 VSS4 TVDD2

Figure 1. Block Diagram

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■ Ordering Guide

AK4611EQ

-20 ∼ +85°C

-40 ∼ +105°C

Evaluation Board for AK4611

80pin LQFP (0.5mm pitch)

AK4611VQ

AKD4611

■ Pin Layout

TST15

TST16

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

LOUT2+ / LOUT2

ROUT1-

ROUT1+ / ROUT1

LOUT1-

LOUT1+ / LOUT1

DVMPD

TST8

OVF1 / DZF1

OVF2 / DZF2

LIN1+ / LIN1

LIN1-

RIN1+ / RIN1

RIN1-

TST7

LIN2+ / LIN2

LIN2-

SDTI4

SDTI3

80 pin LQFP

30

29

28

27

26

25

24

23

22

21

RIN2+ / RIN2

RIN2-

SDTI2

SDTI1

(TOP VIEW)

TST17

BICK

TST18

LRCK

VSS1

TST6

AVDD1

SDTO2

SDTO1

VSS4

VREFH1

VCOM

TST19

TVDD1

XTI / MCKI

TST20

Figure 2. Pin Layout

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■ Compatibility with AK4628

1. Functions

Function

AK4628

AK4611

Number of ADC channel

Number of DAC channel

Input

Output

I/F Format

2-channel

8-channel

Single

I2S, LJ, RJ(20/24bit), TDM

No

4-channel

8-channel

Single or Diff

I2S, LJ, RJ(16/20/24bit), TDM

Fs=48kHz

Yes

TDM512

XTAL OSC

Parallel / Serial Select Pin

Control Data Output Pin

Ta

Yes

No

-40 ∼ +85°C

44pinLQFP

No

Yes

-40 ∼ +105°C

80pinLQFP

Package

2. Power Supply

Voltage Name

AVDD

AVDD1

AVDD2

DVDD

TVDD

TVDD1

TVDD2

AK4628

AK4611

No

3.0 ∼ 3.6V

1.6 ∼ 2.0V

No

4.5 ∼ 5.5V

No

4.5 ∼ 5.5V

2.7 ∼ 5.5V

No

1.6 ∼ 3.6V

No

3. Specification

Parameter

AK4628

AK4611

Fs (AD/DA)

THD+N (AD/DA)

96k / 192k

192k / 192k

Single: 92 / 94

Differential : 97 / 100

Single: 103 / 105

Differential: 104 / 108

256 level

Single: 92 / 90

Differential : - / -

Single: 102 / 106

Differential : - / -

128 level

S/N (AD/DA)

Output DATT

µP I/F

100k I2C, 3wire

400k I2C, 4wire

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PIN/FUNCTION

No. Pin Name

I/O

I

Function

Test Pin

This pin must be connected to VSS4.

Test Pin

This pin must be connected to TVDD2.

Test Pin

This pin must be connected to VSS4.

Test Pin

1

2

3

4

TST1

TST3

TST4

TST5

I

This pin must be connected to VSS4.

5

6

CAD0

CAD1

I

Chip Address 0 Pin

Chip Address 1 Pin

µP I/F Mode Select Pin

7

I2C

I

“L”: 4-wire Serial, “H”: I²C Bus

Control Data Clock Pin in serial control mode

I2C = “L”: CCLK (4-wire Serial)

Control Data Clock Pin in serial control mode

I2C = “H”: SCL (I²C Bus)

CCLK

SCL

I

8

Chip Select Pin in 4-wire serial control mode

This pin must be connected to TVDD2 at I²C bus control mode

Control Data Input Pin in serial control mode

I2C = “L”: CDTI (4-wire Serial)

Control Data Input Pin in serial control mode

I2C = “H”: SDA (I²C Bus)

9

CSN

CDTI

SDA

I

10

I/O

11 CDTO

12 TVDD2

13 VSS3

O

-

Control Data Output Pin in 4-wire serial control mode

Input / Output Buffer Power Supply 1 Pin, 1.6V∼3.6V

Ground Pin, 0V

14 DVDD

-

Digital Power Supply Pin, 1.6V∼2.0V

No Connection.

No internal bonding. This pin must be connected to the ground.

15 NC

Test Pin

16 TST2

I

This pin must be connected to VSS4.

Master Mode Select Pin

17 M/S

I

“L”: Slave Mode “H”: Master Mode

18 MCKO

O

Master Clock Output Pin

Power-Down & Reset Pin

19 PDN

20 XTO

I

When “L”, the AK4611 is powered-down and the control registers are reset to default

state. If the state of CAD1-0 changes, then the AK4611 must be reset by PDN.

X’tal Output Pin

X’tal Input Pin

O

I

XTI

21

MCKI

External Master Clock Input Pin

22 TVDD1

23 VSS4

-

Input / Output Buffer Power Supply 1 Pin, 1.6V∼3.6V

Digital Ground Pin, 0V

24 SDTO1

25 SDTO2

O

Audio Serial Data Output 1 Pin

Audio Serial Data Output 2 Pin

Test Pin

26 TST6

O

This pin must be open.

27 LRCK

28 BICK

29 SDTI1

30 SDTI2

31 SDTI3

32 SDTI4

I/O Input /Output Channel Clock Pin

I/O Audio Serial Data Clock Pin

I

Audio Serial Data Input 1 Pin

Audio Serial Data Input 2 Pin

Audio Serial Data Input 3 Pin

Audio Serial Data Input 4 Pin

Test Pin

33 TST7

I

This pin must be connected to VSS4.

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No. Pin Name

34 TST8

I/O

I

Function

Test Pin

This pin must be connected to VSS4.

DAC output VCOM voltage power down pin

35 DVMPD

I

“L”: DAC outputs are VCOM voltage “H”: DAC outputs are Hi-Z.

Lch Analog Positive Output 1 Pin (DOE1 bit = “H”)

Lch Analog Output 1 Pin (DOE1 bit = “L”)

Lch Analog Negative Output 1 Pin (When DOE1 bit = “L”, this pin must be open.)

Rch Analog Positive Output 1 Pin (DOE1 bit = “H”)

Rch Analog Output 1 Pin (DOE1 bit = “L”)

Rch Analog Negative Output 1 Pin (When DOE1 bit = “L”, this pin must be open.)

Lch Analog Positive Output 2 Pin (DOE2 bit = “H”)

Lch Analog Output 2 Pin (DOE2 bit = “L”)

Lch Analog Negative Output 2 Pin (When DOE2 bit = “L”, this pin must be open.)

Rch Analog Positive Output 2 Pin (DOE2 bit = “H”)

Rch Analog Output 2 Pin (DOE2 bit = “L”)

Rch Analog Negative Output 2 Pin (When DOE2 bit = “L”, this pin must be open.)

Lch Analog Positive Output 3 Pin (DOE3 bit = “H”)

Lch Analog Output 3 Pin (DOE3 bit = “L”)

Lch Analog Negative Output 3 Pin (When DOE3 bit = “L”, this pin must be open.)

Rch Analog Positive Output 3 Pin (DOE3 bit = “H”)

Rch Analog Output 3 Pin (DOE3 bit = “L”)

Rch Analog Negative Output 3 Pin (When DOE3 bit = “L”, this pin must be open.)

Ground Pin, 0V

LOUT1+

36

O

-

LOUT1

37 LOUT1-

ROUT1+

ROUT1

38

39 ROUT1-

LOUT2+

LOUT2

40

41 LOUT2-

ROUT2+

ROUT2

42

43 ROUT2-

LOUT3+

LOUT3

44

45 LOUT3-

ROUT3+

ROUT3

46

47 ROUT3-

48 VSS2

49 AVDD2

50 VREFH2

-

I

Analog Power Supply Pin, 3.0V∼3.6V

Positive Voltage Reference Input Pin, AVDD2

LOUT4+

LOUT4

52 LOUT4-

ROUT4+

ROUT4

54 ROUT4-

O

Lch Analog Positive Output 4 Pin (DOE4 bit = “H”)

Lch Analog Output 4 Pin (DOE4 bit = “L”)

Lch Analog Negative Output 4 Pin (When DOE4 bit = “L”, this pin must be open.)

Rch Analog Positive Output 4 Pin (DOE4 bit = “H”)

Rch Analog Output 4 Pin (DOE4 bit = “L”)

Rch Analog Negative Output 4 Pin (When DOE4 bit = “L”, this pin must be open.)

51

53

Test Pin

This pin must be open.

Test Pin

This pin must be open.

Test Pin

This pin must be open.

Test Pin

This pin must be open.

Test Pin

This pin must be open.

Test Pin

This pin must be open.

Test Pin

This pin must be open.

Test Pin

This pin must be open.

55 TST9

O

56 TST10

57 TST11

58 TST12

59 TST13

60 TST14

61 TST15

62 TST16

OVF1

Analog Input Overflow Detect 1 Pin (Note 1)

This pin goes to “H” if the analog input of Lch or Rch overflows.

63

Zero Input Detect 1 Pin

(Note 2)

DZF1

O

When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,

this pin goes to “H”. And when RSTN bit is “0”, PMDAC bit is “0”, this pin goes to “H”.

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No. Pin Name

OVF2

I/O

O

Function

Analog Input Overflow Detect 2 Pin (Note 1)

This pin goes to “H” if the analog input of Lch or Rch overflows.

Zero Input Detect 2 Pin (Note 2)

64

DZF2

O

When the input data of the group 2 follow total 8192 LRCK cycles with “0” input data,

this pin goes to “H”. And when RSTN bit is “0”, PMDAC bit is “0”, this pin goes to “H”.

LIN1+

65

I

Lch Analog Positive Input 1 Pin (DIE1 bit = “H”)

Lch Analog Input 1 Pin (DIE1 bit = “L”)

LIN1

Lch Analog Negative Input 1 Pin (When DIE1 bit = “L”, this pin must be open.)

(Note 3)

66 LIN1-

-

RIN1+

67

I

Rch Analog Positive Input 1 Pin (DIE1 bit = “H”)

Rch Analog Input 1 Pin (DIE1 bit = “L”)

RIN1

Rch Analog Negative Input 1 Pin (When DIE1 bit = “L”, this pin must be open.)

(Note 3)

68 RIN1-

-

LIN2+

69

I

Lch Analog Positive Input 2 Pin (DIE2 bit = “H”)

Lch Analog Input 2 Pin (DIE2 bit = “L”)

LIN2

Lch Analog Negative Input 2 Pin (When DIE2 bit = “L”, this pin must be open.)

(Note 3)

70 LIN2-

-

RIN2+

71

I

Rch Analog Positive Input 2 Pin (DIE2 bit = “H”)

Rch Analog Input 2 Pin (DIE2 bit = “L”)

RIN2

Rch Analog Negative Input 2 Pin (When DIE2 bit = “L”, this pin must be open.)

(Note 3)

Test Pin

This pin must be open.

Test Pin

This pin must be open.

Ground Pin, 0V

Analog Power Supply Pin, 3.0V∼3.6V

Positive Voltage Reference Input Pin, AVDD1

Common Voltage Output Pin, AVDD1x1/2

Large external capacitor around 2.2µF is used to reduce power-supply noise.

Test Pin

72 RIN2-

73 TST17

74 TST18

-

I

75 VSS1

76 AVDD1

77 VREFH1

-

I

78 VCOM

79 TST19

80 TST20

O

I

This pin must be open.

Test Pin

This pin must be open.

I

Note 1. This pin becomes OVF pin when OVFE bit is set to “1”.

Note 2. This pin becomes DZF pin when OVFE bit is set to “0”.

Note 3. This pin becomes analog negative input pin in differential input mode, and becomes output pin invert the positive

input pin in single-end input mode. This pin must be open in single-end input mode.

Note 4. All digital input pins except for pull-down must not be left floating.

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ABSOLUTE MAXIMUM RATINGS

(VSS1=VSS2=VSS3=VSS4=0V; Note 5)

Parameter

Power Supplies

Symbol

AVDD1,2

DVDD

TVDD1,2

IIN

min

max

4.2

2.2

4.2

±10

Units

V

mA

V

Analog

Digital

Output buffer

-0.3

-

Input Current (any pins except for supplies)

Analog Input Voltage

VINA

-0.3

AVDD1,2+0.3

Digital Input Voltage

(TST2,M/S,PDN,XTI/MCKI,LRCK,BICK,

SDTI1,SDTI2,SDTI3,SDTI4,TST7,TST8,

DVMPD pins)

(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,

CCLK/SCL,CSN,CDTI/SDA pins)

VIND1

VIND2

-0.3

TVDD1+0.3

TVDD2+0.3

V

AK4611EQ

AK4611VQ

Ta

-20

-40

-65

85

105

150

°C

Ambient Temperature (power applied)

Storage Temperature

Tstg

Note 5. All voltages with respect to ground. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog ground

plane. AVDD1 and AVDD2 must be the same voltage.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(VSS1=VSS2=VSS3=VSS4=0V; Note 5)

Parameter

Power Supplies Analog

Symbol

AVDD1,2

DVDD

min

3.0

1.6

typ

3.3

1.8

3.3

max

Units

3.6

2.0

3.6

V

(Note 6)

Digital

I/O buffer 1

TVDD1

DVDD

(Stereo Mode & Normal Speed Mode)

I/O buffer 1

TVDD1

3.0

3.3

3.6

V

(Except Stereo Mode & Normal Speed Mode)

I/O buffer 2

TVDD2

DVDD

3.3

3.6

V

Note 6. The power up sequence between AVDD1, AVDD2, DVDD, TVDD1 and TVDD2 is not critical. Each power

supplies should be powered up during the PDN pin = “L”. The PDN pin should be “H” after all power supplies are

powered up. All power supplies should be powered on, only a part of these power supplies cannot be powered off.

(Power off means power supplies equal to ground or power supplies are floating.) Do not turn off only the

AK4611 under the condition that a surrounding device is powered on and the I2C bus is in use.

WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

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[AK4611]

ANALOG CHARACTERISTICS

(Ta=25°C; AVDD1=AVDD2=TVDD1=TVDD2=3.3V, DVDD =1.8V; VSS1=VSS2=0V; VREFH1=AVDD1,

VREFH2=AVDD2; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement

Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; unless otherwise specified)

Parameter

min

typ

max

Units

ADC Analog Input Characteristics (single inputs)

Resolution

S/(N+D)

24

Bits

dB

fs=48kHz

BW=20kHz

fs=96kHz

BW=40kHz

fs=192kHz

BW=40kHz

-1dBFS

-60dBFS

-1dBFS

-60dBFS

-1dBFS

-60dBFS

84

83

92

40

91

37

91

dB

37

DR

S/N

(-60dBFS with A-weighted)

(A-weighted)

95

90

103

110

0.1

40

dB

Interchannel Isolation

Interchannel Gain Mismatch

Gain Drift

Input Voltage

Input Resistance

0.5

-

2.37

dB

ppm/°C

Vpp

kΩ

AIN=0.65xVREFH1

1.94

7

2.15

9

Power Supply Rejection

(Note 7)

50

dB

ADC Analog Input Characteristics (differential inputs)

S/(N+D)

fs=48kHz

BW=20kHz

-1dBFS

-60dBFS

-1dBFS

-60dBFS

-1dBFS

-60dBFS

88

86

97

40

94

37

94

dB

fs=96kHz

BW=40kHz

fs=192kHz

BW=40kHz

37

DR

S/N

(-60dBFS with A-weighted)

(A-weighted)

96

90

104

110

0.1

40

dB

Interchannel Isolation

Interchannel Gain Mismatch

Gain Drift

Input Voltage

Input Resistance

0.5

-

±2.37

dB

ppm/°C

Vpp

kΩ

AIN=0.65xVREFH1

(Note 8)

±1.94

11

±2.15

13

Power Supply Rejection

(Note 7)

(Note 9)

50

dB

Common Mode Rejection Ratio (CMRR)

DAC Analog Output Characteristics (single outputs)

Resolution

74

24

Bits

dB

S/(N+D)

fs=48kHz

BW=20kHz

fs=96kHz

0dBFS

-60dBFS

0dBFS

84

86

94

44

92

BW=40kHz

fs=192kHz

BW=40kHz

-60dBFS

0dBFS

-60dBFS

41

92

41

DR

S/N

(-60dBFS with A-weighted)

(A-weighted)

97

90

105

110

0.1

20

dB

Interchannel Isolation

Interchannel Gain Mismatch

Gain Drift

Output Voltage

Load Resistance

0.5

-

2.29

dB

ppm/°C

Vpp

kΩ

pF

dB

AOUT=0.63xVREFH2

1.87

5

2.08

(AC Load)

(Note 7)

Load Capacitance

Power Supply Rejection

30

50

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DAC Analog Output Characteristics (differential outputs)

S/(N+D)

fs=48kHz

BW=20kHz

0dBFS

-60dBFS

0dBFS

90

88

100

45

98

dB

fs=96kHz

BW=40kHz

-60dBFS

0dBFS

-60dBFS

42

98

42

fs=192kHz

BW=40kHz

DR

S/N

(-60dBFS with A-weighted)

(A-weighted)

100

90

108

110

0

dB

Interchannel Isolation

Interchannel Gain Mismatch

Gain Drift

0.5

-

20

ppm/°C

Output Voltage

Load Resistance

Load Capacitance

Power Supply Rejection

AOUT=0.63xVREFH2 (Note 8)

(Note 10)

±1.87

2

±2.08

±2.29

Vpp

kΩ

pF

dB

30

(Note 7)

50

Note 7. PSR is applied to AVDD1, AVDD2, DVDD, TVDD1 and TVDD2 with 1kHz, 50mVpp. VREFH1 and VREFH2

pins are held a constant voltage +3.3V.

Note 8. This value is (LIN+) – (LIN-) and (RIN+) – (RIN-). The voltage is proportional to VREFH1, VREFH2 voltage.

Note 9. VREFH1 and VREFH2 are held +3.3V, the input bias voltage is set to AVDD1, 2 x 0.5. The 1kHz, 0.96Vpp

signal is applied to LIN- and LIN+ with same phase (e.g. shorted) or RIN- and RIN+. The CMRR is measured as

the attenuation level from 0dB = -7dBFS (since the normal 0.96Vpp = -7dBFS). This value is guaranteed but not

tested.

Note 10. For AC-load. In the case of DC-load is 5kΩ.

Note 11. This value is Load Capacitance for output pin to GND. In differential mode, this value should be estimated to be

twice, because Load Capacitance exists to GND and between the differential pin.

Parameter

min

typ

max

Units

Power Supplies

Power Supply Current

Normal Operation (PDN pin = “H”)

AVDD1+AVDD2

DVDD

fs=48kHz, 96kHz, 192kHz

63.0

12.0

17.0

28.0

6.0

125.0

24.0

35.0

55.0

8.0

mA

fs=48kHz

fs=96kHz

fs=192kHz

fs=48kHz

fs=96kHz

fs=192kHz

TVDD1+TVDD2

7.0

9.5

Power-down mode

(PDN pin = “L”, DVMPD = “L”)

AVDD1+AVDD2+DVDD+TVDD1+TVDD2

(PDN pin = “L”, DVMPD = “H”)

(Note 12)

200

10

550

200

µA

AVDD1+AVDD2+DVDD+TVDD1+TVDD2

Note 12. In the power-down mode, all digital input pins including clock pins are held VSS3 (TST1, TST3, TST4, TST5,

CAD0, CAD1, I2C, CSN, CCLK, CDTI pins), VSS4 (TST2, M/S, MCKI, LRCK, BICK, SDTI1, SDTI2, SDTI3,

SDTI4,TST7, TST8).

MS1050-E-02

2010/06

- 11 -

[AK4611]

FILTER CHARACTERISTICS (fs=48kHz)

(Ta= Tmin ∼ Tmax; AVDD1=AVDD2=3.0∼ 3.6V, DVDD=1.6∼ 2.0V, TVDD1=TVDD2=1.6∼ 3.6V; DEM=OFF)

Parameter

Symbol

min

typ

max

Units

ADC Digital Filter (Decimation LPF):

Passband

(Note 13) ±0.1dB

−0.2dB

PB

0

-

28

-

68

-

20.0

23.0

-

18.9

-

kHz

dB

μs

−3.0dB

(Note 13)

Stopband

Passband Ripple

Stopband Attenuation

Group Delay Distortion

Group Delay

SB

PR

SA

ΔGD

GD

±0.1

-

0

16

(Note 14)

-

1/fs

ADC Digital Filter (HPF):

Frequency Response (Note 13) −3dB

−0.1dB

FR

-

1.0

6.5

-

Hz

DAC Digital Filter (LPF):

Passband

(Note 13) ±0.06dB

PB

0

-

26.2

-

54

-

21.8

-

kHz

dB

μs

−6.0dB

(Note 13)

24.0

-

0

Stopband

SB

PR

SA

ΔGD

GD

Passband Ripple

Stopband Attenuation

Group Delay Distortion

Group Delay

±0.06

-

(Note 14)

-

22

1/fs

DAC Digital Filter + Analog Filter:

Frequency Response (Note 15) 20kHz

FR

-

-0.1

-

dB

FILTER CHARACTERISTICS (fs=96kHz)

(Ta= Tmin ∼ Tmax; AVDD1=AVDD2=3.0∼ 3.6V, DVDD=1.6∼ 2.0V, TVDD1=TVDD2=1.6∼ 3.6V; DEM=OFF)

Parameter

Symbol

min

typ

max

Units

ADC Digital Filter (Decimation LPF):

Passband

(Note 13) ±0.1dB

−0.2dB

PB

0

-

56

-

68

-

40.0

46.0

-

37.8

-

kHz

dB

μs

−3.0dB

(Note 13)

Stopband

Passband Ripple

Stopband Attenuation

Group Delay Distortion

Group Delay

SB

PR

SA

ΔGD

GD

±0.1

-

0

16

(Note 14)

-

1/fs

ADC Digital Filter (HPF):

Frequency Response (Note 13) −3dB

−0.1dB

FR

-

2.0

13.0

-

Hz

DAC Digital Filter (LPF):

Passband

(Note 13) ±0.06dB

PB

0

-

52.4

-

54

-

43.6

-

kHz

dB

μs

−6.0dB

(Note 13)

48.0

-

0

Stopband

SB

PR

SA

ΔGD

GD

Passband Ripple

Stopband Attenuation

Group Delay Distortion

Group Delay

±0.06

-

(Note 14)

-

22

1/fs

DAC Digital Filter + Analog Filter:

Frequency Response (Note 15) 40kHz

FR

-

-0.3

-

dB

MS1050-E-02

2010/06

- 12 -

[AK4611]

FILTER CHARACTERISTICS (fs=192kHz)

(Ta= Tmin ∼ Tmax; AVDD1=AVDD2=3.0∼ 3.6V, DVDD=1.6∼ 2.0V, TVDD1=TVDD2=1.6∼ 3.6V; DEM=OFF)

Parameter

Symbol

min

typ

max

Units

ADC Digital Filter (Decimation LPF):

Passband

(Note 13) ±0.1dB

−0.2dB

PB

0

-

112

-

70

-

57.0

90.3

-

56.6

-

kHz

dB

μs

−3.0dB

(Note 13)

Stopband

Passband Ripple

Stopband Attenuation

Group Delay Distortion

Group Delay

SB

PR

SA

ΔGD

GD

±0.1

-

0

16

(Note 14)

-

1/fs

ADC Digital Filter (HPF):

Frequency Response (Note 13) −3dB

−0.1dB

FR

-

4.0

26.0

-

Hz

DAC Digital Filter (LPF):

Passband

(Note 13) ±0.06dB

PB

0

-

87.0

-

kHz

dB

μs

−6.0dB

(Note 13)

96.0

-

0

Stopband

SB

PR

SA

ΔGD

GD

104.9

Passband Ripple

Stopband Attenuation

Group Delay Distortion

Group Delay

-

54

-

±0.06

-

(Note 14)

-

22

1/fs

DAC Digital Filter + Analog Filter:

Frequency Response (Note 15) 80kHz

FR

-

-1

-

dB

Note 13. The passband and stopband frequencies scale with fs (sampling frequency). For example, ADC: Passband

(±0.1dB) = 0.39375 x fs (@ fs=48kHz), DAC: Passband (±0.06dB) = 0.45412 x fs.

Note 14. The calculated delay time is resulting from digital filtering. For the ADC, this time is from the input of an analog

signal to the setting of 24bit data for both channels to the ADC output register. For the DAC, this time is from

setting the 24 bit data both channels at the input register to the output of an analog signal.

Note 15. The reference frequency is 1kHz.

MS1050-E-02

2010/06

- 13 -

[AK4611]

DC CHARACTERISTICS

(Ta= Tmin ∼ Tmax; AVDD1=AVDD2=3.0∼3.6; DVDD=1.6∼2.0V; TVDD1=TVDD2=1.6∼3.6V)

Parameter

Symbol

min

typ

max

Units

TVDD1,TVDD2 ≤2.2V

High-Level Input Voltage

(TST2, M/S, PDN, MCKI, LRCK, BICK,

SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,

DVMPD pins)

(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,

CSN,CCLK, CDTI pins)

VIH

80%TVDD1

80%TVDD2

-

V

Low-Level Input Voltage

(TST2, M/S, PDN, MCKI, LRCK, BICK,

SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,

DVMPD pins)

(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,

CSN,CCLK, CDTI pins)

VIL

-

20%TVDD1

20%TVDD2

V

TVDD1,TVDD2 > 2.2V

High-Level Input Voltage

(TST2, M/S, PDN, MCKI, LRCK, BICK,

SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,

DVMPD pins)

(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,

CSN,CCLK, CDTI pins)

VIH

70%TVDD1

70%TVDD2

-

V

Low-Level Input Voltage

(TST2, M/S, PDN, MCKI, LRCK, BICK,

SDTI1, SDTI2, SDTI3, SDTI4,TST7, TST8,

DVMPD pins)

(TST1,TST3,TST4,TST5,CAD0,CAD1,I2C,

CSN,CCLK, CDTI pins)

VIL

-

30%TVDD1

30%TVDD2

V

High-Level Output Voltage

(SDTO1,SDTO2,TST6, LRCK, BICK,

MCKO pins:

(CDTO pin:

(DZF1/OVF1, DZF2/OVF2 pins: Iout=-100µA)

Low-Level Output Voltage

Iout=-100µA)

VOH

TVDD1-0.5

TVDD2-0.5

AVDD2-0.5

-

V

(SDTO1,SDTO2,TST6, LRCK, BICK,

MCKO, CDTO, DZF1, DZF2/OVF pins:

Iout= 100µA)

VOL

-

0.5

0.4

V

(SDA pin, 2.0V≤TVDD2≤3.6V

(SDA pin, 1.6V≤TVDD2<2.0V

Input Leakage Current

Iout= 3mA)

20%TVDD2

Iin

-

±10

µA

MS1050-E-02

2010/06

- 14 -

[AK4611]

SWITCHING CHARACTERISTICS

(Ta= Tmin ∼ Tmax; AVDD1=AVDD2=3.0∼3.6; DVDD=1.6∼2.0V; TVDD1=1.6∼3.6V, TVDD2=1.6∼3.6V; C_L=20pF;

unless otherwise specified)

Parameter

Symbol

min

typ

max

Units

Master Clock Timing

Crystal Resonator

Frequency

fXTAL

11.2896

24.576

MHz

MCKO Output

Frequency (TVDD1 ≥3.0V)

Duty

fMCK

dMCK

5.6448

40

24.576

60

MHz

%

50

External Clock

256fsn:

fCLK

8.192

32

12.288

22

16.384

16

12.288

18.432

24.576

MHz

ns

MHz

ns

MHz

ns

Pulse Width Low

Pulse Width High

384fsn:

tCLKL

tCLKH

fCLK

tCLKL

tCLKH

fCLK

Pulse Width Low

Pulse Width High

512fsn, 256fsd, 128fsq:

Pulse Width Low

Pulse Width High

MCKO Output

tCLKL

tCLKH

Frequency

fMCK

dMCK

4.096

12.288

40

12.288

24.576

60

MHz

%

(TVDD1 ≥3.0V)

Duty

(Note 16)

50

LRCK Timing (Slave mode)

Stereo mode

(TDM0 bit = “0”, TDM1 bit = “0”)

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

fsn

fsd

fsq

Duty

32

64

128

45

48

96

192

55

kHz

%

Duty Cycle

TDM512 mode

(Note 17)

(TDM0 bit = “0”, TDM1 bit = “1”)

LRCK frequency

“H” time

fsn

tLRH

tLRL

32

1/512fs

48

96

kHz

ns

“L” time

TDM256 mode

(TDM0 bit = “1”, TDM1 bit = “0”)

LRCK frequency

“H” time

(Note 18)

fsd

tLRH

tLRL

64

1/256fs

kHz

ns

“L” time

TDM128 mode

(TDM0 bit = “1”, TDM1 bit = “1”)

LRCK frequency

“H” time

(Note 19)

fsq

tLRH

tLRL

128

1/128fs

192

kHz

ns

“L” time

MS1050-E-02

2010/06

- 15 -

[AK4611]

Parameter

Symbol

min

typ

max

Units

LRCK Timing (Master Mode)

Stereo mode

(TDM0 bit = “0”, TDM1 bit = “0”)

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

fsn

fsd

fsq

Duty

32

64

128

-

48

96

192

-

kHz

%

Duty Cycle

50

TDM512 mode

(Note 17)

(TDM0 bit = “0”, TDM1 bit = “1”)

LRCK frequency

fsn

tLRH

32

64

48

96

kHz

ns

“H” time

(Note 20)

1/16fs

1/8fs

1/4fs

TDM256 mode

(Note 18)

(TDM0 bit = “1”, TDM1 bit = “0”)

LRCK frequency

fsd

tLRH

kHz

ns

“H” time

(Note 20)

TDM128 mode

(Note 19)

(TDM0 bit = “1”, TDM1 bit = “1”)

LRCK frequency

fsq

tLRH

128

192

kHz

ns

“H” time

(Note 20)

Note 16. Except the case of DIV bit = “0”.

Note 17. Please use for Normal Speed mode. Master clock should be input the 512fs in Master mode.

Note 18. Please use for Double Speed mode.

Note 19. Please use for Quad Speed mode.

Note 20. If the format is I²S, it is “L” time.

MS1050-E-02

2010/06

- 16 -

[AK4611]

Parameter

Symbol

min

typ

max

Units

Audio Interface Timing (Slave mode)

Stereo mode (TDM0 bit = “0”, TDM1 bit = “0”)

(TVDD1= 1.6V∼3.6V)

BICK Period

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRS

tBSD

tSDH

tSDS

324

130

20

ns

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑”

BICK “↑” to LRCK Edge

(Note 21)

20

LRCK to SDTO(MSB) (Except I²S mode)

BICK “↓” to SDTO

80

SDTI Hold Time

50

SDTI Setup Time

(TVDD1= 3.0V∼3.6V)

BICK Period

BICK Pulse Width Low

Pulse Width High

tBCK

tBCKL

tBCKH

tLRB

tBLR

tLRS

tBSD

tSDH

tSDS

81

33

23

ns

LRCK Edge to BICK “↑”

BICK “↑” to LRCK Edge

(Note 21)

LRCK to SDTO(MSB) (Except I²S mode)

BICK “↓” to SDTO

23

SDTI Hold Time

SDTI Setup Time

10

TDM512 mode (TDM0 bit = “0”, TDM1 bit = “1”)

(TVDD1= 3.0V∼3.6V)

(Note 17)

ns

BICK Period

tBCK

tBCKL

tBCKH

tLRB

tBLR

tBSS

tBSH

tSDH

tSDS

40

16

10

6

5

10

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑”

BICK “↑” to LRCK Edge

SDTO Setup time BICK “↑”

SDTO Hold time BICK “↑”

SDTI Hold Time

(Note 21)

SDTI Setup Time

TDM256 mode (TDM0 bit = “1”, TDM1 bit = “0”)

(TVDD1= 3.0V∼3.6V)

(Note 18)

BICK Period

tBCK

tBCKL

tBCKH

tLRB

tBLR

tBSS

tBSH

tSDH

tSDS

40

16

10

6

5

10

ns

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑”

BICK “↑” to LRCK Edge

SDTO Setup time BICK “↑”

SDTO Hold time BICK “↑”

SDTI Hold Time

(Note 21)

SDTI Setup Time

TDM128 mode (TDM0 bit = “1”, TDM1 bit = “1”)

(TVDD1= 3.0V∼3.6V)

(Note 19)

BICK Period

tBCK

tBCKL

tBCKH

tLRB

tBLR

tBSS

tBSH

tSDH

tSDS

40

16

10

6

5

10

ns

BICK Pulse Width Low

Pulse Width High

LRCK Edge to BICK “↑”

BICK “↑” to LRCK Edge

SDTO Setup time BICK “↑”

SDTO Hold time BICK “↑”

SDTI Hold Time

(Note 21)

SDTI Setup Time

MS1050-E-02

2010/06

- 17 -

[AK4611]

Parameter

Symbol

min

typ

max

Units

Audio Interface Timing (Master mode)

Stereo mode (TDM0 bit = “0”, TDM1 bit = “0”)

(TVDD1= 1.6V∼3.6V)

BICK Frequency

BICK Duty

BICK “↓” to LRCK

BICK “↓” to SDTO

SDTI Hold Time

-

fBCK

dBCK

tMBLR

tBSD

tSDH

tSDS

64fs

50

-

40

70

-

Hz

%

ns

−40

−70

50

-

SDTI Setup Time

(TVDD1= 3.0V∼3.6V)

BICK Frequency

BICK Duty

BICK “↓” to LRCK

BICK “↓” to SDTO

SDTI Hold Time

-

fBCK

dBCK

tMBLR

tBSD

tSDH

tSDS

64fs

50

-

23

-

Hz

%

ns

−23

10

-

SDTI Setup Time

TDM512 mode (TDM0 bit = “0”, TDM1 bit = “1”)

(TVDD1= 3.0V∼3.6V)

BICK Frequency

BICK Duty

BICK “↓” to LRCK

SDTO Setup time BICK “↑”

SDTO Hold time BICK “↑”

SDTI Hold Time

(Note 17)

fBCK

dBCK

tMBLR

tBSS

tBSH

tSDH

tSDS

-

512fs

50

-

10

-

Hz

%

-10

6

5

10

ns

-

SDTI Setup Time

TDM256 mode (TDM0 bit = “1”, TDM1 bit = “0”)

(TVDD1= 3.0V∼3.6V)

BICK Frequency

BICK Duty

BICK “↓” to LRCK

SDTO Setup time BICK “↑”

SDTO Hold time BICK “↑”

SDTI Hold Time

(Note 18)

-

fBCK

dBCK

tMBLR

tBSS

tBSH

tSDH

tSDS

256fs

50

-

10

-

Hz

%

ns

−10

6

5

10

-

SDTI Setup Time

TDM128 mode (TDM0 bit = “1”, TDM1 bit = “1”)

(TVDD1= 3.0V∼3.6V)

BICK Frequency

BICK Duty

BICK “↓” to LRCK

SDTO Setup time BICK “↑”

SDTO Hold time BICK “↑”

SDTI Hold Time

(Note 19)

-

fBCK

dBCK

tMBLR

tBSS

tBSH

tSDH

tSDS

128fs

50

-

10

-

Hz

%

ns

−10

6

5

10

-

SDTI Setup Time

Note 21. BICK rising edge must not occur at the same time as LRCK edge.

MS1050-E-02

2010/06

- 18 -

[AK4611]

Parameter

Symbol

min

typ

max

Units

Control Interface Timing (4-wire Serial mode):

CCLK Period

tCCK

tCCKL

tCCKH

tCDS

tCDH

tCSW

tCSS

tCSH

tDCD

tCCZ

200

80

40

150

50

ns

CCLK Pulse Width Low

Pulse Width High

CDTI Setup Time

CDTI Hold Time

CSN “H” Time

CSN “↓” to CCLK “↑”

CCLK “↑” to CSN “↑”

CDTO Delay

50

70

CSN “↑” to CDTO Hi-Z

Control Interface Timing (I²C Bus mode):

SCL Clock Frequency

fSCL

tBUF

-

400

-

1.0

0.3

-

50

400

kHz

μs

ns

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low Time

Clock High Time

Setup Time for Repeated Start Condition

1.3

0.6

1.3

0.6

0

0.1

-

tHD:STA

tLOW

tHIGH

tSU:STA

tHD:DAT

tSU:DAT

tR

SDA Hold Time from SCL Falling

SDA Setup Time from SCL Rising

Rise Time of Both SDA and SCL Lines

Fall Time of Both SDA and SCL Lines

Setup Time for Stop Condition

(Note 22)

tF

tSU:STO

tSP

Cb

0.6

0

-

Pulse Width of Spike Noise Suppressed by Input Filter

Capacitive load on bus

pF

Power-down & Reset Timing

PDN Pulse Width

PDN “↑” to SDTO valid

(Note 23)

(Note 24)

tPD

tPDV

150

ns

1/fs

518

Note 22. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Note 23. The AK4611 can be reset by setting the PDN pin to “L” upon power-up.

Note 24. These cycles are the numbers of LRCK rising from the PDN pin rising.

Note 25. I²C-bus is a trademark of NXP B.V.

MS1050-E-02

2010/06

- 19 -

[AK4611]

■ Timing Diagram

1/fCLK

VIH

VIL

MCKI

tCLKH

tCLKL

1/fsn, 1/fsd, 1/fsq

VIH

VIL

LRCK

tdLRKH

tdLRKL

Duty

= tdLRKH (or tdLRKL) x fs x 100

tBCK

VIH

VIL

BICK

tBCKH

tBCKL

Figure 3. Clock Timing (TDM1/0 bit = “00” & Slave mode)

1/fCLK

VIH

VIL

MCKI

LRCK

BICK

tCLKH

tCLKL

1/fs

VIH

VIL

tLRH

tLRL

tBCK

VIH

VIL

tBCKH

tBCKL

Figure 4. Clock Timing (Except TDM1/0 bit = “00” & Slave mode)

MS1050-E-02

2010/06

- 20 -

[AK4611]

1/fCLK

VIH

VIL

MCKI

tCLKH

tCLKL

1/fMCK

MCKO

50%TVDD1

tdMCKH

tdMCKL

dMCK

= tdMCKH (or tdMCKL) x fMCK x 100

1/fs

LRCK

50%TVDD1

tdLRKH

tdLRKL

dLRK

= tdLRKH (or tdLRKL) x fs x 100

1/fBCK

50%TVDD1

BICK

tdBCKH

tdBCKL

dBCK

= tdBCKH (or tdBCKL) x fs x 100

Figure 5. Clock Timing (TDM1/0 bit = “00” & Master mode)

1/fCLK

VIH

VIL

MCKI

tCLKH

tCLKL

1/fMCK

MCKO

50%TVDD1

tdMCKH

tdMCKL

dMCK

= tdMCKH (or tdMCKL) x fMCK x 100

1/fs

LRCK

50%TVDD1

tLRH

1/fBCK

50%TVDD1

BICK

tdBCKH

tdBCKL

dBCK

= tdBCKH (or tdBCKL) x fs x 100

Figure 6. Clock Timing (Except TDM1/0 bit = “00” & Master mode)

MS1050-E-02

2010/06

- 21 -

[AK4611]

VIH

VIL

LRCK

BICK

tBLR

tLRS

tLRB

VIH

VIL

tBSD

SDTO

50%TVDD1

tSDH

tSDS

VIH

VIL

SDTI

Figure 7. Audio Interface Timing (TDM1/0 bit = “00” & Slave mode)

VIH

VIL

LRCK

BICK

tBLR

tLRB

VIH

VIL

tBSH

tSDH

tBSS

SDTO

50%TVDD1

tSDS

VIH

VIL

SDTI

Figure 8. Audio Interface Timing (Except TDM1/0 bit = “00” & Slave mode)

MS1050-E-02

2010/06

- 22 -

[AK4611]

LRCK

BICK

SDTO

SDTI

50%TVDD1

tMBLR

tBSD

50%TVDD1

tSDS

tSDH

VIH

VIL

Figure 9. Audio Interface Timing (TDM1/0 bit = “00” & Master mode)

LRCK

BICK

SDTO

SDTI

50%TVDD1

tMBLR

50%TVDD1

tBSS

tSDS

tBSH

tSDH

VIH

VIL

Figure 10. Audio Interface Timing (Except TDM1/0 bit = “00” & Master mode)

MS1050-E-02

2010/06

- 23 -

[AK4611]

VIH

CSN

VIL

tCSS

tCCKL

tCCKH

tCSH

VIH

VIL

CCLK

tCDS

tCDH

VIH

VIL

CDTI

C1

C0

R/W

Hi-Z

Figure 11. WRITE Command Input Timing (4-wire Serial mode)

tCSW

CDTO

VIH

VIL

CSN

tCSH

tCSS

VIH

VIL

CCLK

VIH

VIL

CDTI

D2

D1

D0

Hi-Z

Figure 12. WRITE Data Input Timing (4-wire Serial mode)

CDTO

MS1050-E-02

2010/06

- 24 -

[AK4611]

VIH

VIL

CSN

VIH

VIL

CCLK

CDTI

CDTO

VIH

VIL

A1

A0

tDCD

Hi-Z

D7

D6

50%TVDD2

Figure 13. Read Data Output Timing1(4-wire Serial mode)

tCSW

VIH

VIL

CSN

tCSS

tCSH

VIH

VIL

CCLK

CDTI

CDTO

VIH

VIL

tCCZ

Hi-Z

D2

D1

D0

50%TVDD2

Figure 14. Read Data Output Timing2(4-wire Serial mode)

MS1050-E-02

2010/06

- 25 -

[AK4611]

VIH

VIL

SDA

SCL

tLOW tR

tHIGH

tBUF

tF

tSP

VIH

VIL

tHD:STA

tHD:DAT

tSU:DAT tSU:STA

Start

tSU:STO

Stop

Stop Start

Figure 15. I²C Bus mode Timing

tPD

VIH

VIL

PDN

tPDV

SDTO

50%TVDD1

Figure 16. Power-down & Reset Timing

MS1050-E-02

2010/06

- 26 -

[AK4611]

OPERATION OVERVIEW

■ System Clock

It is possible to select the clock source either extra clock input or X’tal input for the AK4611. (Figure 17, Figure 18) The

external clocks which are required to operate the AK4611 in slave mode are MCLK, LRCK and BICK. MCLK should be

synchronized with LRCK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting

Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0, DFS1 (Table 1). The frequency of MCLK at each

sampling speed is set automatically. (Table 3, Table 4, Table 5). In Auto Setting Mode (ACKS bit= “1”), as MCLK

frequency is detected automatically (Table 6) and the internal master clock attains the appropriate frequency (Table 7), so

it is not necessary to set DFS.

In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bits, and the

sampling speed should be set by the DFS1-0 bits. The frequencies and the duties of the clocks (LRCK, BICK) are not

stabile immediately after setting CKS1-0 bits and DFS1-0 bits up.

After exiting reset at power-up in slave mode, the AK4611 is in power-down mode until MCLK and LRCK are input.

If the clock is stopped, click noise occurs when restarting the clock. Mute the digital output externally if the click noise

influences system applications.

DFS1

DFS0

Sampling Speed Mode (fs)

(default)

0

1

0

1

0

1

Normal Speed Mode

32kHz~48kHz

64kHz~96kHz

128kHz~192kHz

-

Double Speed Mode

Quad Speed Mode

N/A

(N/A: Not available)

Table 1. Sampling Speed (Manual Setting Mode)

CKS1

CKS0

Normal Speed

Mode

Double Speed

Mode

Quad Speed

Mode

128fs

0

1

0

1

0

1

256fs

384fs

512fs

256fs

(default)

Table 2. Master Clock Input Frequency Select (Master Mode)

LRCK

fs

32.0kHz

44.1kHz

48.0kHz

MCLK (MHz)

384fs

BICK (MHz)

256fs

8.1920

11.2896

12.2880

512fs

64fs

12.2880

16.9344

18.4320

16.3840

22.5792

24.5760

2.0480

2.8224

3.0720

Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)

MS1050-E-02

2010/06

- 27 -

[AK4611]

LRCK

fs

MCLK (MHz)

256fs

BICK (MHz)

64fs

88.2kHz

96.0kHz

22.5792

24.5760

5.6448

6.1440

Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)

LRCK

fs

MCLK (MHz)

128fs

BICK (MHz)

64fs

176.4kHz

192.0kHz

22.5792

24.5760

11.2896

12.2880

Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)

MCLK

512fs

256fs

128fs

Sampling Speed Mode

Normal Speed Mode

Double Speed Mode

Quad Speed Mode

Table 6. Sampling Speed (Auto Setting Mode)

MCLK (MHz)

LRCK

fs

Sampling

Speed Mode

128fs

256fs

512fs

32.0kHz

44.1kHz

48.0kHz

88.2kHz

96.0kHz

176.4kHz

192.0kHz

-

16.3840

22.5792

24.5760

Normal Speed

Mode

22.5792

24.5760

-

Double Speed

Mode

Quad Speed

Mode

-

22.5792

24.5760

-

Table 7. System Clock Example (Auto Setting Mode)

MS1050-E-02

2010/06

- 28 -

[AK4611]

■ Clock Source

The clock for the XTI pin can be generated by the two methods.

1) External clock

XTI

External Clock

AK4611

XTO

Figure 17. External clock mode

Note: Input clock must not exceed TVDD1.

2) X’tal

XTI

AK4611

XTO

Figure 18. X’tal mode

Note: External capacitance depends on the crystal oscillator (Typ. 10pF)

TVDD1 should be used in the range of 3.0 ~ 3.6V in X’tal mode.

MS1050-E-02

2010/06

- 29 -

[AK4611]

■ Differential / Single-End Input selection

The AK4611 supports the differential input (Figure 19) by setting DIE1-2 bits = “1”, supports the single-end input (Figure

20) by setting DIE1-2 bits = “0”. In differential input mode, two input pins must not be connected to a signal input in

combination with a VCOM voltage. When single-end input mode, L/RIN1-2 pins should be open, because L/RIN1-2 pins

output an invert signal of the input signal. The AK4611 includes an anti-aliasing filter (RC filter) for both differential

input and the single-end input.

AK4611

L/RIN+

L/RIN

LPF

SCF

LPF

L/RIN-

(Open)

Figure 19. Differential Input (DIE1-2 bit = “1”)

Figure 20. Single-end Input (DIE1-2 bit = “0”)

■ Differential / Single-End Output selection

The AK4611 supports the differential output (Figure 21) by setting DOE1-4 bits = “1”, and the single-end output (Figure

22) by setting DOE1-4 bits = “0”. When single-end output mode, L/ROUT1-4 pins should be open, because of

L/ROUT1-4 pins outputs VCOM voltage. The internal analog filters remove most of the noise beyond the audio passband

generated by the delta-sigma modulator of a DAC in single-end input mode. There is no internal analog filter for

differential output. Use external analog filters if needed to remove this noise.

AK4611

L/ROUT+

L/ROUT

LPF

Diff

to

Single

SCF

L/ROUT-

(Open)

Figure 21. Differential Output (DOE1-4 bit = “1”)

Figure 22. Single-end Output (DOE1-4 bit = “0”)

MS1050-E-02

2010/06

- 30 -

[AK4611]

■ De-emphasis Filter

The AK4611 has a digital de-emphasis filter (tc=50/15µs) by an IIR filter. The de-emphasis filter supports only Normal

Speed Mode. This filter corresponds to three sampling frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC

can be set individually by registers, DAC1(SDTI1), DAC2(SDTI2), DAC3(SDTI3), DAC4(SDTI4).

Mode

Sampling Speed Mode

DEM11

DEM10

DEM

(DEM61-21)

(DEM60-20)

0

1

2

3

Normal Speed Mode

0

1

0

1

0

1

44.1kHz

OFF

48kHz

32kHz

(default)

Table 8. De-emphasis control

■ Digital High Pass Filter

The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz

and scales with the sampling rate (fs).

■ Master Clock Output

The AK4611 has a master clock output pin. If DIV bit = “1”, the MCKO pin output the frequency divided in half.

DIV

0

1

MCKO

XTI x1

XTI x1/2

(default)

Table 9. The select of Master clock output frequency

■ Master Mode and Slave Mode

Master Mode and Slave Mode are selected by setting the M/S pin. (Master Mode= “H”, Slave Mode= “L”)

LRCK and BICK pins are outputs in Master Mode (M/S pin= “H”)

LRCK and BICK pins are inputs in Slave Mode (M/S pin= “L”)

PDN

L

M/S pin

LRCK pin

Input

“L” Output

Input

BICK pin

Input

“L” Output

Input

L

H

L

H

Output

Table 10. LRCK and BICK pins

MS1050-E-02

2010/06

- 31 -

[AK4611]

■ Audio Serial Interface Format

(1) Stereo Mode

When TDM1-0 bits = “00”, ten modes can be selected by the DIF2-0 bits as shown in Table 11. In all modes the serial data

is MSB-first, 2’s compliment format. The data SDTO1-2 is clocked out on the falling edge of BICK and the SDTI1-4 is

latched on the rising edge of BICK.

Mode3/4/8/9/13/14/18/19/23/24/28/29/33/34/38/39 in SDTI input formats can be used for 16-20bit data by zeroing the

unused LSBs.

LRCK

I/O

BICK

Mode M/S TDM1 TDM0 DIF2 DIF1 DIF0 SDTO1-2

24bit, Left

SDTI1-4

I/O

I

16bit, Right

justified

20bit, Right

justified

24bit, Right

justified

0

1

2

0

1

0

1

0

H/L

I

≥ 32fs

justified

24bit, Left

justified

24bit, Left

justified

I

≥ 48fs

24bit, Left

justified

24bit, Left

justified

3

4

5

0

1

0

1

0

1

0

1

0

H/L

L/H

H/L

I

≥ 48fs

64fs

24bit, I²S

24bit, Left

justified

24bit, I²S

16bit, Right

justified

(default)

O

24bit, Left

justified

24bit, Left

justified

20bit, Right

justified

24bit, Right

justified

6

7

1

0

1

0

H/L

O

64fs

O

24bit, Left

justified

24bit, Left

justified

8

9

1

0

1

0

1

0

H/L

L/H

O

64fs

O

24bit, I²S

Table 11. Audio data formats (Stereo mode)

Note. TVDD1 which is the Power of I/O buffer should be kept in the range of 1.6V~3.6V at Normal Speed Mode in Stereo

Mode. TVDD1 should be kept in the range of 3.0V~3.6V at Double Speed Mode and Quad Speed Mode.

MS1050-E-02

2010/06

- 32 -

[AK4611]

(2) TDM Mode

The audio serial interface format is set in TDM mode by the TDM1-0 bits = “01”. Five modes can be selected by the

DIF2-0 bits as shown in Table 12. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO1 is clocked

out on the rising edge of BICK and the SDTI1/2/3 are latched on the rising edge of BICK. In the TDM512 mode (fs =

48kHz), the serial data of all ADC (four channels) is output to the SDTO1 pin. SDTO2 pin = “L”. And the serial data of all

DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed to

512fs. “H” time and “L” time of LRCK should be 1/512fs at least.

TDM256 mode can be set by TDM1-0 bits as show in Table 13. In the TDM256 mode (fs = 48kHz), the serial data of all

ADC (four channels) is output to the SDTO1 pin. SDTO2 pin = “L”. And the serial data of DAC (eight channels; L1, R1,

L2, R2, L3, R3, L4, R4) is input to the SDTI1 pin. The input data to SDTI2-4 pins are ignored. BICK should be fixed to

256fs. “H” time and “L” time of LRCK should be 1/256fs at least. TDM128 mode can be set by TDM1-0 bits as show in

Table 14.

In TDM128 mode (fs=192kHz), the serial data of four ADC (four channels; L1, R1, L2, R2) is output to the SDTO1 pin.

The SDTO2 pin = “L”. And the serial data of DAC (four channels; L1, R1, L2, R2) is input to the SDTI1 pin and the serial

data of DAC (four channels; L3, R3, L4, R4) is input to the SDTI2 pin. The input data to SDTI3-4 pins are ignored. BICK

should be fixed to 128fs. “H” time and “L” time of LRCK should be 1/128fs at least.

LRCK

I/O

BICK

Mode M/S TDM1 TDM0 DIF2 DIF1 DIF0 SDTO1-2

24bit, Left

SDTI1-4

I/O

I

16bit, Right

justified

20bit, Right

justified

24bit, Right

justified

10

11

12

0

1

0

1

0

1

0

I

512fs

↑

justified

24bit, Left

justified

24bit, Left

justified

512fs

I

24bit, Left

justified

24bit, Left

justified

13

14

15

0

1

0

1

0

1

0

1

0

1

0

I

512fs

I

↑

↓

↑

24bit, I²S

24bit, Left

justified

24bit, I²S

16bit, Right

justified

O

24bit, Left

justified

24bit, Left

justified

20bit, Right

justified

24bit, Right

justified

16

17

1

0

1

0

1

0

O

512fs

O

↑

24bit, Left

justified

24bit, Left

justified

18

19

1

0

1

0

1

0

1

0

O

512fs

O

↑

↓

24bit, I²S

Table 12. Audio data formats (TDM512 mode)

MS1050-E-02

2010/06

- 33 -

[AK4611]

LRCK

I/O

BICK

Mode M/S TDM1 TDM0 DIF2 DIF1 DIF0 SDTO1-2

24bit, Left

SDTI1-4

I/O

16bit, Right

justified

20bit, Right

justified

24bit, Right

justified

20

21

22

0

1

0

1

0

1

0

I

256fs

I

↑

justified

24bit, Left

justified

24bit, Left

justified

256fs

24bit, Left

justified

24bit, Left

justified

23

24

25

0

1

0

1

0

1

0

1

0

I

256fs

I

↑

↓

↑

24bit, I²S

24bit, Left

justified

24bit, I²S

16bit, Right

justified

O

24bit, Left

justified

24bit, Left

justified

20bit, Right

justified

24bit, Right

justified

26

27

1

0

1

0

O

256fs

O

↑

24bit, Left

justified

24bit, Left

justified

28

29

1

0

1

0

1

0

O

256fs

O

↑

↓

24bit, I²S

Table 13. Audio data formats (TDM256 mode)

LRCK

BICK

Mode M/S TDM1 TDM0 DIF2 DIF1 DIF0 SDTO1-2

24bit, Left

SDTI1-4

I/O

I

16bit, Right

justified

20bit, Right

justified

24bit, Right

justified

30

31

32

0

1

0

1

0

1

0

I

128fs

↑

justified

24bit, Left

justified

24bit, Left

justified

I

24bit, Left

justified

24bit, Left

justified

33

34

35

0

1

0

1

0

1

0

1

0

I

128fs

I

↑

↓

↑

24bit, I²S

24bit, Left

justified

24bit, I²S

16bit, Right

justified

O

24bit, Left

justified

24bit, Left

justified

20bit, Right

justified

24bit, Right

justified

36

37

1

0

1

0

O

128fs

O

↑

24bit, Left

justified

24bit, Left

justified

38

39

1

0

1

0

1

0

O

128fs

O

↑

↓

24bit, I²S

Table 14. Audio data formats (TDM128 mode)

Note. TVDD1 should be used in the range of 3.0V~3.6V in TDM mode.

MS1050-E-02

2010/06

- 34 -

[AK4611]

LRCK

0

1

2

16

17

18

24

25

31

0

1

2

16

17

18

24

25

31

0

1

BICK(64fs)

SDTO(o)

23 22

8

7

6

0

23 22

8

7

6

0

23

15 14

8

7

1

0

15 14

Rch Data

8

7

1

0

Don’t Care

SDTI(i)

SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB

Lch Data

Figure 23. Mode 0/5 Timing (Stereo Mode)

LRCK

0

1

2

12

13

14

24

25

31

0

1

2

12

13

14

24

28

25

31

0

1

BICK(64fs)

SDTO(o)

23 22

12 11 10

19 18

0

23 22

12 11 10

19 18

Don’t Care

0

23

8

7

1

0

8

7

1

0

Don’t Care

SDTI(i)

SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB

Lch Data

Rch Data

Figure 24. Mode 1/6 Timing (Stereo Mode)

LRCK

1

2

8

9

10

24

25

31

0

1

2

8

9

10

25

1

BICK(64fs)

SDTO(o)

23 22

16 15 14

23 22

0

23 22

16 15 14

23 22

Don’t Care

0

23

8

7

1

0

8

7

1

0

Don’t Care

SDTI(i)

23:MSB, 0:LSB

Lch Data

Rch Data

Figure 25. Mode 2/7 Timing (Stereo Mode)

LRCK

1

2

21

22

23

24

28

29

30

31

0

1

2

22

23

24

29

30

1

BICK(64fs)

SDTO(o)

23 22

2

1

0

23 22

2

1

0

23

Don’t Care

SDTI(i)

23:MSB, 0:LSB

Lch Data

Rch Data

Figure 26. Mode 3/8 Timing (Stereo Mode)

MS1050-E-02

2010/06

- 35 -

[AK4611]

LRCK

0

1

2

3

22

23

24

25

29

30

31

0

1

2

3

22

23

24

25

29

30

31

0

1

BICK(64fs)

SDTO(o)

23 22

2

1

0

23 22

2

1

0

Don’t Care

SDTI(i)

23:MSB, 0:LSB

Lch Data

Rch Data

Figure 27. Mode 4/9 Timing (Stereo Mode)

512BICK

LRCK(Mode15)

LRCK(Mode10)

BICK(512fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

23 22

L1

R1

L2

R2

32 BICK 32 BICK 32 BICK 32 BICK

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15

SDTI1(i)

L1

32 BICK

R1

L2

R2

L3

R3

L4

R4

32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK

Figure 28. Mode 10/15 Timing (TDM512 Mode)

512BICK

LRCK(Mode16)

LRCK(Mode11)

BICK(512fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

23 22

L1

R1

L2

R2

32 BICK 32 BICK 32 BICK 32 BICK

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19

SDTI1(i)

L1

32 BICK

R1

L2

R2

L3

R3

L4

R4

32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK

Figure 29. Mode 11/16 Timing (TDM512 Mode)

512BICK

LRCK(Mode17)

LRCK(Mode12)

BICK(512fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

23 22

L1

R1

L2

R2

32 BICK 32 BICK 32 BICK 32 BICK

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23

SDTI1(i)

L1

32 BICK

R1

L2

R2

L3

R3

L4

R4

32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK

Figure 30. Mode 12/17 Timing (TDM512 Mode)

MS1050-E-02

2010/06

- 36 -

[AK4611]

512BICK

LRCK(Mode18)

LRCK(Mode13)

BICK(512fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

23 22

L1

R1

L2

R2

32 BICK 32 BICK 32 BICK 32 BICK

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

SDTI1(i)

L1

32 BICK

R1

32 BICK

L2

32 BICK

R2

32 BICK

L3

32 BICK

R3

32 BICK

L4

32 BICK

R4

32 BICK

Figure 31. Mode 13/18 Timing (TDM512 Mode)

512BICK

LRCK(Mode19)

LRCK(Mode14)

BICK(512fs)

SDTO1(o)

23

0

23

0

23

0

23

0

23

L1

R1

L2

R2

32 BICK 32 BICK 32 BICK 32 BICK

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDTI1(i)

L1

32 BICK

R1

32 BICK

L2

32 BICK

R2

32 BICK

L3

32 BICK

R3

32 BICK

L4

32 BICK

R4

32 BICK

Figure 32. Mode 14/19 Timing (TDM512 Mode)

256 BICK

LRCK (Mode25)

LRCK (Mode20)

BICK(256fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

L1

R1

L2

R2

32 BICK

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15 14

0

15

SDTI1(i)

R1

R2

R3

R4

L1

L2

L3

L4

32 BICK

Figure 33. Mode 20/25 Timing (TDM256 Mode)

MS1050-E-02

2010/06

- 37 -

[AK4611]

256 BICK

LRCK (Mode26)

LRCK (Mode21)

BICK(256fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

L1

R1

L2

R2

32 BICK

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19 18

0

19

SDTI1(i)

R1

R2

R3

R4

L1

L2

L3

L4

32 BICK

Figure 34. Mode 21/26 Timing (TDM256 Mode)

256 BICK

LRCK (Mode27)

LRCK (Mode22)

BICK(256fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

23 22

L1

R1

L2

R2

32 BICK

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23

SDTI1(i)

R1

R2

R3

R4

L1

L2

L3

L4

32 BICK

Figure 35. Mode 22/27 Timing (TDM256 Mode)

256 BICK

LRCK (Mode28)

LRCK (Mode23)

BICK(256fs)

SDTO1(o)

23 22

0

23 22

0

23 22

0

23 22

0

23 22

L1

32 BICK

R1

32 BICK

L2

32 BICK

R2

32 BICK

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

0

23 22

SDTI1(i)

R1

32 BICK

R2

32 BICK

R3

32 BICK

R4

32 BICK

L1

32 BICK

L2

32 BICK

L3

32 BICK

L4

32 BICK

Figure 36. Mode 23/28 Timing (TDM256 Mode)

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[AK4611]

256 BICK

LRCK (Mode29)

LRCK (Mode24)

BICK(256fs)

SDTO1(o)

23

0

23

0

23

0

23

0

23

L1

32 BICK

R1

32 BICK

L2

32 BICK

R2

32 BICK

23

0

23

0

23

0

23

0

23

0

23

0

23

0

23

0

SDTI1(i)

R1

32 BICK

R2

32 BICK

R3

32 BICK

R4

L1

32 BICK

L2

32 BICK

L3

32 BICK

L4

32 BICK

Figure 37. Mode 24/29 Timing (TDM256 Mode)

128 BICK

LRCK (Mode35)

LRCK (Mode30)

BICK(128fs)

SDTO1(o)

23 22

0

23 22

0

L2

R2

L1

R1

32 BICK

15 14

0

15

0

15

15 14

14

15 14

SDTI1(i)

SDTI2(i)

L2

L1

R1

R2

32 BICK

15 14

L3

R3

L4

R4

32 BICK

Figure 38. Mode 30/35 Timing (TDM128 Mode)

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[AK4611]

128 BICK

LRCK (Mode36)

LRCK (Mode31)

BICK(128fs)

SDTO1(o)

23 22

0

23 22

0

L2

R2

L1

R1

32 BICK

19 18

0

19

0

19

19 18

18

19 18

SDTI1(i)

SDTI2(i)

L2

L1

R1

R2

32 BICK

19 18

L3

R3

L4

R4

32 BICK

Figure 39. Mode 31/36 Timing (TDM128 Mode)

128 BICK

LRCK (Mode37)

LRCK (Mode32)

BICK(128fs)

SDTO1(o)

23 22

0

23 22

0

L1

R1

L2

R2

32 BICK

23 22

0

23

0

23

23 22

22

23 22

SDTI1(i)

SDTI2(i)

L2

L1

R1

R2

32 BICK

23 22

L3

R3

L4

R4

32 BICK

Figure 40. Mode 32/37 Timing (TDM128 Mode)

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[AK4611]

128 BICK

LRCK (Mode38)

LRCK (Mode33)

BICK(128fs)

SDTO1(o)

23 22

0

23 22

0

L1

R1

L2

R2

32 BICK

23 22

0

23

0

23 22

0

23 22

0

22

23 22

SDTI1(i)

SDTI2(i)

L2

L1

R1

R2

32 BICK

0

23

0

23 22

22

23 22

L3

R3

L4

R4

32 BICK

Figure 41. Mode 33/38 Timing (TDM128 Mode)

128 BICK

LRCK (Mode39)

LRCK (Mode34)

BICK(128fs)

SDTO1(o)

23

0

23

22

0

L2

R2

L1

R1

32 BICK

0

23

0

23

0

23

SDTI1(i)

SDTI2(i)

L2

L1

R1

R2

32 BICK

0

L3

R3

L4

R4

32 BICK

Figure 42. Mode 34/39 Timing (TDM128 Mode)

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[AK4611]

■ Overflow Detection

The AK4611 has an overflow detect function for the analog input. The overflow detect function is enabled when the

OVFE bit is set to “1”. Overflow detection is applied to the analog input of each channel, and the result is OR’d. OVF1/2

pins goes to “H” according to the group set by OVFM2-0 bits, if analog input of Lch or Rch overflows (more than

-0.3dBFS). When the analog input is overflowed, the output signal of OVF1/2 pins have the same group delay as ADC

(GD = 16/fs = 333μs @fs=48kHz). OVF1/2 pins are “L” for 518/fs (=11.8ms @fs=48kHz) after PDN = “↑”, and then

overflow detection is enabled.

Mode

OVFM2

OVFM1

OVFM0

LIN1 or RIN1

OVF1

-

LIN2 or RIN2

OVF1

OVF2

OVF1

-

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

OVF2

disable (OVF2=OVF1= “L”)

(default)

Table 15. Overflow detect control (OVFE bit = “1”)

■ Zero Detection

The AK4611 has two pins for zero detect flag outputs. Zero detect function is enabled when the OVFE bit is set to “0”.

Channel grouping can be selected by the DZFM3-0 bits. (Table 16) The DZF1 pin corresponds to the group 1 channels

and the DZF2 pin corresponds to the group 2 channels. DZF1 is AND operation of all eight channels and DZF2 is disabled

(“L”) at mode 0, “H” at mode 1-3. When the input data of all channels in the group 1(group 2) are continuously zeros for

8192 LRCK cycles, the DZF1 (DZF2) pin goes to “H”. The DZF1 (DZF2) pin immediately returns to “L” if input data of

any channels in the group 1(group 2) is not zero.

DZFM

AOUT

Mode

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L1

R1

L2

R2

L3

R3

L4

R4

0

1

2

3

4

5

6

7

8

DZF1 DZF1

DZF1 DZF2

DZF2 DZF2

DZF1

DZF2

DZF1

DZF2

DZF1

DZF2

DZF1

DZF2

DZF1

DZF2

DZF1

DZF2

9

10

11

12

13

14

15

disable (DZF1=DZF2= “L”)

(default)

Table 16. Zero detect control (OVFE bit = “0”)

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[AK4611]

■ Digital Attenuator

AK4611 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of each channel can be

set by each the ATT7-0 bits (Table 17).

ATT7-0

00H

01H

02H

:

Attenuation Level

0dB

(default)

-0.5dB

-1.0dB

:

7DH

7EH

7FH

-62.5dB

-63.0dB

-63.5dB

:

FEH

FFH

-127.0dB

MUTE (-∞)

Table 17. Attenuation level of digital attenuator

Transition time between set values of ATT7-0 bits can be selected by the ATS1-0 bits (Table 18). Transition between set

values is the soft transition in Mode1/2/3 eliminating switching noise in the transition.

Mode

ATS1

ATS0

ATT speed

4096/fs

2048/fs

512/fs

(default)

0

1

2

3

0

1

0

1

0

1

256/fs

Table 18. Transition time between set values of ATT7-0 bits

The transition between set values is a soft transition of 4096 levels in mode 0. It takes 4096/fs (85.3ms@fs=48kHz) from

00H(0dB) to FFH(MUTE). If the PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs also become 00H when

RSTN bit = “0”, and fade to their current value when RSTN bit returns to “1”.

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[AK4611]

■ Soft Mute Operation

Soft mute operation is performed in the digital domain. When the SMUTE bit becomes “1”, the output signal is attenuated

to -∞ in the cycle set by ATS bits (Table 18) from the current ATT level. When the SMUTE bit is returned to “0”, the

mute is cancelled and the output attenuation gradually changes to the ATT level in the cycle set by ATS bits. If the soft

mute is cancelled before attenuating to -∞ after starting the operation, attenuation is discontinued and it is returned to ATT

level by the same cycle. Soft mute is effective for changing the signal source without stopping the signal transmission.

SMUTE bit

(1)

(2)

ATT Level

Attenuation

(4)

-∞

GD

(3)

AOUT

(5)

8192/fs

DZF1,2

Notes:

(1) The time for input data attenuation to -∞ (Table 18). For example, in Normal Speed Mode, this time is 4096LRCK

cycles (4096/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH

(2) The time for input data recovery to ATT level (Table 18). For example, in Normal Speed Mode, this time is

4096LRCK cycles (4096/fs) at ATT-DATA=FFH. ATT transition of soft-mute is from FFH to 00H.

(3) The analog output corresponding to the digital input has group delay, GD.

(4) If the soft mute is cancelled before attenuating to -∞, the attenuation is discontinued and returned to ATT level by

the same cycle.

(5) When the input data at all the channels of the group are continuously zeros for 8192 LRCK cycles, DZF1, 2 pins of

each channel goes to “H”. DZF1/2 pins immediately returns to “L” if the input data of either channel of the group

are not zero after going “H”.

Figure 43. Soft mute and zero detection

■ System Reset

The AK4611 should be reset once by bringing the PDN pin = “L” upon power-up. The AK4611 is powered up and the

internal timing starts clocking by LRCK “↑” after exiting the power down state of reference voltage (such as VCOM) by

MCLK. The AK4611 is in power-down mode until MCLK and LRCK are input.

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[AK4611]

■ Power-Down

All ADCs and DACs of the AK4611 are placed in power-down mode by bringing the PDN pin “L” which resets both

digital filters at the same time. The PDN pin “L” also resets the control registers to their default values. In power-down

mode, when the DVMPD pin “L”, the analog outputs go to VCOM voltage, when the DVMPD pin =“H”, the analog

outputs go to Hi-Z. The SDTO1-2, DZF1-2 pins go to “L” in the power-dwon mode. This reset should always be executed

after power-up. For the ADC, an analog initialization cycle (518/fs) starts 3~4/fs after exiting power-down mode. The

output data, SDTO1-2, is available after 521~522 cycles of the LRCK clock. For the DAC, an analog initialization cycle

(516/fs) starts 3~4/fs after exiting power-down mode. The analog outputs are VCOM voltage when the DVMPD =pin

“L”, and the analog outputs go to Hi-Z when the DVMPD pin =“H” during the initialization. Figure 44 shows the

power-down and power-up sequences.

Power

(10)

3~4/fs

PDN

(12)

(1)

518/fs

ADC Internal

State

Init Cycle

Normal Operation

Power-down

516/fs

(2)

DAC Internal

State

Init Cycle

(3)

GD

ADC In

(Analog)

ADC Out

(Digital)

“0”data

(6)

(4)

“0”data

DAC In

(Digital)

(3)

GD

(5)

(7)

DAC Out

(Analog)

(7)

Clock In

MCLK,LRCK,SCLK

Don’t care

(11)

10~11/fs

(7)

DZF1/DZF2

Don’t care

External

Mute

Mute ON

(9)

Mute ON

Notes:

(1) The analog part of ADC is initialized after exiting power-down state.

(2) The analog part of DAC is initialized after exiting power-down state.

(3) Digital output corresponds to analog input and analog output corresponds to digital input have group delay (GD).

(4) ADC output is “0” data at power-down state.

(5) The analog outputs are VCOM voltage when the DVMPD pin “L”, and the analog outputs go to Hi-Z when the

DVMPD pin “H” in power-down mode.

(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise

influences system applications.

(7) Click noise occurs at the falling edge of PDN and at 519~520/fs after the rising edge of the PDN pin.

(8) DZF1-2 pins are “L” in power-down mode (PDN pin = “L”).

(9) Please mute the analog output externally if the click noise (7) influences system applications.

(10) There is a delay, 3~4/fs from PDN pin “H” to the start of initial cycle.

(11) DZF pin= “L” for 10∼11/fs after PDN pin = “↑”.

(12) The PDN pin must be “L” when power up the AK4611 and set to “H” after all poweres are supplied.

Figure 44. Pin power-down/Pin power-up sequence example

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[AK4611]

All ADCs and all DACs can be powered-down individually through the PMADC bits and PMDAC bits, when the PMVR

bit “1”. ADC1-2 can be power-down individually through the PMAD2-1 bits. DAC1-4 can be power-down individually

by PMDA4-1 bits. In this case, the internal register values are not initialized. When PMADC bit = “0”, SDTO1-2 goes to

“L”. When PMDAC bit = “0”, the analog outputs go to VCOM voltage when the DVMPD pin is “L”, and the analog

outputs go to Hi-Z when the DVMPD pin “H”. When PMDAC bit = “0”, DZF1-2 pins go to “H”. As some click noise

occurs, the analog output should be muted externally if the click noise influences system applications. Figure 45 shows

the power-down and power-up sequences.

PMVR bit

4~5/fs (10)

3~4/fs (11)

518/fs

PMADC/PMDAC bit

(1)

ADC Internal

State

Normal Operation

Power-down

Init Cycle

516/fs

Normal Operation

(2)

DAC Internal

State

Init Cycle

Normal Operation

GD

(3)

GD

ADC In

(Analog)

(4)

ADC Out

(Digital)

(6)

“0”data

DAC In

(Digital)

“0”data

(3)

GD

(7)

(5)

(7)

DAC Out

(Analog)

Clock In

MCLK,LRCK,SCLK

Don’t care

(8)

8∼9/fs (12)

DZF1/DZF2

External

Mute

(9)

Mute ON

Notes:

(1) The analog section of ADC is initialized after exiting power-down state.

(2) The analog section of DAC is initialized after exiting power-down state.

(3) Digital output corresponding to the analog inputs and analog outputs corresponding to the digital inputs have group

delay (GD).

(4) ADC output is “0” data at power-down state.

(5) The analog outputs are VCOM voltage when the DVMPD pin “L”, and the analog outputs go to Hi-Z when the

DVMPD pin “H” in power-down mode.

(6) Click noise occurs at the end of initialization of the analog part. Mute the digital output externally if the click noise

influences system application.

(7) Click noise occurs at 4∼5/fs after PMDAC bit becomes “0”, and occurs at 519∼520/fs after PMDAC bit becomes

“1”.

(8) DZF1-2 pins are “H” in power-down mode (PMDAC bit = “0”).

(9) Mute the analog output externally if the click noise (7) influences system application.

(10) There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable ADC power-down.

There is a delay, 4~5/fs from PMDAC bit becomes “0” to the applicable DAC power-down.

(11) There is a delay, 3~4/fs from PMADC and PMDAC bits become “1” to the start of initial cycle.

(12) DZF pin= “L” for 8∼9/fs after PMDAC bit becomes “1”.

Figure 45. Bit power-down/Bit power-up sequence example

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[AK4611]

■ Reset Function

When RSTN bit= “0”, the analog and digital part of ADC and the digital part of DACs are powered-down, but the internal

register are not initialized. The analog outputs go to VCOM voltage regardless of the DVMPD pin setting, then DZF1-2

pins go to “H” and SDTO1-2 pins go to “L”. As some click noise occurs, the analog output should be muted externally if

the click noise influences system application. Figure 46 shows the power-up sequence.

RSTN bit

4~5/fs (8)

3~4/fs (9)

Internal

RSTN bit

(1)

518/fs

ADC Internal

State

Power-down

Normal Operation

Init Cycle

DAC Internal

State

Digital Block Power-down

Normal Operation

GD

Normal Operation

(2)

GD

ADC In

(Analog)

(3)

ADC Out

(Digital)

(4)

“0”data

DAC In

(Digital)

“0”data

(2)

GD

(6)

(5)

(6)

DAC Out

(Analog)

Clock In

MCLK,LRCK,SCLK

Don’t care

8∼9/fs (7)

DZF1/DZF2

Notes:

(1) The analog section of the ADC is initialized after exiting reset state.

(2) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group

delay (GD).

(3) ADC output is “0” data at power-down state.

(4) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise

influences system application.

(5) The analog outputs go to VCOM voltage regardless of the DVMPD pin setting when RSTN bit becomes “0”.

(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 3∼4/fs after RSTN bit becomes “1”.

(7) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 8~9/fs after RSTN bit becomes “1”.

(8) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.

(9) There is a delay, 3~4/fs from RSTN bit “1” to the start of initial cycle.

Figure 46. Reset sequence example

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[AK4611]

■ ADC partial Power-Down Function

All of the ADCs can be powered-down individually by PMAD2-1 bits. The analog section and the digital section of the

ADC are in power-down mode when the PMAD2-1 bits = “0”. The analog section of ADCs are initialized after exiting the

power-down state. Digital output corresponding to analog input have group delay (GD). ADC output is “0” data at the

power-down state. Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the

click noise influences system applications. Figure 47 shows the power-down and power-up sequences by PMAD2-1 bits.

PMAD2-1 bit

4~5/fs (1)

2~3/fs (2)

4~5/fs (1)

Power Down Channel

ADCDigital

Internal State

Normal Operation

Power-down

Normal Operation

518/fs (3)

Init Cycle

518/fs (3)

Init Cycle

ADC Analog

Internal State

Normal Operation

GD

Normal Operation Power-down

Normal Operation

(4)

GD

(4)

ADCIn

(Analog)

(5)

“0”data

ADCOut

(Digital)

(6)

Normal Operation Channel

(4)

GD

ADC In

(Analog)

(5)

“0”data

ADC Out

(Digital)

Clock In

MCLK,LRCK,SCLK

Notes.

(1) There is a delay, 4~5/fs from PMAD2-1 bits become “0” to the applicable ADC power-down.

(2) There is a delay, 2~3/fs from PMAD2-1 bits “1” to the start of initial cycle.

(3) The analog section of the ADC is initialized after exiting reset state.

(4) Analog output corresponding to the digital inputs have group delay (GD).

(5) ADC output is “0” data at power-down state.

(6) Click noise occurs when the internal RSTN bit becomes “1”. Mute the digital output externally if the click noise

influences system application.

Figure 47. ADC partial power-down example

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[AK4611]

■ DAC partial Power-Down Function

All of the DACs can be powered-down individually by PMDA4-1 bits. The analog section and the digital section of the

DAC are placed in power-down mode when the PMDA4-1 bits = “0”. The analog output of the powered-down channels,

which is by PMDA4-1 bits, go to the voltage of VCOM when the DVMPD pin is “L”, and go to Hi-Z when the DVMPD

pin “H”. Although DZF detection is in operation, the AK4611 stops reflecting the result of DZF detection to DZF1-2 pins.

Some click noise occurs in both set-up and release of power-down. Mute the analog output externally or set PMDA4-1

bits when PMDAC bit = “0” or RSTN bit = “0”, if click noise aversely affects system performance. Figure 48 shows the

sequence of the power-down and the power-up by PMDA4-1 bits.

PMDA4-1 bit

4~5/fs (4)

2~3/fs (5)

4~5/fs (4)

Power Down Channel

DAC Digital

Internal State

Normal Operation

Power-down

Normal Operation

516/fs (6)

Init Cycle

516/fs (6)

Init Cycle

DAC Analog

Internal State

Normal Operation

Normal Operation Power-down

Normal Operation

DAC In

(Digital)

“0”data

(1)

GD

(3)

(2)

(3)

(2)

DAC Out

(Analog)

8192/fs

DZF Detect

Internal State

(7)

Normal Operation Channel

DAC In

(Digital)

“0”data

GD

DAC Out

(Analog)

8192/fs

DZF Detect

Internal State

Clock In

MCLK,LRCK,SCLK

(8)

(9)

DZF1/DZF2

Notes:

(1) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital inputs have group

delay (GD).

(2) Analog output of the DAC powered down by PMDA4-1 = “0” and goes to VCOM voltage when the DVMPD pin

=“L”, and the analog outputs go to Hi-Z when the DVMPD pin =“H”.

(3) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 3∼4/fs after RSTN bit becomes “1”. after

PMDA4-1 bits are changed, some click noise occurs immediately at output of the channel changed by the own PD

bits.

(4) The DACs will be powered-down 4~5fs after PMDA4-1 bits = “0”

(5) The initiation stars 2~3fs after PMDA4-1 bits are set to “1”.

(6) The analog parts of DACs are initilised after exiting power down mode.

(7) Although DZF detection is active at a certain channel set up though PMDA4-1 = “0”, the AK4611 stops reflecting

the result of DZF detection to DZF1-2 pins.

(8) DZF detection of the DAC which is set up by the power-down setting is ignored, and DZF1-2 pins go to “H”.

(9) When signal is input to a DAC, even if the partical power down is applied, DZF1-2 pins will not become “H”.

Figure 48. DAC partial power-down example

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[AK4611]

■ Serial Control Interface

The AK4611’s functions are controlled through registers. The registers may be written by two types of control modes.

The chip address is determined by the state of the CAD0 and CAD1 inputs. The PDN pin = “L” initializes the registers to

their default values. Writing “0” to the RSTN bit can initialize the internal timing circuit, but the register data will not be

initialized.

(1) 4-wire Serial Control Mode (I2C pin = “L”)

The internal registers may be written through the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO). The data on

this interface consists of a 2-bit Chip address, Read/Write, Register address (MSB first, 5bits) and Control data (MSB

first, 8bits). The chip address high bit is fixed to “1” and the lower bit is set by the CAD0 pin. Address and data are

clocked in on the rising edge of CCLK and data is clocked out on the falling edge. After a low-to-high transition of CSN,

data is latched for write operations and CDTO bit outputs Hi-Z. The clock speed of CCLK is 5MHz (max). The value of

internal registers is initialized when the PDN pin = “L”.

CSN

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CCLK

“H” or “L”

CDTI

CDTO

CDTI

C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

Hi-Z

WRITE

READ

“H” or “L”

C1 C0 R/W A4 A3 A2 A1 A0

Hi-Z

CDTO

D7 D6 D5 D4 D3 D2 D1 D0

C1 – C0: Chip Address (C1=CAD1, C0=CA0)

R/W: READ / WRITE (“1”: WRITE, “0”: READ)

A4 - A0: Register Address

D7 – D0: Control Data

Figure 49. Serial Control I/F Timing

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[AK4611]

(2) I²C-bus Control Mode (I2C pin = “H”)

The AK4611 supports the fast-mode I²C-bus (max: 400kHz).

(2)-1. WRITE Operations

Figure 50 shows the data transfer sequence of the I²C-bus mode. All commands are preceded by START condition. A

HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 56). After the START

condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W).

The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1 and CAD0 (device

address bit). This bit identifies the specific device on the bus. The hard-wired input pins (CAD1/0 pins) set these device

address bits (Figure 51). If the slave address matches that of the AK4611, the AK4611 generates an acknowledge and the

operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)

during the acknowledge clock pulse (Figure 57). R/W bit = “1” indicates that the read operation is to be executed. “0”

indicates that the write operation is to be executed.

The second byte consists of the control register address of the AK4611. The format is MSB first, and those most

significant 3-bits are fixed to zeros (Figure 52). The data after the second byte contains control data. The format is MSB

first, 8bits (Figure 53). The AK4611 generates an acknowledge after each byte is received. Data transfer is always

terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH

defines STOP condition (Figure 56).

The AK4611 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4611

generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the

write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is

incremented by one, and the next data is automatically taken into the next address.

The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data

line can only change when the clock signal on the SCL line is LOW (Figure 58) except for the START and STOP

conditions.

S

T

O

P

T

A

R

T

R/W="0"

Slave

Address

Sub

Address(n)

S

Data(n)

Data(n+1)

Data(n+x)

P

SDA

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

Figure 50. Data Transfer Sequence at the I²C-Bus Mode

0

1

0

CAD1 CAD0

R/W

(Those CAD1/0 should match with CAD1/0 pins)

Figure 51. The First Byte

0

A4

A3

A2

A1

D1

A0

D0

Figure 52. The Second Byte

D7

D6

D5

D4

D3

D2

Figure 53. Byte Structure after the second byte

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[AK4611]

(2)-2. READ Operations

Set the R/W bit = “1” for the READ operation of the AK4611. After transmission of data, the master can read the next

address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.

After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is

automatically taken into the next address.

The AK4611 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.

(2)-2-1. CURRENT ADDRESS READ

The AK4611 contains an internal address counter that maintains the address of the last word accessed, incremented by

one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would

access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK4611 generates an

acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal

address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK4611

ceases transmission.

S

T

O

P

T

A

R

T

R/W="1"

Slave

Address

S

Data(n)

Data(n+1)

Data(n+2)

Data(n+x)

P

SDA

M

A

S

T

E

R

M

A

S

T

E

R

M

A

S

T

E

R

M

A

S

T

E

R

M

A

S

T

E

R

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

N

A

C

K

Figure 54. CURRENT ADDRESS READ

(2)-2-2. RANDOM ADDRESS READ

The random read operation allows the master to access any memory location at random. Prior to issuing a slave address

with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave

address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master

immediately reissues the start request and the slave address with the R/W bit =“1”. The AK4611 then generates an

acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an

acknowledge but generates a stop condition instead, the AK4611 ceases transmission.

S

T

A

R

T

S

T

A

R

T

S

T

O

P

R/W="0"

R/W="1"

Slave

Address

Sub

Address(n)

Slave

Address

S

Data(n)

Data(n+1)

Data(n+x)

P

SDA

M

A

S

T

E

R

M

A

S

T

E

R

M

A

S

T

E

R

M

A

S

T

E

R

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

N

A

C

K

Figure 55. RANDOM ADDRESS READ

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[AK4611]

SDA

SCL

S

P

start condition

stop condition

Figure 56. START and STOP Conditions

DATA

OUTPUT BY

TRANSMITTER

not acknowledge

DATA

OUTPUT BY

RECEIVER

acknowledge

SCL FROM

MASTER

2

1

8

9

S

clock pulse for

acknowledgement

START

CONDITION

Figure 57. Acknowledge on the I²C-Bus

SDA

SCL

data line

stable;

data valid

change

of data

allowed

Figure 58. Bit Transfer on the I²C-Bus

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[AK4611]

■ Register Map

Addr Register Name

00H Power Management 1

01H Power Management 2

02H Power Management 3

03H Control 1

04H Control 2

05H De-emphasis1

06H Reserved

D7

0

D6

0

D5

0

D4

0

D3

PMVR

0

PMDA4

DIF0

DFS1

DEM21

0

D2

PMADC

1

PMDA3

ATS1

DFS0

DEM20

1

D1

D0

PMDAC

PMAD2

PMDA2

ATS0

ACKS

DEM11

0

RSTN

PMAD1

PMDA1

SMUTE

DIV

0

1

TDM1

0

DEM41

0

TDM0

MCKO

DEM40

0

DIF2

CKS1

DEM31

0

DIF1

CKS0

DEM30

0

DEM10

1

07H Overflow Detect

08H Zero Detect

09H Input Control

0

OVFE

DZFM3

0

OVFM2

DZFM2

1

OVFM1

DZFM1

DIE2

OVFM0

DZFM0

DIE1

LOOP1

0

LOOP0

0

0AH Output Control

0

1

DOE4

ATT3

DOE3

ATT2

DOE2

ATT1

DOE1

ATT0

0BH LOUT1 Volume Control

0CH ROUT1 Volume Control

0DH LOUT2 Volume Control

0EH ROUT2 Volume Control

0FH LOUT3 Volume Control

10H ROUT3 Volume Control

11H LOUT4 Volume Control

12H ROUT4 Volume Control

ATT7

ATT6

ATT5

ATT4

Note: For addresses from 13H to 1FH, data is not written.

When the PDN pin goes to “L”, the registers are initialized to their default values.

When RSTN bit goes to “0”, the internal timing is reset and the DZF1-2 pins go to “H”, but registers are not

initialized to their default values.

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[AK4611]

■ Register Definitions

Addr Register Name

00H Power Management 1

R/W

D7

0

D6

0

D5

0

D4

0

D3

PMVR

D2

D1

D0

RSTN

PMADC PMDAC

RD

0

RD

0

RD

0

RD

0

R/W

1

R/W

1

R/W

1

R/W

1

Default

RSTN: Internal timing reset

0: Reset. DZF1-2 pins go to “H”, but registers are not initialized.

1: Normal operation

PMDAC: Power management of DAC1-4

0: Power-down

1: Normal operation

PMADC: Power management of ADC1-2

0: Power-down

1: Normal operation

PWVR: Power management of reference voltage

0: Power-down

1: Normal operation

When any blocks are powered-up, the PMVR bit must be set to “1”. PMVR bit can be set to “0” only when

PMADAL=PMADAR= bits = “0”.

Addr Register Name

D7

0

D6

0

D5

0

D4

0

D3

0

D2

1

D1

D0

01H

Power Management 2

PMAD2 PMAD1

RD

0

RD

0

RD

0

RD

0

RD

0

R/W

Default

RD

1

R/W

1

R/W

1

PMAD2-1: Power management of ADC1-2 (0: Power-down, 1: Normal operation)

PMAD1: Power management control of ADC1

PMAD2: Power management control of ADC2

D7

D6

D5

D4

D3

D2

D1

D0

Addr Register Name

02H Power Management 3

R/W

0

RD

0

RD

0

1

RD

1

RD

1

PMDA4 PMDA3 PMDA2 PMDA1

R/W

1

R/W

1

R/W

1

R/W

1

Default

PMDA4-1: Power management of DAC1-4 (0: Power-down, 1: Normal operation)

PMDA1: Power management control of DAC1

PMDA2: Power management control of DAC2

PMDA3: Power management control of DAC3

PMDA4: Power management control of DAC4

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[AK4611]

Addr Register Name

03H Control 1

R/W

D7

D6

D5

DIF2

R/W

1

D4

DIF1

R/W

0

D3

DIF0

R/W

0

D2

ATS1

R/W

0

D1

ATS0

R/W

0

D0

SMUTE

R/W

0

TDM1 TDM0

R/W

0

R/W

0

Default

SMUTE: Soft Mute Enable

0: Normal operation

1: All DAC outputs soft-muted

ATS1-0: Digital attenuator transition time setting (Table 18)

Initial: “00”, mode 0

DIF2-0: Audio Data Interface Modes (Table 11, Table 12, Table 13, Table 14)

Initial: “100”, mode 4

TDM1-0: TDM Format Select (Table 11, Table 12, Table 13, Table 14)

Mode TDM1 TDM0

SDTI

1-6

1

1-2

1-3

Sampling Speed

0

1

2

3

0

1

0

1

Stereo mode (Normal, Double, Quad Speed Mode)

TDM512 mode (Normal Speed Mode)

TDM256 mode (Double Speed Mode)

TDM128 mode (Quad Speed Mode)

Addr Register Name

04H Control 2

D7

0

D6

MCKO

D5

CKS1

D4

CKS0

D3

DFS1

D2

DFS0

D1

ACKS

D0

DIV

R/W

Default

RD

0

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

DIV: Output of Master clock frequency

0: x 1

1: x 1/2

ACKS: Master Clock Frequency Auto Setting Mode Enable

0: Disable, Manual Setting Mode

1: Enable, Auto Setting Mode

Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS are

ignored. When this bit is “0”, DFS0, 1 set the sampling speed mode.

DFS1-0: Sampling speed mode (Table 1)

The setting of DFS is ignored at ACKS bit =“1”.

CKS1-0: Master Clock Input Frequency Select (Table 2)

MCKO: Master clock output enable

0: Output “L”

1: Output “MCKO”

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[AK4611]

Addr Register Name

05H De-emphasis1

R/W

D7

D6

D5

D4

D3

D2

D1

D0

DEM10

R/W

1

DEM41 DEM40 DEM31 DEM30 DEM21 DEM20 DEM11

R/W

0

R/W

1

R/W

0

R/W

1

R/W

0

R/W

1

R/W

0

Default

DEMA11-10: De-emphasis response control for DAC1 data on SDTI1 (Table 8)

Initial: “01”, OFF

DEMA21-20: De-emphasis response control for DAC2 data on SDTI1 (Table 8)

Initial: “01”, OFF

DEMA31-30: De-emphasis response control for DAC3 data on SDTI1 (Table 8)

Initial: “01”, OFF

DEMA41-40: De-emphasis response control for DAC4 data on SDTI1 (Table 8)

Initial: “01”, OFF

Addr Register Name

07H Overflow Detect

R/W

D7

0

RD

0

D6

0

RD

0

D5

0

RD

0

D4

0

RD

0

D3

OVFE

R/W

0

D2

D1

D0

OVFM2 OVFM1 OVFM0

R/W

1

R/W

1

R/W

1

Default

OVFM2-0: Overflow detect mode select (Table 15)

Initial: “111”, disable

OVFE: Overflow detection enable (Table 15)

0: Disable, pin#33 becomes DZF2 pin.

1: Enable, pin#33 becomes OVF pin.

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[AK4611]

Addr Register Name

08H Zero Detect

D7

LOOP1

R/W

0

D6

LOOP0

R/W

0

D5

0

D4

0

D3

DZFM3

R/W

1

D2

DZFM2

R/W

1

D1

DZFM1

R/W

1

D0

DZFM0

R/W

1

RD

0

RD

0

R/W

Default

DZFM3-0: Zero detect mode select (Table 16)

Initial: “1111”, disable

LOOP1-0: Loopback mode enable

00: Normal (No loop back)

01: LIN1 → LOUT1, LOUT2

RIN1 → ROUT1, ROUT2

LIN2 → LOUT3, LOUT4

RIN2 → ROUT3, ROUT4

The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to

SDTI1-4 are ignored. The audio format of SDTO at loopback mode becomes mode 3 at mode 0 or 1,

and mode 5 at mode 2, respectively.

10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)

SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)

In this mode, the input DAC data to SDTI2-4 are ignored.

11: Not Available

LOOP1-0 should be set to “00” at TDM mode.

Addr Register Name

09H Output Control

R/W

D7

0

RD

0

D6

0

RD

0

D5

0

RD

0

D4

0

RD

0

D3

0

RD

0

D2

1

RD

1

D1

DIE2

R/W

1

D0

DIE1

R/W

1

Default

DIE2-1: ADC1-2 Differential Input Enable (0: Single-End Input, 1: Differential Input)

DIE1: ADC1 Differential Input Enable

DIE2: ADC2 Differential Input Enable

Addr Register Name

0AH Output Control

R/W

D7

0

RD

0

D6

0

RD

0

D5

1

RD

1

D4

1

RD

1

D3

DOE4

R/W

1

D2

DOE3

R/W

1

D1

DOE2

R/W

1

D0

DOE1

R/W

1

Default

DOE4-1: DAC1-4 Differential Output Enable (0: Single-End Input, 1: Differential Input)

DOE1: DAC1 Differential Output Enable

DOE2: DAC2 Differential Output Enable

DOE3: DAC3 Differential Output Enable

DOE4: DAC4 Differential Output Enable

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[AK4611]

Addr Register Name

D7

D6

D5

D4

D3

D2

D1

D0

0BH LOUT1 Volume Control

0CH ROUT1 Volume Control

0DH LOUT2 Volume Control

0EH ROUT2 Volume Control

0FH LOUT3 Volume Control

10H ROUT3 Volume Control

11H LOUT4 Volume Control

12H ROUT4 Volume Control

R/W

ATT7 ATT6

ATT5

R/W

ATT4

R/W

ATT3

R/W

ATT2

R/W

ATT1

R/W

ATT0

R/W

0

R/W

0

Default

0

ATT7-0: Attenuation Level (Table 17)

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[AK4611]

SYSTEM DESIGN

Condition: Differential Input (DIE2-1 bit = “11”), Differential Output (DOE4-1 bit = “1111”)

4-wire Serial Control Interface (I2C pin = “L”)

Master mode (M/S pin = “H”)

The AK4611 has the analog Anti-Alias Filter for Differential Input.

The AK4611 does not have the analog Smoothing Filter for Differential Output.

+

LPF

LPF LPF

LPF

MUTE

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

LOUT2+ 40

ROUT1- 39

ROUT1+- 38

LOUT1- 37

LOUT1+ 36

DVMPD 35

TST8 34

TST15

TST16

OVF1 / DZF1

OVF2 / DZF2

LIN1+

LPF

MUTE

LIN1-

RIN1+

RIN1-

TST7 33

SDTI4

SDTI3 31

SDTI2

LIN2+

32

LIN2-

AK4611

RIN2+

30

SDTI1 29

BICK 28

RIN2-

DSP

TST17

TST18

VSS1

LRCK

TST6 26

27

10u 0.1u

+

Analog 3.3V

SDTO2

SDTO1

AVDD1

VREFH1

VCOM

TST19

TST20

25

24

0.1u

2.2u

+

0.1u 10u

+

VSS4 23

TVDD1

XTI / MCLK 21

22

1.6V to 3.6V

Digital

+

C1

Analog Ground

Digital Ground

µP

Figure 59. Typical Connection Diagram1

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[AK4611]

Condition: Single-end Input (DIE2-1 bit = “00”), Single-end Output (DOE4-1 bit = “0000”)

I²C Bus Control Interface (I2C pin = “H”)

Slave mode (M/S pin = “L”)

The AK4611 has the analog Anti-Alias Filter for Single-Ended Input.

The AK4611 has the analog Smoothing Filter for Single-Ended Output.

+

61

LOUT2 40

ROUT1- 39

ROUT1 38

LOUT1- 37

LOUT1 36

DVMPD 35

TST8 34

TST15

62 TST16

OVF1 / DZF1

MUTE

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

MUTE

OVF2 / DZF2

LIN1

LIN1-

RIN1

TST7 33

RIN1-

SDTI4 32

SDTI3 31

SDTI2 30

SDTI1 29

BICK 28

LIN2

LIN2-

AK4611

RIN2

RIN2-

DSP

TST17

TST18

VSS1

LRCK 27

TST6 26

10u 0.1u

+

Analog 3.3V

SDTO2 25

AVDD1

VREFH1

VCOM

TST19

TST20

SDTO1

24

0.1u

2.2u

+

0.1u 10u

+

VSS4 23

TVDD1 22

1.6V to 3.6V

Digital

XTI / MCLK 21

+

Analog Ground

Digital Ground

µP

Figure 60. Typical Connection Diagram2

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[AK4611]

1. Grounding and Power Supply Decoupling

The AK4611 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2, TVDD1 and

TVDD2 are usually supplied from analog supply in system. Alternatively if AVDD1, AVDD2, TVDD1 and TVDD2 are

supplied separately, the power up sequence is not critical. VSS1, VSS2, VSS3 and VSS4 of the AK4611 must be

connected to analog ground plane. System analog ground and digital ground should be connected together near to

where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4611 as

possible, with the small value ceramic capacitor being the nearest.

2. Voltage Reference Inputs

The voltage of VREFH1, VREFH2 set the analog input/output range. The VREFH1 pin is normally connected to AVDD1

with a 0.1µF ceramic capacitor. The VREFH2 pin is normally connected to AVDD2 with a 0.1µF ceramic capacitor.

VCOM is a signal ground of this chip and output the voltage AVDD1x1/2. An electrolytic capacitor 2.2µF parallel with a

0.1µF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. Ceramic capacitors

should be as near to the pin as possible. No load current may be drawn from the VCOM pin. All signals, especially clocks,

should be kept away from the VREFH1, VREFH2 and VCOM pins in order to avoid unwanted coupling into the AK4611.

3. Analog Inputs

The ADC inputs correspond to single-ended and differential are able to select by DIE2-1 bits. When the inputs are

single-ended, internally biased to the common voltage (AVDD1x1/2) with 9kΩ(typ) resistance. The input signal range

scales with the supply voltage and nominally 0.65xVREFH1 Vpp (typ) @fs=48kHz. When the inputs are differential,

internally biased to the common voltage (AVDD2x1/2) with 13kΩ(typ) resistance. The input signal range between

LIN(RIN)+ and LIN(RIN)− scales with the supply voltage and nominally ±0.65xVREFH1 Vpp (typ) @fs=48kHz The

ADC output data format is 2’s complement. The internal HPF removes the DC offset.

The AK4611 samples the analog inputs at 128fs (@ fs=48kHz). The digital filter rejects noise above the stop band except

for multiples of the sampling frequency of analog inputs. The AK4611 includes an anti-aliasing filter (RC filter) to

attenuate a noise around the sampling frequency of analog inputs.

4. Analog Outputs

The DAC outputs correspond to single-ended and differential are able to select by DOE4-1 bits. When the outputs are

single-ended, the output signal range is centered around the VCOM voltage and nominally 0.63 x VREFH2 Vpp. When

the outputs are differential, the output signal ranges are ±0.63 x VREFH2 Vpp (typ) centered around the VCOM voltage.

The differential outputs are summed externally, V_AOUT= [L(R)OUT+]-[L(R)OUT-] between L(R)OUT+ and L(R)OUT-.

If the summing gain is 1, the output range is 4.16Vpp (typ@AVDD2=3.3V). The bias voltage of the external summing

circuit is supplied externally. The DAC input data format is 2’s complement. The output voltage is a positive full scale for

7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for

000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC

beyond the audio passband, when the single-end input mode. The differential output mode does not have the internal

analog filters, therefore this noise should be remove by the external analog filters.

DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.

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[AK4611]

5. External Analog Inputs Circuit

Figure 61 shows the input buffer circuit example 1. The input level of this circuit is 4.3Vpp (AK4611: typ. ±2.15Vpp).

5.1kΩ

4.7kΩ

Analog In

VP+

4.3Vpp

4.7kΩ

10kΩ

2.15Vpp

22μ

AIN+

VP-

VA

NJM5532

AK4611

Bias NJM5532

Bias

10k

0.1μ 10μ

AIN-

VA = +3.3V

VP+ = +12V

VP- = -12V

Bias

Figure 61. Input buffer circuit example 1 (DC coupled single-end input)

Figure 62 shows the input buffer circuit example 2. The input level of this circuit is 4.3Vpp (AK4611: typ. ±2.15Vpp).

5.1kΩ

4.7kΩ

Analog In

VP+

4.3Vpp

4.7kΩ

10kΩ

2.15Vpp

22μ

AIN+

VP-

NJM5532

10μ

VP+ = +12V

VP- = -12V

NJM5532

AK4611

AIN-

Figure 62. Input buffer circuit example 2 (AC coupled single-end input)

Figure 63 shows the input buffer circuit example 3. The input level of this circuit is ±2.15Vpp (AK4611: typ. ±2.15Vpp).

Analog In

2.15Vpp

AIN+

10μ

AK4611

Analog In

2.15Vpp

AIN-

Figure 63. Input buffer circuit example 3 (AC coupled differential input)

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Figure 64 shows the input buffer circuit example 4. The input level of this circuit is ±2.15Vpp (AK4611: typ. ±2.15Vpp).

Analog In

2.15Vpp

AIN+

10μ

AK4611

AIN-

Open

Figure 64. Input buffer circuit example 4 (AC coupled single-end input)

6. External Analog Outputs Circuit

Figure 65 shows the output buffer circuit example 1. The output level of this circuit is 4.16Vpp (AK4611: typ. ±2.08Vpp).

2.08Vpp

20Ω

A

4.7kΩ

AOUT-

470p

R1

2200p

VP+

VP-

AK4611

3900p

4.7kΩ

20Ω

Analog Out

4.16Vpp

AOUT+

B

VP+ = +12V

VP- = -12V

470p

2.08Vpp

4.7kΩ

NJM5532

WhenR1=200Ω

fc=93.2kHz, Q=0.712, g=-0.1B at40kHz

WhenR1=180Ω

fc=98.2kHz, Q=0.681, g=-0.2dBat40kHz

Figure 65. Output buffer circuit example 1 (DC coupled differential output)

Figure 66 shows the output buffer circuit example 2. The output level of this circuit is 4.16Vpp (AK4611: typ. ±2.08Vpp).

2.08Vpp

4.7kΩ

20Ω

A

AOUT-

22μ

470p

R1

2200p

3900p

4.7kΩ

AK4611

VP+

20Ω

Analog Out

4.16Vpp

AOUT+

VP-

B

VP+ = +12V

VP- = -12V

2.08Vpp

4.7kΩ

470p

NJM5532

WhenR1=180Ω

fc=90.1kHz, Q=0.735, g=-0.04Bat40kHz

WhenR1=150Ω

fc=99.0kHz, Q=0.680, g=-0.23dBat40kHz

Figure 66. Output buffer circuit example 2 (AC coupled differential output)

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Figure 67 shows the output buffer circuit example 3. The output level of this circuit is 4.16Vpp (AK4611: typ. 2.08Vpp).

470p

AOUT-

OPEN

4.7kΩ

VP+

AK4611

2.08Vpp

4.7kΩ

10kΩ

4.7kΩ

470p

Analog Out

4.16Vpp

AOUT+

22μ

VP-

NJM5532

VP+ = +12V

VP- = -12V

Figure 67. Output buffer circuit example 3 (AC coupled single-end output)

Figure 68 shows the output buffer circuit example 4. The output level of this circuit is 2.08Vpp (AK4611: typ. 2.08Vpp).

AOUT-

OPEN

AK4611

2.08Vpp

AOUT+

Analog Out

2.08Vpp

22μ

10kΩ

Figure 68. Output buffer circuit example 4 (AC coupled single-end output)

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PACKAGE

z

80-pin LQFP

( Unit: mm )

14.0±0.2

12.0±0.2

60

41

61

40

80

21

1

20

0° ~ 10°

0.20±0.1

M

0.50

0.08

1.25TYP

0.50±0.2

0.10

■ Package & Lead frame material

Package molding compound:

Lead frame material:

Epoxy resin, Halogen (bromine and chlorine) free

Cu

Lead frame surface treatment:

Solder (Pb free) plate

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MARKING (AK4611EQ)

AK4611EQ

XXXXXXX

1) Pin #1 indication

2) Date Code: XXXXXXX(7 digits)

3) Marking Code: AK4611EQ

4) Asahi Kasei Logo

MARKING (AK4611VQ)

AK4611VQ

XXXXXXX

1) Pin #1 indication

2) Date Code: XXXXXXX(7 digits)

3) Marking Code: AK4611VQ

4) Asahi Kasei Logo

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REVISION HISTORY

Date (YY/MM/DD) Revision Reason

Page

10

Contents

09/02/06

09/06/05

00

01

First Edition

Specification

Change

ANALOG CHARACTERISTICS

ADC Analog Input Characteristics (differential)

S/(N+D) fs=48kHz, -1dBFS: 89 → 88 (min)

AK4611EQ was added.

10/06/14

02

Description

Addition

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

z Descriptions of external circuits, application circuits, software and other related information contained in this

document are provided only to illustrate the operation and application examples of the semiconductor products. You

are fully responsible for the incorporation of these external circuits, application circuits, software and other related

information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third

parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,

intellectual property, or other rights in the application or use of such information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,

or strategic materials.

z AKM products are neither intended nor authorized for use as critical components_Note1)in any safety, life support, or

other hazard related device or system_Note2), and AKM assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety

or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or

perform may reasonably be expected to result in loss of life or in significant injury or damage to person or

property.

z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places

the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer

or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all

claims arising from the use of said product in the absence of such notification.

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型号：	AK4611
厂家：	ASAHI KASEI MICROSYSTEMS
描述：	4/8-Channel Audio CODEC 4/8声道音频编解码器解码器编解码器
文件：	总68页 (文件大小：986K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AK4611 [AKM]

相关型号：

AK4611EQ

AK4611VQ

AK4612

AK4612EQ

AK4612VQ

AK4613

AK4613EQ

AK4613VQ

AK4614

AK4614VQ

AK4616

AK4616VQ