AK5434D [AKM]
Dual channel 14bit 30MHz A/D Converter with differential input; 双通道14位30MHz的A / D转换器，带有差分输入
| 型号： | AK5434D |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Dual channel 14bit 30MHz A/D Converter with differential input |
| 文件： | 总13页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK5434D]
AK5434D
Dual channel 14bit 30MHz A/D Converter with
differential input
Features
【Power Supply】
3.0V~3.45V Single-Supply
【Operation Temperature】 −40°C~+105°C
【Package】 30pinVSOP (Pin pitch 0.65mm)
Input range：
4V (Differential input @ Gain 0dB)
Input signal bandwidth： DC ~ 400MHz (typ.)
S/H Gain：
ADC：
0dB/6dB/12dB
14bit, 30MHz
S/(N+D)：
69dB (typ.)
(30MHz operation, input signal frequency 14.9MHz@1ch)
14bit parallel data with straight binary
172mW @typ. (power consumption @Power Down mode: under 1mW)
Outputs：
Power consumption：
Circuit Block Diagram
Ch1
S/H1
REF
AI1P
AI1N
MUX
A/D
D13~D0
Ch2
S/H2
14
AI2P
AI2N
CONTROL
MS1515-E-00
-1-
2013/02
ASAHI KASEI
[AK5434D]
Clock
S/H1, S/H2
MUX
Function
Sample/Hold AMP
Switch that selects input signal to A/D from S/H1 and S/H2
14bit 30MSPS A/D Converter
A/D
REF
Reference voltage generator
CONTROL
Operation control circuit
Pin Allocation
SS
CHSEL
AVSS
AVDD
AI1P
D0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
15
14
13
12
11
10
9
D1
D2
D3
D4
AI1N
D5
VCM
AI2N
D6
D7
8
AI2P
D8
7
VRP
D9
6
CLKI
D10
D11
D12
D13
PDN
5
GAIN
IREF
4
3
DVSS
DVDD
2
1
MS1515-E-00
-2-
2013/02
ASAHI KASEI
[AK5434D]
Pin Description
No.
Name
I/O @Power
down
Description
1
2
3
4
5
6
7
8
9
PDN
I
−
Power down（H: Normal Operation, L: Power down）
D13
D12
D11
D10
D9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
High-Z ADC output data MSB Straight binary code
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data
High-Z ADC output data LSB
D8
D7
D6
10 D5
11 D4
12 D3
13 D2
14 D1
15 D0
16 SS
−
Sampling timing setting
L: Sampling timing is determined by applying Logic to
CHSEL-pin.
H: The sampling timing is the timing of CHSEL=L. Ch1 and Ch2
are sampled simultaneously.
17 CHSEL
18 AVSS
19 AVDD
20 AI1P
21 AI1N
22 VCM
I
−
−
−
−
−
Ch1/Ch2 select（L:Ch1, H:Ch2）
Analog Ground
PWR
PWR
Analog supply（3.0V～3.45V）
Ch1 differential input P side
I
I
Ch1 differential input N side
O
High-Z Common-mode voltage output
Connect 1μF between AVSS and this pin.
23 AI2N
24 AI2P
25 VRP
I
I
−
−
L
Ch2 differential input N side
Ch2 differential input P side
O
ADC Reference-voltage output.
Connect 1μF between AVSS and this pin.
ADC clock input
26 CLKI
27 GAIN
28 IREF
I
I
−
−
S/H gain setting (L:0dB, M:12dB, H:6dB)
O
High-Z bias current output
Connect 8.2kΩ between AVSS and this pin.
Digital Ground
Digital Power Supply（3.0V~3.45V）
29 DVSS
PWR
PWR
−
−
30 DVDD
(NOTE)IO
I: INPUT, O: OUTPUT, PWR: POWER/GROUND
MS1515-E-00
-3-
2013/02
ASAHI KASEI
[AK5434D]
Absolute Maximum Ratings
AVSS, DVSS=0V,All voltages are with respect to ground
Parameter
Power Supplies
Analog
Digial
Symbol
Min.
Max.
Unit
Note
AVDD
DVDD
−0.3
−0.3
4.0
4.0
V
V
IIN
−10
−0.3
−0.3
10
mA
Except AVDD, AVSS,
DVDD, DVSS pins
Input Current
Analog Input Voltage Range
(Note 1)
Digital Input Voltage Range
(Note 2)
VINA
VIND
AVDD+0.3
DVDD+0.3
V
V
Ta
−40
−65
105
150
°C
°C
Operating Temperature
Storage Temperature
Tstg
(Note 1) AI1P, AI1N, AI2P, AI2N, GAIN, CLKI
(Note 2) CHSEL, SS, PDN
All power supply ground pins (AVSS, DVSS) should be at the same potential.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal Operating Specifications are not guaranteed at these extremes.
Operating Condition
Parameter
Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
Note
Analog (Core)
Digital (Core, IO)
AVDD
DVDD
3.0
3.0
3.3
3.3
3.45
3.45
V
V
Power supply voltages are values where each ground pin (AVSS=DVSS) is at 0V (Voltage reference)
All power supply ground pins (AVSS, DVSS) should be at the same potential.
MS1515-E-00
-4-
2013/02
ASAHI KASEI
[AK5434D]
Electrical Characteristics
Analog Specifications
(AVDD=DVDD=3.3V, S/H gain=0dB, Ta=25°C, CLKI=30MHz, fin=14.9MHz, Signal Level=3.4Vpp-diff)
Parameter
Symbol
Condition
min
Typ
Max
Units
DC Characteristics
Resolution
Integral
RES
INL
14
±10.5
Bits
LSB
±2.8
±0.8
Non-Linearity
Differential
Non-Linearity
Offset
Gain Error
Gain
DNL
±4.0
LSB
EOC
GERR
AIxP=AIxN=VCM (x=1,2)
Gain setting 0dB
Gain setting 6dB
LSB
%FS
dB
±100
+10
6.5
-10
5.5
0
6
Gain setting 12dB
AINFS Gain setting 0dB
11.5
3.6
1.26
1.8
12
4.0
1.4
2.0
12.5
4.4
1.54
2.2
dB
Vpp-diff
V
Input Range
Common Voltage
ADC Reference
Voltage
VCM
VRP
V
AC Characteristics
S/N
SNR
SND
SND2
SFDR
68
64
66
73
69
71
70
70
dB
dB
dB
dB
dBc
S/(N+D)
S/(N+D) (Note 1)
SFDR
Total
Distortion
Input
(Note 1)
Input Capacitance CIN
(Note 1)
Input
bandwidth (Note 1)
CMRR
Crosstalk
Current
fin=1MHz
(Note 4)
Harmonic THD
64
50
Resistance RIN
60
5
kΩ
pF
8
Signal BW
-3dB Level
400
MHz
CMR
CTK
IA
fin=1MHz, common swing -26dB
fin=7.45MHz
Analog fin=1MHz
56
−80
46
6
dB
dB
mA
mA
mA
mA
mA
−70
68
9
0.3
0.1
0.1
Consumption
ID
Digital(Note 2) fin=1MHz
IPD
IAS
IDS
Current
Consumption in
power down
Analog
Digital
(Note 3)
(Note 1) Design Value
(Note 2) CL=10pF are connected to D0~D13 pins.
(Note 3) Power down PDN=Low, CLKI=Low fix, Current consumption without no input signal.
(Note 4) Equivalent resistance that from VCM operation middle point to differential input pins AI1P/N,
AI2P/N. It is in inverse proportion to sampling frequency.
MS1515-E-00
-5-
2013/02
ASAHI KASEI
Switching Characteristics
[AK5434D]
(AVDD=DVDD=3.0~3.45V, Ta=−40~105°C, CL=10pF)
Parameter
Symbol
Conditions
min.
15
33.3
typ.
max.
30
66.7
15
Unit
MHz
ns
Conversion rate
Clock cycle
Clock rise time
Note 1
Clock fall time
Note 1
fs
tcy
tr
0.3AVDD
to 0.7AVDD
0.7AVDD
to 0.3AVDD
2
2
ns
tf
15
ns
Clock High width
Clock Low width
Clock duty
Pipeline delay
Note 2
tH
tL
tduty
tpd
15
15
40
ns
ns
%
50
8
60
CLKI
Aperture delay
Note 2
tap
2
6
4
ns
AD output delay
CHSEL setup
CHSEL hold
Start up time 1
Start up time 2
tdl
tset
thold
tst1
tst2
0
10
10
20
ns
ns
ns
ms
ms
2
2
5
5
Note 1) Clock high width and Low width must be fulfilled.
Note 2) Design Value
tap
N+1
N+8
AI1P/N
AI2P/N
N
0.7AVDD
0.3AVDD
CLKI
tr
tH
tf
tL
tdl
tcy
0.8DVDD
D13~D0
CHSEL
N-8
N
0.2DVDD
tset
thold
0.7DVDD
0.3DVDD
MS1515-E-00
-6-
2013/02
ASAHI KASEI
[AK5434D]
0.7AVDD
PDN
tst1
0.7AVDD
CLKI
tst2
D13~D0
Digital DC Characteristics
(AVDD=DVDD=3.0~3.6V, Ta=－40~105°C)
Parameter
Symbol
VIH1
VIL1
VIH2
VIL2
Pin
Min.
Max.
Unit Remark
V
V
V
V
V
V
V
V
High level input threshold 1
Low level input threshold 1
High level input threshold 2
Low level input threshold 2
High level input threshold 3
Note 1
Note 1
Note 2
Note 2
GAIN
GAIN
GAIN
0.7×DVDD
0.3×DVDD
0.3×AVDD
0.7×AVDD
VIH3
0.8×AVDD
0.3×AVDD 0.7×AVDD
0.2×AVDD
Middle level input threshold 3 VIM3
Low level input threshold 3
High level output voltage
Low level output voltage
Input leakage current
VIL3
VOH
VOL
Note 3, Note 4
Note 3, Note 5
0.8×DVDD
V
0.2×DVDD
ILKG Note 1, Note2,
GAIN
±10
μA
High-Z leakage current
Note 1) CHSEL, SS, PDN,
Note 2) CLKI
IOZ
Note 3
±10
μA
Note 3) D13~D0
Note 4) IOH = −1mA
Note 5) IOL = 1mA
MS1515-E-00
-7-
2013/02
ASAHI KASEI
[AK5434D]
Functional Description
Power down function
Power Down mode can be activated by applying a logic Level “0” to the PDN-pin. All the data
output pins [D13: D0] become Low state.at Power Down mode.
PDN
L
Condition
Power down
H
Normal opration
S/H AMP gain select
The gain of the S/H amplifier can be selected by the input level of GAIN-pin.
GAIN
AVSS
AVDD
VCM
Gain
0dB
Input full scale
4Vpp-diff
6dB
2Vpp-diff
12dB
1Vpp-diff
Sampling timing setting
The sampling timing of two channels can be set with SS-pin.
SS
L
Sampling timing
S/H1 or S/H2 samples the signal according to CHSEL.
H
At CHSEL=L, S/H1 and S/H2 sample the signal at the same time.
Sampling channel select
The samples timing can be selected with CHSEL-pin.
Separate sampling (@SS=Low)
CHSEL
Sampling channel
S/H1
S/H2
L
H
Simultaneous sampling (@SS=High)
CHSEL
Sampling channel
L
S/H1 & S/H2
Not sampled
H
Only at CHSEL=Low, sampling is done at the same timing (SS=High).
MS1515-E-00
-8-
2013/02
ASAHI KASEI
[AK5434D]
Operation timing
At SS=”L”
CLKI
CHSEL
S/H1
S
Hold
S
S
S
Hold
S
S
Hold
S
S/H2
Hold
S
Hold
Hold
A/D sampling
channel
2
1
2
1
2
1
1
2
1
2
1
2
Pipeline delay（ 8CLKI）
D13~D0
CH1 CH2 CH1 CH2 CH1 CH2
At SS=”H”
CLKI
CHSEL
S/H1
S
S
Hold
Hold
S
S
S
S
Hold
Hold
S
S
Hold
Hold
S
S
Hold
Hold
S/H2
Sampling timing
A/D sampling
channel
2
1
2
1
2
1
1
2
1
2
1
2
1
Pipeline delay（ 9CLKI）
Pipeline delay（ 8CLKI）
D13~D0
CH1 CH2 CH1 CH2 CH1 CH2 CH1
MS1515-E-00
-9-
2013/02
ASAHI KASEI
[AK5434D]
External Circuit Examples
0.1μF, 10μF
8.2kΩ±1%
1μF±10%
1μF±10%
IREF
AVDD
AVSS
AVSS
AVSS
AVSS
AVSS
VCM
VRP
0.1μF, 10μF
DVDD
DVSS
DVSS
0.1μF
AIN1P
AIN2P
1kΩ±5%
VCM
1kΩ±5%
0.1μF
AIN1N
AIN2N
Note) Resisters must be metal-film type.
MS1515-E-00
-10-
2013/02
ASAHI KASEI
[AK5434D]
Packages
30-VSOP-0.65
MS1515-E-00
-11-
2013/02
ASAHI KASEI
[AK5434D]
Marking
Marketing Code: AK5434D
Date Code: XXXXXXX
MS1515-E-00
-12-
2013/02
ASAHI KASEI
[AK5434D]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to
current status of the products.
z Descriptions of external circuits, application circuits, software and other related
information contained in this document are provided only to illustrate the operation and
application examples of the semiconductor products. You are fully responsible for the
incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses
incurred by you or third parties arising from the use of these information herein. AKM
assumes no liability for infringement of any patent, intellectual property, or other rights in
the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export
pertaining to customs and tariffs, currency exchange, or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in
any safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure
to function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes,
disposes of, or otherwise places the product with a third party, to notify such third party in
advance of the above content and conditions, and the buyer or distributor agrees to assume
any and all responsibility and liability for and hold AKM harmless from any and all claims
arising from the use of said product in the absence of such notification.
MS1515-E-00
-13-
2013/02
相关型号：
AK5471
ADC, Proprietary Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, CMOS, PDSO24, VSOP-24
AKM
©2020 ICPDF网 联系我们和版权申明