AK6440A [AKM]
2K / 4K / 8Kbit Serial CMOS EEPROM; 2K / 4K / 8Kbit串行EEPROM CMOS
| 型号： | AK6440A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 2K / 4K / 8Kbit Serial CMOS EEPROM |
| 文件： | 总15页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK6420A/40A/80A]
AK6420A / 40A / 80A
2K / 4K / 8Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
Wide Vcc (1.8V 5.5V) operation
•
•
AK6420A 2048 bits: 128 × 16 organization
•
•
AK6440A 4096 bits: 256 × 16 organization
•
•
AK6480A 8192 bits: 512 × 16 organization
ONE CHIP MICROCOMPUTER INTERFACE
- Interface with one chip microcomputer's serial communication port directly
LOW POWER CONSUMPTION
- 0.75mA Max (Read operation)
- 0.8µA Max (Standby mode)
HIGH RELIABILITY
-Endurance
: 100K cycles
: 10 years
-Data Retention
SPECIAL FEATURES
- High speed operation ( fMAX=1MHz:Vcc=2.5V )
- Automatic write cycle time-out with auto-ERASE
- Automatic address increment (READ)
- Ready/Busy status signal
- Software and Hardware controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (SOP, SSOP)
Block diagram
DAS01E-00
1999/05
- 1 -
ASAHI KASEI
[AK6420A/40A/80A]
General Description
The AK6420A/40A/80A is a 2048/4096/8192bit, serial, read/write, non-volatile memory device fabricated using an
advanced CMOS EEPROM technology. The AK6420A has 2048bits of memory organized into 128 registers of 16
bits each. The AK6440A has 4096bits of memory organized into 256 registers of 16 bits each. The AK6480A has
8192bits of memory organized into 512 registers of 16 bits each. The AK6420A/40A/80A can operate full function
under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation
that is used for write operation.
The AK6420A/40A/80A can connect to the serial communication port of popular one chip microcomputer directly (3
line negative clock synchronous interface). At write operation, AK6420A/40A/80A takes in the write data from data
input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation,
AK6420A/40A/80A takes out the read data from a register to data output pin (DO) synchronously with falling edge of
SK.
The AK6420A/40A/80A has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS (write disable).
Each instruction is organized by op-code block (8bits), address block (8bits) and data (8bits × 2). When input level of
SK pin is high level and input level of chip select (CS) pin is changed from high level to low level, AK6420A/40A/80A
can receive the instructions.
Special features of the AK6420A/40A/80A include : automatic write time-out with auto-ERASE, Ready/Busy status
signal output and ultra-low standby power mode when deselected (CS=high).
•
Software and Hardware controlled write protection
The AK6420A/40A/80A has 2 (hardware and software) write protection functions.
After power on or after execution of WRDS (write disable) instruction, execution of WRITE instruction will be disabled.
This write protection condition continues until WREN instruction is executed or Vcc is removed from the part.
Execution of READ instruction is independent of both WREN and WRDS instructions.
Reset pin should be low level when WRITE instruction is executed. When the Reset pin is high level, the WRITE
instruction is not executed.
•
Ready/Busy status signal
During the automatic write time-out period (BUSY status), the AK6420A/40A/80A can't accept the other instructions.
The AK6420A/40A/80A has 2 functions to know the Busy status from exterior.
The RDY/BUSY pin indicates the Busy status regardless of the CS pin status. The RDY/BUSY pin outputs the low
level regardless of the CS pin status during Busy status. Except the above status, this pin outputs high level.
Also the DO pin indicates the Busy status. When input level of SK pin is low level and input level of CS pin is changed
from high level to low level, the AK6420A/40A/80A is in the status output mode and the DO pin indicates the
Ready/Busy status. The Ready/Busy status outputs on DO pin until CS pin is changed from low level to high level, or
first bit ("1") of op-code of next instruction is given to the part. Except when the device is in the status output mode or
outputs data, the DO pin is in the high impedance state.
Type of Products
Model
AK6420AF
Memory size
2Kbits
Temp.Range
-40°C 85°C
-40°C 85°C
-40°C 85°C
-40°C 85°C
-40°C 85°C
-40°C 85°C
Vcc
Package
1.8V 5.5V
1.8V 5.5V
1.8V 5.5V
1.8V 5.5V
1.8V 5.5V
1.8V 5.5V
8pin Plastic SOP
8pin Plastic SSOP
8pin Plastic SOP
8pin Plastic SSOP
8pin Plastic SOP
8pin Plastic SSOP
AK6420AM
AK6440AF
AK6440AM
AK6480AF
AK6480AM
4Kbits
8Kbits
DAS01E-00
1999/05
- 2 -
ASAHI KASEI
[AK6420A/40A/80A]
Pin arrangement
Pin Function
Pin No.
SOP / SSOP
Pin name
I/O
O
Note
1 / 7
2 / 8
RDY/BUSY
Vcc
I : Input pin
3 / 1
4 / 2
CS
SK
I
I
O: Output pin
5 / 3
DI
I
6 / 4
DO
O
7 / 5
8 / 6
GND
RESET
I
DAS01E-00
1999/05
- 3 -
ASAHI KASEI
[AK6420A/40A/80A]
Pin Description
CS (Chip Select)
When SK is high level and CS is changed from high level to low level, AK6420A/40A/80A can receive the
instructions. CS should be kept low level while receiving op-code, address and data and while outputting data.
If CS is changed to high level during the above period, AK6420A/40A/80A stops the instruction execution.
When SK is low and CS is changed from high level to low level, AK6420A/40A/80A will be in status output
mode. The CS need not be low level during the automatic write time-out period (BUSY status).
SK (Serial Clock)
The SK clock pin is the synchronous clock input for input/output data. At write operation, AK6420A/40A/80A
takes in the write data from data input pin (DI) synchronously with rising edge of input pulse of serial clock pin
(SK). And at read operation, AK6420A/40A/80A takes out the read data to data output pin (DO)
synchronously with falling edge of SK. The SK clock is not needed during the automatic write time-out period
(BUSY status), the status output period and when the device isn't selected (CS = high level).
DI (Data Input)
The op-code, address and write data is input to the DI pin.
DO (Data Output)
The DO pin outputs the read data and status signal and will be high impedance except for this timing.
RDY/BUSY (Ready/Busy status)
This pin outputs the internal programming status. When the AK6420A/40A/80A is in the automatic write time-
out period, this pin outputs the low level (BUSY status), and outputs the high level except for this timing.
RESET (Reset)
The AK6420A/40A/80A stops executing the write instruction when the RESET pin is high level. The RESET
pin should be low level while the write instruction input period and the automatic write time-out period. If the
RESET pin is high level while the automatic write time-out period, the AK6420A/40A/80A stops execution of
internal programming and the device returns to ready status. In this case the word data of the specified
address will be incomplete. When inputting the new instruction after RESET, the CS should be set to high
level. The read, write enable and write disable instructions are not affected by RESET pin status.
Vcc (Power Supply)
GND (Ground)
DAS01E-00
1999/05
- 4 -
ASAHI KASEI
[AK6420A/40A/80A]
Functional Description
The AK6420A/40A/80A has 4 instructions such as READ, WRITE, WREN (write enable) and WRDS (write
disable). Each instruction is organized by op-code block (8bits), address block (8bits) and data (8bits × 2).
When input level of SK pin is high level and input level of chip select (CS) pin is changed from high level to low
level, AK6420A/40A/80A can receive the instructions.
When the instructions are executed consecutively, the CS pin should be brought to high level for a minimum of
250ns(Tcs) between consecutive instruction cycle.
Instruction Set For 6420A
Instruction
READ
Op-Code
1 0 1 0 1 0 0 0
1 0 1 0 0 1 0 0
1 0 1 0 0 0 1 1
1 0 1 0 0 0 0 0
1 0 1 0 1 1 1 1
Address
Data
D15 -D0
A6 A5 A4 A3 A2 A1 A0 0
A6 A5 A4 A3 A2 A1 A0 0
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
WRITE
WREN
D15 -D0
WRDS
( WRAL )
D15 -D0
Instruction Set For 6440A
Instruction
Op-Code
Address
Data
READ
WRITE
WREN
WRDS
( WRAL )
1 0 1 0 1 0 0 0
1 0 1 0 0 1 0 0
1 0 1 0 0 0 1 1
1 0 1 0 0 0 0 0
1 0 1 0 1 1 1 1
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
D15 -D0
D15 -D0
D15 -D0
Instruction Set For 6480A
Instruction
Op-Code
Address
Data
READ
WRITE
WREN
WRDS
( WRAL )
1 0 1 0 1 0 0 A8
1 0 1 0 0 1 0 A8
1 0 1 0 0 0 1 1
1 0 1 0 0 0 0 0
1 0 1 0 1 1 1 1
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
ýýýÕýýÕýýÕýýÕýýÕýýÕýýÕýýÕ
D15 -D0
D15 -D0
D15 -D0
Õ:don't care
(Note) The WRAL instruction is used for factory function test only. User can't use this instruction .
DAS01E-00
1999/05
- 5 -
ASAHI KASEI
[AK6420A/40A/80A]
Write
The write instruction is followed by 16 bits of data to be written into the specified address. After the 32nd
rising edge of SK to read D0 in, the AK6420A/40A/80A will be put into the automatic write time-out period.
During the automatic write time-out period (Busy status)and while entering write instruction, the RESET pin
should be low level. If the RESET pin is set to high level during the automatic write time-out period, the
AK6420A/40A/80A stops execution of internal programming and the device returns to ready status. In this
case the word data of the specified address will be incomplete. When inputting the new instruction after
RESET, the CS should be set to high level. When the RESET pin is kept at high level, the write is not
executed. This becomes write protection function.
The CS pin need not be high level during automatic write time-out period (BUSY status).
DAS01E-00
1999/05
- 6 -
ASAHI KASEI
[AK6420A/40A/80A]
Read
The read instruction is the only instruction which outputs serial data on the DO pin. When the 17th falling
edge of SK is received , the DO pin will come out of high impedance state and shift out the data from D15 first
in descending order which is located at the address specified in the instruction.
The data in the next address can be read sequentially by continuing to provide clock. The address
automatically cycles to the next higher address after the 16bit data shifted out.
•
•
AK6420A
AK6440A
AK6480A
When the highest address is reached ($7F), the address counter rolls over to
address $00 allowing the read cycle to be continued indefinitely.
•
•
When the highest address is reached ($FF), the address counter rolls over to
address $00 allowing the read cycle to be continued indefinitely.
•
•
When the highest address is reached ($1FF), the address counter rolls over to
address $000 allowing the read cycle to be continued indefinitely.
DAS01E-00
1999/05
- 7 -
ASAHI KASEI
[AK6420A/40A/80A]
WREN / WRDS ( Write Enable and Write Disable )
When Vcc is applied to the part, it powers up in the programming disable (WRDS) state. Programming must
be preceded by a programming enable (WREN) instruction. Programming remains enabled until a
programming disable (WRDS) instruction is executed or Vcc is removed from the part. The programming
disable instruction is provided to protect against accidental data disturb. Execution of a read instruction is not
affected by both WREN and WRDS instructions.
DAS01E-00
1999/05
- 8 -
ASAHI KASEI
[AK6420A/40A/80A]
Absolute Maximum Ratings
Parameter
Power Supply
Symbol
VCC
Min
-0.6
-0.6
Max
+7.0
Unit
V
All Input Voltages
VIO
VCC+0.6
V
with Respect to Ground
Ambient storage temperature
Tst
-65
+150
°C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of the
specification is not implied. Exposure to absolute maximum conditions for extended
periods may affect device reliability.
Recommended Operating Condition
Parameter
Power Supply
Ambient Operating Temperature
Symbol
VCC
Ta
Min
1.8
-40
Max
5.5
Unit
V
+85
°C
DAS01E-00
1999/05
- 9 -
ASAHI KASEI
[AK6420A/40A/80A]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
( 1.8V≤Vcc≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified )
Parameter
Symbol
ICC1
Condition
Min.
Max.
4.0
Unit
mA
mA
mA
mA
mA
mA
mA
mA
uA
Current Dissipation
VCC=5.5V, tSKP=500ns, *1
VCC=2.5V, *1 6420A
ICC2
2.0
(WRITE)
tSKP=500ns
VCC=1.8V, *1 6420A
tSKP=1.5us
6440A/80A
2.5
ICC3
1.5
6440A/80A
2.0
Current Dissipation
(READ,WREN,
WRDS)
ICC4
ICC5
ICC6
ICCSB
VCC=5.5V, tSKP=500ns, *1
VCC=2.5V, tSKP=500ns, *1
VCC=1.8V, tSKP=1.5us, *1
0.75
0.3
0.15
0.8
Current Dissipation
(Standby)
VCC=5.5V
*2
Input High Voltage1 VIH1
CS, SK, RESET pin
VCC+0.5
V
1.8V≤VCC≤5.5V
0.8 Õ VCC
Input High Voltage2 VIH2
VCC+0.5
VCC+0.5
0.2ÕVCC
V
V
V
2.5V≤VCC≤5.5V
1.8V≤VCC<2.5V
1.8V≤VCC≤5.5V
0.7 Õ VCC
0.8 Õ VCC
0
DI pin
VIH3
Input Low Voltage1
CS, SK, RESET pin
VIL1
Input Low Voltage2
DI pin
VIL2
VIL3
0
0
V
V
V
0.3 Õ VCC
0.2 Õ VCC
2.5V≤VCC≤5.5V
1.8V≤VCC<2.5V
Output High Voltage VOH1
VOH2
VCC-0.3
2.5V≤VCC≤5.5V
IOH=-50µA
VCC-0.3
V
1.8V≤VCC<2.5V
IOH=-50µA
Output Low Voltage
VOL1
VOL2
0.4
0.4
V
V
2.5V≤VCC≤5.5V
IOL=1.0mA
1.8V≤VCC<2.5V
IOL=0.1mA
Input Leakage
ILI
VCC=5.5V,VIN=5.5V
uA
uA
1.0
1.0
Output Leakage
ILO
VCC=5.5V
VOUT=5.5V, CS=VCC
*1: VIN=VIH/VIL,DO=RDY/BUSY=Open
*2: CS=Vcc, SK/DI/RESET=Vcc/GND,DO=RDY/BUSY=Open
DAS01E-00
1999/05
- 10 -
ASAHI KASEI
[AK6420A/40A/80A]
(2) A.C. ELECTRICAL CHARACTERISTICS
( 1.8V≤Vcc≤5.5V, -40°C≤Ta≤85°C, unless otherwise specified )
Parameter
Symbol
tSKP1
Condition
2.5V≤VCC≤5.5V
1.8V≤VCC<2.5V
Min.
500
Max.
Unit
ns
SK Cycle Time
tSKP2
tSKW1
tSKW2
tSKH1
tSKH2
1.5
250
750
250
500
us
ns
ns
ns
ns
SK Pulse Width
2.5V≤VCC≤5.5V
1.8V≤VCC<2.5V
4.5V≤VCC≤5.5V
2.5V≤VCC<4.5V
1.8V≤VCC<2.5V
SK High Pulse Width
*3
tSKH3
tCSS
tCSH
750
100
100
100
ns
ns
ns
ns
CS Setup Time
CS Hold Time
SK Setup Time
tSKSH
/tSKSL
RESET Setup Time
RESET Hold Time
Data Setup Time
tRESS
tRESH
tDIS1
tDIS2
tDIH1
0
ns
ns
ns
ns
ns
0
100
200
100
4.5V≤VCC≤5.5V
1.8V≤VCC<4.5V
4.5V≤VCC≤5.5V
1.8V≤VCC<4.5V
4.5V≤VCC≤5.5V, *4
2.5V≤VCC<4.5V, *4
1.8V≤VCC<2.5V. *4
CL=100pF
Data Hold Time
tDIH2
tPD1
tPD2
tPD3
tPD
200
ns
ns
ns
ns
us
DO pin
150
300
500
1
Output delay
RDY/BUSY pin
Output delay
Selftimed Programming tE/W
Time
10
ms
Write Recovery Time
Min CS High Time
tRC
tCS
100
250
ns
ns
DO High-Z Time
tOZ
500
ns
*3: tSKH is the high pulse width of 16th SK pulse in READ operation. When the data in
the next
address are read sequentially by continuing to provide clock, tSKH are applied to the high
SK
pulse width of 32nd and 48th (multiple of 16)
*4: CL=100pF
pulse in READ operation.
DAS01E-00
1999/05
- 11 -
ASAHI KASEI
[AK6420A/40A/80A]
Synchronous DataTiming
Instruction Input
(note) * = "A0" for AK6420A, "A1" for AK6440A/80A
+ = "0" for AK6420A, "A0" for AK6440A/80A
Data Output (READ)
DAS01E-00
1999/05
- 12 -
ASAHI KASEI
[AK6420A/40A/80A]
DAS01E-00
1999/05
- 13 -
ASAHI KASEI
[AK6420A/40A/80A]
DAS01E-00
1999/05
- 14 -
IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
zAKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
zAny export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
zAKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
zIt is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.
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