AK7780 [AKM]
24bit 5ch ADC & SRC + Audio DSP; 24位ADC 5CH和SRC +音频DSP
| 型号： | AK7780 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 24bit 5ch ADC & SRC + Audio DSP |
| 文件： | 总28页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK7780]
AK7780
24bit 5ch ADC & SRC + Audio DSP
GENERAL DESCRIPTION
The AK7780 is a highly integrated audio processor, including a 28-bit floating point DSP, two 24-bit stereo
ADC’s and one mono ADC. The stereo ADC’s feature high performance, achieving 96dB dynamic range,
they include 8:1 input selectors. The ADC supports sampling frequencies from 7.35 kHz to 96 kHz. The
AK7780 also includes a stereo sample rate converter (SRC), so it can be used as a master device when
it receives digital audio inputs. The DSP includes 168kbits of SRAM for audio delay data that is suitable
for creating simulated surround fields. The programmable DSP block is realized with 2560step/fs DSP. It
supports sampling frequencies from 7.35kHz to 96 kHz. The AK7780 is used to implement complete
sound field control, such as echo, 3D, parametric equalization, and other sound enhancements. It is
packaged in a 100-lead LQFP package.
FEATURES
[DSP]
Main
Word length: 28-bit (Data RAM F24.4 limited range floating point)
Instruction cycle time: 8.1 ns (2560step/fs fs=48kHz; 1280step/fs fs=96kHz)
Multiplier: 24 x 16 → 40-bit (Double precision available)
Divider: 24 / 24 → 24-bit
ALU: 44-bit arithmetic operation (overflow margin: 4-bits)
F24.4 arithmetic and logic operation
Shift+Register: Flexible setting
Program RAM: 2048 x 36-bit
Coefficient RAM: 2048 x 16-bit
Data RAM: 2048 x 28-bit (F24.4[sign bit + 23-bit mantissa + 4-bit exponent])
Offset RAM: 64 x 13-bit
Internal Delay RAM: 168kbits
( 6144 x 28 bit / 2048 x 28 bit + 8192 x 14 bit / 3072 x 28 bit + 6144 x 14 bit
/ 4096 x 28 bit + 4096 x 14 bit) 4 pattern setting
28bit = F24.4 [24 bit sign & mantissa: 4 bit exponent]
14bit = F10.4 [10 bit sign & mantissa: 4 bit exponent]
Sampling frequency: 7.35kHz ~ 96kHz
Serial interface port for microcontroller or I2C BUS control
Master Clock: 2560fs (generated by PLL from 32fs ,64fs, 256fs and 384fs)
Master/Slave operation
Serial signal input port (10ch): MSB justified 24-bit / LSB justified 16/20/24-bit and I2S
Serial signal output port(12ch): MSB justified 24-bit / LSB justified 24,16-bit and I2S
(SDOUT1,SDOUT2 and SDOUT3)
[ADC]
4 channels (2 stereo pairs)
24-bit 64X over-sampling delta-sigma (fs = 7.35kHz ~ 96kHz)
DR, S/N: 96dBA (fs = 48kHz, fully-differential input)
S/(N+D): 92dB (fs = 48kHz)
Digital HPF (fc = 1Hz)
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[AK7780]
[ADC]
Mono single channel
24-bit 64X over-sampling delta sigma (fs = 7.35kHz ~ 96kHz)
DR, S/N: 95dBA ( fs = 48kHz)
Includes digital attenuator
[SRC]
Stereo pair
Input frequency 7.35kHz ~ 96kHz → Output frequency 44.1kHz ~ 96kHz
[Other]
Power supply: +3.3V ±0.3V, +1.7V~+2.0V(typ +1.8V)
Operating temperature range: -40°C~85°C
Package: 100pin LQFP(0.5mm pitch)
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[AK7780]
BLOCK DIAGRAM
4
2
2 2 2 2 2 2
pull down
Hi-z
I/O
ctrl reg sw
AVDD
3
3
ADCM
VREFH
VREF
ADC1
ADC2
VCOM
VREFL
AVSS
VOL
MUX
SELOA1[1:0]
0
OUTA1E_
1
2
3
SDOUTA1
N
SELOA2[1:0]
0
1
2
3
SEL_SDO6
SDOUT6
SDIN6
SDOUT6
SDOUT5
SWIRP
T
OUT6E_
N
SELI5
SELI4
SDOUT5
SDOUT4
SWG1
OUT5E_
N
SDOUT4
SDOUT3
SDOUT2
SDIN5
SDIN4
SDIN5
SDIN4
OUT4E_
N
SWG0
OUT3E_
N
SDOUT3
SDOUT2
SEL_SDO2
OUT2E_
N
SELI3
SDIN3
SDIN2
SDIN1
SDOUT1
SDOUT1
SDIN3
SDIN2
OUT1E_
N
SEL_SDO1
IRPT
GPO1
GPO0
I2CSEL
RQ_N/CAD1
MICIF
SELI1
SCLK/SCL
SI/CAD0
SO
SDIN1
SRCI
SDA
RDY
DSP
SRCOUT
R_SRCSMUTE
R_SRCRST_N
P_SRCSMUTE
JX2
JX1
JX2
JX1
P_SRCRST
SRC_LRCK
SRC_BICK
JX0
JX0
SRC
WDT
WDTE_N
CRC
STO
CRC_E
SRCSET[1]
SRCSET[0]
SRC_LFLT
TESTO
LOCK_E
UNLOCK
LRCLK_O
BITCLK_O
CONTROLLER
TESTI2
TESTI1
CKM[2:0]
3
XTI
CKRST_N
P_CKRST
XTO
R_CKRST_N
(Master="H",Slave="L")
SMODE
CLKO2
CLKO2E_N
CLKO1E_N
DSPRST_N
CLKO1
P_DSPRST
P_ADRST
R_DSPRST_N
R_ADRST_N
S_RESET_N
BVSS
2
7
3
8
DVDD18
DVSS
ADRST_N
INIT_RESET
3
DVDD
6
LRCLK_I BITCLK_I LFLT
Figure 1. Whole Block Diagram
* Figure 1 shows a simplified diagram of the AK7780, which isn’t the perfect same as the actual circuit diagram.
Each \ describes the relationship of reset control and target reset blocks.
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[AK7780]
DP1
DLP0,DLP1
CP0,CP1
DP0
DLRAM
OFRAM
1024w×28bit
1024w×28bit
CRAM
6kw×28bit (Default)
64w×13bit
DRAM
2048w×16bit
CBUS(16bit)
DBUS(28bit)
Micon I/F
MPX16
MPX24
Control
Serial I/F
PRAM
DEC
X
Y
2048w × 36bit
Multiply
PC
16bit×24bit→40bit
Stack : 5level(max)
TMP 8×28bit
28bit
40bit
PTMP(LIFO) 6×28bit
MUL
DBUS
SDIN6
2×24bit
SHIFT
SDIN5
SDIN4
SDIN3
SDIN2
SDIN1
44bit
2×24/20/16bit
44bit
2×24/20/16bit
2×24/20/16bit
2×24/20/16bit
A
B
ALU
2×24/20/16bit
44bit
Overflow Margin: 4bit
2×24bit
SDOUT6
SDOUT5
SDOUT4
44bit
2×24/16bit
2×24/16bit
2×24/16bit
2×24bit
DR0~3
44bit
SDOUT3
SDOUT2
Over Flow Data
Generator
2×24bit
SDOUT1
Division 24÷24→24
Peak Detector
Figure 2. DSP Block Diagram
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[AK7780]
■ Ordering Guide
AK7780VQ
AKD7780
-40 ∼ +85°C
100pin LQFP(0.5mm pitch)
Evaluation Board for AK7780
■ Pin layout
76
77
78
79
80
81
82
83
84
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TESTO
AINM
SO
DVDD
AINR4
AINL4
DVSS
DVDD18
SCLK/SCL
SI / CAD0
AINR3
AINL3
AINR2
RQ / CAD1
AINL2
AVDD
P_DSPRST
P_ADRST
P_CKRST
INIT_RESET
DVSS
85
VREFH
100 pin LQFP
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VCOM
VREFL
AVSS
AINR-
DVDD18
(TOP VIEW)
LRCLK_I
BITCLK_I
AINR+
SDIN5
SDIN4
AINL-
AINL+
AINR5
AINL5
SDIN3
SDIN2
AINR6
DVDD18
DVSS
AINL6
AINR7
AINL7
AINR8
AINL8
DVDD
CLKO1
SDOUT5
SDOUT4
pin
Input
Output
I/O
Power
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[AK7780]
PIN FUNCTION
No
1
Pin Name I/O
Function
Classification
Analog Output
Filter connection pin for AK7780 core PLL
LFLT
O
When using the PLL function, connect with R (1.5kΩ) and C (47nF) in series
and connected to analog ground (AVSS) see. 9. System design (1)
Analog ground 0V
2
3
AVSS
-
-
Analog Power
Supply
Power supply pin for analog section 3.3V (typ)
AVDD
TEST pin (Internal pull-down)
4
5
TESTI1
I2CSEL
I
I
TEST
* Connect to DVSS
I2CBUS select pin
* I2CSEL= “L”: Normal serial interface
* I2CSEL= “H”: I2CBus selected mode. SCL and SDA are active.
I2CSEL must be set to “L (DVSS)” or ”H (DVDD)”.
SRC select pin 1
I2C Select
SRC
6
7
SRCSET [1]
SRCSET [0]
I
I
SRC select pin 0
Silicon substrate potential 0V
Analog Power
Supply
8
BVSS
-
Connect to AVSS.
Power supply pin for digital section 3.3V (typ)
Ground pin for digital section 0V
9
DVDD
DVSS
-
-
Digital Power
Supply
10
Master clock input pin
11
XTI
I
Connect a crystal between this pin and the XTO pin, or input an external
CMOS clock signal to the XTI pin.
System Clock
Crystal oscillator output pin
12
13
XTO
O
When using a crystal, connect it between XTI and XTO.
When using an external clock, keep this pin open.
DVSS
- Ground pin for digital section 0V
Digital Power
Supply
14
15
16
17
18
19
20
DVDD18
CKM [1]
CKM [0]
CKM [2]
DVDD18
DVSS
- Power supply pin for digital section 1.8V (typ)
I
I
I
-
Clock mode select pin 1
Mode select
Clock mode select pin 0
Clock mode select pin 2
Power supply pin for digital section 1.8V (typ)
Digital Power
Supply
- Ground pin for digital section 0V
DVDD
-
Power supply pin for digital section 3.3V (typ)
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MS0581-E-00-PB
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[AK7780]
No Pin Name I/O
Function
Classification
System Clock
LR channel select clock output pin
21 LRCLK_O
22 BITCLK_O
O
O
Master mode: Outputs fs clock.
Slave mode: Outputs LRCLK_I clock.
Serial bit clock output pin
Master mode: Outputs 64fs clock.
Slave mode: Outputs BITCLK_I clock
DSP Serial data output pin
23
24
25
26
SDOUT1
SDOUT2
SDOUT3
SDOUT4
O
O
O
O
* Compatible with MSB justified 24 bits / I2S.
DSP Serial data output pin
* Compatible with MSB justified 24 bits / I2S.
Digital section
Serial output data
DSP Serial data output pin
* Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S.
DSP Serial data output pin
* Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S.
DSP Serial data output pin
27
28
SDOUT5
CLKO1
O
O
* Compatible with MSB justified 24 bits / LSB justified 24 and 16 bits/ I2S.
Clock output pin 1
Clock output
Select the output frequency through a control register.
29
30
31
DVDD
DVSS
- Power supply pin for digital section 3.3V(typ)
- Ground pin for digital section 0.0V
Digital Power
Supply
DVDD18
- Power supply pin for digital section 1.8V(typ)
DSP serial data input pin
32
33
34
35
SDIN2
SDIN3
SDIN4
SDIN5
I
I
I
I
Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S.
* If not used, connect to DVSS
DSP serial data input pin
Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S.
* If not used, connect to DVSS
Digital section
Serial input data
DSP serial data input pin
Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S.
* If not used, connect to DVSS
DSP serial data input pin
Compatible with MSB justified 24 bits / LSB justified 24, 20 and 16 bits / I2S.
* If not used, connect to DVSS
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MS0581-E-00-PB
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[AK7780]
No
36
Pin Name
I/O
I
Function
Classification
System Clock
BITCLK_I
Serial bit clock input pin
37
38
39
LRCLK_I
DVDD18
DVSS
I LR channel select clock input pin.
- Power supply pin for digital section 1.8V(typ)
Digital power
supply
- Ground pin for digital section 0.0V
Reset pin ( for initialization)
40 INIT_RESET
I
I
Use for initialization. When changing CKM[2:0], XTI or BITCLK_I input
frequency, this reset pin must be used.
Clock reset pin
When changing CKM[2:0] and XTI or BITCLK_I input frequency without
using INIT_RESET, pin control is necessary. The control register
R_CKRST_N can also rest the clock.
41
42
P_CKRST
P_ADRST
P_DSPRST
Reset
ADC Reset pin
The control register R_ADRST_N can also reset the ADC.
P_ADRST = “L” and P_DSPRST = “L” state causes a system reset
(S_RESET).
I
DSP Reset pin
The control register R_DSPRST_N can also rest the DSP.
P_ADRST = “L” and P_DSPRST = “L” state causes a system reset
(S_RESET).
43
44
I
I
I2CSEL= “L”
Microcomputer
Interface.
RQ
Microcomputer interface write request pin.
After initial reset, if the microcomputer interface is not used, leave RQ = “H”
CAD1
I I2CSEL=”H” I2C Bus address setting pin 1
I2C
Microcomputer interface serial data input and serial data output control
pin.
When SI is not used, leave SI = “L”.
Microcomputer
Interface.
45
46
SI
I
CAD0
SCLK
I I2CSEL= “H” I2C Bus address pin 0
I2C
I2CSEL= “L”
Microcomputer interface serial data clock pin.
Microcomputer
Interface.
I
When SCLK is not used, leave SCLK= “H”
SCL
DVDD18
DVSS
I I2CSEL= “H” I2C bus data clock pin
I2C
47
48
49
- Power supply pin for digital section 1.8V(typ)
Digital power
supply
-
Ground pin for digital section 0.0V
DVDD
- Power supply pin for digital section 3.3V(typ)
Microcomputer
Interface.
Serial data output pin for microcomputer interfaces.
50
SO
O
When RQ = “H”, SO = Hi-Z
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[AK7780]
No
51
Pin Name
RDY
I/O
O
Function
Classification
Microcomputer
Interface.
Data write ready output pin for microcomputer interface.
Status output pin
Normal state output “H”.
When WDT, CRC error or SRC UNLOCK occurs, then output “L”.
See 3.(1) Whole block diagram.
52
STO
O
Status
DSP or ADC Serial data output pin
53
54
55
SDOUTA1
SDOUT6
CLKO2
O
O
O
* Compatible with MSB justified 24 bits / I2S.
Digital section
Serial output data
DSP or ADC Serial data output pin
* Compatible with MSB justified 24 bits / I2S.
Clock output pin 2
Clock output
Select the output frequency through a control register.
56
57
58
DVDD
DVSS
-
-
-
Power supply pin for digital section 3.3V(typ)
Ground pin for digital section 0.0V
Digital power
supply
DVDD18
Power supply pin for digital section 1.8V(typ)
External condition jump pin
* When not used, connect to DVSS
External condition jump pin
* When not used, connect to DVSS
External condition jump pin
* When not used, connect to DVSS
DSP/SRC Serial input pin
59
60
61
62
JX2
JX1
I
I
I
I
Conditional input
JX0
Digital section
Serial input data
SDIN1
Input pin for SRC. When not used, connect to DVSS.
63
64
SRC_BICK
SRC_LRCK
I SRC Serial bit clock input pin.
SRC
I
I
SRC LR channel select clock input pin.
I2CSEL= “L”
SDA Outputs “L” level.
I2CSEL= “H”
65
SDA
I2C
I/O
I
I2C bus interface data pin
SRC Reset pin
66
P_SRCRST
RESET
The control register R_SRCRST_N can also rest the SRC.
67
68
69
DVDD18
DVSS
-
-
Power supply pin for digital section 1.8V(typ)
Ground pin for digital section 0.0V
Digital power
supply
DVDD
- Power supply pin for digital section 3.3V(typ)
Analog power
supply
Silicon substrate potential 0V
Connect to AVSS.
SRC Soft mute pin
70
71
72
BVSS
-
P_SRC
SMUTE
I
I
The control register R_SRCSMUTE can also execute a soft mute on the SRC
SRC.
TEST pin ( Internal pull-down )
TESTI2
TEST
* Connect to DVSS.
73
74
AVDD
AVSS
- Power supply pin for analog section 3.3V (typ)
Analog power
supply
- Analog ground 0V
RC Filter connection pin for SRC.
75
SRC_LFLT
O
Analog output
See p.86 10-2-5-2: SRC PLL loop filter setting.
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[AK7780]
No
76
Pin Name
TESTO
I/O
O
Function
Classification
TEST OUT pin
Hi-Z Output pin. Leave it open.
TEST
77
78
79
80
81
82
83
AINM
AINR4
AINL4
AINR3
AINL3
AINR2
AINL2
I ADCM single ended analog input
I ADC1 or ADC2 Rch single ended analog input 4
I ADC1 or ADC2 Lch single ended analog input 4
I
Analog input
ADC1 or ADC2 Rch single ended analog input 3
I
I
I
ADC1 or ADC2 Lch single ended analog input 3
ADC1 or ADC2 Rch single ended analog input 2
ADC1 or ADC2 Lch single ended analog input 2
Analog Power
Supply
84
AVDD
-
Power supply pin for analog section 3.3V (typ)
Analog reference voltage input pin.
Connect to AVDD, and connect 0.1μF and 10μF bypass capacitors between
this pin and AVSS.
85
VREFH
I
Analog input
Common voltage
86
VCOM
O
Analog output
Analog input
Connect to 0.1μF and 10μF capacitors between this pin and AVSS.
Do not connect to external circuitry.
Analog reference voltage input pin for low-level.
Connect to AVSS.
87
88
VREFL
AVSS
I
-
Analog Power
Supply
Analog ground 0V
I
I
I
I
89
90
91
92
93
94
95
96
97
98
99
100
AINR–
AINR+
AINL–
AINL+
AINR5
AINL5
AINR6
AINL6
AINR7
AINL7
AINR8
AINL8
ADC1 or ADC2 Rch inverted input pin
ADC1 or ADC2 Rch non- inverted input pin
ADC1 or ADC2 Lch inverted input pin
ADC1 or ADC2 Lch non- inverted input pin
I ADC1 or ADC2 Rch single ended analog input 5
I ADC1 or ADC2 Lch single ended analog input 5
Analog input
I
I
I
I
I
I
ADC1 or ADC2 Rch single ended analog input 6
ADC1 or ADC2 Lch single ended analog input 6
ADC1 or ADC2 Rch single ended analog input 7
ADC1 or ADC2 Lch single ended analog input 7
ADC1 or ADC2 Rch single ended analog input 8
ADC1 or ADC2 Lch single ended analog input 8
Note 1. Digital input pins must not be allowed to float
Note 2. If analog input pins (AINR–, AINR+, AINL–, AINL+, AINL2-8, AINR2-8, AINM) are not used, leave them
open.
Note 3. I2CSEL should be set to “L” (DVSS) or “H” (DVDD).
Relationship with I2CSEL and SDA.
I2CSEL
L
INIT_RESET
L
SDA
L
Normal
Microcontroller
Interface
L
H
H
H
L
H
L
I2C bus compatible
“Hi-Z” → pull-up
function
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MS0581-E-00-PB
2007/09
[AK7780]
ABSOLUTE MAXIMUM RATINGS
(AVSS = BVSS = DVSS = 0V: All indicated voltages are with respect to ground.)
Item
Power supply voltage
Symbol
min
max
Unit
Analog(AVDD)
Digital(DVDD)
Digital(DVDD18)
|AVSS(BVSS) – DVSS|
VA
VD
VD18
ΔGND
IIN
-0.3
-0.3
-0.3
4.3
4.3
2.5
0.3
V
V
V
V
mA
(Note 4)
Input current (except for power supply pin )
-
±10
Analog input voltage
AINL+, AINL–, AINR+, AINR–,
AINL2-8, AINR2-8, AINM
VREFH,VREFL
VINA
-0.3
VA+0.3
V
Digital input voltage
Operating ambient temperature
Storage temperature
VIND
Ta
Tstg
-0.3
-40
-65
VD+0.3
85
150
V
°C
°C
Note 4. AVSS (BVSS) should be at the same level as DVSS.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these critical conditions.
RECOMMENDED OPERATING CONDITIONS
(AVSS = BVSS = DVSS = 0V: All indicated voltages are with respect to ground.)
Items
Power supply voltage
AVDD
Symbol
min
typ
max
Unit
VA
VD
VD18
3.0
3.0
1.7
3.3
3.3
1.8
3.6
3.6
2.0
V
V
V
DVDD
DVDD18
Reference voltage (VREF)
VREFH (Note 5)
VREFL (Note 6)
VRH
VRL
VA
0.0
V
V
Note 5. VREFH normally connects to AVDD.
Note 6. VREFL normally connects to AVSS
Note: The analog input voltage and output voltage are proportional to the VREFH-VREFL voltages.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
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[AK7780]
ELECTRIC CHARACTERISTICS
(1) Analog Characteristics
1) ADC Characteristics
(Unless otherwise specified, Ta = 25°C; AVDD = DVDD = 3.3V, DVDD18=1.8V; VREFH = AVDD, VREFL = AVSS;
BITCLK = 64 fs; signal frequency = 1kHz; Measurement bandwidth = 20Hz to 20kHz @ 48kHz, 20Hz ~ 40kHz @
96kHz; ADC specified with differential inputs (ADC1, ADC2); CKM Mode 1(CKM[2:0]= “000”), SRC RESET)
Parameter
min
typ
max
Unit
Resolution
Dynamic characteristics
S/(N+D) fs = 48kHz (-1dBFS)
Fs = 96kHz (-1dBFS)
Dynamic range fs = 48kHz (A filter) (Note 7, Note 8)
fs = 96kHz
24
Bits
Stereo
ADC
(Note 7)
82
88
88
90
92
90
96
93
96
dB
dB
dB
dB
dB
dB
dB
ADC1
ADC2
S/N
fs = 48kHz (A filter)
fs = 96kHz
(Note 7)
93
115
Inter-channel isolation (f=1kHz)
DC accuracy
(Note 9)
Channel gain mismatch
Analog input
0.1
0.3
dB
Input voltage ( Differential input )
Input voltage ( Single-ended input )
Input impedance
(Note 10)
(Note 11)
(Note 12)
±1.85
1.85
22
±2.00
2.00
33
±2.15
2.15
Vp-p
Vp-p
kΩ
Resolution
Dynamic characteristics
24
Bits
Monaural
ADC part
S/(N+D
fs = 48kHz (-1dBFS)
fs = 96kHz ( -1dBFS)
78
87
87
88
87
95
92
95
92
dB
dB
dB
dB
dB
dB
ADCM
Dynamic range fs = 48kHz (A filter)
fs = 96kHz
S/N
(Note 8)
fs = 48kHz (A filter)
fs = 96kHz
Analog input
Input voltage
Input impedance
(Note 13)
(Note 14)
1.85
22
2.00
33
2.15
Vp-p
kΩ
Note 7. This value is not guaranteed for single-ended inputs.
Note 8. Indicates S/(N+D) when -60 dBFS signal is applied.
Note 9. Indicates isolation between L and R when -1dBFS signal is applied.
Note 10. Target input pins are AINL+, AINL-, AINR+ and AINR-.
Differential full scale is (±FS=(VREFH-VREFL)x(2.0/3.3))
Note 11. Target input pins are AINL2~L8, AINR2~R8.,
Single-ended full scale is (FS=(VREFH-VREFL) x (2.0/3.3))
Note 12. Target input pins are AINL+, AINL–, AINR+, AINR–, AINL2-L8, AINR2-R8.
Note 13. Target input pin is AINM, The full scale of this pin is (FS=(VREFH-VREFL) x (2.0/3.3))
Note 14. Target input pin is AINM.
- 12 -
MS0581-E-00-PB
2007/09
[AK7780]
2) SRC Characteristics
(Ta=25°C; AVDD = 3.3V; DVDD=3.3V; DVDD18=1.8V; data = 24-bits; measurement bandwidth = 20Hz∼ FSO/2;
unless otherwise specified.)
Parameter
Resolution
Symbol
min
typ
max
24
Units
Bits
Input Sample Rate
Output Sample Rate
FSI
FSO
7.35
44.1
96
96
kHz
kHz
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=48kHz/8kHz
-113
-112
-113
-113
-112
dB
dB
dB
dB
dB
-103
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=44.1kHz/48kHz
114
114
114
114
114
dB
dB
dB
dB
dB
FSO/FSI=44.1kHz/96kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=48kHz/96kHz
FSO/FSI=48kHz/8kHz
110
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted
FSO/FSI=44.1kHz/48kHz
Ratio between Input and Output Sample Rate
116
dB
-
FSO/FSI
0.45
6
- 13 -
MS0581-E-00-PB
2007/09
[AK7780]
(2) DC Characteristics
(Ta = -40°C ~ 85°C; AVDD = DVDD = 3.0~3.6V; DVDD18 = 1.7~2.0V)
Parameter
High level input voltage
Low level input voltage
SCL,SDA High level input voltage
SCL,SDA Low level input voltage
High level output voltage Iout=-100μA
Low level output voltage Iout=100μA (Note 16)
SDA Low level output voltage Iout=3mA
Symbol
VIH
VIL
VIH
VIL
VOH
VOL
VOL
Iin
min
80%DVDD
typ
max
Unit
V
V
V
V
V
V
V
(Note 15)
(Note 15)
20%DVDD
30%DVDD
70%DVDD
DVDD-0.5
0.5
0.4
±10
Input leak current
Input leak current (pull-down)
Input leak current (XTI pin )
(Note 17)
(Note 18)
μA
μA
μA
Iid
Iix
22
26
Note 15. SCL (I2CSEL=1) and SDA pins are not included. (SCLK pin is included when I2CSEL=0)
Note 16. SDA pin is not included.
Note 17. The pull-down pins and XTI pin are not included.
Note 18. The pull-down pins (Typ150kΩ) are: TESTI1, TESTI2
(3) Current Consumption
(Ta=25°C; AVDD=DVDD=3.0~3.6V(typ=3.3V,max=3.6V); DVDD18=1.7~2.0V(typ=1.8V, max=2.0V))
Power supply
Parameter
Power supply current
min
typ
max
Unit
(Note 19)
1)
a) AVDD
b) DVDD
c) DVDD18
52
8
110
1
70
15
165
mA
mA
mA
mA
2) INIT_RESET = “L” (reference)
(Note 20)
Note 19. Varies slightly according to the system frequency and contents of the DSP program.
Note 20. This is a reference value when using a crystal oscillator.
Since most of the supply current at the initial reset state is in the oscillator section, the value may vary slightly
according to the crystal type and the external circuit. This is a “reference value” only.
- 14 -
MS0581-E-00-PB
2007/09
[AK7780]
(4) Digital Filter Characteristics
1) ADC Section: ADC1, ADC2
(Ta=-40°C~85°C; AVDD = DVDD =3.0V~3.6V; DVDD18=1.7V~2.0V; fs=48kHz; Note 21)
Parameter
Symbol
PB
min
0
typ
max
21.5
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
Pass band (±0.005dB)
(Note 22)
21.768
24.00
(-0.02dB)
(-6.0dB)
Stop band
Pass band ripple
SB
PR
SA
ΔGD
GD
26.5
80
(Note 22)
±0.005
0
Stop band attenuation
Group delay distortion
Group delay
(Note 23, Note 24)
(Ts=1/fs)
29
Digital filter + SFC
Amplitude characteristics (20Hz~20.0kHz)
±0.01
dB
Note 21. Each parameter is related to the sampling frequency (fs). HPF response is not included.
Note 22. The pass band is from DC to 21.5kHz at fs = 48kHz.
Note 23. The stop band is from 26.5kHz to 3.0455MHz at fs = 48kHz.
Note 24. When fs = 48kHz, the analog modulator samples the analog input at 3.072MHz. The input signal is not
attenuated by the digital filter in multiple bands (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3...) of the sampling
frequency.
2) ADC Section ADCM
(Ta=-40°C~85°C; AVDD = DVDD =3.0V~3.6V; DVDD18=1.7V~2.0V; fs = 48 kHz; Note 25)
Parameter
Pass band (±0.005dB)
Symbol
min
0
typ
max
21.5
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
PB
(Note 26)
21.768
24.00
(-0.02dB)
(-6.0dB)
Stop band
Pass band ripple
SB
PR
SA
ΔGD
GD
26.5
80
(Note 26)
±0.005
0
Stop band attenuation
Group delay distortion
Group delay
(Note 27, Note 28)
(Ts=1/fs)
(Note 29)
29
Digital filter + SFC
Amplitude characteristics (20Hz~20.0kHz)
±0.1
dB
Note 25. Each parameter is related to the sampling frequency (fs). HPF response is not included.
Note 26. The pass band is from DC to 21.5kHz at fs = 48kHz.
Note 27. The stop band is from 26.5kHz to 3.0455MHz at fs = 48kHz.
Note 28. When fs = 48kHz, the analog modulator samples the analog input at 3.072MHz. The input signal is not
attenuated by the digital filter in the multiple bands (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3...) of the sampling
frequency.
Note 29. VOL+ MUX path adds one additional Ts.
- 15 -
MS0581-E-00-PB
2007/09
[AK7780]
3) SRC
(Ta=-40°C~85°C; AVDD=DVDD=3.0~3.6V; DVDD18 = 1.7~2.0V)
Parameter
Pass band -0.01dB
Range
Symbol
PB
min
0
0
0
0
0
typ
max
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
dB
0.4583FSI
0.4167FSI
0.2182FSI
0.2177FSI
0.1948FSI
0.980 ≤ FSO/FSI ≤ 6.000
0.900 ≤ FSO/FSI < 0.990
0.533 ≤ FSO/FSI < 0.909
0.490 ≤ FSO/FSI < 0.539
0.450 ≤ FSO/FSI < 0.495
0.980 ≤ FSO/FSI ≤ 6.000
0.900 ≤ FSO/FSI < 0.990
0.533 ≤ FSO/FSI < 0.909
0.490 ≤ FSO/FSI < 0.539
0.450 ≤ FSO/FSI < 0.495
PB
PB
PB
PB
SB
SB
SB
SB
Stop band
0.5417FSI
0.5021FSI
0.2974FSI
0.2812FSI
0.2604FSI
SB
PR
SA
Pass band ripple
Stop band attenuation
Group delay (Ts=1/fs)
(Note 30)
±0.01
95.2
dB
GD
56
Ts
Note 30. Measured from the rising edge of SRC_LRCK on the input to the rising edge of LRCLK_O on the output,
with there is no phase difference between input and output.
- 16 -
MS0581-E-00-PB
2007/09
[AK7780]
(5) Switching Characteristics
[ #h means hexadecimal code. (#=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F)]
1) System Clock
(Ta = -40~85°C; AVDD=DVDD=3.0V~3.6V; DVDD18 = 1.7V~2.0V)
Parameter
Symbol
min
typ
max
Unit
XTI
CKM[2:0] 0h,1h,2h,3h
a) with a crystal oscillator:
CKM[2:0]=0h,2h
fXTI
fXTI
-
-
11.2896
12.288
16.9344
18.432
-
-
MHz
MHz
CKM[2:0]=1h,3h
b) with an external clock
Duty cycle
40
50
60
%
CKM[2:0]=0h,2h
fXTI
fXTI
11.0
12.4
MHz
CKM[2:0]=1h,3h
16.5
18.6
MHz
Clock rise time
Clock fall time
tCR
tCF
6
6
ns
ns
fs
7.35
48
96
kHz
LRCLK_I frequency
(Note 31)
Clock rise time
Clock fall time
tLR
tLF
6
6
ns
ns
BITCLK_I frequency
High level width
Low level width
Clock rise time
Clock fall time
a) CKM[2:0]=2h,3h
Duty cycle
CKM[2:0]=2h,3h
b) CKM[2:0]=4h,5h
tBCLKH
tBCLKL
tBR
tBF
fBCLK
64
64
ns
ns
ns
ns
fs
%
MHz
fs
6
6
-
60
6.2
-
-
40
0.23
-
64
50
64
50
(Note 32)
fBCLK
Duty cycle
40
2.75
5.5
60
3.1
6.2
%
CKM[2:0]=4h
CKM[2:0]=5h
fBCLK
fBCLK
MHz
MHz
Note 31. LRCLK and sampling rate (fs) should match.
Note 32. When BITCLK_I uses as a resource of master clock, it should be 64 clocks correctly divided within 1fs.
- 17 -
MS0581-E-00-PB
2007/09
[AK7780]
(Ta = -40°C ~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V)
Parameter
SRC_LRCK frequency
Symbol
min
7.35
typ
48
max
96
Unit
kHz
fs
(Note 33)
Clock rise time
Clock fall time
tLR
tLF
6
6
ns
ns
SRC_BICK frequency
High level width
Low level width
Clock rise time
Clock fall time
tBCLKH
tBCLKL
tBR
tBF
fBCLK
60
60
ns
ns
ns
ns
fs
6
6
128
(Note 34)
32
40
Duty factor
50
60
%
0.23
6.2
MHz
Note 33. SRC_LRCK and sampling rate (fs) should match.
Note 34. 128fs is up to fs = 48kHz.
2) Reset
(Ta=-40°C ~85°C; AVDD=DVDD=3.0~3.6V; DVDD18 = 1.7~2.0V)
Parameter
Symbol
min
typ
max
Unit
tRST
600
ns
INIT_RESET
P_CKRST
(Note 35)
tRST
tRST
tRST
tRST
600
600
600
600
ns
ns
ns
ns
P_ADRST
P_DSPRST
P_SRCRST
Note 35. “L” is acceptable when power is turned on, but a stable master clock must present before transitioning to “H”.
- 18 -
MS0581-E-00-PB
2007/09
[AK7780]
3) Audio interface
3-1) SDIN1~SDIN5,SDOUT1~SDOUT6,SDOUTA1 (Up to fs = 96kHz)
AKM Normal and I2S Compatible Format
(Ta = -40°C~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V, CL=20pF)
Parameter
Symbol
min
typ
max Unit
Slave mode CKM[2:0]=2h, 3h, 4h, 5h
Delay time from BITCLK_I “↑” to LRCLK_I
Delay time from LRCLK_ I to BITCLK_I “↑” (Note 36)
tBLRD
tLRBD
20
20
ns
ns
(Note 36)
Delay time from LRCLK_I, LRCLK_O to serial data output tLRD
40
40
ns
ns
Delay time from BITCLK_I, BITCLK_O to serial data
output
tBSOD
Serial data input latch setup time
Serial data input latch hold time
tBSIDS
tBSIDH
40
40
ns
ns
Master mode CKM[2:0]=0h, 1h
BITCLK_O frequency
BITCLK_O duty cycle
Delay time from BITCLK_O “↓” to LRCLK_O
Delay time from LRCLK_O to serial data output
Delay time from BITCLK_O to serial data output
Serial data input latch setup time
fBCLK
64
50
fs
%
ns
ns
ns
ns
ns
tBLRD
tLRD
tBSOD
tBSIDS
tBSIDH
-20
40
40
40
40
40
Serial data input latch hold time
Note 36. LRCLK_I edge and BITCLK_I "↑“edge cannot be synchronous.
3-2) SDIN1(SRCI Input) (Up to fs = 96kHz)
(Ta=-40°C~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V)
Parameter
Symbol min
typ
max
Unit
Slave mode
tBLRD
tLRBD
tBSIDS
tBSID
H
20
20
40
40
ns
ns
ns
ns
Delay time from SRC_BICK “↑” to SRC_LRCK
Delay time from SRC_LRCK to SRC_BICK “↑”
Serial data input latch setup time
(Note 37)
(Note 37)
Serial data input latch hold time
Note 37. SRC_BICK edge and SRC_LRCK edge cannot be synchronous.
- 19 -
MS0581-E-00-PB
2007/09
[AK7780]
3) Microcontroller Interface
(Ta = -40~85°C; AVDD=DVDD=3.0V~3.6V, DVDD18 = 1.7~2.0V, CL = 20pF)
Parameter
Symbol
min
typ
max
Unit
Microcomputer interface signal
RQ Fall time
RQ Rise time
tWRF
tWRR
30
30
ns
ns
SCLK fall time
SCLK rise time
tSF
tSR
30
30
ns
ns
SCLK frequency
SCLK low level width
SCLK High level width
fSCLK
tSCLKL
tSCLKH
2.1
MHz
ns
ns
200
200
Microcomputer to AK7780
Time from P_DSPRST , P_ADRST “↓” to RQ “↓”
tREW
tWRE
tWRQH
tWSC
500
500
500
500
800
ns
ns
ns
ns
ns
Time from RQ “↑” to P_DSPRST , P_ADRST “↑”
RQ high level width
Time from RQ “↓” to SCLK“↓”
Time from SCLK“↑” to RQ “↑”
tSCW
SI latch setup time
SI latch hold time
tSIS
tSIH
200
200
ns
ns
AK7780 to Microcomputer
tSOS
tSOH
300
ns
ns
Delay time from SCLK“↓” to SO output
Hold time from SCLK“↑” to SO output
200
(Note 38)
Time from RQ “↓” to SO Hi-Z (Iout=±360μA) release
tRQHR
tRQHS
600
600
ns
ns
RQ “↑” to SO Hi-Z set (Iout=±360μA)
Note 38. Except last 1bit of the command code.
- 20 -
MS0581-E-00-PB
2007/09
[AK7780]
4) I2C BUS Interface
(Ta = -40°C~85°C; AVDD=DVDD=3.0~3.6V, DVDD18 = 1.7~2.0V)
Parameter
Symbol
Min
Typ
Max Unit
I2C Timing
SCL clock frequency
fSCL
tBUF
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock pulse)
Clock Low Time
1.3
0.6
1.3
0.6
0.6
0
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
0.9
0.1
0.3
0.3
tF
tSU:STO
tSP
0.6
0
Pulse Width of Spike Noise Suppressed By Input Filter
50
Capacitive load on bus
Cb
400
pF
Note 39. I2C is a registered trademark of Philips Semiconductors.
- 21 -
MS0581-E-00-PB
2007/09
[AK7780]
(6) Timing Diagram
1) System clock
1/fXTI
1/fXTI
tXTI=1/fXTI
VIH
VIL
XTI
tCF
tCR
ts=1/fs
1/fs
VIH
LRCLK_I
SRC_LRCK
VIL
tLR
tLF
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
VIL
BITCLK_I
SRC_BICK
tBR
tBF
tBCLKH
tBCLKL
2) RESET
NIT_RESET
tRST
P_CKRST
P_ADRST
P_DSPRST
P_SRCRST
VIL
- 22 -
MS0581-E-00-PB
2007/09
[AK7780]
3) Audio Interface
c Normal and I2S compatible format
LRCLK I
50%DVDD
LRCLK_O
tMB tMBL
tBLRD
tLRD
tLRBD
BITCLK_I
50%DVDD
50%DVDD
50%DVDD
BITCLK_O
tBSOD
SDOUT *
SDIN *
tBSIDS
tBSIDH
SDIN * =SDIN1, SDIN2, SDIN3, SDIN4, SDIN5
SDOUT * =SDOUT1, SDOUT2, SDOUT3, SDOUT4, SDOUT5, SDOUT6, SDOUTA1
d SRC
SRC_LRCK
50%DVDD
50%DVDD
tLRBD
tBLRD
SRC_BICK
tBSIDS
tBSIDH
SRCI=SDIN1
50%DVDD
- 23 -
MS0581-E-00-PB
2007/09
[AK7780]
4) Microcontroller Interface
♦ Microcontroller interface
VIH
VIL
RQ
tWRF
tSF
tWRR
tSR
VIH
VIL
SCLK
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
♦ Microcontrollerr Æ AK7780
tWRE
tREW
P_DSPRST
VIL
P_ADRST
VIH
VIL
tWRQH
RQ
tWSC
VIH
VIL
SI
tSIS
tSIH
VIH
VIL
SCLK
tSCW
tWSC
tSCW
- 24 -
MS0581-E-00-PB
2007/09
[AK7780]
♦ AK7780 Æ Microcontroller
VIH
VIL
SCLK
VIH
VIL
SO
tSOH
tSOS
Note: Timing during the RUN state is identical, except that P_DSPRST and P_ADRST are “H”.
VIH
VIL
RQ
tRQHS
tRQHR
Hi-Z
SO
5) I2C Bus Interface
VIH
VIL
SDA
tLOW tR
tHIGH
tBUF
tF
tSP
VIH
VIL
SCL
tHD:STA
Stop Start
tHD:DAT
tSU:DAT tSU:STA
Start
tSU:STO
Stop
- 25 -
MS0581-E-00-PB
2007/09
[AK7780]
PACKAGE
• 100 pin LQFP
(Unit: mm )
1.70 Max.
0.20max
16.0±0.3
ꢀ 14.0
51
75
50
76
100
26
25
1
0.17±0.05
0.22±0.05
0.5
0.10
M
1.0
0°~10°
0.5±0.2
0.10
■ Material & Lead finish
Package: Epoxy
Lead-frame: Cu
Lead-finish: Solder (Pb free) plate
- 26 -
MS0581-E-00-PB
2007/09
[AK7780]
MARKING
AKM
AK7780VT
XXXXXXX
1) Pin #1 indication
2) Date Code: XXXXXXX(7digits)
3) Marking Code: AK7780VT
4) Asahi Kasei Logo
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
- 27 -
MS0581-E-00-PB
2007/09
[AK7780]
Thank you for your access to AKEMD product informations.
More detail product informations are available, please contact
our sales office or authorized distributors.
- 28 -
MS0581-E-00-PB
2007/09
相关型号：
AK7832AB
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AKM
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