AK8813VQ [AKM]
NTSC/PAL Digital Video Encoder; NTSC / PAL数字视频编码器
| 型号： | AK8813VQ |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | NTSC/PAL Digital Video Encoder |
| 文件： | 总51页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHIKASEI
[AK8813/14]
AK8813/14
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The AK8813/14 is low voltage, low power and small packaged Digital Video Encoder. It is suitable
for a STB or Digital TV. It converts ITU-R.BT601/656 standard 8- bit parallel data into analog
composite video signal, S-video in NTSC and PAL formats.
AK8813/14 supports Copy protection, Closed Captioning and Video Blanking ID(CGMS-A) and WSS.
These functions are controlled by high-speed I2C Bus interface.
FEATURES
• NTSC-M, PAL-B,D,G,H,I,M,N encoding.
• Simultaneous composite video signal and S-video signal outputs
• ITU-R BT.656 4:2:2 8-bit Parallel Input
- EAV Decoding
• Master/Slave Operation
- Digital Field Sync I/O
- Digital Vertical/Horizontal Sync I/O
• Y filtering
• C filtering
2 x over-sampling
4 x over-sampling
• Single 27MHz Clock (The polarity could be inverted by SYSINV pin)
• Triple 10-bit DACs
• I2C Bus Interface (400kHz)
• Closed Caption encoding (NTSC: line 21,284-SMPTE PAL: line 22,335-CCIR)
• Macrovision Copy Protection Rev. 7.1 * (only AK8814 )
• VBID, CGMS-A(EIAJ CPR-1024)
• WSS
• On-chip color bar generator
• Low power consumption
• 2.8V to 3.3V operation CMOS Monolithic
• 48pin LQFP Package / 57pin FBGA Package
(*Note) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other
intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized
by Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise
authorized in written by Macrovision. Reverse engineering or disassembly is prohibited.
Rev.00
- 1 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Block Diagram
SELA SCL SDA CLKNV CLK HSYNC VSYNC/PD /RESET
VREFOUT VREFIN
u-PI/F(I2C)
&
Register
VREF
Generator
IREF
Timing Generator
Macrovision
CGMS-A
WSS
Sync-Form
Generator
Luma Filter
Y
Delay
10-bit
DAC
Y
(x 2Interpolator)
10-bit
DAC
Data[7:0]
Composite
C
Chroma
LPF Filter
(x 2 Interpolator)
Sub-Carrier
Generator
10-bit
DAC
4:2:2 to 4:4:4
(x 2 Interpolator)
C
Delay
DVDD DVSS
AVDD AVSS
Rev.00
- 3 -
2004/Oct
ASAHIKASEI
[AK8813/14]
ORDERING GUIDE
AK8813VQ: LQFP48 Non-Macrovision (Pb Free)
AK8813VG: FBGA57 Non-Macrovision
AK8813VGP: FBGA57 Non-Macrovision (Pb Free)
AK8814VQ: LQFP48 Macrovision (Pb Free)
AK8814VG: FBGA57 Macrovision (Pb Free)
Rev.00
- 4 -
2004/Oct
ASAHIKASEI
48pin LQFP
[AK8813/14]
PIN LAYOUT
36 35 34 33 32 31 30 29 28 27 26 25
UD5
UD6
CVBS
AVSS
C
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
UD7
DVSS
DVDD
UD8
AVDD
Y
AVSS
/RESET
PD
DVDD
FID/VSYNC
HSYNC
DVSS
SDA
SCL
SELA
TEST
SYSINV
1
2
3
4
5
6
7
8
9 10 11 12
57pin FBGA
9
8
7
6
5
4
3
2
1
A
B
C
F
G
H
J
Bottom View
- 5 -
Rev.00
2004/Oct
ASAHIKASEI
[AK8813/14]
PIN/FUNCTION
48pin LQFP
No.
Pin Name
I/O
Description
1
UD9
I/O
Test pin. Open for normal operation
27MHz 8-Bit 4:2:2 multiplexed Y,Cb,Cr Data Input.
For Rec.656 format, AK8813/14 decodes EAV.
2-5,
D7 - D0
TEST
I
8-11
For non-Rec.656 format (without EAV), AK8813/14 operates in Master or
Slave mode.
12-13
I
I
Test pin. Ground for normal operation
The slave address is set with this pin.
“L”:40H “H”:42H
Serial interface clock
14
15
16
17
SELA
SCL
SDA
PD
I
I/O
I
Serial interface data
Power Down Pin. After returning from PD mode to normal operation,
RESET Sequence should be done to AK8813/14.
After this pin becomes “L”, AK8813/14 starts the internal initializing
sequence.
After initializing sequence, AK8813/14 is set NTSC mode, Rec.656
decoding mode. All DACs Off condition.
18
/RESET
I
After power up, AK8813/14 must be initialized with this pin.
(27MHz Clock is necessary for reset sequence.)
Y
C
O
Output of Luminance Signal.
20
22
Output of the Chrominance signal
O
O
COMPOSITE
VREFOUT
Output of Composite Video signal
24
27
Output of the Internal Vref. Terminate with 0.1uF or more capacitor.
O
I
VREFIN
IREF
Input of the Reference Voltage
28
29
The currents flow this pin adjusts the full-scale output current of the DAC.
O
Connect this pin to Analog ground via a 6.8kohm resistor ( better than +/-
1% accuracy ).
32-39
41
UD0-UD7
SYSCLK
UD8
I/O
I
Test pin. Open for normal operation
27MHz Clock Input. The polarity could be inverted by SYSINV.
Test pin. Open for normal operation
43
I/O
Either of FID or VSYNC selected by the register.
Rec.656 decode mode :Output
FID
Master mode : Output
45
46
I/O
I/O
/VSYNC
Slave mode : Input
FID shows that “L” is odd field and ”H” is even field.
Rec.656 decode mode : Output
Master mode : Output
Slave mode : Input
HSYNC
“L “ : data is latched with rising edge.
I
48
SYSINV
AVDD
“H” : data is latched with falling edge.
21,26
P
Analog Power Supply
Digital Power Supply
Analog Ground
6,31,
DVDD
AVSS
P
42,44
G
19,23,25
7,30,
DVSS
G
Digital Ground
40,47
Rev.00
- 6 -
2004/Oct
ASAHIKASEI
[AK8813/14]
57pin FBGA
No.
Pin Name
I/O
Description
A1
NC
-
Open for normal operation
B1
C1
C2
D1
AVSS
AVDD
VREFOUT
G
P
Analog Ground
Analog Power Supply
Output of the Internal Vref. Terminate with 0.1uF or more capacitor.
O
I
VREFIN
IREF
Input of the Reference Voltage
The currents flow this pin adjusts the full-scale output current of the DAC.
D2
O
Connect this pin to Analog ground via a 6.8kohm resistor ( better than +/-
1% accuracy ).
E1
E2
F2
F1
G2
G1
H1
J1
DVSS
DVDD
UD0
G
P
Digital Ground
Digital Power Supply
I/O
I/O
I/O
I/O
I/O
-
Test pin. Open for normal operation
Test pin. Open for normal operation
Test pin. Open for normal operation
Test pin. Open for normal operation
Test pin. Open for normal operation
Open for normal operation
UD1
UD2
UD3
UD4
NC
J2
UD5
I/O
I/O
I/O
G
Test pin. Open for normal operation
Test pin. Open for normal operation
Test pin. Open for normal operation
Digital Ground
H2
H3
J3
UD6
UD7
DVSS
SYSCLK
DVDD
UD8
H4
J4
I
27MHz Clock Input. The polarity could be inverted by SYSINV.
Digital Power Supply
P
H5
J5
I/O
P
Test pin. Open for normal operation
Digital Power Supply
DVDD
Either of FID or VSYNC selected by the register.
Rec.656 decode mode :Output
Master mode : Output
J6
FID/VSYNC
I/O
Slave mode : Input
FID shows that “L” is odd field and ”H” is even field.
Rec.656 decode mode : Output
Master mode : Output
Slave mode : Input
H6
HSYNC
DVSS
I/O
H7
J7
G
I
Digital Ground
“L “ : data is latched with rising edge.
“H” : data is latched with falling edge.
SYSINV
UD9
H8
I/O
Test pin. Open for normal operation
J9
J8
NC
D7
D6
-
I
I
Open for normal operation
Video data input (MSB)
Video data input
G8
Rev.00
- 7 -
2004/Oct
ASAHIKASEI
[AK8813/14]
H9
G9
F8
F9
D5
I
I
Video data input
Video data input
Digital Power Supply
D4
P
G
DVDD
DVSS
Digital Ground
-
I
I
I
I
I
I
-
Open for normal operation
Video data input
E8
E9
D8
D9
C8
C9
B9
A9
NC
D3
D2
Video data input
D1
Video data input
D0
Video data input
TEST
TEST
NC
Open for normal operation
Open for normal operation
Open for normal operation
The slave address is set with this pin.
“L”:40H “H”:42H
A8
SELA
I
Serial interface clock
Serial interface data
B8
B7
SCL
SDA
I
I/O
Power Down Pin. After returning from PD mode to normal operation,
RESET Sequence should be done to AK8813/14.
PD
I
I
A7
After this pin becomes “L”, AK8813/14 starts the internal initializing
sequence.
After initializing sequence, AK8813/14 is set NTSC mode, Rec.656
decoding mode. All DACs Off condition.
/RESET
A6
After power up, AK8813/14 must be initialized with this pin.
(27MHz Clock is necessary for reset sequence.)
B6
A5
B5
B4
A4
B3
A3
B2
A2
C3
G
-
Analog Ground
AVSS
NC
Open for normal operation
Output of Luminance Signal.
Analog Power Supply
Output of the Chrominance signal
Analog Ground
Y
O
P
AVDD
C
O
G
AVSS
CVBS
O
-
Output of Composite Video signal
Open for normal operation
Open for normal operation
Open for normal operation
NC
NC
NC
-
-
(Note1) At ITU-R.BT656 I/F mode operation, FID/VSYNC, HSYNC pins should be pulled up to VDD with
100k-ohm Resistor
(Note2) This device requires reset operation. Before resetting the state of the pin of I/O are unknown state. After
reset sequence, I/Opins (FID/VSYNC, HSYNC) turns Hi-Z states.
Rev.00
- 8 -
2004/Oct
ASAHIKASEI
[AK8813/14]
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Min
-0.3
Max
4.6V
Units
V
Supply Voltage (VDD)
DVDD, AVDD
Input Pin Voltage (Vin)
-0.3
VDD+0.3
±10
V
Input Pin Current (Iin)
Analog Reference Current (IREF)
Analog Output Current
-
-
mA
mA
mA
°C
0.37
-
11.6
Storage Temperature
-40
125
(Note) When all Ground pins(DVSS, AVSS) are set to 0V.
Recommended Operating Conditions
Parameter
Min
2.8
-20
Typ.
3.3
Max
3.6
85
Units
V
Supply Voltage (VDD)
Operating Temperature
°C
Rev.00
- 9 -
2004/Oct
ASAHIKASEI
[AK8813/14]
DC Characteristics
[Power Supply:2.8 ~ 3.6V Temperature:-20 ~ 85°C]
Parameter
Digital Input High Voltage
Digital Input Low Voltage
Digital Input leak Current
Symbol
VIH1
VIL1
IL
Min
Max
Units
V
Conditions
0.7VDD
Note1)
Note1)
Note1)
0.3VDD
V
±10
uA
V
2.4/2.2
Note 3)
Digital Output High Voltage
VOH
IOH =-1mA Note 2)
IOL = 2mA Note 2)
Digital Output Low Voltage
I2C Input High Voltage
I2C(SDA,SCL)
VOL1
0.4
V
V
VIH2
0.7VDD
I2C Input Low Voltage
I2C(SDA,SCL)
VIL2
0.3VDD
0.4
V
V
I2C(SDA) Output Voltage
VOL2
IOL = 3mA
Note 1) D[9:0],FID/VSYNC, HSYNC, SYSCLK, /RESET pin
Note 2) FID/VSYNC, HSYNC pin
Note 3) DVDD=2.8V~3.0V VOH 2.2V
Note ) Connected Test Pin to Ground, SELA and SYSINV Pin are desired polarity.
Analog Characteristics
[AVDD:3.3V Temperature:25°C Load Resistance 220ohm IREF Resistance 6.8kohm]
Parameter
DAC Resolution
Min
Typ
10
Max
Units
bit
Conditions
DAC Integral linearity error
DAC Differential linearity error
DAC Output Full Scale Voltage
DAC Output offset Voltage
Unbalances between DACs
Isolation between DACs
±0.6
±0.4
1.28
± 2
± 1
1.35
5.0
±5
LSB
LSB
V
mV
%
1.21
Note1)
Note2)
±1
50
Note3)
dB
pF
1MHz Full Scale
Note4)
DAC Load Capacitance
30
Internal Reference Voltage
Internal Reference Drift
1.17
1.235
-50
1.30
V
ppm/°C
Note 1) Under the condition of output load 220Ω, IREF pin with 6.8kΩ, using internal reference. The output full-scale current IOUT is
calculated as Full scale output voltage (typ. 1.28V) /220Ω=typ. 5.82mA.
Note 2) DAC output when feeding code of 0 (Decimal).
Note 3) Deviation between the DAC output when feeding 1V generating code of 800(Decimal).
Note 4) The value is a design target. This value is not tested.
Dissipation Current
[AVDD=DVDD=:3.3V Temperature:-25~85°C ]
Parameter
DAC Current (Active mode)
DAC Current (Sleep mode)
Power Down Current
Total Current
Min
Typ
24
10
10
50
Max
Units
mA
uA
uA
mA
Conditions
Note1)
Note2)
100
65
Note3)
Note4)
Note 1) All DACs are operating.
Note 2) All DACs are turned off with no system clock.
Note 3) In case the value after power down sequence.
Note 4) NTSC internal color bar with 3ch DACs operation and slave mode operation. DAC output pins is connected with only 220Ω load.
Rev.00
- 10 -
2004/Oct
ASAHIKASEI
[AK8813/14]
AC Characteristics (2.8V - 3.6V Temperature –20 ~ 85°C CL=30pF)
(1). SYSCLK
fCLK
50%Level between VIH and VIL
tCLKL
tCLKH
VIH
VIL
CLK
Parameter
Symbol
fSYSCLK
tCLKH
Min.
Typ.
27
Max
Unit
MHz
nsec
nsec
SYSCLK
SYSCLK Pulse width H
SYSCLK Pulse width L
15
15
tCLKL
(2). Pixel Data Input Timing
(2-1) SYSINV = Low
VIH
VIL
CLK
tDH
tDS
D7:D0
(2-2) SYSINV = High
VIH
VIL
CLK
tDH
tDS
D7:D0
Parameter
Data Setup Time
Data Hold Time
Symbol
tDS
Min
5
Typ
Max
Units
nsec
nsec
tDH
8
Rev.00
- 11 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(3). Synchronizing Signal ( FID/VSYNC, HSYNC )
(3-1) SYSINV=Low
(3-1-1) Input Timing
VIH
VIL
SYSCLK
tDH
tDS
FID/VSYNC, HSYNC
Parameter
Data Setup Time
Symbol
tDS
Min
5
Typ.
Max
Units
nsec
nsec
Data Hold Time
tDH
8
(3-1-2) Output Timing
VIH
SYSCLK
tDEL
FID/VSYNC, HSYNC
Parameter
Symbol
tDEL
Min
Typ.
Max
27
Units
nsec
Delay from SYSCLK
Rev.00
- 12 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(3-2) SYSINV = High
(3-2-1) Input Timing
VIH
VIL
SYSCLK
tDH
tDS
FID/VSYNC, HSYNC
Parameter
Data Setup Time
Data Hold Time
Symbol
tDS
Min
5
Typ.
Max
Units
nsec
nsec
tDH
8
(3-2-2) Output Timing
SYSCLK
tDEL
FID/VSYNC, HSYNC
Parameter
Symbol
tDEL
Min
Typ.
Max
27
Units
nsec
Delay from SYSCLK
Rev.00
- 13 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(4). Reset (Initialize)
Reset Timing
/RESET
pRES
1
2
9
10
SYSCLK
Hi-Z
HSYNC,VSYNC,SDA
Indefinite state
Parameter
/RESET Pulse Width
Symbol
pRES
Min
10
Typ.
Max
Units
SYSCLK
After power up, I/O pins of AK8813/14 are in the indefinite state. It should be initialize with Reset
sequence. While reset sequence system clock should be input to AK8813/14 and SCL, SDA should be
High state.
(5) Power Down Sequence
/RESET
PD
VSS
VDD
pPD
1
2
99
100
101
SYSCLK
Parameter
/RESET Pulse Width
Symbol
pSTOP
Min
100
Typ.
Max
Units
SYSCLK
During “Power Down” state, control signal should be set to VDD state or VSS state.
Rev.00
- 14 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(5). I2C Bus (SCL 400kHz cycle mode)
(5-1) I/O Timing 1
tHD:STA
tF
tR
tBUF
tSU:STO
tF
SDA
SCL
tR
tSU:STA
tLOW
Parameter
Symbol
tBUF
Min
1.3
0.6
1.3
Max
Units
usec
usec
usec
nsec
nsec
usec
usec
Bus Free Time
Hold Time (Start Condition)
Clock Pulse Low Time
tHD:STA
tLOW
tR
Bus Signal Rise Time
300
300
Bus Signal Fall Time
tF
Setup Time(Start Condition)
Setup Time(Stop Condition)
tSU:STA
tSU:STO
0.6
0.6
All the figures shown above list are not restricted by AK8813/14 but are restricted by I2C Bus standard.
Please see the I2C Bus standard for further details.
(5-2) I/O Timing 2
tHD:DAT
SDA
SCL
tHIGH
tSU:DAT
Max.
Parameter
Symbol
Min.
100 (1)
0.0
Unit.
nsec
usec
usec
Data Setup Time
Data Hold Time
tSU:DAT
tHD:DAT
tHIGH
0.9 (2)
Clock Pulse High Time
0.6
(Note1) In case of normal I2C bus mode tSU:DAT ≥250nsec
(Note2) Using under minimum tLOW, this value must be satisfied.
(Note3) I2C I/F reset is done by reset sequence of AK8813/14, System clock (27MHz) is necessary to do
reset sequence. However, SDA pin is always Hi-Z state when PD pin is set to High.
Rev.00
- 15 -
2004/Oct
ASAHIKASEI
[AK8813/14]
FUNCTIONAL DESCRIPTION
♦ Reset
When the reset pin [ /RESET ] set to “L”, AK8813/14 is in reset state. AK8813/14 starts in the internal
initializing sequence at the trailing edge of the first SYSCLK after the reset pin is “L”. All internal registers
are set to be default value by this initializing sequence. AK8813/14 needs at least 10 clock counts of
SYSCLK for this reset operation. After the reset operation, the video output pins are in high-impedance.
AK8813/14 requires SYSCLK for the reset operation.
♦ Master Clock
AK8813/14 requires 27MHz clock at SYSCLK pin for operation. Video input data (ITU-R BT.656) is
sampled at the trailing edge of this 27MHz. SYSINV decides the edge direction.
SYSINV = L
SYSINV = H
Data is sampled at rising edge of SYSCLK.
Data is sampled at falling edge of SYSCLK.
♦ Video Signal Interface
AK8813/14 can interface with the video input data by the following 3 modes. The mode is set by the
register [ Interface mode register(00H) ].
1. ITU-R BT.656 Format
AK8813/14 decodes EAV in stream data and manages an internal synchronization.
In this case, AK8813/14 outputs FID (odd : “L” even : “H”)/ VSYNC and HSYNC.
CCIR-bit of [ Interface mode register (00H) ] should be set “1” .
2. ITU-R BT.656 like Format (4:2:2 Y/Cb/Cr)
There are Master and Slave modes, for ITU-R BT.656 like Format which does not include EAV. In this
mode, CCIR-bit of [ Interface mode register(00H) ] should be set “0” .
<Master Mode>
AK8813/14 provides FID/VSYNC and HSYNC to an external device according to the AK8813/14
internal timing counter. AK8813/14 starts to sample the input data at the fixed value on the internal
pixel counter.
In this mode, following setting should be done to [Interface mode register(00H)].
CCIR-bit = 0
MAS-bit = 1
<Slave Mode>
FID/VSYNC and HSYNC are supplied by an external device. AK8813/14 samples the data as same
manner of Master mode.
In this mode, following setting should be done to [Interface mode register(00H)].
CCIR-bit = 0
MAS-bit = 0
Rev.00
- 16 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Video Signal Conversion
Video reconstruction module converts the multiplexed data (ITU-R. BT601 Y/Cb/Cr) to the interlace
format of NTSC-M, PAL-M, PAL-B,D,G,H,I,N and other formats (ex. NTSC-4.43 and PAL60). The video
reconstruction format, the line number, the color encode way(NTSC or PAL) and the frequency of Color
Sub-carrier is specified by [Video Process 1 register(01H)]. (cf. Burst Signal Table) The frequency and the
phase of Color Sub-carrier are also adjustable by [Sub C. Freq. register(06H)] and [Sub C. Phase
register(07H)]. The Sub-carrier has a free-running mode and a reset-mode. In the reset-mode, the
Sub-carrier is reset automatically to the initial phase for every 4 fields (NTSC) or 8 fields (PAL).
Rev.00
- 17 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Luminance Filter
Luminance signal passes through the 2x Low Pass filter with sin(x)/x compensation. Fig.1 is the
characteristic of Luminance Filter.
Luma Filter
10
0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0 11.0 12.0 13.0
-10
-20
-30
-40
-50
-60
Frequency [MHz]
Fig. 1 Luminance Filter
Rev.00
- 18 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Chrominance Filter
Chrominance signals (Cb,Cr) before Sub-carrier modulation pass through the 1.3 MHz Low pass filter
shown in Fig.2. Chrominance signal modulated by Sub-carrier passes through the filter shown in Fig.3.
Frequency [MHz]
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
10
0
-10
-20
-30
-40
-50
-60
-70
Fig. 2 Chroma-1 LPF
Frequency [MHz]
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
10
0
-10
-20
-30
-40
-50
-60
-70
Fig. 3 Chroma-2 LPF
Rev.00
- 19 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Color burst signal
Color burst signal is generated by 32bits-length Digital Frequency Synthesizer. The Default frequency of
the color burst is selected by [Video Process 1 Register(0x01)].
Sub-carrier Freq. Video Process
Standard
[MHz]
1
[VM1,VM0]
[0,0]
NTSC-M
3.57954545
PAL-M
3.57561188
4.43361875
3.5820558
4.43361875
4.43361875
4.43361875
[0,1]
[1,1]
[1,0]
[1,1]
[1,1]
[1,1]
PAL-B,D,G,H,I
PAL-N(Arg.)
PAL-N(non-Arg.)
PAL60
NTSC-4.43
Burst Signal Table
Sub-carrier frequency 3.57561188MHz is allowed when PAL-M mode is selected.
The burst frequency and initial phase resolution are as follows.
Frequency resolution
SCH Phase resolution
0.8046Hz
360°/256
♦ Video DAC
AK8813/14 has the three current driven 10bits-DACs at 27MHz operation. The full scale voltage of DAC
is determined by the current output from IREF pin. Typical output voltage is 1.28Vo-p under the condition
of VREFIN 1.235V, 6.8KΩ between IREF pin and Ground(AVSS) and DAC load resistance of 220Ω. This
full-scale voltage should be set in the range of 1.17V to 1.33V by adjusting the resistor which terminates
IREF pin. Each DAC output can be set to “active state” or to “inactive state” individually by [DAC Mode
register(05H)]. When DAC is in “inactive state”, the output is Hi-impedance. When all DACs are set to
“inactive state”, the analog part of AK8813/14 goes into sleep mode. In this case AK8813/14 stops
outputting the reference voltage(VREF) output. When any DAC is switched over in “active state” from sleep
mode, AK8813/14 starts outputting reference voltage. In this case AK8813/14 needs several milliseconds
for VREF wake-up time.
Using internal VREF as the reference voltage, connect [VREF OUT] pin with [VREF IN] pin and [VREF
OUT] pin is terminated with more than 0.1uF capacitor.
♦ Use external Reference Voltage
In order to improve the accuracy of DAC output, external reference voltage may be used. In this case,
VREFOUT pin still needs to be terminated with more than 0.1uF capacitor.
Rev.00
- 20 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Copy Protection
AK8814 has the function of Macrovision copy protection. Information about the Macrovision encoding
functions of the AK8814 is available to Macrovision licensees.
AK8813 doesn’t have this function.
Macrovision Corporation
2830 De La Cruz Boulevard
Santa Clara, California 95050 U.S.A.
Main Telephone (switchboard): +1 408 743-8600
Main Fax: +1 408 743-8610
Technical Support Group Fax: +1 408 743-8617
Rev.00
- 21 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Closed Caption and Extended Data
AK8813/14 supports both Closed Captioning and Extended Data. They are controlled “ON” or ”OFF”
respectively by [ Video Process 2 Register(02H) ]. Each data consists of 2 continuous bytes
register( Closed Caption R (16H,17H) ), and it is recognized as the data is renewed when the second
byte(17H register) is written in the register. After the data is renewed, AK8813/14 encodes Closed
Captioning and Extended Data at the designated line. If the data isn’t renewed, AK8813/14 outputs
“ASCII-NULL” code. The data is supposed as Odd Parity and 7 bit US-ASCII code. Host should provide a
parity bit.
*In PAL encoding mode, AK8813/14 outputs them at the same timing and same pattern as NTSC.
*The line where Closed Captioning data is encoded is as follows.
525/60 System (SMPTE)
21 Line default
625/50 System (CCIR)
22 Line default
Closed Caption
Extended Data
284 Line default
335 Line default
240+/- 48nsec
240+/- 48nsec
10.5 +/- 0.25usec
12.91 usec
Two 7-bit + PARITY ASCII
Characters Data
D0-D6
D0-D6
50 +/- 2 IRE
40IRE
10.003 +/- 0.25usec
27.382 usec
33.764 usec
61 usec
Fig. 4 Closed Captioning Wave form
Rev.00
- 22 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Video ID
AK8813/14 supports Video ID (EIAJ standard, CPR-1204) encoding for the distinction of an aspect ratio
or CGMS-A etc. Setting or Resetting the VBID-bit of [ Video Process 2 Register(02H) ], this function is
switched On/Off. The data is set by using [ Video ID Data Register(1AH, 1BH) ].
VBID Data Renewal Timing.
VSYNC
Set Control Register
I2C SDA
NEW DATA
DATA
OLD DATA
NEW DATA
Fig. 5 VBID Data renewal Timing
VBID Data Layout
VBID is consists of 20 bits and its format is shown as follows.
AK8813/14 generates CRC code automatically and appends it to the data. Initial value of the
Polynomial is 1.
DATA
bit1
bit20
WORD0
2bit
WORD1
4bit
WORD2
8bit
CRC
6bit
Fig. 6 VBID code assignment
Rev.00
- 23 -
2004/Oct
ASAHIKASEI
[AK8813/14]
VBID Waveform
bit1 bit2 bit3
bit20
Ref.
•••
70IRE +/- 10IRE
+ 10 IRE
0IRE
− 5 IRE
2.235usec +/- 50nsec
11.2usec +/- 0.3usec
11.2usec +/- 0.3usec
1H
Fig. 7 VBID Wave Form
525/60 system
70 IRE
625/50 system
490 mV
Amplitude
Encode Line
20/283
20/333
VBID parameter table
Rev.00
- 24 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ WSS
AK8813/14 supports WSS(ITU-R.Bt.1119) encoding for the distinction of an aspect ratio etc. Setting or
Resetting the WSS-bit of [ Video Process 2 Register(02H) ], this function is switched On/Off. The data is
set by using [ WSS Data Register(08H, 09H) ].
WSS Data Renewal Timing
VSYNC
Set Control Register
I2C SDA
NEW DATA
DATA
OLD DATA
NEW DATA
Fig. 8 WSS Data Renewal Timing
500mV +/- 50%
0H
27.4usec
1.5usec
10.5usec
11.0 +/- 0.25usec
38.4usec
44.5usec
Fig. 9 WSS Wave Form
Encode Line: Line 23
Coding: bi-phase modulation coding
Clock: 5MHz (Ts = 200ns)
Group 2
Group 1
Group 3
Subtitles
Group4
Run-in
Start code
Enhanced
Aspect ratio
Reserved
Services
29 elements
24 elements
24 elements
24 elements
18 elements
18 elements
Bit numbering
11 12 13
LSB MSB
0 : 000111
Bit numbering
Bit numbering
Bit numbering
0
1
3
4
5
7
2MSB
LSB
6MSB
8
9
10
MSB
LSB
LSB
0 : 000111
1 : 111000
0 : 000111
1 : 111000
0 : 000111
1 : 111000
1 : 111000
0x1F1C71C7
0x1E3C1F
Rev.00
- 25 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ AK8813/14 Interface Timing (Part 1) Master mode & ITU-R BT. 656 mode
On ITU-R BT.656 decoding mode or master mode operation, AK8813/14 outputs HSYNC and FID or
VSYNC (selected by register).
When AK8813/14 receives ITU-R BT. 656 signal, AK8813/14 decodes [EAV] code in the data for
synchronization then outputs the HSYNC. AK8813 outputs HSYNC at the rising edge of SYSCLK in the
timing of the 32nd/24th(NTSC/PAL) data slot, which is counted from the [EAV] starting point as below.
(See also AC Characteristics 2-2[Input Synchronizing Signal])
On master mode operation, the front device connected with AK8813/14 (ex. MPEG Decoder) starts to set
Cb on the 276th/288th(NTSC/PAL) slot, after starting to count HSYNC falling edge as
32nd/24th(NTSC/PAL) slot.
FID/VSYNC is output synchronously with HSYNC at the timing of solid line as in Fig. 10 Video Field.
EAV
Cr
SAV
Cr
Y/Cb/Cr Cb
Data#
Y
Y
Cb
Y
Cr
Y
Cb
Y
Cr
Y
Cb
Y
Y
Cb
0
Y
0
Cr
0
Y
1
Cb
1
360 720 360 721 361 722 361 723
368 736 368
855 428 856 428 857
525 system
Data#
360 720 360 721 361 722 361 723
366 732 366
861 431 862 431 863
0
0
0
1
1
625 system
SYSCLK
33 / 25T (525 / 625)
243 / 263T (525 / 625)
276/ 288T (525 / 625)
HSYNC
TBDT
Analog OUT
Fig. 10 Interface Timing (ITU-R BT.656 or Master mode)
Rev.00
- 26 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ AK8813/14 Interface Timing (Part 2) Slave mode
On slave mode operation, HSYNC and FID or VSYNC (Selected by register) are input to AK8813/14.
AK8813/14 monitors the transition of HSYNC at the timing of the rising edge of SYSCLK. (Refer to AC
Characteristic 2-1. [Input Synchronizing Signal]) After AK8813/14 recognizes HSYNC is Low-logic,
AK8813/14 sets the slot number to the 32nd/24th(NTSC/PAL), internally, then AK8813/14 starts to sample
the data as Cb on 276th/288th(NTSC/PAL) slot.
Video field is recognized the transition timing between FID/VSYNC and HSYNC. (Fig.10. Video Field) As
in the figure, there is a tolerance of ±1/4H.
244T / 264T (525/625)
27MHz
Data
Cb0
Y0
Cr0
Y1
Cb1
Y2
Cr1
HSYNC
TBD-clk
Fig. 11 Interfacing timing (Slave mode)
1/2 H
1/2 H
HSYNC
1/4 H1/4 H
Start of 1st Field
VSYNC/FIELD
1/4 H1/4 H
Start of 2nd Field
VSYNC/FIELD
Fig. 12 Video Field
Rev.00
- 27 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ HSYNC FID/VSYNC Timing
525 System
525
1
2
3
4
5
6
7
8
9
10
11
Digital
Line-No.
HSYNC
VSYNC
FID
262
622
310
263
264
265
266
267
268
269
270
271
272
273
274
Digital
Line-No.
HSYNC
VSYNC
FID
625 System
623
624
625
1
2
3
4
5
6
7
8
Digital
Line-No.
HSYNC
VSYNC
FID
311
312
313
314
315
316
317
318
319
320
Digital
Line-No.
HSYNC
VSYNC
FID
Fig. 13 HSYNC FID/VSYNC Timing
- 28 -
Rev.00
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Internal Color Bars Generator
AK8813/14 generates the Common Color Bar signal for NTSC and PAL internally. The generated Color
Bar is “100% Amplitude, 100% Saturation”. When AK8813/14 is set to Black Burst output mode, AK8813/14
does not output Color bar even Color bar output register is set.
Luminance
100%White
Blanking Level
Synctip Level
Chrominance
Fig. 14 Luminance and Chrominance waveform
The following values are code for ITU-R. BT601
WHITE
128
YELLOW
16
CYAN
166
170
16
GREEN
54
MAGENTA
202
RED
90
BLUE
240
41
BLACK
128
Cb
Y
235
128
210
146
145
106
81
16
Cr
34
222
240
110
128
♦ Internal Black Burst Generator
AK8813/14 generates Black burst signal for NTSC and PAL internally. When AK8813/14 is set to Black
burst output mode, AK8813/14 works same operation as that the input Y/Cb/Cr data is 16/128/128. In this
mode, AK8813/14 does not output Color bar even Color bar output register is set.
Rev.00
- 29 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Synchronizing Signal and Burst Waveform
(1-1) NTSC / NTSC-4.43 / PAL-M( Video Process 1 Register [VM3:VM2]-bit = 00 / 01 ) (SMPTE-170M)
H o riz o n ta l B la n k in g ris e tim e
9 0 %
5 0 %
5 0 %
B u rs t E n v e lo p e
ris e tim e
9 0 %
S yn c ris e tim e
1 0 %
1 0 %
B u rs t H e ig h t
9 0 %
5 0 %
1 0 %
B u rs t
S yn c L e v e l
5 0 %
H o riz o n ta l
re fe re n c e p o in t
S yn c
H . re f. to B u rs t S ta rt
re fe re n c e to B la n k in g E n d
H
b la n k in g s ta rt
H
to H -re fe re n c e
Fig. 15 Synchronizing Signal and Burst Waveform
measurement
point
Recommended
tolerance
units
value
Total line period(derived)
63.556
40
usec
IRE
nsec
nsec
nsec
usec
usec
Sync Level
+/- 1
+/- 20
+/- 20
Horizontal Blanking rise time
Sync rise time
10% - 90%
10% - 90%
10% - 90%
50%
140
140
300
1.5
Burst envelope rise time
H-Blanking start to H-reference
Horizontal Sync
+200 -100
+/- 0.1
50%
4.7
+/- 0.1
Horizontal reference point to
burst start
50%
19
defined by SC/H
cycles
H reference to H-blanking end
Burst
50%
50%
9.2
9
40
+ 0.2 –0.1
+/- 1
+/- 1
usec
cycles
IRE
Burst Height *
* Burst height of PAL-M is 306mV
9 cycles
19 cycles +/-10°
50%
Fig. 16 Synchoronizing Signal and Burst Waveform(NTSC)
Rev.00
- 30 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(1-2-1) HSYNC Timing (NTSC/NTSC4.43)
3H
3H
E
3H
B
0.5H
F
A
D
1
2
3
4
5
6
7
8
9
19
C
19 +1/- 2Line
(Set C ontrol R egister)
3H
3H
3H
0.5H
263
264
265
266
267
268
269
270
271
272
273
283
Fig. 17 HSYNC Timing
Symbol
Duration
429T
858T
31T
429T
858T
63T
Measurement point
Reference
A
B
C
D
E
F
50%
13.5MHz Clock
G
H
I
I
I
I
286mV
Equalizing Pulse
Serration Pulse
Fig. 18 Equalizing Pulse and Serration Pulse
Measurement
Value
Recommended
Symbol
units
point
tolerance
Field Period (derived)
Frame period (derived)
16.6833
33.3667
msec
msec
Vertical blanking start before first
equalizing pulse
50%
1.5
+/- 0.1
usec
Vertical blanking
19* lines + 1.5
0
lines
usec
lines
usec
lines
usec
lines
usec
nsec
(63.556usec x 20lines + 1.5usec)
Pre-equalizing duration
Pre-equalizing pulse width
Vertical sync duration
usec
3
+/- 0.1
G
H
50%
50%
50%
2.3
3
+/- 0.1
+/- 0.1
Vertical serration pulse width
Post-equalizing duration
Post-equalizing pulse width
Sync rise time
4.7
3
2.3
140
G
I
+/- 0.1
+/- 20
*This value can be set by the register.
Rev.00
- 31 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(1-2-2) FID/VSYNC Timing and Phase of Burst (PAL-M)
A
B
519
520
521
522
523
524
525
1
2
3
4
5
6
7
8
9
10
A
B
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
A
B
519
520
521
522
523
524
525
1
2
3
4
5
6
7
8
9
10
A
B
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
Fig. 19 FID/VSYNC Timing and Phase of Burst
A : Phase of Burst : nominal Value + 135°
B : Phase of Burst : nominal Value - 135°
Rev.00
- 32 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(2-1) PAL-B,D,G,H,I,N / PAL-60 ( Video Process 1 Register [VM3:VM2]-bit = 11)
H o riz o n ta l B la n k in g ris e tim e
9 0 %
5 0 %
5 0 %
B u rs t E n v e lo p e
ris e tim e
9 0 %
S yn c ris e tim e
1 0 %
1 0 %
B u rs t H e ig h t
9 0 %
B u rs t
5 0 %
1 0 %
5 0 %
H o riz o n ta l
S yn c L e v e l
re fe re n c e p o in t
H o riz o n ta l S yn c
H . re f. to B u rs t S ta rt
re fe re n c e to B la n k in g E n d
H
b la n k in g s ta rt
H
to H -re fe re n c e
Fig. 20 PAL Waveform
measurement
Recommended
tolerance
units
value
point
Total line period(derived)
64.0
300
0.3
usec
mV
usec
usec
nsec
usec
usec
Sync Level
Horizontal Blanking rise time
Sync rise time
10% - 90%
10% - 90%
10% - 90%
50%
+/- 0.1
+/- 0.1
0.2
Burst envelope rise time
H-Blanking start to H-reference
Horizontal Sync
1.5
4.7
+/- 0.3
+/- 0.2
50%
Horizontal reference point to
burst start
50%
19
defined by SC/H
cycles
H reference to H-blanking end
Burst *
50%
50%
10.5
10
300
usec
cycles
mV
+/- 1
Burst Height **
Rev.00
- 33 -
2004/Oct
ASAHIKASEI
[AK8813/14]
(2-2) FID/VSYNC Timing and Phase of Burst PAL-B,D,G,H,I,N / PAL-60
( Video Process 1 Register [VM3:VM2]-bit = 11)
A
B
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
A
B
620
621
622
623
624
625
1
2
3
4
5
6
7
8
A
B
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
A
B
620
621
622
623
624
625
1
2
3
4
5
6
7
8
Fig. 21 FID/VSYNC Timing and Phase of Burst
A : Phase of Burst : nominal Value + 135°
B : Phase of Burst : nominal Value - 135°
Rev.00
- 34 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ I2C Control Sequence
AK8813/14 is controlled by I2C bus. The slave address can be selected as 40H or 42H by selecting SELA
pin.
SELA
SLAVE Address
0x40
PULL Down [Low]
PULL UP [High]
0x42
Operation :
Write Sequence:
(a)1byte Write Sequence
Slave
Sub
A
S
w
A
Data
A
Stp
Address
Address
1-
bit
1-
1-
bit
8-bits
8-bits
bit
8-bits
(b) Sequential Write Operation
Slave
Sub
•••
S
w
A
A
Data(n)
8-bits
A
Data(n+1)
8-bits
A
Data(n+m)
8-bits
A
stp
Address
Address(n)
1-
bit
1-
bit
1-
bit
1-
bit
1-
bit
8-bits
8-bits
Read Sequence:
Slave
Sub
Slave
Address
S
rS
Data1
8-bits
Data2
8-bits
Data3
8-bits
Data n
8-bits
stp
w
A
A
R
A
A
A
A
Ā
•••
Address
Address(n)
8-bits
1
8-bits
1
8-bits
1
1
1
1
1
S, rS : Start Condition
A :
Acknowledge (SDA Low )
Ā :
Not Acknowledge (SDA High)
stp : Stop Condition
R/W 1 : Read 0 : Write
: Master device (Host)
: Slave device (AK8813/14)
Rev.00
- 35 -
2004/Oct
ASAHIKASEI
[AK8813/14]
♦ Register Map
Sub
Address
Register
Default
R/W
Function
Interface Mode Register
Video Process 1 Register
Video Process 2 Register
Setting Interface mode
0x00
0x01
0x02
0x00
0x00
0x00
R/W
R/W
R/W
Setting Standard (NTSC, PAL etc.)
Setting Closed Caption/Extended Data/VBID
Setting Composite signal or Component signal
Adjusting Chrominance/Luminance Delay
Video Process 3 Register
0x03
0x00
R/W
Reserved Register
DAC Mode Register
Sub Carrier Frequency
Register
Sub Carrier Phase
Register
WWS Data 1 Register
WWS Data 2 Register
Closed Caption 1 Register
Closed Caption 2 Register
Closed Caption Extended 1
Register
0x04
0x05
0xAA
0x00
R/W
R/W
Each DAC On/Off Switch
Adjusting Sub-carrier frequency
0x06
0x00
R/W
Adjusting Sub-carrier phase
0x07
0x00
R/W
WSS Data Register
WSS Data Register
Closed Caption Lower byte Data
Closed Caption Upper byte Data
0x08
0x09
0x16
0x17
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
Extended Lower byte Data
0x18
0x00
R/W
Closed Caption Extended 2
Register
Extended Upper byte Data
0x19
0x00
R/W
Video ID Lower byte Data
Video ID Upper byte Data
Status
0x1A
0x1B
0x24
0x25
0x26
Video ID 1 Register
Video ID 2 Register
Status Register
Device ID Register
Device Revision Register
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R
R
R
Device ID
Revision
Rev.00
- 36 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Interface Mode Register (R/W) [Address 0x00]
Sub Address 0x00
Default Value 0xA4
bit 7
BLN4
bit 6
BLN3
bit 5
BLN2
bit 4
BLN1
bit 3
BLN0
bit 2
FID
bit 1
MAS
bit 0
REC656
Default Value
1
0
1
0
0
1
0
0
Interface Mode Register Definition
BIT
Register Name
R/W
Definition
0 : REC656 non-decode
1 : REC656 decode
(At Rec.656 mode operation, MAS-bit should be 0.)
0 : Slave mode
1 : Master mode When REC=0,it’s valid
0 : Select VSYNC
1 : Select FID
REC656
bit 0
REC656
R/W
I/F mode bit
Master mode
Set bit
bit 1
bit 2
MAS
FID
R/W
R/W
Field ID Set bit
bit 3
~
bit 7
BLN0
~
BLN4
Blanking Line
No bit
R/W
Line Blanking No.
Rev.00
- 37 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Video Process 1 Register (R/W) [Address 0x01]
Sub Address 0x01
Default Value 0x30
bit 7
BBG
bit 6
CBG
bit 5
SETUP
bit 4
SCR
bit 3
VM3
bit 2
VM2
bit 1
VM1
bit 0
VM0
Default Value
0
0
1
1
0
0
0
0
Video Process 1 Register Definition
Register
Name
BIT
R/W
Definition
[VM1:VM0]-bit
00 : 3.57954545 MHz
01 : 3.57561188 MHz
10 : 3.5820558 MHz
11 : 4.43361875 MHz
[VM3:VM2]-bit
Video Mode 0
Register
~
Video Mode 3
Register
bit 0
~
bit 3
VM0
~
VM3
R/W
00 : 525/60
01 : 525/60 PAL (PAL-M etc.)
10 : Reserved
11 : 625/50 PAL (PAL-B,D,G,H,I,N)
0 : Sub C. Phase Reset off
1 : Standard Field Reset
0 : No Set-up
Sub Carrier
Reset bit
bit 4
bit 5
bit 6
bit 7
SCR
SETUP
CBG
R/W
R/W
R/W
R/W
Setup bit
1 : 7.5 IRE Set-up
Color Bar
0 : Video Encode
Generator bit
Black Burst
Generator
1 : Generates color bar
0 : Video Encode
BBG
1 : Generates black burst
Register Setting of each standard is shown as following ;
VM3-VM0
NTSC-M
PAL-B,D,G,H,I
PAL-M
PAL-60
NTSC4.43
0000
1111
0101
0111
0011
• When SCR is “ON”, the Subcarrier Phase is reset every 4 fields for NTSC, every 8 fields for PAL.
• Even when SETUP is “ON”, there is no Set-up (Pedestal) during the blanking lines.
Rev.00
- 38 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Video Process 2 Register (R/W) [Address 0x02]
Sub Address 0x02
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
Reserved
bit 4
Reserved
bit 3
WSS
bit 2
CC284
bit 1
CC21
bit 0
VBID
Default Value
0
0
0
0
0
0
0
0
Video Process 2 Register Definition
Register
Name
BIT
R/W
Definition
0 : Video ID off
1 : Video ID on
bit 0
bit 1
bit 2
bit 3
VBID
CC21
CC284
WSS
Video ID bit
R/W
R/W
R/W
R/W
0 : Closed caption off
1 : Closed Caption on
0 : Extended Data off
1 : Extended data on
0 : WSS off
Closed Caption bit
Closed Caption
Extended Data bit
WSS set bit
1 : WSS on
bit 4
~
bit 7
Reserved
Reserved bit
R/W
Reserved
Video Process 3 Register (R/W) [Address 0x03]
Sub Address 0x03
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
SYD2
bit 4
SYD1
bit 3
SYD0
bit 2
CYD2
bit 1
CYD1
bit 0
CYD0
Default Value
0
0
0
0
0
0
0
0
Video Process 3 Register Definition
Register
Name
BIT
R/W
Definition
bit 0
~
CYD0
Composite Y
Delay bit
~
R/W
R/W
R/W
S-Video Y Component delay no. from Chroma: 2's comp.
Composite Y Component delay no. from Chroma: 2's comp.
Reserved
bit 2
bit 3
~
CYD2
SYD0
~
S-video Y Delay bit
Reserved bit
bit 5
SYD2
bit 6
~
bit 7
Reserved
• S-video and Y component of the composite signal can be shifted for the chroma signal
independently at ±3-system clock (27MHz).
Rev.00
- 39 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Reserved Register (R/W) [Address 0x04]
Sub Address 0x04
default Value 0xAA
bit 7
Reserved
bit 6
Reserved
bit 5
Reserved
bit 4
Reserved
bit 3
Reserved
bit 2
Reserved
bit 1
Reserved
bit 0
Reserved
Default Value
1
0
1
0
1
0
1
0
Reserved
Register
Name
BIT
R/W
Definition
bit 0
~
bit 7
Reserved
Reserved bit.
Reserved
R/W
DAC Mode Register (R/W) [Address 0x05]
Sub Address 0x05
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
Reserved
bit 4
Reserved
bit 3
Reserved
bit 2
OUTCP
bit 1
OUTC
bit 0
OUTY
Default Value
0
0
0
0
0
0
0
0
DAC Mode Register Definition
Register
BIT
R/W
R/W
Definition
Name
0: Y signal output : OFF
1: Y signal output : ON
bit 0
bit 1
bit 2
OUTY
OUTC
YDAC Out bit
CDAC Out bit
CPDAC Out bit
0: Chrominance signal output : OFF
1: Chrominance signal output : ON
R/W
R/W
R/W
0: Composite video signal or U signal output : OFF
1: Composite video signal or U signal output : ON
OUTCP
bit 3
~
bit 7
Reserved
Reserved bit.
Reserved
• Video output of AK8813/14 (DAC) can be forced “OFF” independently.
The output of DAC that is forced “OFF” is Hi-impedance. When three DACs are forced
“OFF”, then the internal VREF is also forced “OFF”. In this case, it takes several milliseconds
before the internal VREF reaches the proper voltage after any DAC becomes “ON”.
Rev.00
- 40 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Sub Carrier Frequency Control Register (R/W) [Address 0x06]
Sub Address 0x06
default Value 0x00
bit 7
SUBF7
Bit 6
SUBF6
bit 5
SUBF5
bit 4
SUBF4
bit 3
SUBF3
bit 2
SUBF2
bit 1
SUBF1
bit 0
SUBF0
Default Value
0
0
0
0
0
0
0
0
Sub Carrier Frequency Control Register Definition
Register
BIT
R/W
Definition
Name
SUBF0
~
bit 0
~
bit 7
Sub Carrier
Frequency Control
bit
Adjustment of frequency between
+127 and –128 step of 0.8Hz
R/W
SUBF7
Sub Carrier Phase Control Register (R/W) [Address 0x07]
Sub Address 0x07
default Value 0x00
bit 7
SUBP7
Bit 6
SUBP6
bit 5
SUBP5
bit 4
SUBP4
bit 3
SUBP3
bit 2
SUBP2
bit 1
SUBP1
bit 0
SUBP0
Default Value
0
0
0
0
0
0
0
0
Sub Carrier Phase Control Register Definition
Register
Name
BIT
R/W
Definition
bit 0
~
bit 7
SUBP0
Sub Carrier
Phase Control
bit
Adjustment of frequency between
+127 and –128 step of 0.8Hz
~
R/W
SUBP7
• Sub- carrier phase is adjustable by (360° /256) step.
WSS Data 1 Register (R/W) [Address 0x08]
WSS Data 2 Register (R/W) [Address 0x09]
Sub Address 0x08
default Value 0x00
bit 7
G2-7
bit 6
G2-6
bit 5
G2-5
bit 4
G2-4
bit 3
G1-3
bit 2
G1-2
bit 1
G1-1
bit 0
G1-0
Default Value
0
0
0
0
0
0
0
0
Sub Address 0x09
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
G4-13
bit 4
G4-12
bit 3
G4-11
bit 2
G3-10
bit 1
G3-9
bit 0
G3-8
Default Value
0
0
0
0
0
0
0
0
• AK8813/14 generates the necessary sub-carrier frequency from a system clock by DFS
(Digital Frequency Synthesizer)
• Frequency of default is adjustable by specifying this bit. This bit adjusts the default
frequency.
Rev.00
- 41 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Closed Caption Data 1 Register (R/W) [Address 0x16]
Closed Caption Data 2 Register (R/W) [Address 0x17]
Sub Address 0x16
default Value 0x00
bit 7
CC7
bit 6
CC 6
bit 5
CC5
bit 4
CC4
bit 3
CC3
bit 2
CC2
bit 1
CC1
bit 0
CC0
Default Value
0
0
0
0
0
0
0
0
Sub Address 0x17
default Value 0x00
bit 7
CC15
bit 6
CC14
bit 5
CC13
bit 4
CC12
bit 3
CC11
bit 2
CC10
bit 1
CC9
bit 0
CC8
Default Value
0
0
0
0
0
0
0
0
Closed Caption Extended Data 1 Register (R/W) [Address 0x18]
Closed Caption Extended Data 2 Register (R/W) [Address 0x19]
Sub Address 0x18
default Value 0x00
bit 7
EXT7
bit 6
EXT6
bit 5
EXT5
bit 4
EXT4
bit 3
EXT3
bit 2
EXT2
bit 1
EXT1
bit 0
EXT0
Default Value
0
0
0
0
0
0
0
0
Sub Address 0x19
default Value 0x00
bit 7
EXT15
bit 6
EXT14
bit 5
EXT13
bit 4
EXT12
bit 3
EXT11
bit 2
EXT10
bit 1
EXT9
bit 0
EXT8
Default Value
0
0
0
0
0
0
0
0
• When the 2nd byte of Closed Caption Data and Extended Data is written in, AK8813/14
recognizes the renewed data and encodes it in the video line.
When the data is not renewed AK8813/14 outputs NULL code.
Rev.00
- 42 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Video ID 1 Register (R/W) [Address 0x1A]
Video ID 2 Register (R/W) [Address 0x1B]
Sub Address 0x1A
default Value 0x00
bit 7
Reserved
bit 6
Reserved
bit 5
VBID1
bit 4
VBID2
bit 3
VBID3
bit 2
VBID4
bit 1
VBID5
bit 0
VBID6
Default Value
0
0
0
0
0
0
0
0
Sub Address 0x1B
default Value 0x00
bit 7
VBID7
bit 6
VBID8
bit 5
VBID9
bit 4
VBID10
bit 3
VBID11
bit 2
VBID12
bit 1
VBID13
bit 0
VBID14
Default Value
0
0
0
0
0
0
0
0
• Please write value 0 at Reserved bit.
• Bit numbers correspond to Fig. 5 VBID code assignment.
• AK8813/14 generates CRC 6 bit data automatically.
Status Register (R/W) [Address 0x24]
Sub Address 0x24
bit 7
Reserved
bit 6
Reserved
bit 5
EN284
bit 4
EN21
bit 3
SYNC
bit 2
STS2
bit 1
STS1
bit 0
STS0
Status Register Definition
Register
Name
BIT
R/W
Definition
bit 0
~
STS0
~
Status bit
R
R
R
R
R
Shows the processing field No.
bit 2
STS2
0 : Missing synchronization in slave mode.
1 : Synchronization was achieved.
bit 3
bit 4
bit 5
SYNC bit
S-video Y Delay bit
Encode21 bit
0 : Wait for the appointed video line to encode.
1 : Ready for the C.C. data input to the register.
0 : Wait for the appointed video line to encode.
1 : Ready for the C.C. data input to the register.
EN21
EN284
Encode 284 bit
Reserved bit.
bit 6
~
bit 7
Reserved
Reserved
• Status Register becomes effective when SYNC bit turns to “1”.
When in master mode operation, this bit is ”1”.
• STS2-STS2 holds the field number of processing. Some time lag is inevitable for theI2C
acquisition.
• Closed caption data should be renewed after firm that the EN* flag is “1”.
EN* flag bit is cleared after the second byte( Sub address 17H,19H) was accessed.
• Reserved-bit is always value 0.
Rev.00
- 43 -
2004/Oct
ASAHIKASEI
[AK8813/14]
Device ID Register (R/W) [Address 0x25]
Sub Address 0x25
default Value 0x14
bit 7
DEV7
Bit 6
DEV6
bit 5
DEV5
bit 4
DEV4
bit 3
DEV3
bit 2
DEV2
bit 1
DEV1
bit 0
DEV0
Default Value
0
0
0
1
0
1
0
0
Device ID Register Definition
Register
Name
BIT
R/W
Definition
Shows the Device ID.
bit 0
~
bit 7
DEV0
~
DEV7
Device ID bit
“0x13” is assigned for AK8813.
“0x14” is assigned for AK8814.
R
Revision ID Register (R/W) [Address 0x26]
Sub Address 0x26
default Value 0x00
bit 7
REV7
Bit 6
REV6
bit 5
REV5
bit 4
REV4
bit 3
REV3
bit 2
REV2
bit 1
REV1
bit 0
REV0
Default Value
0
0
0
0
0
0
0
0
Revision ID Register Definition
Register
Name
BIT
R/W
Definition
This value will be modified when the control software
has to be modified.
bit 0
~
bit 7
REV0
~
REV7
Revision ID bit
R
Shows the Revision ID.
Rev.00
- 44 -
2004/Oct
ASAHIKASEI
[AK8813/14]
SYSTEM CONNECTION EXAMPLE
Amp + LPF
COMPOSITE -
D0 - D7
Y
C
-
-
MPEG
220
75
Ω
Ω
SYSCLK
Decoder
VREFOUT
VREFIN
FID/ VSYNC
HSYNC
0.1uF
10uF
AK8813/14
SDA
SCL
I2C Bus
IREF
6.8k
Ω
DVDD DVSS
0.1uF
AVSS
AVDD
Digital 3.3V
Analog 3.3V
10uF
10uF
0.1uF
Digital GND
Analog GND
Rev.00
- 45 -
2004/Oct
ASAHIKASEI
48pin LQFP
[AK8813/14]
PACKAGE
1.70 Max
1.4 TYP
9.0 ± 0.2
7.0
0.13 ± 0.13
48
1
0.17 ± 0.08
0.22 ± 0.08
0.5
M
0.10
0°∼10°
Units = mm
0.5 ± 0.2
0.10
Package & Lead frame material
Package molding compound : Epoxy
Lead frame material : Cu
Lead frame surface treatment : Solder plate
Rev.00
- 46 -
2004/Oct
ASAHIKASEI
57Pin FBGA
[AK8813/14]
5.0 ± 0.1
57 − Φ0.3 ± 0.05
M
S AB
Φ0.05
9 8 7 6 5 4
3 2 1
A
B
C
D
B
E
F
G
H
J
0.5
4.0 0.5 8
=
×
0.5
S
0.20
S
SEATING PLANE
0.08
S
Package & Lead frame material
Package molding compound: Epoxy
Interposer material: BT resin
Rev.00
- 47 -
2004/Oct
ASAHIKASEI
[AK8813/14]
48pin LQFP (Pb Free Package)
1) Asahi Kasei Logo
2) Marketing Code : AK8813
3) Date Code : XXXXXXX (7 digits)
4) Pin #1 indication
AK8813VQ
Rev.00
- 48 -
2004/Oct
ASAHIKASEI
57Pin FBGA
[AK8813/14]
1) Pin #1 indication
2) Marketing Code : 8813
3) Date Code : YWWL (4 digits)
Y: Year
8813
WW: week
L: Lot
YWWL
57Pin FBGA (Pb Free Package)
1) Pin #1 indication
2) Marketing Code : 8813P
3) Date Code : YWWL (4 digits)
Y: Year
8813P
YWWL
WW: week
L: Lot
Rev.00
- 49 -
2004/Oct
ASAHIKASEI
[AK8813/14]
48pin LQFP (Pb Free Package)
1) Asahi Kasei Logo
2) Marketing Code : AK8814
3) Date Code : XXXXXXX (7 digits)
4) Pin #1 indication
AK8814VQ
Rev.00
- 50 -
2004/Oct
ASAHIKASEI
[AK8813/14]
57Pin FBGA (Pb Free Package)
1) Pin #1 indication
2) Marketing Code : 8814
3) Date Code : YWWL (4 digits)
Y: Year
8814
YWWL
WW: week
L: Lot
Rev.00
- 51 -
2004/Oct
ASAHIKASEI
[AK8813/14]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or
use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency
exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or
other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with
the express written consent of the Representative Director of AKM. As used here:
safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure
to function or perform may reasonably be expected to result in loss of life or in significant injury or
damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system
containing it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise
places the product with a third party to notify that party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any
and all claims arising from the use of said product in the absence of such notification.
Rev.00
- 52 -
2004/Oct
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