AK93C55CU [AKM]
1K/2K/4Kbit Serial CMOS EEPROM; 1K / 2K / 4k位串行CMOS EEPROM的
| 型号： | AK93C55CU |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 1K/2K/4Kbit Serial CMOS EEPROM |
| 文件： | 总16页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK93C45C/55C/65C]
AK93C45C/55C/65C
1K/2K/4Kbit Serial CMOS EEPROM
Features
ꢀ ADVANCED CMOS EEPROM TECHNOLOGY
ꢀ READ/WRITE NON-VOLATILE MEMORY
ꢀ WIDE VCC OPERATION : VCC = 1.5V to 5.5V(READ)
VCC = 1.6V to 5.5V(WRITE/WRAL/PAGE WRITE)
ꢀ AK93C45C ・・1024 bits, 64 x 16 organization
AK93C55C ・・2048 bits, 128 x 16 organization
AK93C65C ・・4096 bits, 256 x 16 organization
ꢀ SERIAL INTERFACE
- Interfaces with popular microcontrollers and standard microprocessors
-1.0MHz(1.5V≤VCC<2.5V), 4.0MHz(2.5V≤VCC≤5.5V)
ꢀ LOW POWER CONSUMPTION
- 0.8µA Max. Standby
ꢀ High Reliability
- Endurance
: 1000K E/W cycles / Address
- Data Retention : 10 years
ꢀ Automatic address increment (READ)
ꢀ Automatic write cycle time-out with auto-ERASE
ꢀ Busy/Ready status signal
ꢀ Software and Hardware controlled write protection
ꢀ IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (TMSOP, SON, USON)
DO
DATA
REGISTER
16
16
R/W AMPS
AND
AUTO ERASE
INSTRUCTION
REGISTER
DI
EEPROM
INSTRUCTION
DECODE,
CONTROL
AND
93C45C=1024bit
93C55C=2048bit
93C65C=4096bit
CLOCK
GENERATION
ADD.
BUFFERS
DECODER
CS
VPP SW
SK
PE
VPP
GENERATOR
VREF
Block Diagram
- 1 -
DAM06E-01
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
General Description
The AK93C45C/55C/65C is a 1024/2048/4096-bit serial CMOS EEPROM divided into 64/128/256
registers of 16 bits each. The AK93C45C/55C/65C has 6 instructions such as READ, WRITE,
PAGE WRITE, EWEN, EWDS and WRAL. Those instructions control the AK93C45C/55C/65C.
The AK93C45C/55C/65C can operate full function under wide operating voltage range. The
charge up circuit is integrated for high voltage generation that is used for write operation.
A serial interface of AK93C45C/55C/65C, consisting of chip select (CS), serial clock (SK), data-in
(DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard
microprocessors. AK93C45C/55C/65C takes in the write data from data input pin (DI) to a register
synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation,
AK93C45C/55C/65C takes out the read data from a register to data output pin (DO) synchronously
with rising edge of SK.
The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data
output or Busy/Ready signal output.
x Software controlled write protection
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction
is disabled. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must
be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or
VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
The PE is internally pulled up to VCC. If the PE is left unconnected, the part will accept WRITE,
PAGE WRITE, WRAL, EWEN and EWDS instructions.
x Busy/Ready status signal
After a WRITE, PAGE WRITE, WRAL instruction, the DO output serves as a Busy/Ready status
indicator. After the falling edge of the CS initiates the self-timed programming cycle, the DO
indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state.
The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
DAM06E-01
2005/10
- 2 -
ASAHI KASEI
[AK93C45C/55C/65C]
Type of Products
Model
Memory size
Temp. Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VCC
Package
AK93C45CT
AK93C45CL
AK93C45CU
AK93C55CT
AK93C55CL
AK93C55CU
AK93C65CT
AK93C65CL
AK93C65CU
1.5V to 5.5V
1.5V to 5.5V
1.5V to 5.5V
1.5V to 5.5V
1.5V to 5.5V
1.5V to 5.5V
1.5V to 5.5V
1.5V to 5.5V
1.5V to 5.5V
8pin Plastic TMSOP
8pin Plastic SON
8pin Plastic USON
8pin Plastic TMSOP
8pin Plastic SON
8pin Plastic USON
8pin Plastic TMSOP
8pin Plastic SON
8pin Plastic USON
1K bits
2K bits
4K bits
Pin Arrangement
AK93C45CT/55CT/65CT AK93C45CL/55CL/65CL
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
PE
VCC
NC
PE
1
2
3
4
8
7
6
5
CS
SK
DI
DO
GND
GND
DO
8pin TMSOP
8pin SON
AK93C45CU/55CU/65CU
1
2
3
4
VCC
NC
PE
8
7
6
5
CS
SK
DI
GND
DO
8pin USON
Pin Name
CS
Function
Chip Select
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Program Enable
Power Supply
Ground
DI
DO
PE
VCC
GND
NC
Not Connected
*1
(note) The PE is internally pulled up to VCC ( R = typ.2.5MΩ, VCC=5V ).
*1: Please Open NC pin.
DAM06E-01
2005/10
- 3 -
ASAHI KASEI
[AK93C45C/55C/65C]
Functional Description
The AK93C45C/55C/65C has 6 instructions such as READ, WRITE, PAGE WRITE, EWEN, EWDS
and WRAL. A valid instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the
desired memory Address location.
The CS pin must be brought low for a minimum of ‘tCS’ between each instruction when the
instruction is continuously executed.
Start Op
Instruction
Address
Data
Comments
Bit
Code
Reads data stored in memory, at specified address.
Writes register.
READ
1
10
01
11
00
00
00
A5-A0
A5-A0
A5-A0
11XXXX
00XXXX
010000
D15-D0
D15-D0
D15-D0
WRITE
PAGE WRITE
EWEN
EWDS
WRAL
1
1
1
1
1
Page Write register.
Write enable must precede all programming modes.
Disables all programming instructions.
Writes all registers.
D15-D0
X: Don't care
table1. Instruction Set for the AK93C45C
Start Op
Bit Code
Instruction
Address
Data
Comments
Reads data stored in memory, at specified address.
Writes register.
READ
1
10
01
11
00
00
00
XA6-A0
XA6-A0
XA6-A0
D15-D0
D15-D0
D15-D0
WRITE
PAGE WRITE
EWEN
EWDS
WRAL
1
1
1
1
1
Page Write register.
Write enable must precede all programming modes.
Disables all programming instructions.
Writes all registers.
11XXXXXX
00XXXXXX
010000000
D15-D0
X: Don't care
table2. Instruction Set for the AK93C55C
Start Op
Bit Code
Instruction
Address
Data
Comments
Reads data stored in memory, at specified address.
Writes register.
READ
1
10
01
11
00
00
00
A7-A0
A7-A0
A7-A0
D15-D0
D15-D0
D15-D0
WRITE
PAGE WRITE
EWEN
EWDS
WRAL
1
1
1
1
1
Page Write register.
Write enable must precede all programming modes.
Disables all programming instructions.
Writes all registers.
11XXXXXX
00XXXXXX
010000000
D15-D0
X: Don't care
table3. Instruction Set for the AK93C65C
(Note) x The AK93C45C/55C/65C perceives the start bit in the logic"1" and also "01".
DAM06E-01
2005/10
- 4 -
ASAHI KASEI
[AK93C45C/55C/65C]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. After the
last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the
SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO
indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
PE
CS
tCS
0
1
2
3
4
5
8
9
10
11
23
D2
24
D1
25
D0
SK
DI
0
1
0
1
A5
A4
A1
A0
D15 D14
Start Bit
Op code
Busy
Hi-Z
DO
Ready
AK93C45C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
tE/W
WRITE (AK93C45C)
PE
CS
SK
DI
tCS
0
1
2
3
4
5
10
A1
11
A0
12
13
25
D2
26
D1
27
D0
0
1
0
1
X
A6
D15 D14
Start Bit
Op code
Busy
Hi-Z
DO
Ready
AK93C55C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
tE/W
X: Don't care
WRITE (AK93C55C)
PE
CS
SK
DI
tCS
0
1
2
3
4
5
10
A1
11
A0
12
13
25
D2
26
D1
27
D0
0
1
0
1
A7
A6
D15 D14
Start Bit
Op code
Busy
Hi-Z
DO
Ready
AK93C65C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
tE/W
WRITE (AK93C65C)
- 5 -
DAM06E-01
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
PAGE WRITE
AK93C45C/55C/65C has Page Write mode, which can write the data within 4 words with one
programming cycle. The input data sent to the shift register within 4 words. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the
Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
After the receipt of each word, the two lower order address pointer bits internally incremented by
one. The higher order six bits of the word address remains constant. When the highest address
is reached ”XXXX XX11”, the address counter rolls over to address ”XXXX XX00” allowing the page
write cycle to be continued indefinitely.
If AK93C45C/55C/65C is transmitted more than 4 words, the address counter will ”roll over” and the
previously written data will be overwritten. When AK93C45C/55C/65C is transmitted 6 words, fifth
word will be overwritten to first word, and sixth word will be overwritten to second word.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
PE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
23
24
25
SK
Data(n)
D2 D1 D0
DI
0
1
1
1
A5 A4 A3 A2 A1 A0 D15 D14 D13
Hi-Z
DO
AK93C45C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
PE
CS
SK
26
27
39
40
41
tCS
Data(n+1)
Data(n+3)
D0 D15 D14 D2 D1 D0
DI
D15 D14
D2 D1 D0 D15
Hi-Z
Busy
tE/W
DO
Ready
PAGE WRITE (AK93C45C)
DAM06E-01
2005/10
- 6 -
ASAHI KASEI
[AK93C45C/55C/65C]
PE
CS
SK
0
1
2
3
4
5
6
7
8
9
10
11
12
25
26
27
Data(n)
D2 D1 D0
DI
0
1
1
1
X
A6 A5 A4 A3 A2 A1 A0 D15
Hi-Z
DO
AK93C55C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
PE
CS
SK
28
29
41
42
43
tCS
Data(n+1)
Data(n+3)
D0 D15 D14 D2 D1 D0
DI
D15 D14
D2 D1 D0 D15
Hi-Z
Busy
tE/W
DO
Ready
X: Don't care
PAGE WRITE (AK93C55C)
PE
CS
SK
0
1
2
3
4
5
6
7
8
9
10
11
12
25
26
27
Data(n)
D2 D1 D0
DI
0
1
1
1
A7 A6 A5 A4 A3 A2 A1 A0 D15
Hi-Z
DO
AK93C65C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
PE
CS
SK
28
29
41
42
43
tCS
Data(n+1)
Data(n+3)
D0 D15 D14 D2 D1 D0
DI
D15 D14
D2 D1 D0 D15
Hi-Z
Busy
tE/W
DO
Ready
PAGE WRITE (AK93C65C)
DAM06E-01
2005/10
- 7 -
ASAHI KASEI
[AK93C45C/55C/65C]
WRAL
The write instruction is followed by 16 bits of data to be written into all address. After the last bit of
data is put on the DI pin, the CS pin must be brought low before the next rising edge of the SK clock.
This falling edge of the CS initiates the self-timed programming cycle. The DO indicates the
Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’. DO=logical "0"
indicates that programming is still in progress. DO=logical "1" indicates that the register at the
address specified in the instruction has been written with the new data pattern contained in the
instruction and the part is ready for a next instruction.
PE
CS
tCS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
25
D0
SK
DI
0
1
0
0
0
1
0
0
0
0
D15 D14 D13 D12
Start Bit
Busy
Hi-Z
DO
Ready
AK93C45C output a logic "1" (Ready status),
if previous instruction is W RITE, PAGE WRITE, WRAL.
tE/W
WRAL (AK93C45C)
PE
CS
SK
DI
tCS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
27
D0
0
1
0
0
0
1
0
0
0
0
0
0
D15 D14
Start Bit
Busy
Hi-Z
DO
Ready
AK93C55C output a logic "1" (Ready status),
if previous instruction is W RITE, PAGE WRITE, WRAL.
tE/W
WRAL (AK93C55C)
PE
CS
SK
DI
tCS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
27
D0
0
1
0
0
0
1
0
0
0
0
0
0
D15 D14
Start Bit
Busy
Hi-Z
DO
Ready
AK93C65C output a logic "1" (Ready status),
if previous instruction is W RITE, PAGE WRITE, WRAL.
tE/W
WRAL (AK93C65C)
DAM06E-01
2005/10
- 8 -
ASAHI KASEI
[AK93C45C/55C/65C]
READ
The read instruction is the only instruction which outputs serial data on the DO pin.
Following the Start bit, first Op code and address are decoded, then the data from the selected
memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from
the selected memory location. The output data changes are synchronized with the rising edges of
the serial clock (SK).
The data in the next address can be read sequentially by continuing to provide clock. The address
automatically cycles to the next higher address after the 16bit data shifted out.
When the highest address is reached, the address counter rolls over to address 00h allowing the
read cycle to be continued indefinitely.
CS
0
1
2
3
4
5
8
9
10
11
25
26
40
41
SK
DI
0
1
1
0
A5
A4
A1
A0
Start bit
Op code
Hi-Z
0
D15 D14
D0 D15
D1
D0
DO
Dummy
Bit
AK93C45C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE,
WRAL.
address[A5–A0]
address[A5–A0]+1
READ (AK93C45C)
CS
SK
DI
0
1
2
3
4
5
10
A1
11
A0
12
13
27
28
42
43
0
1
1
0
X
A6
Start bit
Op code
Hi-Z
0
D15 D14
D0 D15
D1
D0
DO
Dummy
Bit
AK93C55C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE,
WRAL.
address[A6–A0]
address[A6–A0]+1
X: Don't care
READ (AK93C55C)
CS
SK
DI
0
1
2
3
4
5
10
A1
11
A0
12
13
27
28
42
43
0
1
1
0
A7
A6
Start bit
Op code
Hi-Z
0
D15 D14
D0 D15
D1
D0
DO
Dummy
Bit
AK93C65C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE,
WRAL.
address[A7–A0]
address[A7–A0]+1
READ (AK93C65C)
- 9 -
DAM06E-01
2005/10
ASAHI KASEI
[AK93C45C/55C/65C]
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE, PAGE WRITE, WRAL instruction
is disable. Before WRITE, PAGE WRITE, WRAL instruction is executed, EWEN instruction must
be executed. The ERASE/WRITE enable state continues until EWDS instruction is executed or
VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
PE
CS
0
1
2
3
4
5
6
7
8
9
SK
DI
0
1
0
0
X
X
X
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C45C output a logic "1" (Ready status),
X: Don't care
if previous instruction is WRITE PAGE WRITE, WRAL.
EWEN / EWDS (AK93C45C)
PE
CS
SK
DI
0
0
1
2
3
4
5
6
7
8
9
10
11
1
0
0
X
X
X
X
X
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C55C output a logic "1" (Ready status),
if previous instruction is WRITE PAGE WRITE, WRAL.
X: Don't care
EWEN / EWDS (AK93C55C)
PE
CS
SK
DI
0
1
2
3
4
5
6
7
8
9
10
11
0
1
0
0
X
X
X
X
X
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C65C output a logic "1" (Ready status),
if previous instruction is WRITE PAGE WRITE, WRAL.
X: Don't care
EWEN / EWDS (AK93C65C)
DAM06E-01
2005/10
- 10 -
ASAHI KASEI
[AK93C45C/55C/65C]
Absolute Maximum Ratings
Parameter
Power Supply
All Input Voltages
Symbol
VCC
VIO
Min
-0.6
-0.6
Max
+6.5
VCC+0.6
Unit
V
V
with Respect to Ground
Ambient storage temperature
Tst
-65
+150
°C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter
Power Supply 1(Except READ)
Power Supply 2(READ)
Symbol
VCC1
VCC2
Ta
Min
1.6
1.5
-40
Max
5.5
5.5
Unit
V
V
Ambient Operating Temperature
+85
°C
DAM06E-01
2005/10
- 11 -
ASAHI KASEI
[AK93C45C/55C/65C]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
( 1.5V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
Symbol
ICC1
Condition
Min.
Max.
2.5
Unit
mA
VCC=5.5V, tSKP=250ns, *1
Current Dissipation
(WRITE)
ICC2
ICC3
ICC4
ICC5
ICC6
1.5
2.5
1.5
1.5
0.1
0.8
mA
mA
mA
mA
mA
µA
VCC=1.8V, tSKP=1.0µs, *1
VCC=5.5V, tSKP=250ns, *1
VCC=1.8V, tSKP=1.0µs, *1
VCC=5.5V, tSKP=250ns, *1
VCC=1.5V, tSKP=1.0µs, *1
Current Dissipation
(WRAL)
Current Dissipation
(READ)
Current Dissipation
(Standby)
ICCSB VCC=5.5V
*2
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
2.0
VCC + 0.5
V
V
V
V
V
V
V
VCC=5.0V±10%
Input High Voltage
0.8 x VCC VCC + 0.5
0.8 x VCC VCC + 0.5
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
VCC=5.0V±10%
-0.1
-0.1
-0.1
2.2
0.8
Input Low Voltage
0.15 x VCC
0.1 x VCC
1.8V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 1.8V
Output High Voltage VOH1
VCC=5.0V±10%
IOH=-0.4mA
VOH2
VOH3
0.8 x VCC
0.8 x VCC
V
V
2.5V ≤ VCC ≤ 5.5V
IOH=-0.1mA
1.5V ≤ VCC < 2.5V
IOH=-0.1mA
Output Low Voltage
VOL1
VOL2
VOL3
ILI
0.4
0.4
V
VCC=5.0V±10%
IOL=1.5mA
V
2.5V ≤ VCC ≤ 5.5V
IOL=1.0mA
0.4
V
1.5V ≤ VCC < 2.5V
IOL=0.1mA
Input Leakage
VCC=5.5V, VIN=5.5V
*3
±1.0
±1.0
µA
µA
Output Leakage
ILO
VCC=5.5V,
VOUT=5.5V, CS=GND
*1 : VIN=VIH/VIL, DO=Open
*2 : VIN=VCC/GND, CS=GND, DO=Open, PE=VCC/Open
*3 : CS, SK, DI pin
DAM06E-01
2005/10
- 12 -
ASAHI KASEI
[AK93C45C/55C/65C]
(2) A.C. ELECTRICAL CHARACTERISTICS
( 1.5V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
SK Cycle Time
Symbol
tSKP1
Condition
Min.
250
Max.
Unit
ns
2.5V ≤ VCC ≤ 5.5V
tSKP2
tSKW1
tSKW2
tCSS1
tCSS2
tCSH
1.0
100
400
80
1.5V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SK Pulse Width
CS Setup Time
CS Hold Time
Data Setup Time
200
0
tDIS1
tDIS2
tDIH1
tDIH2
tPD1
50
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
100
50
Data Hold Time
Output delay
100
60
*4
tPD2
300
Selftimed
Programming Time
tE/W
5
ms
1.6V ≤ VCC ≤ 5.5V
tCS1
tCS2
tCCH1
tCCH2
tSV1
60
200
60
ns
ns
ns
ns
ns
ns
ns
ns
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.6V ≤ VCC < 2.5V
2.5V ≤ VCC ≤ 5.5V
1.5V ≤ VCC < 2.5V
Min CS Low Time
SK HOLD Time
200
CS to Status Valid
125
300
75
tSV2
CS to Output High-Z
tOZ1
tOZ2
100
E/W
Endurance
*5
1,000,000
cycles/
Address
5.5V, 25°C, PAGE WRITE
*4 : CL=100pF
*5 : This parameter is not tested to all samples.
DAM06E-01
2005/10
- 13 -
ASAHI KASEI
[AK93C45C/55C/65C]
Synchronous Data timing
CS
SK
DI
tCSS
tSKW
tSKW
tSKP
tDIS tDIH
1
0
tSV
Hi-Z
DO
AK93C45C/55C/65C output a logical "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
The Start of Instruction
CS
SK
DI
tCSH
tPD
tPD
tPD
tOZ
Hi-Z
D3
D2
D1
D0
DO
The End of Instruction
DAM06E-01
2005/10
- 14 -
ASAHI KASEI
[AK93C45C/55C/65C]
tCS
CS
SK
DI
tCSH
tCCH
tDIS tDIH
D1
D0
tSV
Hi-Z
Busy
Ready
DO
tE/W
Busy/Ready Signal Output
DAM06E-01
2005/10
- 15 -
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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