AK9844A [AKM]
4Kbit EEPROM with 4ch 8bit D/A Converter; 4k位EEPROM，带有4通道8位D / A转换器
| 型号： | AK9844A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 4Kbit EEPROM with 4ch 8bit D/A Converter |
| 文件： | 总17页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK9844A]
AK9844A
4Kbit EEPROM with 4ch 8bit D/A Converter
General Description
The AK9844A includes 4 channel, 8-bit D/A converters with on-chip output buffer amps and it is
capable to store the input digital data of each D/A converter by on-chip non-volatile CMOS
EEPROM. The AK9844A is optimally designed for various circuit adjustments for consumer and
industrial equipments and it is ideally suited for replacing mechanical trimmers.
Features
ꢀ EEPROM section
・4 word x 8-bit organization (Dedicated for DAC data)
・256 word x 16-bit organization (General purpose memory)
・Serial data interface
・Sequential register read
・Automatic write cycle
・100K write cycles
・10 year data retention
ꢀ D/A section
・4 channels
・Resolution
: 8-bits
・Differential Non-Linearity : ±1.0 LSB
・Linearity Error
: ±1.5 LSB
・Output Voltage Range
: GND to VCC
ꢀ AUTO READ Function
ꢀ Power down mode
SK CS
VREF1
Control Logic
Latch Decoder
PROTECT
DI
--
+
Instruction
Register
AO0
AO1
AO2
AO3
8
8
8
8
8bit Latch
8bit Latch
8bit Latch
8bit D/A
8bit D/A
8bit D/A
Data
--
+
Register
DO
8
8
VCC
GND
--
+
EEPROM
4128bit
256 x 16bit
--
+
+ 4 x 8bit
8bit Latch
PD
8bit D/A
VREF2
Block Diagram
- 1 -
DAD05E-00
2005/03
ASAHI KASEI
[AK9844A]
Ordering Guide
AK9844AV
-40°C to +85°C
AK9844AV
16-pin TSSOP
Pin Layout
GND
1
2
3
4
5
6
7
8
16
DI
PROTECT
PD
15
14
13
12
11
10
9
DO
SK
VCC
CS
NC
NC
VREF1
AO0
VREF2
AO3
AO2
AO1
16pin TSSOP
Pin Description
No.
1
Pin Name I/O
Function
GND
-
Ground Pin, 0V
Protect Pin
2
3
PROTECT
I
"L" : Programming to the D/A Section of EEPROM is
disabled.
"H" : Normal operation
PD
I
Power-down Pin
"L" : Power down mode
"H" : Normal mode
4
6
VCC
-
I
Power Supply
VREF1
Voltage Reference Input1
The analog output ranges of the AO0 and the AO1 are
set by the VREF1 pin.
7
8
9
AO0
AO1
AO2
AO3
O
I
Analog Output Pins (8-bit D/A outputs)
10
11
VREF2
Voltage Reference Input1
The analog output ranges of the AO2 and the AO3 are
set by the VREF2 pin.
13
14
15
16
CS
SK
DO
DI
I
I
Chip Select Pin
(Schmitt-trigger input)
(Schmitt-trigger input)
Serial Clock Pin
O
I
Serial Data Output Pin
Serial Data Input Pin
Not Connected
5, 12 NC
-
DAD05E-00
2005/03
- 2 -
ASAHI KASEI
[AK9844A]
Functional Description
The AK9844A includes the EEPROM section and the D/A converter section which consists of 4
channel, 8bit D/A converters with output buffer amps. The EEPROM section is divided into
memory block and DAC register block. The capacity of the memory block is 4096bits which are
organized into 256 registers of 16bits each. The DAC digital input data for D/A converters are
stored in the DAC register block which is organized into 4 registers of 8bits each. The address for
the memory block is "000000000" to "011111111". The address for the DAC register is
"100000000" to "100000011".
The configuration of the EEPROM section is showed on figure.1.
The AK9844A can connect to the serial communication port of popular one chip microcontrollers
directly (3 line negative clock synchronous interface). At write operation, the AK9844A takes in the
write data from the DI pin to a register synchronously with rising edge of the SK pin. At read
operation, the AK9844A takes out the read data from a register to the DO pin synchronously with
falling edge of the SK pin.
The AK9844A has 6 instructions such as READ, WRITE, WREN, WRDS, PDEN and PDDS. The
each instruction is organized by op-code block(8bits), address block(8bits), and data(8bits x 2).
The output of DAC is set by storing the DAC digital input data in the DAC register block.
The DO pin is high impedance except that the DO pin outputs the read data and the status signal.
000000000
$000
Memory Block
011111111
100000000
$0FF
$100
100000000
100000001
100000010
100000011
$100
$101
$102
$103
Digital input data
for DAC (A00)
DAC Register Block
100000011
$103
Digital input data
for DAC (A01)
Digital input data
for DAC (A02)
Digital input data
for DAC (A03)
Figure 1. Configuration of the EEPROM section
DAD05E-00
2005/03
- 3 -
ASAHI KASEI
[AK9844A]
Data Protection
To protect against accidental data disturb, the AK9844A has programming enable state and
programming disable state. In programming disable state, the programming operation is not
executed.
When VCC is applied to the AK9844A, the AK9844A is powered up in the programming disable
mode. The programming instruction should be preceded by the WREN instruction. Once the
WREN instruction is executed, the programming state remains enabled until the WRDS instruction
is executed or VCC is removed from the device. Execution of the READ instruction is independent
of both WREN and WRDS instructions.
The AK9844A also can prohibit to program into the DAC register block by the control of the
PROTECT pin. When the PROTECT pin is "L", the programming into the DAC register block is not
executed.
PROTECT pin
Programming State
Memory Block
PROTECT="H"
PROTECT="L"
Enable
Disable
×
Enable
Disable
×
○
○
○
×
DAC Register Block
×
×
○: Programming into the block is executed.
×: Programming into the block is not executed.
Table 1. Relation between the programming operation and the PROTECT pin
DAD05E-00
2005/03
- 4 -
ASAHI KASEI
[AK9844A]
Output of D/A converter
The AK9844A includes 4 channel, 8bit D/A converter. The output voltage ranges for AO0 and AO1
are set by the VREF1 pin and the output voltage ranges for AO2 and AO3 are set by the VREF2 pin.
The output voltage can be set by the READ or WRITE instruction.
When the DAC register block is specified in the WRITE instruction, the output voltage for the
specified D/A converter is set. When the WRITE instruction is executed in case that the PROTECT
pin is "H" and the programming state is enabled, the output voltage for the specified D/A converter is
set and the specified address in the DAC register block in EEPROM is written with the data
specified in the instruction.
When the WRITE instruction is executed in case that the PROTECT pin is "H" and the programming
state is disabled, the output voltage for the specified D/A converter is set and the specified address
in the DAC register block in EEPROM is not written with the data specified in the instruction. When
the WRITE instruction is executed in case that the PROTECT pin is "L", the output voltage for the
specified D/A converter is not set and the specified address in the DAC register block in EEPROM is
not written with the data specified in the instruction. The relation between the WRITE instruction
and the DAC register block is showed on the Table 2.
When the DAC register block is specified in the READ instruction, the output voltage for the
specified D/A converter is set by the data which is stored in the DAC register block in EEPROM, and
the DO pin outputs the data in the specified address.
Execution of the READ instruction is independent of the PROTECT pin and the programming state.
PROTECT
pin
Programming
State
DAC register block
(EEPROM section)
Output of DAC
(D/A Converter section)
The specified address in the
DAC register block is written
with the data specified in the
instruction.
The output voltage for the
specified D/A converter is set
by the data specified in the
instruction.
Enable
"H"
"L"
Disable
Enable
Disable
The data in the DAC register
section does not change.
The output of the DAC does
not change.
Table 2. Relation between the WRITE instruction and the DAC register block
○ AUTO READ Function
When VCC is applied to the AK9844A, the data on EEPROM are read out and loaded at a time to
each corresponding D/A (4 channels total) automatically, starting from AO0 to AO3 in ascending
order. Then each D/A analog output is settled to pre-determined value.
If the CS pin goes to "H" and then goes to "L" after "power-up" with the PROTECT pin and the CS
pin left "L", AUTO READ cycle is initiated. After the CS pin goes to "L", 4 channel D/A outputs are
settled to pre-determined value within 2ms.
In AUTO READ cycle, the SK pin and the DI pin become "don't care" and the serial data do not
output.
If the WREN instruction is executed after AUTO READ cycle is completed, programming into the
memory block on the internal EEPROM is enabled.
DAD05E-00
2005/03
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ASAHI KASEI
[AK9844A]
Instruction and Data Format
The instructions consist of op-code(8bits), address(8bits) and data(8bits x 2). The followings are
the instruction and data set at WRITE execution.
First
MSB
Last
LSB
1
0
1
0
0
1
0
A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12
D2 D1 D0
Op-code
Address
Function
A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Memory Block
0
1
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
Data for A00
Data for A01
Data for A02
Data for A03
DAC Register Block
Data
D/A Output Voltage
( VREF / 256 ) x1
( VREF / 256 ) x2
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
≒
≒
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
( VREF / 256 ) x255
VREF
≒
≒
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DAD05E-00
2005/03
- 6 -
ASAHI KASEI
[AK9844A]
Power Down Function
There are the power down mode and the normal mode in AK9844A. When the AK9844A is in
power down mode, the outputs of D/A are "High impedance" and the DAC section is in the standby
mode and the power consumption of the AK9844A is decreased.
The power down mode of AK9844A can be determined by the control of the PD pin or the
PDEN/PDDS instructions.
When the PD pin is low level, the AK9844A is in power down mode. When the PD pin is high level,
the state of the AK9844A can be determined by PDEN/PDDS instructions. When the PD pin is
High level and the PDEN instruction is executed, the AK9844A becomes the power down mode.
Once the AK9844A becomes the power down mode, the AK9844A is in the power down mode until
the PDDS instruction is executed. When the PDDS instruction is executed, the AK9844A becomes
the normal mode.
If the CS pin is High level in the power down mode, the EEPROM section also becomes the standby
mode and the AK9844A becomes the lower power-down mode.
The relation between the PD pin and the PDEN/PDDS instructions is showed on Table 3. The
relation between the power down mode and the DAC/EEPROM section is showed on Table 4. The
state at the time AK9844A is powered up is showed on Table 5.
PD pin
instruction
PDEN
PDDS
mode
Low level
power down mode
PDEN
PDDS
power down mode
normal mode
High level
Table 3. Relation between the PD pin and the PDEN/PDDS instructions
State
DAC section
normal mode
standby mode
standby mode
EEPROM section
normal mode
normal mode
normal mode
power down mode1 CS pin="L"
power down mode2 CS pin="H"
standby mode
Table 4. Relation between the power down mode and the DAC/EEPROM section
Condition at the time AK9844A is powered on
State
CS pin="L"
CS pin="H" power down mode2
normal mode
power down mode1
PD pin="L"
PD pin="H"
Table 5. State at the time AK9844A is powered up
Precautions for use
1) Output voltage of D/A converter at the time the AK9844A is powered up
At the time the AK9844A is powered up, the D/A converters output "VREF/2" until the instruction
or AUTO READ is executed.
2) Power Supply Decoupling
On the boards, decoupling capacitors(0.1µF) between power supply pins(VCC,VREF1,VREF2)
and GND should be located as near as possible to the part.
DAD05E-00
2005/03
- 7 -
ASAHI KASEI
[AK9844A]
Instruction Set
The AK9844A has 6 instructions such as READ, WRITE, WREN, WRDS, PDEN, PDDS. Each
instruction consists of Op-code, address and data. The instruction set is showed on Table 6.
When the instructions are executed consecutively, the CS pin should be brought to high level for a
minimum of 250ns(tCS) between consecutive instruction cycle.
Instruction Op-code
Data
Comments
Address
READ
WRITE
WREN
WRDS
PDEN
PDDS
1010100
1010010
1010001
1010000
1010110
1010011
A8
A8
1
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
D15-D0
Read register
D15-D0
Write register
X
X
X
X
Write enable
0
Write disable
0
Power down enable
Power down disable
0
X: Don't care
Table 6. Instruction set
WRITE
The WRITE instruction is followed by 16 bits of data to be written into the specified address. After
the 32nd rising edge of SK to read DO in, the AK9844A will be put into the automatic write time-out
period. During the automatic write time-out period (Busy status), the CS pin need not be high level.
The DO pin indicates the Ready/Busy status of the EEPROM in AK9844A. After the 32nd rising
edge of SK to read DO in, the AK9844A will be put into the automatic write time-out period. When
the automatic write time-out period start, the DO pin outputs the Ready/Busy status. When the DO
pin outputs low level, the AK9844A is in the automatic write time-out and the next instruction can not
be accepted. When the DO pin outputs high level, the automatic write time-out period has ended
and the AK9844A is ready for a next instruction.
When the CS pin is changed to high level after confirmation of Ready/Busy signal on the DO pin,
the DO pin becomes "Hi-Z". The Ready/Busy signal can be confirmed until the initial 1 bit of the
next instruction inputs from the execution of the WRITE instruction.
CS
1
1
2
0
3
1
4
0
5
0
6
1
7
0
8
9
10 11 12 13 14 15 16 17 18 19
31 32
D1 D0
SK
DI
D15D14D13
A8 A7 A6 A5 A4 A3 A2 A1 A0
Hi-Z
BUSY
tE/W
DO
READY
Status output (READY),
if previous instruction is WRITE.
WRITE instruction
DAD05E-00
2005/03
- 8 -
ASAHI KASEI
[AK9844A]
READ
The read instruction is the only instruction which outputs serial data on the DO pin.
After a read instruction is received, the instruction and address are decoded, followed by data
transfer from the memory register into a 16 bit serial-out shift register. When the 17th falling edge
of SK is received, the DO pin will come out of high impedance state and shift out the data from D15
first in descending order which is located at the address specified in the instruction.
○ Sequential register read
The data in the next address can be read sequentially to provide clock. The memory
automatically cycles to the next register after each 16 data bits are clocked out.
The sequential register read function is effective for address: A7~A0. When the highest address
is reached ($0FF/$103), the address counter rolls over to address $000/$100 allowing the read
cycle to be continued indefinitely.
CS
1
1
2
0
3
1
4
0
5
1
6
0
7
0
8
9
10 11 12 13 14 15 16 17 18 19
31 32 33 34 35
SK
DI
A8 A7 A6 A5 A4 A3 A2 A1 A0
Hi-Z
Hi-Z
D15D14D13
D1 D0 D15D14D13
2nd Data
DO
Status output (READY),
if previous instruction is WRITE.
1st Data
READ instruction
WREN / WRDS
When VCC is applied to the part, it powers up in the programming disable(WRDS) state.
Programming must be preceded by a programming enable(WREN) instruction. Programming
remains enabled until a programming disable(WRDS) instruction is executed or VCC is removed
from the part. The programming disable instruction is provided to protect against accidental data
disturb. Execution of a read instruction is not affected by both WREN and WRDS instruction.
CS
1
1
2
0
3
1
4
0
5
0
6
0
7
8
9
10 11 12 13 14 15 16 17
SK
DI
X
X
X
X
X
X
X
X
WREN=11
WRDS=00
Hi-Z
DO
Status output (READY),
if previous instruction is WRITE.
WREN / WRDS instruction
DAD05E-00
2005/03
- 9 -
ASAHI KASEI
[AK9844A]
PDEN / PDDS
The AK9844A has the power-down mode and the normal mode. When the PDEN instruction is
executed while the PD pin is high level, the AK9844A becomes the power-down mode. The
AK9844A is in the power-down mode until PDDS instruction is executed. After the PDDS
instruction is executed, the AK9844A changed to normal mode from power-down mode.
In case that the PD pin is low level, the PDEN/PDDS instructions are invalid and are not executed.
CS
1
1
2
0
3
1
4
0
5
1
6
1
7
0
8
9
10 11 12 13 14 15 16 17
SK
DI
0
X
X
X
X
X
X
X
X
Hi-Z
DO
Status output (READY),
if previous instruction is WRITE.
PDEN instruction
CS
SK
DI
1
1
2
0
3
1
4
0
5
0
6
1
7
1
8
9
10 11 12 13 14 15 16 17
0
X
X
X
X
X
X
X
X
Hi-Z
DO
Status output (READY),
if previous instruction is WRITE.
PDDS instruction
DAD05E-00
2005/03
- 10 -
ASAHI KASEI
[AK9844A]
Absolute Maximum Ratings
Parameter
Power Supply
Input Voltage
Ambient Temperature
Storage Temperature
Symbol
VCC
VIO
Condition
Relative to GND
Relative to GND
Min
-0.6
-0.6
-40
Max
+7.0
VCC+0.6
+85
Unit
V
V
°C
°C
Ta
Tst
-65
+150
Recommended Operating Condition
Condition
DAC operation
EEPROM operation
Parameter
Power Supply
Symbol
VCC1
VCC2
AOC
Min
2.7
1.8
Typ
Max
5.5
5.5
Unit
V
V
Analog Output
100
pF
Load Capacitance
DAD05E-00
2005/03
- 11 -
ASAHI KASEI
[AK9844A]
Electrical Characteristics
D.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, GND=0V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
Symbol
IDD1
Condition
Min.
Typ.
Max.
6.5
Unit
mA
Normal mode
WRITE, 1/tSKP=2MHz
Power Consumption
IDD2
IDD3
Normal mode
READ, 1/tSKP=2MHz
3.3
mA
mA
Power down mode1
READ, 1/tSKP=2MHz
0.75
0.8
(Note1, Note2)
IDD4
VIH1
Power down mode2
µA
Input High Voltage1
CS, SK, PROTECT pin
0.8xVCC
V
Input High Voltage2
PD, DI pin
VIH2
VIH3
VIL1
0.7xVCC
0.8xVCC
V
V
V
2.2V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.2V
Input Low Voltage1
0.2xVCC
CS, SK, PROTECT pin
Input Low Voltage2
PD, DI pin
VIL2
VIL3
VOH
VOL1
0.3xVCC
0.2xVCC
V
V
V
V
2.2V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.2V
IOH=-50µA
Output High Voltage
Output Low Voltage
VCC-0.3
0.4
0.4
2.2V ≤ VCC ≤ 5.5V
IOL=1.0mA
VOL2
V
1.8V ≤ VCC < 2.2V
IOL=0.1mA
µA
µA
Input Leakage
ILI
VIN=VCC
CS="H"
±1.0
±1.0
3 State Leakage
Current
IOZ
Note1: VCC=5.5V, VIN=VCC/GND, DO=OPEN
Note2: Please refer to "Power Down Function" regarding power down mode.
DAD05E-00
2005/03
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ASAHI KASEI
[AK9844A]
A.C. ELECTRICAL CHARACTERISTICS
1) EEPROM section
( 1.8V ≤ VCC ≤ 5.5V, GND=0V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
SK Cycle Time
tSKP1
500
ns
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V
tSKP2
tSKW1
tSKW2
tSKH1
tSKH2
1.5
250
750
250
500
750
100
100
µs
ns
ns
ns
ns
ns
ns
ns
SK Pulse Width
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V
4.0V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.0V
1.8V ≤ VCC < 2.5V
SK High Pulse Width
(Note3) tSKH3
tCSS
CS Setup Time
CS Hold Time
tCSH1
READ, WREN, WRDS,
PDEN, PDDS
tCSH2
tSKS
WRITE
(Note4)
1000
100
100
150
200
100
150
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SK Setup Time
tDIS1
4.0V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.0V
1.8V ≤ VCC < 2.5V
4.0V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.0V
1.8V ≤ VCC < 2.5V
4.0V ≤ VCC ≤ 5.5V
2.5V ≤ VCC < 4.0V
2.2V ≤ VCC < 2.5V
1.8V ≤ VCC < 2.2V
Data Setup Time
tDIS2
tDIS3
tDIH1
tDIH2
tDIH3
tPD1
tPD2
tPD3
Data Hold Time
150
250
300
500
Data Output Delay
(READ)
(Note5) tPD4
Data Output Delay
(RDY/BUSY) (Note5)
tPD
1000
ns
Selftimed
Programming Time
tE/W1
tE/W2
tRC
7
ms
ms
ns
2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V
10
Write Recovery Time
Min CS High Time
DO High-Z Time
100
250
tCS
ns
tOZ
500
ns
Note3: tSKH is the high pulse width of 16th SK pulse in READ operation. When the
data in the next address are read sequentially by continuing to provide clock,
tSKH are applied to the high pulse width of 32nd and 48th (multiple of 16) SK
pulse in READ operation.
Note4: In case that the data of the DAC section is not changed and the output of the DAC
is changed, tCSH is min. 1µs. In case of the other WRITE instruction, tCSH is
min. 100ns.
Note5: CL=100pF
DAD05E-00
2005/03
- 13 -
ASAHI KASEI
[AK9844A]
2) DAC section
( 2.7V ≤ VCC ≤ 5.5V, GND=0V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
D/A Reference Voltage
A0, A1
A2, A3
D/A Reference Current
Resolution
Differential Non-Linearity DNL
Integral Non-Linearity
(Note7)
VREF1
VREF2
IREF
2.7
2.7
VCC
VCC
400
8
+1
+1.5
V
V
µA
bit
LSB
LSB
VREF=5.0V
200
Monotonicity
VCC=VREF=5.0V
1LSB=VREF/256
IAO=0.0µA
-1
-1.5
0
0
NL
Error for Input data "00"
(Note6)
Error for Input data "FF"
(Note6)
EZERO
EFULL
+0.1
+0.1
V
V
CL=100pF
Buffer-AMP Output
Voltage Range(1)
3.6V ≤ VCC ≤ 5.5V
(Note8)
Buffer-AMP Output
Voltage Range(2)
2.7V ≤ VCC < 3.6V
Setup Time in
VAO1
VAO2
VAO3
VAO4
0.1
0.2
0.3
0.1
VCC-0.1
VCC-0.2
VCC-0.3
VCC-0.1
V
V
V
V
|IAO| = 0µA
|IAO| ≤ 200µA
|IAO| ≤ 1mA
|IAO| = 0µA
VAO5
tARS
0.3
VCC-0.3
V
|IAO| ≤ 500µA
500
µs
AUTO READ
D/A Settling Time
(CL=100pF)
tLDD1
tLDD2
100
200
400
3.6V ≤ VCC ≤ 5.5V
2.7V ≤ VCC < 3.6V
µs
µs
Note6: Please refer to the Figure 2.
Note7: Integral Non-Linearity is the error between the actual line and the ideal line. The
ideal line exhibits a perfect linear DAC output characteristics between the input
digital data "00" and the input digital data "FF".
Note8: VCC=VREF
* Please refer to "Instruction and Data Format" regarding the relation between input digital data
and DAC output voltage.
DAC Output Voltage
5.0V
VCC=VREF=5V
CL=100pF
5.0V
EFULL
EZERO
00
FF
00
FF
Input digital data
Figure 2. DAC output characteristics (IAO=0.0µA)
DAD05E-00
2005/03
- 14 -
ASAHI KASEI
[AK9844A]
Timing Waveform
tCS
tCSS
tSKP
CS
SK
DI
tSKS
tSKW
tSKW
tDIS tDIH
0
1
1
tRC
Hi-Z
DO
Input Waveform
CS
tSKH
tCSH
16
SK
DI
A0
tPD
tOZ
D15
D2
D1
D0
DO
tLDD
D/A
Waveform in READ instruction
DAD05E-00
2005/03
- 15 -
ASAHI KASEI
[AK9844A]
CS
SK
DI
tCSH
D2
D1
D0
tLDD
D/A
Programming Waveform in WRITE instruction
CS
SK
DI
D0
tPD
tE/W
tOZ
BUSY
READY
DO
tLDD
D/A
Status Output
(Note) In case that the data of the DAC section is not changed and the output of the DAC is
changed, Ready/Busy signal does not output on DO pin.
VCC
tARS
min. 2ms
CS
PROTECT
AO0
(D/A OUT)
:
AO3
(D/A OUT)
Waveform in AUTO READ
- 16 -
DAD05E-00
2005/03
IMPORTANT NOTICE
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