AKD4120 [AKM]
Sample Rate Converter with Mixer and Volume; 采样率转换器与混频器和卷
| 型号： | AKD4120 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Sample Rate Converter with Mixer and Volume |
| 文件： | 总30页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AK4120]
AK4120
Sample Rate Converter with Mixer and Volume
GENERAL DESCRIPTION
The AK4120 is a stereo asynchronous sample rate converter. The input sample rate range is from 8kHz
to 48kHz. The output sample rate is fixed at 32kHz, 44.1kHz, 48kHz or 96kHz. AK4120 includes a
digital mixer and digital volume control. Applications for this device include pro audio mastering,
consumer format conversion and desktop audio production and playback.
FEATURES
o Stereo Asynchronous Sample Rate Converter
o Digital Mixer
o Digital Volume
o Input Sample Rate Range (FSI): 8kHz to 48kHz
o Output Sample Rate (FSO): 32kHz, 44.1kHz, 48kHz and 96kHz
o Input to Output Sample Rate Ratio: FSO/FSI = 0.667 to 6
o THD+N: –113dB at 1kHz input
o I/F format: MSB justified (20bit), LSB justified (16bit/20bit), I2S
o Master clock: 256/512fs
o 3-wire Serial or I2C Bus µP I/F for mode setting
o Power Supply: 2.7 to 3.6V
I2S
I2C
PDN
VDD
VSS
SDTI1
ILRCK1
IBICK1
Input#1
Audio
I/F
Sample
Rate
Converter
Volume#1
TEST
IMCLK1
IMCLK2
OMCLK
SDTI2
ILRCK2
IBICK2
SDTO
Input#2
Audio
I/F
Output
Audio
I/F
Volume#2
OLRCK
OBICK
m P I/F
I2MODE
CAD0
CSN/CAD1
CDTI/SDA
OMODE
CCLK/SDL
MS0134-E-00
2002/1
- 1 -
ASAHI KASEI
[AK4120]
n Ordering Guide
AK4120VF
AKD4120
-40 ~ +85°C
24pin VSOP (0.65mm pitch)
Evaluation Board for AK4120
n Pin Layout
IMCLK1
SDTI1
IBICK1
ILRCK1
TEST
I2S
1
2
24
23
22
21
20
19
18
17
16
15
14
13
IMCLK2
SDTI2
3
IBICK2
ILRCK2
I2MODE
VDD
4
5
6
Top
View
I2C
7
VSS
CAD0
8
OMODE
OMCLK
SDTO
CSN/CAD1
9
CCLK/SCL
CDTI/SDA
PDN
10
11
12
OBICK
OLRCK
MS0134-E-00
2002/1
- 2 -
ASAHI KASEI
[AK4120]
PIN/FUNCTION
No.
1
2
Pin Name
I/O
Function
IMCLK1
SDTI1
I
I
I
Master Clock Input Pin for Input#1
Audio Serial Data Input Pin for Input#1
Audio Serial Data Clock Pin for Input#1
3
IBICK1
4
5
ILRCK1
TEST
I
I
L/R Clock Pin for Input#1
Test Pin. Connect to VSS.
Audio I/F Select Pin
6
I
I2S
“L”: Set by Register, “H”: I2S
I2C Select Pin. “L”: 3-wire, “H”: I2C
7
8
I2C
I
I
I
I
CAD0
CSN
Chip Address 0 Pin
Chip Select Pin in 3wire serial control mode in 3-wire Serial Control Mode.
Chip Address 1 Pin in I2C control mode.
Control Data Clock Pin in 3wire serial control mode in 3-wire Serial Control
Mode.
Control Data Clock Pin in I2C control mode.
Control Data Input Pin in 3wire serial control mode in 3-wire Serial Control
Mode.
Control Data Pin in I2C serial control mode in I2C control mode.
Power-Down pin
When “L”, the AK4120 is powered-down and reset.
L/R Clock Pin for Output
Audio Serial Data Clock Pin for Output
Audio Serial Data Pin for Output
9
CAD1
CCLK
SCL
I
I
10
CDTI
SDA
PDN
I
11
12
I/O
I
13
14
15
16
OLRCK
OBICK
SDTO
I/O
I/O
O
OMCLK
I
Master Clock Pin for Output
Master/Slave select pin for Output Audio Data
17
OMODE
I
“L”: Slave,
“H”: Master
18
19
VSS
I
I
Digital Ground Pin
VDD
Digital Power Supply Pin, 3.3V
Master/Slave select pin for Input Audio Data #2
20
I2MODE
I
“L”: Slave,
“H”: Master
21
22
23
24
ILRCK2
IBICK2
SDTI2
I/O
I/O
I
L/R Clock Pin for Input#2
Audio Serial Data Clock Pin for Input#2
Audio Serial Data Input Pin for Input#2
Master Clock Input Pin for Input#2
IMCLK2
I
MS0134-E-00
2002/1
- 3 -
ASAHI KASEI
[AK4120]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Power Supplies
Parameter
Symbol
VDD
IIN
min
-0.3
-
max
Units
V
4.6
Input Current, Any Pin Except Supplies
Input Voltage
mA
V
±10
VDD+0.3
85
VIN
Ta
-0.3
-40
-65
Ambient Temperature (Power applied)
Storage Temperature
°C
°C
Tstg
150
Note 1: All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 2)
Parameter
Symbol
min
typ
max
Units
Power Supplies
Note 2: All voltages with respect to ground.
VDD
2.7
3.3
3.6
V
SRC PERFORMANCE
(Ta=-40~ 85°C; VDD = 2.7~3.6V; data = 20bit; measurement bandwidth = 20Hz~ FSO/2; unless otherwise specified.)
Parameter
Symbol
min
typ
max
20
Units
Bits
Resolution
Input Sample Rate (Note 3)
Output Sample Rate (Note 4)
FSI
FSO
8
32
48
96
kHz
kHz
Dynamic Range (Input= 1kHz, -60dBFS, Note 5)
FSO/FSI=44.1kHz/48kHz
-
-
-
115
116
114
119
-
-
-
-
-
-
dB
dB
dB
dB
dB
FSO/FSI=48kHz/44.1kHz
FSO/FSI=32kHz/48kHz
FSO/FSI=96kHz/32kHz
-
Worst Case (FSO/FSI=32kHz/48kHz)
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted, Note 5)
FSO/FSI=44.1kHz/48kHz
112
-
117
-
dB
THD+N
(Input= 1kHz, 0dBFS, Note 5)
FSO/FSI=44.1kHz/48kHz
FSO/FSI=48kHz/44.1kHz
FSO/FSI=32kHz/48kHz
-
-
-
-
-
-112
-113
-111
-111
-
-
-
-
-
dB
dB
dB
dB
dB
FSO/FSI=96kHz/32kHz
Worst Case (FSO/FSI=48kHz/8kHz)
-103
Ratio between Input and Output Sample Rate
(FSO/FSI, Note 6, Note 7)
FSO/FSI
0.667
6
-
Note 3. 32kHz~96kHz for INPUT#2 at Path Mode 0. 8kHz~96kHz at Path Mode 2 and 3.
Note 4. Min = 8kHz at Path Mode 2 and 3.
Note 5. Measured by Rohde & Schwarz UPD04, Rejection Filter= wide, 8192point FFT. Refer Figure 1 and Figure 2.
Note 6. The “0.667” is the ratio of FSO/FSI when FSI is 48kHz and FSO is 32kHz
Note 7. The “6” is the ratio when FSI is 8kHz and FSO is 48kHz.
MS0134-E-00
2002/1
- 4 -
ASAHI KASEI
[AK4120]
-101
-103
-105
-107
-109
-111
-113
-115
32
37
42
47
FSI [kHz]
Figure 1: Input Sample Rate (FSI) vs. THD+N (FSO=48kHz)
-80
-85
-90
-95
-100
-105
-110
-115
-120
10
100
1000
10000
100000
Input Frequency [Hz]
Figure 2: Input Frequency vs. THD+N (FSI=44.1kHz, FSO=48kHz)
MS0134-E-00
2002/1
- 5 -
ASAHI KASEI
[AK4120]
DIGITAL FILTER
(Ta=-40 85 C; VDD=2.7 3.6V; FSO=FSI=fs)
~
°
~
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 8)
-0.001dB
(Note 8)
PB
SB
PR
SA
GD
0
0.4583fs
± 0.01
-
kHz
kHz
dB
dB
1/fs
0.5417fs
97
-
(Note 9)
56.5
Note 8. The passband and stopband frequencies scale with fs (system sampling rate).
Note 9. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is
output, when LRCK for Output data corresponds with LRCK for Input.(at 20bit MSB justified, 16bit and 20bit
LSB justified)
DC CHARACTERISTICS
(Ta=-40~85°C; VDD=2.7~3.6V)
Parameter
Power Supply Current
Symbol
min
typ
Max
Units
Normal operation: (PDN = “H”, Path Mode 0)
FSI=FSO=48kHz at Slave Mode
(I2MODE= OMODE = “L”): VDD=3.3V
FSI=48kHz,FSO=96kHz at Master Mode
(I2MODE=OMODE= “H”) : VDD=3.3V
: VDD=3.6V
8.5
-
mA
10.2
11.5
10
-
-
mA
mA
mA
V
20
100
-
Power down: PDN = “L”
High-Level Input Voltage
Low-Level Input Voltage
(Note 10)
VIH
VIL
0.7xVDD
-
-
0.3xVDD
V
VOH
VDD-0.4
-
-
V
High-Level Output Voltage
Low-Level Output Voltage
(Iout=-400mA)
VOL
VOL
Iin
-
-
-
-
-
-
0.4
0.4
V
V
(Except SDA pin: Iout=400mA);
SDA pin: Iout= 3mA)
Input Leakage Current
(
± 10
mA
Note 10. All digital inputs including clock pins are held VSS.
MS0134-E-00
2002/1
- 6 -
ASAHI KASEI
[AK4120]
SWITCHING CHARACTERISTICS
(Ta=-40~ 85°C; VDD=2.7~3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Input (IMCLK1)
Frequency
Duty Cycle (at FSI > 33kHz)
Duty Cycle (at FSI £ 33kHz)
Master Clock Input (IMCLK2)
Frequency
Duty Cycle (at FSI > 33kHz)
Duty Cycle (at FSI £ 33kHz)
Master Clock Input (OMCLK)
Frequency (Note 11)
Duty Cycle (at FSI > 33kHz)
Duty Cycle (at FSI £ 33kHz)
L/R clock for Input data #1 (ILRCK1)
Frequency
fCLK
dCLK
dCLK
2.048
40
28
24.576
60
72
MHz
%
%
fCLK
dCLK
dCLK
2.048
40
28
24.576
60
72
MHz
%
%
fCLK
dCLK
dCLK
8.192
40
28
24.576
60
72
MHz
%
%
fs
Duty
8
48
48
52
kHz
%
Duty Cycle
50
L/R clock for Input data #2 (ILRCK2)
Frequency
Duty Cycle
(Note 12)
Slave Mode
Master Mode
fs
Duty
Duty
8
48
96
52
kHz
%
%
50
50
L/R clock for Output data (OLRCK)
Frequency
Duty Cycle
(Note 13)
Slave Mode
Master Mode
fs
Duty
Duty
32
48
96
52
kHz
%
%
50
50
Audio Interface Timing
(Note 14)
Input#1 at Path Mode 0 and 2
Input#2 (Slave Mode) at Path Mode 1
BICK Period
BICK Pulse Width Low
BICK Pulse Width High
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
325
130
130
45
45
40
ns
ns
ns
ns
ns
ns
ns
LRCK Edge to BICK “• ”
BICK “• ” to LRCK Edge
(Note 15)
(Note 15)
SDTI1-2, Hold Time from BICK “• ”
SDTI1-2, Setup Time to BICK “• ”
Input#2 (Slave Mode) at Path Mode 0 and 3
BICK Period
BICK Pulse Width Low
BICK Pulse Width High
25
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
162
65
65
45
45
40
25
ns
ns
ns
ns
ns
ns
ns
LRCK Edge to BICK “• ”
BICK “• ” to LRCK Edge
(Note 15)
(Note 15)
SDTI2, Hold Time from BICK “• ”
SDTI2, Setup Time to BICK “• ”
Output (Slave Mode)
OBICK Period
OBICK Pulse Width Low
OBICK Pulse Width High
OLRCK Edge to OBICK “• ”
OBICK “• ” to OLRCK Edge
OLRCK to SDTO (MSB)
OBICK “¯” to SDTO
tBCK
tBCKL
tBCKH
tBLR
tLRB
tLRS
162
65
65
45
45
ns
ns
ns
ns
ns
ns
ns
(Note 15)
(Note 15)
40
40
tBSD
MS0134-E-00
2002/1
- 7 -
ASAHI KASEI
[AK4120]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing
Input#2(Master Mode) at Path Mode 1
BICK Frequency
BICK Duty
BICK “¯” to LRCK
BICK “¯” to SDTO
SDTI2 Hold Time from BICK “• ”
SDTI2 Setup Time to BICK “• ”
Input#2 (Master Mode) at Path Mode0 and 3
Output (Master Mode)
BICK Frequency
BICK Duty
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
64fs
50
Hz
%
ns
ns
ns
ns
- 25
- 25
50
25
40
50
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
64fs
50
Hz
%
ns
ns
ns
ns
- 20
- 20
40
20
30
BICK “¯” to LRCK
BICK “¯” to SDTO
SDTI2 Hold Time from BICK “• ”
SDTI2 Setup Time to BICK “• ”
Note 11. Min is 2.048MHz at Path Mode 2 and 3.
Note 12. Max is 48kHz at Path Mode 1
Note 13. Min is 8kHz at Path Mode 2 and 3.
25
Note 14. BICK means all audio serial data clocks (IBICK1, IBICK2 and OBICK).
LRCK means all L/R clocks (ILRCK1, ILRCK2 and OLRCK).
Note 15. BICK rising edge must not occur at the same time as LRCK edge.
MS0134-E-00
2002/1
- 8 -
ASAHI KASEI
[AK4120]
Parameter
Symbol
min
typ
max
Units
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “¯” to CCLK “• ”
tCSH
CCLK “• ” to CSN “• ”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
tBUF
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
100
-
-
-
-
-
-
-
kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
(Note 10)
1.0
0.3
-
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Maximum Pulse Width of Spike Noise Suppressed by
Input Filter
tF
tSU:STO
tSP
4.0
30
Power-down & Reset Timing
PDN Pulse Width
(Note 11)
tPD
150
ns
Note 10. Data must be held long enough to bridge the 300 ns transition time of SCL.
Note 11. The AK4120 can be reset by bringing PDN “L” to “H” upon power-up.
Note 12. I2C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips
I2C patent to use the components in the I2C system, provided the system conform to the I2C
specifications defined by Philips.
MS0134-E-00
2002/1
- 9 -
ASAHI KASEI
[AK4120]
n Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
VIL
LRCK
tBCK
VIH
VIL
BICK
tBCKH
tBCKL
Clock Timing
VIH
VIL
LRCK
BICK
SDTO
tBLR
tLRS
tLRB
VIH
VIL
tBSD
70%VDD
30%VDD
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing at Slave Mode
Note: MCLK means IMCLK1, IMCLK2 and OCLK.
BICK means IBICK1,IBICK2 and OBICK.
LRCK means ILRCK1,ILRCK2 and OLRCK.
SDTI means SDTI1 and SDTI2.
MS0134-E-00
2002/1
- 10 -
ASAHI KASEI
[AK4120]
LRCK
BICK
SDTO
SDTI
50%VDD
50%VDD
tMBLR
dBCK
tBSD
50%VDD
tSDS
tSDH
VIH
VIL
Audio Interface Timing at Master Mode
VIH
VIL
CSN
tCSS
tCCKL tCCKH
tCDS tCDH
VIH
VIL
CCLK
CDTI
VIH
VIL
C1
C0
R/W
A4
WRITE Command Input Timing (3-wire Serial mode)
tCSW
VIH
VIL
CSN
tCSH
VIH
VIL
CCLK
CDTI
VIH
VIL
D3
D2
D1
D0
WRITE Data Input Timing (3-wire Serial mode)
MS0134-E-00
2002/1
- 11 -
ASAHI KASEI
[AK4120]
VIH
VIL
SDA
SCL
tLOW tR
tHIGH
tBUF
tF
tSP
VIH
VIL
tHD:STA
tHD:DAT
tSU:DAT tSU:STA
Start
tSU:STO
Stop
Stop Start
I2C Bus mode Timing
tPD
VIH
PDN
VIL
tPDV
70%VDD
30%VDD
SDTO
Power-down & Reset Timing
MS0134-E-00
2002/1
- 12 -
ASAHI KASEI
[AK4120]
OPERATION OVERVIEW
n I/O Data flow
The AK4120 has two input audio data interfaces (Input#1 and Input#2). The AK4120 has four modes of operation, each
corresponding to a different internal audio path as shown in Table 1. These path modes are selected by the PATH1-0
bits.
Path Mode
0
(see Figure 3)
PATH1-0 bits
“00”
Output Data
The sample rate of Input#1 data is converted by SRC block. This converted
data paths through Volume#1 and Input#2 data is paths through Volume#2.
These data are mixed and this mixed data is output. The sample rata of
Input#1 is defined by IMCLK1 and the sample rate of Output data is
defined by OMCLK. The sample rate of Input#2 should be same as Output
data.
1
“01”
The sample rate of Input#2 data is converted by SRC block. This converted
data volume is controlled by Volume#1 and this data is output. The sample
rata of Input#2 is defined by IMCLK2 and the sample rate of Output data is
defined by OMCLK.
(see Figure 4)
2
“10”
“11”
Input#1 data paths through Volume#2 and is output. Output data should
synchronous with IMCLK.
Input#2 data paths through Volume#2 and is output. Input#2 should
synchronous with OMCLK.
(see Figure 5)
3
(see Figure 6)
Table 1. Path Mode
Note: When Path Mode is changed, the AK4120 should be powered down using the “PW” bit
MS0134-E-00
2002/1
- 13 -
ASAHI KASEI
[AK4120]
I2S
I2C
PDN
VDD
VSS
SDTI1
ILRCK1
IBICK1
Input#1
Audio
I/F
Sample
Rate
Converter
Volume#1
TEST
IMCLK1
IMCLK2
OMCLK
SDTI2
ILRCK2
IBICK2
SDTO
Input#2
Audio
I/F
Output
Audio
I/F
Volume#2
OLRCK
OBICK
m P I/F
I2MODE
CAD0
CSN/CAD1 CCLK/SDL CDTI/SDA
OMODE
Figure 3. Path Mode 0 (Input#1 SRC + Mixer)
I2S
I2C
PDN
VDD
VSS
SDTI1
ILRCK1
IBICK1
Sample
Rate
Converter
Volume#1
TEST
IMCLK1
IMCLK2
OMCLK
SDTI2
ILRCK2
IBICK2
SDTO
Input#2
Audio
I/F
Output
Audio
I/F
OLRCK
OBICK
m P I/F
I2MODE
CAD0
CSN/CAD1
CDTI/SDA
OMODE
CCLK/SDL
Figure 4. Path Mode 1 (Input#2 SRC)
MS0134-E-00
2002/1
- 14 -
ASAHI KASEI
[AK4120]
I2S
I2C
PDN
VDD
VSS
SDTI1
ILRCK1
IBICK1
Input#1
Audio
I/F
TEST
IMCLK1
IMCLK2
OMCLK
SDTI2
ILRCK2
IBICK2
SDTO
Input#2
Audio
I/F
Output
Audio
I/F
Volume#2
OLRCK
OBICK
m P I/F
I2MODE
CAD0
CSN/CAD1
CDTI/SDA
OMODE
CCLK/SDL
Figure 5. Path Mode 2 (Input#1 through output)
I2S
I2C
PDN
VDD
VSS
SDTI1
ILRCK1
IBICK1
TEST
IMCLK1
IMCLK2
OMCLK
SDTI2
ILRCK2
IBICK2
SDTO
Input#2
Audio
I/F
Output
Audio
I/F
Volume#2
OLRCK
OBICK
m P I/F
I2MODE
CAD0
CSN/CAD1
CDTI/SDA
OMODE
CCLK/SDL
Figure 6. Path Mode 3 (Input#2 through output)
MS0134-E-00
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- 15 -
ASAHI KASEI
[AK4120]
n System Clock
The external clocks required to operate the AK4120 in each mode are shown in Table 3 and Table 4. The Input#1 port
works in slave mode only. The Input#2 and Output ports have both slave and master modes that are selected by the
IMODE2 and OMODE pins. The required external clock shown in Table 2 should be always present whenever the
AK4120 is in a normal operating mode (PDN=”H”).
Path Mode
Synchronizing
Group A
SRC
Synchronizing
Group B
(Not used)
0
1
2
3
SDTI1
SDTI2
SDTI1, SDTO
SDTI2, SDTO
Active
Active
(Not used)
(Not used)
SDTI2, SDTO
-
SDTO
SDTI1
SDTI2
SDTI1
-
-
Table 2. Clock Synchronization
Path Mode
IMCLK1
Input
(Not used)
Input
IMCLK2
(Not used)
Input
(Not used)
(Not used)
OMCLK
Input
Input
(Not used)
Input
0
1
2
3
(Not used)
Table 3. Master Clock
Path Mode
ILRCK1,
ILRCK2, IBICK2
OLRC, OBICK
IBICK1
I2MODE = “L” I2MODE = “H”
OMODE= “L”
OMODE= “H”
0
1
2
3
Input
(Not used)
Input
(Not used)
Input
(Not used)
(Not used)
Output
Output
(Not used)
Output
Input
Input
(Not used)
Input
Output
Output
Output
Output
(Not used)
Table 4. LRCK/BICK
(1) Path Mode 0
IMCLK1 does not need to be synchronized with OMCLK when using Path Mode 1. IMCLK1 should be synchronized
with ILRCK1 (clock phase is not important). STDI2 should be synchronized with OLRCK and OBICK. When the
output is slaved, OMCLK should be synchronized with OLRCK (clock phase is not important). When input#2 is in
slave mode, OLRCK and OBICK are used while ILRCK2 and IBICK2 are not.
(2) Path Mode 1
IMCKL2 does not need to be synchronized with OMCLK. When Input#2 port is in slave mode, IMCLK2 should be
synchronized with ILRCK2 (clock phase is not important). When Output#2 port is in slave mode, OMCLK should be
synchronized with OLRCK (clock phase is not important).
(3) Path Mode 2
IMCLK1 should be synchronized with ILRCK1 (clock phase is not important). SDTO should be synchronized with
ILRCK1 and IBICK1. When the Output is in slave mode, the OLRCK and OBICK pins are not used. In master mode,
ILRCK1 is output through OLRCK and IBICK1 is output through OBICK.
(4) Path Mode 3
OMCLK should be synchronized with OLRCK (clock phase is not important). SDTI2 should be synchronized with
OLRCK and OBICK. When Input#2 is in slave mode, ILRCK2 and IBICK2 pins are not used. In master mode, OLRCK
is output through ILRCK2 and OBICK is output through IBICK2.
MS0134-E-00
2002/1
- 16 -
ASAHI KASEI
[AK4120]
The frequency of IMCLK1, IMCLK2, and OMCLK are fixed based on the sampling rate and clock speed (256fs/512fs).
IMCKS1, IMCKS2 and OMCKS bits in register 01H select clock speed.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96kHz
MCLK (MHz)
BICK (MHz)
64fs
256fs
512fs
16.384
22.5792
24.576
N/A
8.1920
11.2896
12.2880
22.5792
24.5760
2.0480
2.8224
3.0720
5.6448
6.1440
N/A
Table 5. System Clock Example
n Volume
AK4120 has two digital volumes (Volume#1 and Volume#2). Volume#1 can control the volume level of data from
Input#1 while in Path Mode 0 or from Input#2 while in Path Mode 1. It then passes this data through SRC block.
Volume#2 can control the volume level of data from Input#2 while in Path Mode 0 and Path Mode 3, or from Input#1
in Path Mode 2. These volume ranges are from –83.25dB to 12dB in 0.75dB steps. The volume level and mute of each
channel can be controlled by register 3-6H.
MS0134-E-00
2002/1
- 17 -
ASAHI KASEI
[AK4120]
n Audio Serial Interface Format
Four serial data modes can be selected by the I2S pin and D5-D0 bits in register 00H as shown in Table 6~8. In all
modes the serial audio data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of
BICKO and the SDTI1 and SDTI2 are latched on the rising edge of BICKI1 and BICKI2.
I2S pin
DIFI11
DIFI10
SDTI1
20bit, MSB justified
20bit, I2S
20bit, LSB justified
16bit, LSB justified
20bit, I2S
LRCK
H/L
L/H
H/L
H/L
L
L
L
L
H
0
0
1
1
X
0
1
0
1
X
Default
Default
Default
L/H
Table 6. Audio data formats for Input#1 port
I2S pin
DIFI21
DIFI20
SDTI2
20bit, MSB justified
20bit, I2S
LRCK
H/L
L/H
H/L
H/L
L
L
L
L
H
0
0
1
1
X
0
1
0
1
X
20bit, LSB justified
16bit, LSB justified
20bit, I2S
L/H
Table 7. Audio data formats for Input#2 port
I2S pin
DIFO1
DIFO0
SDTO
20bit, MSB justified
20bit, I2S
LRCK
H/L
L/H
H/L
H/L
L
L
L
L
H
0
0
1
1
X
0
1
0
1
X
20bit, LSB justified
16bit, LSB justified
20bit, I2S
L/H
Table 8. Audio data formats for Output port
Note: When the Audio Serial Interface Mode is changed, the AK4120 should be powered down using the PW bit.
(“PW”=0)
MS0134-E-00
2002/1
- 18 -
ASAHI KASEI
[AK4120]
LRCK
0
1
12
13
14
15
16
31
0
1
12
13
14
15
16
31
0
1
BICK
(64fs)
SDTI
16bit
Don’t care
15:MSB, 0:LSB
19 18
19:MSB, 0:LSB
15
0
0
Don’t care
Don’t care
15
0
0
SDTI
20bit
19 18
Don’t care
17 16 15
17 16 15
Lch Data
Rch Data
Figure 7. LSB justified Timing
LRCK
0
1
2
18
19
20
30
31
0
1
2
18
19
20
30
31
0
1
BICK
(64fs)
SDTI
19 18
1
0
Don’t care
19 18
1
0
Don’t care
19 18
20:MSB, 0:LSB
Lch Data
Figure 8. MSB justified Timing
Rch Data
LRCK
0
1
2
3
19
20
21
31
0
1
2
3
19
20
21
31
0
1
BICK
(64fs)
SDTI
0
1
19 18
19:MSB, 0:LSB
Don’t care
19 18
1
0
Don’t care
19
Lch Data
Rch Data
Figure 9. I2S Timing
MS0134-E-00
2002/1
- 19 -
ASAHI KASEI
[AK4120]
n Serial Control Interface
The AK4120 is controlled via registers. Internal registers can be written using one of two control modes, I2C or 3-wire,
that are selected via I2C pin. PDN = “L” initializes the registers to their default values. When the I2C pin is changed,
the AK4120 should be reset using the PDN pin.
* When PDN= “L”, internal registers cannot be written.
* The AK4120 does not support the read command while using the 3-wire Serial Control Mode.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal registers may be written to using the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this
interface consists of a Chip address that is fixed to “10” and a Read/Write status (1bit, Fixed to “1”; Write only).
Also a Register address (MSB first, 5bits) and Control data (MSB first, 8bits) are used. Address and data is
clocked in on the rising edge of CCLK and data is clocked out on the falling edge. For write operations, data is
latched after a low-to-high transition of CSN. The clock speed of CCLK is 5MHz(max)
CSN
0
1
2
1
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1:1,C0:CAD0)
Read/Write (Fixed to “1” : Write only)
Register Address
Control Data
Figure 10. 3-wire Serial Control I/F Timing
Note: Do not write to the address except 00H through 06H.
MS0134-E-00
2002/1
- 20 -
ASAHI KASEI
[AK4120]
2) I2C-bus Control Mode (I2C= “H”)
The AK4120 supports the standard I2C-bus interface (max:100kHz). Then AK4120 cannot support fast-mode I2C (max:
400kHz).
(2)-1. WRITE Operations
Figure 11 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 17). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction
bit (R/WN). The most significant five bits of the slave address are fixed as “00100”. The next two bits are CAD1 and
CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-wired input pins (CAD1
pin and CAD0 pin) set them (Figure 12). If the slave address matches that of the AK4120, the AK4120 generates the
acknowledge and the operation is executed. The master must generate an acknowledge-related clock pulse and release
the SDA line (HIGH) during the acknowledge clock pulse (Figure 18). A “1” for R/WN bit indicates that the read
operation is to be executed. A “0” indicates that the write operation is to be executed.
The second byte is the control register address of the AK4120. The format is MSB first, and three most significant bits
are fixed to zero (Figure 13). Subsequent bytes contain control data. The format is MSB first, 8-bits (Figure 14). The
AK4120 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP
condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition (Figure 17).
The AK4120 is capable of more than one byte write operation per sequence. After receipt of the third byte, the AK4120
generates an acknowledge, and awaits the next data. The master can transmit multiple bytes rather than terminating the
write cycle after the first data byte is transferred. After the receipt of each data, the internal 5-bit address counter is
incremented by one, and the next data is taken into next address automatically. If the address exceeds 06H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. (If an
address greater than 07H is set, this function will not work properly.)
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 19) except for START and STOP conditions.
S
S
T
T
A
R
T
R/WN= “0”
Sub
O
P
Slave
Address
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
Address(n)
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 11. Data transfer sequence at the I2C-bus mode
0
0
0
1
0
0
CAD1 CAD0 R/WN
(Those CAD1/0 should match with CAD1/0 pins)
Figure 12. The first byte
0
0
A4
A3
A2
A1
D1
A0
D0
Figure 13. The second byte
D7
D6
D5
D4
D3
D2
Figure 14. Byte structure after the second byte
MS0134-E-00
2002/1
- 21 -
ASAHI KASEI
[AK4120]
(2)-2. READ Operations
To enable a READ operation in the AK4120, set R/WN bit = “1”. After transmission of data, the master can read the
next data address by generating an acknowledge instead of terminating the write cycle after the receipt the first data
word. After the receipt of each data, the internal 5-bit address counter is incremented by one, and the next data is taken
into next address automatically. If the address exceeds 06H prior to generating the stop condition, the address counter
will “roll over” to 00H and the previous data will be overwritten. If an address greater than 07H is set, this function will
not work properly.)
The AK4120 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
(2)-2-1. CURRENT ADDRESS READ
The AK4120 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/WN bit set to “1”, the AK4120 generates an
acknowledge, transmits 1data byte whose address is set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates a the stop
condition, the AK4120 ceases transmission
S
S
T
O
P
T
A
R
T
R/WN= “1”
Slave
Address
S
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 15. CURRENT ADDRESS READ
(2)-3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/WN bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start
request, slave address(R/WN=“0”) and the register address to read. After the register address’s acknowledged, the
master immediately reissues the start request and the slave address with the R/WN bit set to “1”. The AK4120 generates
a stop condition instead of an acknowledge, an acknowledge, 1byte data and increments the internal address counter by
1. If the master generates a stop condition instead of an acknowledge, the AK4120 stops transmitting.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
R/WN= “0”
R/WN= “1”
Slave
Address
Sub
Address(n)
Slave
Address
S
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 16. RANDOM ADDRESS READ
MS0134-E-00
2002/1
- 22 -
ASAHI KASEI
[AK4120]
SDA
SCL
S
P
start condition
stop condition
Figure 17. START and STOP conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 18. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 19. Bit transfer on the I2C-bus
Note: Only addresses 00H through 06H are valid write addresses. All others should not be read from or written to.
MS0134-E-00
2002/1
- 23 -
ASAHI KASEI
[AK4120]
n System Reset
The AK4120 is reset by bringing the power down pin “PDN” =“L”. The digital filters are also reset when this occurs.
The AK4120 should be reset once by bringing PDN =“L” upon power-up. After a reset, the required clocks shown in
Table 2 must be input.
The SRC block starts 2*LRCK1 or 2*LRCK2 after a reset. The SRC block starts outputting data 2053*ORCK after a
reset occurs. Before 2053*ORCK, the SRC block outputs “L”.
n Zero cross detection function of Volume
When ZELM=“0”, the Zero Cross detection function is enabled. Then, if a Volume value is written to the register, the
volume will not change until a Zero crossing is detected or this process times out. The ZTM1-0 bits in 01H set this
timeout. When ZELM=“1”, Volume changes soon after volume value is written.
(3) Zero crossing timeout(ZTM1-0)
(1)
(2)
Figure 20. Zero crossing process
(1) At this point, volume value is written in register.
(2) This is a zero crossing point. At this point, volume is changed.
(3) This is time of Zero crossing timeout that is set by ZTM1-0.
MS0134-E-00
2002/1
- 24 -
ASAHI KASEI
[AK4120]
n Mapping of Program Registers
Default
Addr Register Name
00H Control 1
01H Control 2
02H Control 3
D7
PW
D6
0
D5
DIFO1
D4
DIFO0
D3
DIFI21
0
D2
DIFI20
OMCKS
D1
DIFI11
D0
DIFI10
IMCKS1
80H
20H
00H
10H
10H
10H
10H
IMCKS2
0
ZELM ZTM1 ZTM0
MUTE2R
MUTE2L
GAIN6
GAIN6
GAIN6
GAIN6
MUTE1R
GAIN5
GAIN5
GAIN5
GAIN5
MUTE1L
GAIN4
GAIN4
GAIN4
GAIN4
0
0
PATH1
GAIN1
GAIN1
GAIN1
GAIN1
PATH0
GAIN0
GAIN0
GAIN0
GAIN0
Lch Volume#1 Control
0
0
0
0
GAIN3
GAIN3
GAIN3
GAIN3
GAIN2
GAIN2
GAIN2
GAIN2
03H
04H
05H
06H
Rch Volume#1 Control
Lch Volume#2 Control
Lch Volume#2 Control
Note: When the PDN goes to “L”, the registers are initialized to their default values.
Data must not be written to the address except 00H through 06H.
n
Register Definitions
Addr Register Name
00H Control 1
Default
D7
PW
1
D6
0
D5
DIFO1
0
D4
DIFO0
0
D3
DIFI21
0
D2
DIFI20
0
D1
DIFI11
0
D0
DIFI10
0
0
DIFI11-0: Audio Data Formats for Input#1 port (See Table 6).
DIFI21-0: Audio Data Formats for Input#2 port (See Table 7).
DIFO1-0: Audio Data Formats for Output port (See Table 8).
PW: Power down control
0: Power Down
At PW=”0”, internal registers can be written.
1: Normal Operation (Default)
Addr Register Name
01H Control 2
Default
D7
0
D6
D5
D4
D3
0
D2
OMCKS
D1
IMCKS2
D0
IMCKS1
ZELM ZTM1 ZTM0
0
0
1
0
0
0
0
0
IMCKS1: Master Clock Speed of the Master Clock for Input#1 (IMCLK1)
0: 256fs(default)
1: 512fs
IMCKS2: Master Clock Speed of the Master Clock for Input#2 (IMCLK2)
0: 256fs(default)
1: 512fs
OMCKS: Master Clock Speed of the Master Clock for Output (OMCLK)
0: 256fs(default)
1: 512fs
Note: Set the PW= “0” when those master clocks are changed.
MS0134-E-00
2002/1
- 25 -
ASAHI KASEI
[AK4120]
ZTM1•0:Duration of zero-crossing timeout when ZELM= “0”
Time of Timeout
ZTM1
ZTM0
48kHz
10.7ms
44.1kHz
11.6ms
23.2ms
46.5ms
92.9ms
32kHz
16.0ms
32.0ms
64.0ms
128.0ms
0
0
1
1
0
1
0
1
513/fs
1025/fs 21.4ms
2049/fs 42.7ms
4097/fs 85.4ms
Default
Note: Fs is the output sample rate
Table 9. Time of Timeout
ZELM: Select Zero Crossing Enable
0: Enable (Default)
1: Disable
Addr Register Name
02H Control 3
Default
D7
D6
D5
D4
D3
0
D2
0
D1
PATH1
D0
PATH0
MUTE2R
MUTE2L
MUTE1R
MUTE1L
0
0
0
0
0
0
0
0
PATH1-0: Path Mode Select (See Table 1 and Figure 3-4)
MUTE1L: Mute control for Lch of Volume#1
0: Mute off (Default)
1: Mute On
MUTE1R: Mute control for Rch of Volume#1
0: Mute off (Default)
1: Mute On
MUTE2L: Mute control for Lch of Volume#2
0: Mute off (Default)
1: Mute On
MUTE2R: Mute control for Rch of Volume#2
0: Mute off (Default)
1: Mute On
MS0134-E-00
2002/1
- 26 -
ASAHI KASEI
[AK4120]
Addr Register Name
D7
0
D6
D5
D4
D3
D2
D1
D0
Lch Volume#1 Control
GAIN6
GAIN6
GAIN6
GAIN6
GAIN5
GAIN5
GAIN5
GAIN5
GAIN4
GAIN4
GAIN4
GAIN4
GAIN3
GAIN3
GAIN3
GAIN3
GAIN2
GAIN2
GAIN2
GAIN2
GAIN1
GAIN1
GAIN1
GAIN1
GAIN0
GAIN0
GAIN0
GAIN0
03H
04H
05H
06H
Rch Volume#1 Control
Lch Volume#2 Control
Rch Volume#2 Control
0
0
0
Default
0
0
0
1
0
0
0
0
GAIN6-0: Volume control shown in Table 10 .
Volume Range: -83.25dB ~12dB(Step 0.75dB)
GAIN6-0
00H
01H
02H
:
Volume Level
12dB
11.25dB
10.5dB
:
9H
0.75dB
0dB
-0.75dB
:
10H
11H
:
Default
7DH
7EH
7FH
-81.75
-82.50
-83.25
Table 10. Output Volume level
Note: |Gain error| < 0.3dB, |Step error| < 0.1dB.
MS0134-E-00
2002/1
- 27 -
ASAHI KASEI
[AK4120]
SYSTEM DESIGN
Figure 21 illustrates a typical system connection diagram. An evaluation board is available which demonstrates this
application circuit, the optimum layout, power supply arrangement and performance measurement results.
Condition: VDD=3.3V, 3-wire serial control mode, Chip Address = “10”
Path Mode 0, Input#2 and Output are slave mode
IMCLK1
SDTI1
IBICK1
ILRCK1
TEST
I2S
IMCLK2
SDTI2
IBICK2
ILRCK2
I2MODE
VDD
1
2
24
23
22
21
20
19
18
Digital
Audio
Source
Analog
Input
ADC
3
(DIR)
4
5
AK4120
0.1u
3.3V Supply
6
I2C
7
VSS
CAD0
8
Top View OMODE
17
16
OMCLK
9
CSN/CAD1
CCLK/SCL
CDTI/SDA
PDN
SDTO
10
11
12
15
14
13
Audio
DSP
uP
OBICK
OLRCK
Figure 21. Example of a typical design
MS0134-E-00
2002/1
- 28 -
ASAHI KASEI
[AK4120]
PACKAGE
24pin VSOP (Unit: mm)
±
1.25 0.2
±
*7.8 0.15
24
13
A
12
1
±
0.22 0.1
0.65
±
0.15 0.05
±
0.1 0.1
Detail A
Seating Plane
0.10
°
0-10
NOTE: Dimension "*" does not include mold flash.
n
Package & Lead frame material
Package molding compound:
Lead frame material:
Epoxy
Cu
Lead frame surface treatment:
Solder plate (Pb free)
MS0134-E-00
2002/1
- 29 -
ASAHI KASEI
[AK4120]
MARKING
AKM
AK4120VF
AAXXXX
Contents of AAXXXX
AA:
Lot#
XXXX:
Date Code
IMPORTANT NOTICE
· These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
· AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
· Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export pertaining
to customs and tariffs, currency exchange, or strategic materials.
· AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which
its failure to function or perform may reasonably be expected to result in loss of life or in
significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected
to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device
or system containing it, and which must therefore meet very high standards of performance
and reliability.
· It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and
liability for and hold AKM harmless from any and all claims arising from the use of said product in
the absence of such notification.
MS0134-E-00
2002/1
- 30 -
相关型号：
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