AKD4633-A [AKM]
16bit mono CODEC with MIC/SPK amplifier.; 16位单声道编解码器MIC / SPK放大器。
| 型号： | AKD4633-A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 16bit mono CODEC with MIC/SPK amplifier. |
| 文件： | 总38页 (文件大小：904K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AKD4633-A]
AKD4633-A
AK4633 Evaluation board Rev.3
GENERAL DESCRIPTION
AKD4633-A is an evaluation board for the AK4633VN, 16bit mono CODEC with MIC/SPK amplifier. The
AKD4633-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D
→ D/A). AKD4633-A also has the digital audio interface and can achieve the interface with digital audio
systems via opt-connector.
Ordering guide
AKD4633-A
---Evaluation board for AK4633VN
(Cable for connecting with printer port of IBM-AT, compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
AVDD DVDD SVDD
GND
5V
3.3V
Regulator
Control Data
10pin Header
MIC-Jack
MIC
DSP
BEEP/MIN/MOUT
AOUT
AK4633VN
10pin Header
SPK-Jack
Opt In
Opt Out
AK4114
Clock
Gen
Figure 1. AKD4633-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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[AKD4633-A]
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD, SVDD, and VCC are supplied from the regulator. (AVDD, DVDD, SVDD, and
VCC jack should be open.). See “Other jumper pins set up (page 10)”. <default>
[REG]
(red )
= 5V
[AVDD] (orange)
[DVDD] (orange)
[SVDD] (blue)
= open
= open
= open
= open
= 0V
: 3.3V is supplied to AVDD of AK4633VN from regulator.
: 3.3V is supplied to DVDD of AK4633VN from regulator.
: 3.3V is supplied to SVDD of AK4633VN from regulator.
: 3.3V is supplied to logic block from regulator.
: for analog ground
[VCC]
(orenge)
[AVSS] (black)
[AGND] (black)
[DGND] (black)
= 0V
= 0V
: for analog ground
: for logic ground
1-2) When AVDD, DVDD, SVDD, and VCC are not supplied from the regulator. (AVDD, DVDD, SVDD, and
VCC jack should be junction.) See “ (page 10)”.
Other jumper pins set up
[REG]
(red)
= “REG” jack should be open.
[AVDD] (orange)
[DVDD] (orange)
[SVDD] (blue)
= 2.6 ∼ 3.6V : for AVDD of AK4633VN (typ. 3.3V)
= 2.6 ∼ 3.6V : for DVDD of AK4633VN (typ. 3.3V)
= 2.6 ∼ 5.25V: for SVDD of AK4633VN (typ. 3.3V, 5.0V)
= 2.6 ∼ 3.6V : for logic (typ. 3.3V)
[VCC]
(orenge)
[AVSS] (black)
[AGND] (black)
[DGND] (black)
= 0V
= 0V
= 0V
: for analog ground
: for analog ground
: for logic ground
Each supply line should be distributed from the power supply unit.
AVDD and DVDD must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4633VN and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
Evaluation mode
In case of AK4633VN evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4633VN and AK4114. About AK4633VN’s audio interface format, refer to datasheet of AK4633VN.
About AK4114’s audio interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI
pin)
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or
FCK pin)
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
(5)
Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
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→
(1) Evaluation of loop-back mode (A/D
D/A) : PLL, Master Mode
a) Set up jumper pins of MCKI clock
X’tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set in X2. X’tal of 12.288MHz
(Default) is set on the AKD4633VN. Set “No.8 of SW3” to “H”.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
XTL
EXT 256fs 512fs
1024fs MCKO
DIR
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4633VN.
There is no necessity for set up JP19.
JP29
BICK_INV
JP19
BICK_SEL
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
16fs
EXT
32fs
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4633VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
following.
JP30
SDTI
JP26
4631_SDTI
ADC
ADC
DAC/LOOP
DIR
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[AKD4633-A]
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
X’tal of 12.288MHz (Default) is set on the AKD4633-A. In this case, the AK4633VN corresponds to PLL
reference clock of 12.288MHz. In this evaluation mode, the output clock from MCKO-pin of the AK4633VN is
supplied to a divider (U3: 74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO bit”
in the AK4633VN should be set to “1”. When an external clock through a RCA connector (J8: EXT/BICK) is
supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly
selected in order to match the output impedance of the clock generator.
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
XTL
EXT 256fs 512fs
1024fs MCKO
DIR
b) Set up jumper pins of BICK clock
JP29
BICK_INV
JP19
BICK_SEL
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
16fs
EXT
32fs
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4633VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
following.
JP30
SDTI
JP26
4631_SDTI
ADC
ADC
DAC/LOOP
DIR
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[AKD4633-A]
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(3) Evaluation of loop-back mode (A/D D/A) : PLL, Slave Mode (PLL Reference CLOCK: BICK or FCK
pin)
a) Set up jumper pins of BICK clock
When an external clock through a RCA connector J8 (EXT/BICK) is supplied, select EXT on JP19
(MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to match the
output impedance of the clock generator.
JP29
BICK_INV
JP17
XTE
JP20
BICK
JP27
BICK
JP21
MCLK_SEL
XTL
EXT
DIR
DIR ADC
INV THR
INV
THR
In this evaluation mode, the selected clock from JP21 (MCLK_SEL) is supplied to a divider (U3: 74VHC4040),
BICK and FCK clocks are generated by the divider. Input frequency of master clock is set up in turn “256fs”,
“512fs”, “1024fs” from left.
JP18
JP18
JP18
MKFS
MKFS
MKFS
256fs
512fs
1024fs MCKO
256fs 512fs
256fs 512fs
1024fs MCKO
1024fs MCKO
And input frequency of BICK is set up in turn “16fs”, “32fs”, “64fs” from left.
JP19
JP19
JP19
BICK_SEL
BICK_SEL
BICK_SEL
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
64fs 32fs 16fs EXT
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[AKD4633-A]
b) Set up jumper pins of FCK clock
When an external clock through a RCA connector J9 (FCK) is supplied, select EXT on JP22 (FCK_SEL). JP24
(EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP22
JP28
FCK_SEL
FCK
DIR
ADC
2fs 1fs EXT
c) Set up jumper pins of DATA
When the AK4633VN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
following.
JP30
SDTI
JP26
4633_SDTI
ADC
ADC
DAC/LOOP
DIR
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ASAHI KASEI
[AKD4633-A]
(4) Evaluation of using DIR of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
256fs
512fs1024fs
XTL
EXT
DIR
b) Set up jumper pins of BICK clock
JP19
BICK_SEL
JP29
BICK_INV
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
EXT
32fs 16fs
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When D/A converter of the AK4633VN is evaluated by using DIR of AK4114, the jumper pins should be set to
the following.
JP30
SDTI
JP26
4633_SDTI
ADC
ADC
DAC/LOOP
DIR
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ASAHI KASEI
[AKD4633-A]
(5) Evaluation of using DIT of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
JP6
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
MCKI
256fs
512fs1024fs
XTL
EXT
DIR
b) Set up jumper pins of BICK clock
JP19
BICK_SEL
JP29
BICK_INV
JP20
BICK
JP27
BICK
DIR ADC
INV THR
INV
THR
64fs
EXT
32fs 16fs
c) Set up jumper pins of FCK clock
JP24 (EXT2) and R27 should be properly selected in order to match the output impedance of the clock generator.
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When A/D converter of the AK4633VN is evaluated by using DIR of AK4114, the jumper pins should be set to
the following.
JP30
SDTI
JP26
4633_SDTI
ADC
ADC
DAC/LOOP
DIR
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[AKD4633-A]
DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4633-VN and AK4114
ON is “H”, OFF is “L”.
No.
1
2
Name
DIF0
DIF1
ON (“H”)
OFF (“L”)
AK4114 Audio Format Setting
See Table 2
3
DIF2
4
5
CM0
CM1
Clock Operation Mode select
See Table 3
6
7
8
OCKS0
OCKS1
M/S
Master Clock Frequency Select
See Table 4
Master mode
Slave mode
Note. When the AK4633VN is evaluated Master mode, “No.8 of SW3” is set to “H”.
Table 1. Mode Setting for AK4633VN and AK4114
Resistor setting
for AK4633VN Audio
Interface Format
Setting for AK4114 Audio Interface Format
DIF1 bit
DIF0 bit
DIF0
DIF1
DIF2
DAUX
SDTO
0
1
1
1
0
1
L
L
H
L
L
L
L
H
H
24bit, Left justified
24bit, Left justified
24bit, I2S
16bit, Right justified
24bit, Left justified
24bit, I2S
Default
Note. When the AK4633VN is evaluated by using DIR/DIT of AK4114, “No.8 of SW3” is set to “L”.
Table 2. Setting for AK4114 Audio Interface Format
Mode
0
1
CM1
0
0
CM0 UNLOCK
PLL
ON
OFF
ON
ON
ON
X'tal
ON(Note)
ON
Clock source SDTO
0
1
-
-
PLL
X'tal
PLL
X'tal
X'tal
RX
DAUX
RX
DAUX
DAUX
0
1
-
ON
ON
ON
2
3
1
1
0
1
Default
ON: Oscillation (Power-up), OFF: STOP (Power-down)
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off.
Default setting is recommended.
Table 3. Clock Operation Mode select
No. OCKS1
MCKO1
256fs
512fs
MCKO2
256fs
256fs
X’tal
256fs
512fs
Default
0
2
0
1
Table 4. Master Clock Frequency Select (Stereo mode)
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[AKD4633-A]
Other jumper pins set up
1. JP1 (GND)
OPEN
: Analog ground and Digital ground
: Separated.
SHORT
: Common. (The connector “DGND” can be open.) <Default>
2. JP2 (MICP)
MICP
: Connection between MICP pin and BEEP pin of the AK4633VN.
: MIC Differential input.
BEEP
: BEEP input. <Default>
3. JP3 (AVDD_SEL) : AVDD of the AK4633VN
REG
AVDD
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
: AVDD is supplied from “AVDD ” jack.
4. JP9 (DVDD_SEL) : DVDD of the AK4633VN
AVDD
DVDD
: DVDD is supplied from “AVDD”. < Default >
: DVDD is supplied from “DVDD ” jack.
5. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
VCC
: Logic block of LVC is supplied from “DVDD”. < Default >
: Logic block of LVC is supplied from “VCC ” jack.
6. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
VCC
: Logic is supplied from supply line of LVC. < Default >
: Logic block of LVC is supplied from “VCC ” jack.
7. JP4 (SVDD_SEL) : SVDD of the AK4633VN
REG
SVDD
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
: SVDD is supplied from “SVDD ” jack.
8. JP8 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1
MCKO2
: The check from MCKO1 of AK4114 is provided to MCKI of the AK4633VN. < Default >
: The check from MCKO2 of AK4114 is provided to MCKI of the AK4633VN.
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ASAHI KASEI
[AKD4633-A]
The function of the toggle SW
[SW1] (DIR) : Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
[SW2] (PDN) : Power control of AK4633VN. Keep “H” during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4633VN can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT2
(CTRL) with PC by 10 wire flat cable packed with the AKD4633-A
CSN
CCLK
CDTI
Connect
AKD4633-A
PC
10 wire
10pin
10pin Header
flat cable
Connector
Figure 2. Connect of 10 wire flat cable
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[AKD4633-A]
Analog Input / Output Circuits
(1) Input Circuits
a) MIC Input Circuit
J1
MIC-JACK
6
4
3
JP12
MIC_SEL
AVSS
JACK
RCA
INT
J3
MIC
2
3
1
MR-552LS
AVSS
Figure 3. MIC Input Circuit
(a-1) Analog signal is input to MIC pin via J1 connector.
JP12
MIC_SEL
RCA JACK
(a-2) Analog signal is input to MIC pin via J3 connector.
JP12
MIC_SEL
RCA JACK
b) BEEP Input Circuit
J4
BEEP
C26
1u
R19
20k
2
3
1
2
1
BEEP
R18
47k
MR-552LS
AVSS
AVSS
Figure 4. BEEP Input Circuit
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[AKD4633-A]
(2) Output Circuits
a) AOUT Output Circuit
C28
R20
220
J5
AOUT
1
2
2
3
1
AOUT
1u
R21
20k
MR-552LS
AVSS
AVSS
Figure 5. AOUT Output Circuit
b) SPK Output Circuit
Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14
(SPN_SEL) should be open, or “PMSPK bit” in the AK4633VN should be set to “0”.
JP31
Dynamic
J2
R15
10
SPK-JACK
3
4
SVSS
SPN
6
JP13
D1
Dynamic(EXT)
Piezo(EXT)
Dynamic
A
A
K
SPK1
SVSS
DIODE ZENER
SPN_SEL
020S16
CN5
R
L
JP14
D2
K
Dynamic(EXT)
Piezo(EXT)
Dynamic
2
SVSS
SPP
DIODE ZENER
SPP_SEL
1
R17
10
Figure 6. SPK Output Circuit
(b-1) An external dynamic speaker is evaluated by using J2 (SPK-JACK) connector.
JP13
JP14
JP31
Dynamic
SPN_SEL
SPP_SEL
Dynamic
Dynamic(EXT) Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
(b-2) An external Piezo speaker is evaluated by using J2 (SPK-JACK) connector.
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[AKD4633-A]
JP13
JP14
JP31
Dynamic
SPN_SEL
SPP_SEL
Dynamic
Dynamic(EXT) Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
(b-3) Analog signal of SPP/SPN pins are output from “Dynamic Speaker” on the evaluation (SPK1).
JP13
JP14
JP31
SPN_SEL
SPP_SEL
Dynamic
Dynamic
Dynamic(EXT) Dynamic
Dynamic(EXT)
Piezo(EXT)
Piezo(EXT)
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
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[AKD4633-A]
2. Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD4633-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4633-A by 10-line type flat cable (packed with AKD4633-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AK4633VN Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4633.exe” to set up the control program.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
Explanation of each buttons
1. [Port Reset] :
2. [Write default] :
3. [All Write] :
4. [Function1] :
5. [Function2] :
6. [Function3] :
7. [Function4] :
8. [Function5]:
Set up the USB interface board (AKDUSBIF-A) .
Initialize the register of AK4633VN.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
9. [SAVE] :
10. [OPEN] :
11. [Write] :
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
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Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4633VN, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box:
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4633VN, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL
Address Box:
Start Data Box:
End Data Box:
Interval Box:
Step Box:
Input registers address in 2 figures of hexadecimal.
Input starts data in 2 figures of hexadecimal.
Input end data in 2 figures of hexadecimal.
Data is written to AK4633VN by this interval.
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4633VN, click [OK] button. If not, click [Cancel] button.
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4. [Save] and [Open]
4-1. [Save]
Save the current register setting data. The extension of file name is “akr”.
(Operation flow)
(1) Click [Save] Button.
(2) Set the file name and push [Save] Button. The extension of file name is “akr”.
4-2. [Open]
The register setting data saved by [Save] is written to AK4633VN. The file type is the same as [Save].
(Operation flow)
(1) Click [Open] Button.
(2) Select the file (*.akr) and Click [Open] Button.
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[AKD4633-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [Start] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file
name is “aks”.
Figure 1. Window of [F3]
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[AKD4633-A]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure 2 opens.
Figure 2. [F4] window
<KM079406>
2007/04
- 19 -
ASAHI KASEI
[AKD4633-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks).
The sequence file name is displayed as shown in Figure 3.
Figure 3. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
3-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4.
[OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
3-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
<KM079406>
2007/04
- 20 -
ASAHI KASEI
[AKD4633-A]
7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When
[F5] button is clicked, the following window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 5.
(2) Click [WRITE] button, then the register setting is executed.
<KM079406>
2007/04
- 21 -
ASAHI KASEI
[AKD4633-A]
Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5.
[OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to
reflect the change.
<KM079406>
2007/04
- 22 -
ASAHI KASEI
[AKD4633-A]
8. [Filter Dialog]
It is possible to calculate the coefficients of HPF and EQ filters, write these coefficients to registers and confirm the
frequency response of these filters. Click [Filter] button, then the window as shown in Figure 6 opens.
Figure 6. [Filter] Window
(1) Setup the Parameters
Set up the parameters of HPF and EQ filters.
Parameter
Sampling Rate
HPF Cut Off Frequency
EQ1 Center Frequency
EQ1 Band Width
EQ1 Gain
Contents
Sampling Frequency (fs)
High Pass Filter Cut Off Frequency
EQ1 Center Frequency
Setup range
48000Hz ≥ fs ≥ 7350Hz
(fs/2 – 1) ≥ fc > fs/10000
fs/2 ≥ EQ1 > 0Hz
fs/2 ≥ EQ1 >1Hz
3 > EQ1 ≥- 1
EQ1 Band Width
EQ1 Gain
(Note 1)
(Note 2)
EQ2 Center Frequency
EQ2 Band Width
EQ2 Gain
EQ2 Center Frequency
EQ2 Band Width
EQ2 Gain
fs/2 ≥ EQ2 > 0Hz
fs/2 ≥ EQ2 >1Hz
3 > EQ2 ≥- 1
(Note 1)
(Note 2)
Note 1. Band width of 3dB gain difference from center frequency
Note 2. This filter is notch filter when this gain is -1.
(2) Filter ON/OFF
Set up the ON or OFF of filters by the check button of "HPFAD", "HPF", "EQ1" and "EQ2". The filter is ON when the
button is checked.
Figure 7. Filter ON/OFF check button
<KM079406>
2007/04
- 23 -
ASAHI KASEI
[AKD4633-A]
(3) Calculation of Register Setting
When [Register Setting] is clicked, the register setting of filters are displayed in "Register Setting" area. At the same this,
these setting are written to HPFAD bit, HPF bit, EQ1 bit, EQ2 bit and 10H-1FH registers. If the parameter is out of range,
then the error message is displayed and these writing to register aren't executed.
Figure 8. Calculation result to register parameters
(4) Frequency Response
When [Register Setting] is clicked, the frequency response is displayed. At the same this, these setting are written to
HPFAD bit, HPF bit, EQ1 bit, EQ2 bit and 10H-1FH registers. If [UpDate] button is clicked after setting the frequency
range, the display of frequency response is updated.
Figure 9. Frequency characteristic indicates result
<KM079406>
2007/04
- 24 -
ASAHI KASEI
[AKD4633-A]
Revision History
Date
Manual
Board
Reason
Contents
Revision
Revision
05/07/14
05/08/23
05/09/16
05/10/21
06/04/14
KM079400
KM079401
KM079402
KM079403
KM079404
0
1
1
2
2
First Edition
Update
Change of a figure & circuit
Error Correct Port Numbers are corrected in circuit.
Update
Update
Device revision of AK4633 is changed to “Rev.B”.
Part change in LOGIC circuit diagram.
U9: 74LVC541Æ74HC541
07/02/15
07/04/02
KM079405
KM079406
3
3
Error Correct Port number was corrected in both silkscreen printing and
circuit diagram. JP1(MICP) Æ JP2 (MICP)
Error Correct Port number was corrected in both silkscreen printing and
circuit diagram.
Silkscreen printing: JP2 (MCKI) Æ JP6 (MCKI)
Circuit diagram: JP5 (MCKI) Æ JP6 (MCKI)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM079406>
2007/04
- 25 -
A
B
C
D
E
JP1
GND
REG_IN
C1
T1
TA48033F
VCC3.3V
T45_O
REG
AVDD
DVDD
AVSS
SVDD
SVSS
DGND
IN
OUT
REG
AVSS
C3
T45_R T45_O T45_O
T45_BK
T45_BU
T45_BK
T45_BK
+
C2
0.1u
AVSS
SVSS
0.1u
47u
E
D
C
B
A
E
D
C
B
A
CN1
32pin_4
VCC3.3V
REG_IN
AVDD
DVDD
SVDD
AVSS
AVSS
SVSS
JP2
MICP
C1
+
R1
1u
2.2k
BEEP
MICP
TP2
AOUT
1
TP1
MIC MPI
TP3
TP4
C2
0.22u
BEEP
1
1
1
C3
10u
R2
2.2k
CN3
24
REG
AVSS
C5
0.1u
REG
CN2
TP11
AVSS
TP6
SVDD
23
VCOM
JP4 REG
SVDD_SEL
SVDD
JP3
1
2
3
4
5
6
7
8
AVDD_IN
REG AVDD_SEL
TP13
SPN
22
L2
+
TP7
AVSS
C6
2.2u
C4
U1
L1
0.1u
SVDD
1
2
1
2
21
SPN
SPP
R4
(open)
TP9
SPP
(short)
C13
47u
(short)
AVDD
TP8
AVSS AVDD
C7
10u
C8
0.1u
C16
+
47u
+
+
1
2
3
4
5
6
18
17
16
15
14
13
VCOM
AVSS
AVDD
VCOC
PDN
SPN
SPP
20
AVDD
AVSS
TP10 MCKO
TP12 MCKI
JP6 MCKI
19
4633_MCKO
4633_MCKI
TP14
VCOC
MCKO
MCKI
AVSS
R5 10k
AK4633VN
18
SVSS
C9
4.7n
DVSS
DVDD
C10
C11
+
17
0.1u
10u
CSN
AVSS
TP15
PDN
AVSS
32pin_3
PDN
R7 51
32pin_1
AVDD
TP16 TP17 TP18 TP19 TP20 TP21 TP22
CSN CCLK CDTI SDTI SDTO FCK
TP23
DVDD
BICK
JP9
AVDD DVDD_SEL
1
1
1
1
1
1
1
1
DVDD_IN
R14 10
L4
DVDD
1
2
R8
51
R9
51
R10
51
R11
51
R12
51
R13
51
R22
51
C22
47u
(short)
DVDD
R40
(short)
JP10
LVC_SEL
+
DVDD
LVC
AVSS
VCC3.3V
VCC
LVC
JP11
VCC_SEL
CN4
L5
32pin_2
D3.3V
1
2
C23
47u
(short)
VCC
+
Title
Size
AKD4633-A
Document Number
Rev
3
A3
AK4633-VN
Date:
Sheet
of
Friday, March 30, 2007
1
5
A
B
C
D
E
A
B
C
D
E
J1
MIC-JACK
6
JP31
Dynamic
4
3
J2
JP12
MIC_SEL
R15
10
SPK-JACK
E
D
C
B
A
E
D
C
B
A
AVSS
JACK
RCA
SVSS
3
4
INT
SPN
J3
MIC
6
2
3
1
JP13
D1
Dynamic(EXT)
Piezo(EXT)
Dynamic
A
A
K
SPK1
020S16
MR-552LS
AVSS
SVSS
DIODE ZENER
SPN_SEL
CN5
R
L
JP14
D2
K
Dynamic(EXT)
Piezo(EXT)
Dynamic
2
J4
BEEP
C26
1u
1
R19
20k
2
3
1
2
BEEP
SVSS
SPP
DIODE ZENER
SPP_SEL
1
R18
47k
MR-552LS
R17
10
AVSS
AVSS
C28
R20
220
J5
AOUT
1
2
2
3
1
AOUT
1u
R21
20k
MR-552LS
AVSS
AVSS
Title
Size
AKD4633-A
Document Number
Rev
3
A3
Input/Output
Date:
Sheet
of
Thursday, February 15, 2007
2
5
A
B
C
D
E
A
B
C
D
E
for
74HCU04,74AC74,74VHC4040,74HC14,74HC14,74LVC541,74HCT04
D3.3V
12.288MHz
X1
C30
0.1u
C31
0.1u
C32
0.1u
C33
0.1u
C34
0.1u
C35
0.1u
C36
0.1u
E
D
C
B
A
E
D
C
B
A
+
C37
47u
1
2
R24
1M
U2C
U2B
5
6
3
4
74HCU04
74HCU04
JP17
XTE
C38
(open)
C39
(open)
EXT_MCLK
D3.3V
D3.3V
JP18
MKFS
U4A
U4B
74AC74
74AC74
256fs
U3
CLK
JP19
512fs
10
11
9
7
6
5
3
2
4
13
12
14
15
1
BICK_SEL
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
2
3
5
12
11
9
1024fs
MCKO
64fs
32fs
16fs
EXT
THR
JP20
BICK
D
Q
D
Q
R25
short
RST
JP21
CLK
CLK
EXT_BICK
XTL
DIR
EXT
1
2
6
8
INV
DIR_MCLK
Q
Q
U5A
74HC14
MCLK_SEL
Q10
Q11
Q12
JP22
2fs
1fs
74VHC4040
EXT
EXT_FCK
FCK_SEL
MCKO
J8
EXT/BICK
2
3
1
R26
51
MR-552LS
AVSS
JP23
EXT1
J9
FCK
2
3
1
R27
51
MR-552LS
AVSS
JP24
EXT2
Title
AKD4633-A
Size
A3
Document Number
Rev
3
CLOCK
Date:
Sheet
of
5
Thursday, February 15, 2007
3
A
B
C
D
E
A
B
C
D
E
C40 C41
0.1u 0.1u
D3.3V
D3.3V
L6
(short)
R28
10k
D3
E
D
C
B
A
E
D
C
B
A
HSU119
PORT1
VCC
GND
OUT
C42
0.1u
3
2
1
U5B
U5C
C43
10u
4
3
6
5
R29
470
2
1
74HC14
74HC14
D3.3V
TORX141
L
H
C45
0.1u
C44
0.1u
SW1
DIR
C46
0.47u
R30
18k
SW3
U6
DIF0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DIF1
DIF2
R31
1k
LED1
ERF
CM0
U7D
CM1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
9
8
K
A
IPS0
INT0
OCKS0
OCKS1
CM1
D3.3V
OCKS0
OCKS1
M/S
74HC04
NC
OCKS0
RP1
9
8
7
6
5
4
3
2
1
3
DIF0
OCKS1
CM1
CM0
CM1
OCKS0
OCKS1
M/S
4
TEST2
DIF1
NC
5
CM0
CM0
47k
6
PDN
C47
(open)
AK4114
7
DIF2
IPS1
P/SN
XTL0
XTL1
VIN
XTI
X2
11.2896MHz
C48
(open)
8
XTO
9
DAUX
MCKO2
BICK
DAUX
10
11
12
DIR_BICK
SDTO
DIR_SDTI
C49
0.1u
C50
0.1u
JP25
MCKO_SEL
DIR_FCK
MCKO2
MCKO1
DIR_MCLK
1
2
1
2
C51
10u
C52
10u
D3.3V
D3.3V
PORT2
IN
VCC
GND
3
2
1
D3.3V
C53
0.1u
TOTX141
Title
AKD4633-A
Size
A3
Document Number
Rev
3
DIR/DIT
Date:
Sheet
E
of
Thursday, February 15, 2007
4
5
A
B
C
D
A
B
C
D
E
U8
LVC
74HC541
1
19
2
20
10
18
17
16
15
14
13
12
11
E
D
C
B
A
E
D
C
B
A
DIR
G
VCC
GND
B1
11
12
13
14
15
16
17
18
10
20
9
8
7
6
5
4
3
2
19
1
Y8
A8
M/S
C54
0.1u
Y7
A7
A6
A5
A4
A3
A2
A1
G2
G1
MCKO
4633_MCKI
DAUX
4633_MCKO
EXT_MCLK
4633_SDTO
RP2
47k
RP3
47k
7
6
5
4
3
2
1
7
6
5
4
3
2
1
A1
A2
A3
A4
A5
A6
A7
A8
Y6
3
B2
Y5
JP26
4633_SDTI DAC/LOOP
4
B3
Y4
4633_SDTI
5
B4
ADC
Y3
6
B5
Y2
7
B6
JP27
BICK
Y1
ADC
EXT_BICK
DIR_BICK
8
B7
4633_BICK
4633_FCK
GND
VCC
DIR
C55
0.1u
9
B8
JP28
FCK
ADC
DIR
EXT_FCK
DIR_FCK
74LVC245
U9
LVC
JP29
U10F
+
C56
47u
13
12
INV
THR
74HC14
BICK_INV
U11
R32
R34
R36
10k
10k
10k
R33
R35
R37
470
470
470
2
3
4
5
6
7
8
9
18
D3.3V
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
CSN
17
16
15
14
13
12
11
CCLK
CDTI
PDN
4633_MCKI
PORT3
MCLK
BICK
FCK
SDTI
VCC
1
2
3
4
5
10
9
8
7
6
PORT4
1
2
3
4
5
10 CSN
9
8
7
6
CCLK
CDTI
1
19
20
10
ROM
G1
G2
VCC
GND
D3.3V
R38
10k
74LVC541
CTRL
D3.3V
ADC
DAUX
D3.3V
JP30
SDTI
R39
10k
D4
HSU119
DIR_SDTI
DIR
U5D
U5E
9
8
11
10
U7A
U2A
U2F
U10B
74HC14
74HC14
1
9
2
13
3
12
1
11
13
2
3
5
9
4
L
H
74HC04
74HCU04
74HCU04
74HC14
SW2
PDN
C57
0.1u
U7B
4
U7E
10
U2D
8
U10C
6
U10E
10
11
1
74HC04
74HC04
74HCU04
74HC14
74HC14
U7C
6
U7F
12
U2E
10
U10D
8
U10A
2
Title
Size
11
5
AKD4633-A
LOGIC
74HC04
74HC04
74HCU04
74HC14
74HC14
Document Number
Rev
3
A3
Date:
Sheet
E
of
Thursday, February 15, 2007
5
5
A
B
C
D
相关型号：
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