AKD4682 [AKM]
Multi-channel CODEC with 2Vrms Stereo Selector; 多通道编解码器与立体声2Vrms的选择
| 型号： | AKD4682 |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Multi-channel CODEC with 2Vrms Stereo Selector |
| 文件： | 总43页 (文件大小：673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK4682]
AK4682
Multi-channel CODEC with 2Vrms Stereo Selector
GENERAL DESCRIPTION
The AK4682 is a single chip CODEC that includes two channels of ADC and four channels of DAC. The ADC
outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. The AK4682 integrates stereo
selector supporting 2Vrms I/O. The AK4682 has a dynamic range of 96dB for ADC, 102dB for DAC and is well
suited for digital TV and home theater system.
FEATURES
ADC/DAC part
Asynchronous ADC/DAC Operation
8:1 Stereo Selector for ADC Input
8:3 Stereo Selector with 2Vrms Output Buffer
2-channel 24bit ADC
- 64x Oversampling
- Sampling Rate up to 48kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 88dB
- Dynamic Range, S/N: 96dB
- Digital HPF for Offset Cancellation
- Channel Independent Digital Volume (+24/-103dB, 0.5dB/step)
- Soft Mute
4-channel 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- S/(N+D): 86dB
- Dynamic Range, S/N: 102dB
- Channel Independent Digital Volume (+12/-115dB, 0.5dB/step)
- Soft Mute
- De-emphasis Filter
- Output Mode: Stereo, Mono, Reverse, Mute
High Jitter Tolerance
TTL Level Digital I/F
External Master Clock Input:
256fs, 384fs, 512fs 768fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs 384fs (fs=64kHz ∼ 96kHz)
128fs, 192fs (fs=120kHz ~ 192kHz)
2 Audio Serial I/F (PORTA, PORTB)
- Master/Slave mode (for PORTB)
- I/F format
PORTA: Left(24 bit)/Right(20/24 bit) justified, I2S, TDM
PORTB: Left justified, I2S
I2C Bus μP I/F for mode setting
Operating Voltage:
- Digital I/O: 2.7V ∼ 5.25V,
- Analog: 4.75V ~ 5.25V and 8.5V ~ 12.6V
Package: 48pin LQFP (0.5mm pitch)
MS0610-E-01
2007/07
- 1 -
[AK4682]
2Vrms
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
PORTB
MCLKB
2ch
HPF, Serial
BICKB
LRCKB
SDTOB
ADC DVOL I/F
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
MSB
2Vrms
LOUT1
ROUT1
LOUT2
ROUT2
PORTA
MCLKA
BICKA
LRCKA
SDTIA1
SDTIA2
L1
2ch DVOL
Serial
Stereo
Matrix
R1
DAC
I/F
L2
2ch DVOL
DAC
Stereo
Matrix
R2
SDA
SCL
Control
I/F
LOUT3
ROUT3
AK4682 Block Diagram
MS0610-E-01
2007/07
- 2 -
[AK4682]
■ Ordering Guide
AK4682EQ
AKD4682
-20 ∼ +85°C
Evaluation Board
48pin LQFP (0.5mm pitch)
■ Pin Layout
24
23
22
21
LIN3
RIN3
NC
37
38
39
40
41
42
43
44
45
46
47
48
LOUT3
PVSS
PVDD
ROUT2
LOUT2
MSB
LIN4
RIN4
NC
AK4682EQ
20
19
18
17
16
15
14
13
LIN5
RIN5
NC
ROUT1
LOUT1
DVSS2
DVDD2
SCL
Top View
LIN6
RIN6
DVDD1
SDA
MS0610-E-01
2007/07
- 3 -
[AK4682]
PIN/FUNCTION
No. Pin Name
I/O
Function
1
2
3
4
5
6
DVSS1
MCLKB
TVDD
LRCKB
BICKB
SDTOB
-
I
-
ADC Digital Ground Pin, 0V
ADC Master Clock Input Pin
Output Buffer Power Supply Pin, 2.7V∼5.25V
I/O Channel Clock B Pin
I/O Audio Serial Data Clock B Pin
O
Audio Serial Data Output B Pin
Power-Down Mode & Reset Pin
7
PDN
I
When “L”, the AK4682 is powered-down, all registers are reset. And then all digital
output pins go “L”. The AK4682 must be reset once upon power-up.
Input Channel Clock A Pin
Audio Serial Data Clock A Pin
DAC Master Clock Input Pin
8
9
LRCKA
BICKA
I
I
I
I
I
10 MCLKA
11 SDTIA1
12 SDTIA2
13 SDA
Audio Serial Data Input A1 Pin
Audio Serial Data Input A2 Pin
I/O Control Data Pin
14 SCL
I
-
-
O
O
Control Data Clock Pin
DAC Digital Power Supply Pin, 4.75V∼5.25V
DAC Digital Ground Pin, 0V
Lch Analog Output Pin1
Rch Analog Output Pin1
15
DVDD2
16 DVSS2
17 LOUT1
18 ROUT1
PORTB Master Mode Select Pin.
“L”(connected to the ground): Master/Slave mode. ORed with MSB bit.
“H”(connected to DVDD2) : Master mode.
Lch Analog Output Pin2
Rch Analog Output Pin2
Output Buffer Power Supply Pin, 8.5V ~ 12.6V.
Output Buffer Ground Pin, 0V.
19 MSB
I
20 LOUT2
21 ROUT2
22 PVDD
23 PVSS
O
O
-
-
24 LOUT3
25 ROUT3
26 AVDD2
27 AVSS2
O
O
-
Lch Analog Output Pin 3
Rch Analog Output Pin 3
DAC Analog Power Supply Pin, 4.75V∼5.25V
DAC Analog Ground Pin, 0V
-
Common Voltage Output Pin for Output Buffer. AVDD2 x 0.734(typ).
10μF capacitor should be connected to AVSS2 externally.
DAC/ADC Common Voltage Output Pin. AVDD2 x 0.6(typ).
10μF capacitor should be connected to AVSS2 externally.
ADC Analog Ground Pin, 0V
28 VCOM36
29 VCOM3
-
-
30 AVSS1
31 AVDD1
32 LIN1
-
-
I
I
ADC Analog Power Supply Pin, 4.75V∼5.25V
Lch Input 1 Pin
33 RIN1
Rch Input 1 Pin
No Connection.
34 NC
-
No internal bonding. This pin should be connected to the ground.
35 LIN2
36 RIN2
37 LIN3
38 RIN3
I
I
I
I
Lch Input 2 Pin
Rch Input 2 Pin
Lch Input 3 Pin
Rch Input 3 Pin
No Connection.
39 NC
-
No internal bonding. This pin should be connected to the ground.
40 LIN4
41 RIN4
I
I
Lch Input 4 Pin
Rch Input 4 Pin
No Connection.
42 NC
-
No internal bonding. This pin should be connected to the ground.
MS0610-E-01
2007/07
- 4 -
[AK4682]
PIN/FUNCTION (continued)
No. Pin Name
43 LIN5
44 RIN5
I/O
I
I
Function
Lch Input 5 Pin
Rch Input 5 Pin
No Connection.
45 NC
-
No internal bonding. This pin should be connected to the ground.
46 LIN6
47 RIN6
48 DVDD1
I
I
-
Lch Input 6 Pin
Rch Input 6 Pin
ADC Digital Power Supply Pin, 4.75V∼5.25V
Note: All digital input pins must not be left floating.
Note: Analog input pins (LIN1, RIN1, LIN2, RIN2, LIN3, RIN3, LIN4, RIN4, LIN5, RIN5, LIN6, RIN6 pin) must use
the AC-coupling capacitor for signal input.
Note: Analog output pins (LOUT1, ROUT1, LOUT2, ROUT2, LOUT3, ROUT3 pins) must use the AC-coupling
capacitor for signal output.
■ Handling of Unused Pin
The unused I/O pins should be processed appropriately as below.
Classification Pin Name
Setting
Analog
LOUT1-3, ROUT1-3, LIN1-6, RIN1-6
SDTOB, LRCKB(Master), BICKB(Master)
These pins should be open.
These pins should be open.
These pins should be connected to DVSS.
MCLKA, LRCKA, BICKA, SDTIA1-2, MCLKB,
LRCKB(Slave), BICKB(Slave), MSB
Digital
SDA, SCL
These pins should be pulled-up to DVDD2.
MS0610-E-01
2007/07
- 5 -
[AK4682]
ABSOLUTE MAXIMUM RATINGS
(AVSS1, AVSS2, DVSS1, DVSS2, PVSS=0V; Note: 1)
Parameter
Power Supply
Symbol
TVDD
DVDD1
DVDD2
AVDD1
AVDD2
PVDD
IIN
min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
max
6.0
6.0
6.0
6.0
6.0
14.0
±10
Units
V
V
V
V
V
V
mA
Input Current (any pins except for supplies)
Digital Input Voltage 1
VIND1
-0.3
DVDD1+0.3
V
(MCLKB pin)
Digital Input Voltage 2
VIND2
-0.3
DVDD2+0.3
V
(PDN, LRCKA, BICKA, MCLKA,
SDTIA1-2, SDA, SCL, MSB pins)
Digital Input Voltage 3
(LRCKB, BICKB pins)
Analog Input Voltage 1
(LIN1-6, RIN1-6 pins)
VIND3
VINA1
-0.3
-0.3
TVDD+0.3
PVDD+0.3
V
V
Ambient Operating Temperature
Storage Temperature
Ta
Tstg
-20
-65
85
150
°C
°C
Note: 1. AVSS1, DVSS1, AVSS2, DVSS2 and PVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS1, AVSS2, DVSS1, DVSS2, PVSS=0V; Note: 1)
Parameter
Power Supply (Note: 2)
Symbol
TVDD
DVDD1
DVDD2
AVDD1
AVDD2
PVDD
min
2.7
4.75
4.75
4.75
4.75
8.5
typ
3.3
5.0
5.0
5.0
5.0
9.0
max
5.25
5.25
5.25
5.25
5.25
12.6
Units
V
V
V
V
V
V
Note: 2. The AVDD1, AVDD2, DVDD1 and DVDD2 must be the same voltage.
The TVDD must not exceed any of AVDD1, AVDD2, DVDD1 and DVDD2 voltage.
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0610-E-01
2007/07
- 6 -
[AK4682]
ANALOG CHARACTERISTICS
(Ta=25°C; TVDD = 3.3V; DVDD1, DVDD2, AVDD1, AVDD2= 5.0V; PVDD = 9V; AVSS1, AVSS2, DVSS1,
DVSS2, PVSS = 0V; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency = 20Hz∼
20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; 20Hz~40kHz at fs=192kHz, all blocks are synchronized, unless
otherwise specified)
Parameter
min
typ
max
Units
Analog Input to Analog Output Characteristics (LIN1-6, RIN1-6 pin to LOUT1-3, ROUT1-3 pin)
S/(N+D)
S/N
Input=2Vrms
Input=0ff, A-weighted
-
-
92
96
dB
dB
Input Impedance
Maximum Input Voltage
Gain
40
2
-
kΩ
Vrms
dB
(Note: 4)
-
0
-
-
Analog Input (LIN1-6, RIN1-6 pin) to ADC Analog Input Characteristics
Resolution
S/(N+D)
DR
S/N
Interchannel Isolation
Interchannel Gain Mismatch
Gain Drift
Input Voltage
Power Supply Rejection
24
Bits
dB
dB
dB
dB
(-1dBFS) fs=48kHz
(-60dBFS) fs=48kHz, A-weighted
(input off) fs=48kHz, A-weighted
80
88
88
90
88
96
96
100
0.2
50
2.2
60
(Note: 3)
0.6
-
2.4
dB
ppm/°C
Vrms
dB
AIN= 2.2 x AVDD1/5
(Note: 5)
2
DAC to Analog Output (LOUT1-3, ROUT1-3 pin) Characteristics
Resolution
24
Bits
S/(N+D)
(0dBFS) fs=48kHz
fs=96kHz
fs=192kHz
(-60dBFS) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
(“0” data) fs=48kHz, A-weighted
fs=96kHz
76
-
-
94
-
-
-
-
94
-
-
86
84
84
102
96
102
96
102
102
96
102
96
102
100
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
DR
S/N
fs=96kHz, A-weighted
fs=192kHz
fs=192kHz, A-weighted
-
-
90
Interchannel Isolation
Interchannel Gain Mismatch
Gain Drift
Output Voltage
Load Resistance
Load Capacitance
Power Supply Rejection
0.2
50
2
0.5
-
2.15
dB
ppm/°C
Vrms
AOUT= 2 x AVDD2/5
(AC Load)
1.85
5
kΩ
pF
dB
30
(Note: 5)
50
Note: 3. This value is the interchannel isolation between all the channels of the LIN1-6 and RIN1-6.
Note: 4. Maximum input level that satisfy S/(N+D)>80dB.
Note: 5. PSR is applied to AVDD1, AVDD2, DVDD1, DVDD2 and PVDD with 1kHz, 50mVpp.
MS0610-E-01
2007/07
- 7 -
[AK4682]
Power Supplies
Parameter
min
typ
max
Units
Power Supply Current
Normal Operation (PDN pin = “H”)
TVDD
DVDD1+AVDD1
DVDD2+AVDD2
PVDD
1
3
mA
mA
mA
mA
37
33
15
55
50
25
Power-Down Mode (PDN pin = “L”; Note: 6)
TVDD
10
10
10
10
100
100
100
100
μA
μA
μA
μA
DVDD1+AVDD1
DVDD2+AVDD2
PVDD
Note: 6. All digital inputs including clock pins (MCLKA, MCLKB, BICKA, BICKB, LRCKA, LRCKB and
SDTIA1-0) are held at DVDD1, DVDD2, DVSS1 or DVSS2.
FILTER CHARACTERISTICS
(Ta=-20°C ~+85°C; TVDD=2.7 ~ 5.25V; DVDD1, DVDD2, AVDD1, AVDD2=4.75 ~ 5.25V; PVDD=8.5 ~ 12.6V;
fs=48kHz)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note: 7)
PB
0
-
-
18.9
-
-
kHz
kHz
kHz
±0.1dB
-0.2dB
-3.0dB
20.0
23.0
Stopband
SB
PR
SA
GD
ΔGD
28.0
68
kHz
dB
dB
1/fs
µs
Passband Ripple
Stopband Attenuation
Group Delay
±0.04
(Note: 8)
16
0
Group Delay Distortion
ADC Digital Filter (HPF):
Frequency Response (Note: 7)
-3dB
-0.1dB
FR
1.0
6.5
Hz
Hz
DAC Digital Filter:
Passband
(Note: 7)
-0.1dB
-6.0dB
PB
0
-
26.2
21.8
-
kHz
kHz
kHz
dB
dB
1/fs
24.0
Stopband
SB
PR
SA
GD
Passband Ripple
Stopband Attenuation
Group Delay
±0.02
54
(Note: 8)
20
DAC Digital Filter + Analog Filter:
FR
FR
FR
dB
dB
dB
Frequency Response: 0 ∼ 20.0kHz
±0.2
±0.3
±1.0
40.0kHz (Note: 9)
80.0kHz (Note: 9)
Note: 7. The passband and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs (DAC). The reference frequency of these responses is 1kHz.
Note: 8. The calculating delay time occurred at digital filtering. This time is from setting the input of analog s signal to
setting the 24bit data of both channels to the output register of PORTB.
For DAC, this time is from setting the 20/24bit data of both channels on input register of PORTA to the
output of analog signal.
Note: 9. 40.0kHz@fs=96kHz, 80.0kHz@fs=192kHz.
MS0610-E-01
2007/07
- 8 -
[AK4682]
DC CHARACTERISTICS
(Ta=-20°C ~+85°C; TVDD=2.7 ~ 5.25V; DVDD1, DVDD2, AVDD1, AVDD2=4.75 ~ 5.25V; PVDD=8.5∼12.6V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
2.2
-
-
-
-
-
0.8
-
V
V
High-Level Output Voltage ( Iout=-400μA)
Low-Level Output Voltage
VOH
VOL
TVDD-0.4
-
V
V
0.4
(Iout= -400μA(except SDA pin), 3mA(SDA pin))
Input Leakage Current
Iin
-
-
±10
μA
SWITCHING CHARACTERISTICS
(Ta=-20°C ~+85°C; TVDD=2.7 ~ 5.25V; DVDD1, DVDD2, AVDD1, AVDD2=4.75 ~ 5.25V; PVDD=8.5∼12.6V; CL=
20pF (except for SDA pin), Cb=400pF(SDA pin))
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fECLK
dECLK
8.192
40
36.864
60
MHz
%
Duty
50
Master Clock (Note: 10)
256fsn, 128fsd:
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd, 128fsq:
Pulse Width Low
Pulse Width High
768fsn, 384fsd, 192fsq:
Pulse Width Low
Pulse Width High
LRCKA (LRCKB) Timing (Slave Mode)
Normal mode
fCLK
8.192
27
27
12.288
20
20
16.384
15
15
24.576
10
10
12.288
18.432
24.576
36.864
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
kHz
kHz
%
TDM 128 mode
LRCKA frequency
“H” time
“L” time
LRCKB Timing (Master Mode)
Normal mode
LRCKB frequency
Duty Cycle
fs
tLRH
tLRL
32
1/128fs
1/128fs
96
48
kHz
ns
ns
fs
Duty
32
kHz
%
50
Power-down & Reset Timing
PDN Pulse Width
PDN “↑” to SDTOB valid
(Note: 11)
(Note: 12)
tPD
tPDV
150
ns
1/fs
522
Note: 10 MCLKB supports only the normal mode (256fsn, 384fsn, 512fsn, 768fsn).
Note: 11 The AK4682 can be reset by bringing the PDN pin = “L”.
Note: 12 These cycles are the number of LRCKB rising from PDN rising.
MS0610-E-01
2007/07
- 9 -
[AK4682]
Parameter
Symbol
min
typ
max
Units
Audio Interface Timing (Slave Mode)
Normal mode(PORTA)
BICKA Period
BICKA Pulse Width Low
Pulse Width High
LRCKA Edge to BICKA “↑” (Note: 13)
BICKA “↑” to LRCKA Edge (Note: 13)
SDTIA1-2 Hold Time
SDTIA1-2 Setup Time
Normal mode(PORTB)
BICKB Period
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
81
32
32
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
324
128
128
80
ns
ns
ns
ns
ns
ns
ns
BICKB Pulse Width Low
Pulse Width High
LRCKB Edge to BICKB “↑” (Note: 13)
BICKB “↑” to LRCKB Edge (Note: 13)
LRCKB to SDTOB (MSB)
BICKB “↓” to SDTOB
TDM 128 mode
80
80
80
tBSD
BICKA Period
BICKA Pulse Width Low
Pulse Width High
LRCKA Edge to BICKA “↑”
BICKA “↑” to LRCKA Edge
SDTIA1-2 Hold Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
81
32
32
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
(Note: 13)
(Note: 13)
SDTIA1-2 Setup Time
Audio Interface Timing (Master Mode)
Normal mode
BICKB Frequency
BICKB Duty
fBCK
dBCK
tMBLR
tBSD
64fs
50
Hz
%
ns
ns
BICKB “↓” to LRCKB Edge
-40
40
20
BICKB “↓” to SDTO
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
tBUF
tHD:STA
-
1.3
0.6
400
-
-
kHz
μs
μs
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
0.1
-
-
0.6
-
-
-
-
-
-
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note: 14)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
0.3
0.3
-
50
400
tF
tSU:STO
tSP
Cb
0
Note: 13 BICK rising edge must not occur at the same time as LRCK edge.
Note: 14 Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 15 I2C is a registered trademark of Philips Semiconductors.
MS0610-E-01
2007/07
- 10 -
[AK4682]
■ Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
VIL
LRCK
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing (Normal mode)
1/fCLK
VIH
VIL
MCLK
LRCK
BICK
tCLKH
tCLKL
1/fsn, 1/fsd
VIH
VIL
tLRH
tLRL
tBCK
VIH
VIL
tBCKH
tBCKL
Clock Timing (TDM 128 mode)
LRCK= LRCKB, LRCKA,
BICK= BICKA, BICKB,
SDTI= SDTIA,
SDTO= SDTOB.
MS0610-E-01
2007/07
- 11 -
[AK4682]
VIH
VIL
LRCK
BICK
tBLR
tLRB
tLRS
VIH
VIL
tBSD
SDTO
50% TVDD
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (Normal mode)
VIH
VIL
LRCK
BICK
tBLR
tLRB
VIH
VIL
tBSD
SDTO
50%TVDD
tSDS
tSDH
VIH
VIL
SDTI
Audio Interface Timing (TDM 128 mode)
MS0610-E-01
2007/07
- 12 -
[AK4682]
LRCK
BICK
50% TVDD
50% TVDD
tMBLR
tBSD
50% TVDD
SDTO
Audio Interface timing (Master Mode)
tPD
VIH
VIL
PDN
tPDV
SDTO
50% TVDD
Power Down & Reset Timing
VIH
VIL
SDA
tLOW tR
tHIGH
tBUF
tF
tSP
VIH
VIL
SCL
tHD:STA
Stop Start
tHD:DAT
tSU:DAT tSU:STA
tSU:STO
Stop
Start
I2C Bus mode Timing
MS0610-E-01
2007/07
- 13 -
[AK4682]
OPERATION OVERVIEW
■ System Clock
The AK4682 has two audio serial interface (PORTA, PORTB) can operate asynchronously. At each PORT, the external
clocks, which are required to operate the AK4682, are MCLKA (MCLKB), LRCKA (LRCKB) and BICKA (BICKB).
The MCLKA (MCLKB) must be synchronized with LRCKA (LRCKB) but the phase is not critical. The PORT A is the
audio data interface for DAC and the PORTB is for ADC.
■ Master/Slave Mode
The MSB pin and MSB bit are internally ORed and select the master/slave mode of PORTB. PORTA is slave mode only.
In master mode, LRCKB pin and BICKB pin are output pins. In slave mode, LRCKA (LRCKB) pin and BICKA
(BICKB) pin are input (Table 1).
The AK4682 is slave mode at power-down (PDN pin = “L”). To change to the master mode, set MSB pin “H” or write
“1” to MSB bit. Until when setting MSB pin “H” or writing “1” to MSB bit, LRCKB and BICKB pins are input pins.
Pull-up (or down) resistor with around 100kohm is required to prevent the floating of these input pins.
MSB bit
(default: “0”)
PORTB (ADC)
BICKB, LRCKB
PORTA (DAC)
BICKA, LRCKA
PDN pin
L
MSB pin
L
H
L
L
H
x
x
0
1
x
Input (slave mode)
Output “L”(master mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
(x: Don’t care)
H
Output (master mode)
Output (master mode)
Table 1. Master/Salve Mode
■ ADC Clock Control
In master mode (MSB bit = “1”), the CKSB1-0 bits select the clock frequency (Table 2). The external clock (MCLKB)
must always be supplied except in the power-down mode. The ADC is in power-down mode until MCLKB is supplied.
CKSB1
CKSB0
Clock Speed
256fs
0
0
1
1
0
1
0
1
(default)
384fs
512fs
768fs
Table 2. PORTB Master Clock Control (ADC Master Mode)
In slave mode (MSB bit = “0”. default), external clocks (MCLKB, BICKB, LRCKB) must always be present whenever
the ADC is in normal operation mode (PDN pin = “H” and PWAD = “1”). The master clock (MCLKB) must be
synchronized with LRCKB but the phase is not critical. If these clocks are not provided, the ADC may draw excess
current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC
must be in the power-down mode (PDN pin = “L” or PWAD = “0”) or in the reset mode (RSTN bit = “0”). After
exiting reset at power-up etc., the ADC is in the power-down mode until MCLKB and LRCKB are input.
MS0610-E-01
2007/07
- 14 -
[AK4682]
LRCKB
fs
MCLKB (MHz)
Sampling
Speed
128fs
192fs
256fs
384fs
512fs
768fs
32.0kHz
44.1kHz
48.0kHz
-
-
-
-
-
-
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Normal
Table 3. System clock example (ADC Slave Mode)
■ DAC Clock Control
External clocks (MCLKA, BICKA, LRCKA) must always be present whenever the DAC is in normal operation mode
(PDN pin = “H” and PWDA = “1”). The master clock (MCLKA) must be synchronized with LRCKA but the phase is
not critical. If these clocks are not provided, the DAC may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the DAC must be in the power-down mode (PDN pin =
“L” or PWDA = “0”) or in the reset mode (RSTN bit = “0”). After exiting reset at power-up etc., the DAC is in the
power-down mode until MCLKA and LRCKA are input.
There are two modes for controlling the sampling speed of DAC. One is the Manual Setting Mode (ACKS bit = “0”)
using the DFS1-0 bits, and the other is Auto Setting Mode (ACKS bit = “1”).
1. Manual Setting Mode (ACKS bit = “0”)
When the ACKS bit = “0”, DAC is in Manual Setting Mode and the sampling speed is selected by DFS1-0 bits (Table
4).
DFS1
DFS0
DAC Sampling Speed (fs)
(default)
0
0
1
1
0
1
0
1
Normal Speed Mode
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
-
Double Speed Mode
Quad Speed Mode
Not Available
(Note: ADC is always in Normal Speed Mode)
Table 4.DAC sampling speed (ACKS bit = “0”, Manual Setting Mode)
LRCKA
fs
32.0kHz
44.1kHz
48.0kHz
MCLKA (MHz)
BICKA (MHz)
256fs
8.1920
11.2896
12.2880
384fs
512fs
768fs
64fs
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
2.0480
2.8224
3.0720
Table 5. DAC system clock example (DAC Normal Speed Mode @Manual Setting Mode)
LRCKA
fs
MCLKA (MHz)
BICKA (MHz)
64fs
128fs
192fs
256fs
384fs
88.2kHz
96.0kHz
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
5.6448
6.1440
Table 6. DAC system clock example(DAC Double Speed Mode @Manual Setting Mode)
MS0610-E-01
2007/07
- 15 -
[AK4682]
LRCKA
Fs
MCLKA (MHz)
192fs 256fs
BICKA (MHz)
128fs
384fs
64fs
176.4kHz
192.0kHz
22.5792
24.5760
33.8688
36.8640
-
-
-
-
11.2896
12.2880
Table 7. DAC system clock example (DAC Quad Speed Mode @Manual Setting Mode)
2. Auto Setting Mode (ACKS bit = “1”)
When the ACKS bit = “1”, DAC is in Auto Setting Mode and the sampling speed is selected automatically by the ratio
MCLKA/LRCKA as shown in the Table 8. and the internal master clock is set to the appropriate frequency (Table 9). In
this mode, the setting of DFS1-0 bits are ignored.
MCLKA
DAC Sampling Speed (fs) LRCKA
512fs, 768fs
256fs, 384fs
128fs, 192fs
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
(Note: ADC is always in Normal Speed Mode)
Table 8. DAC Sampling Speed (ACKS bit = “1”, Auto Setting Mode)
LRCKA
fs
MCLKA (MHz)
Sampling
Speed
128fs
192fs
256fs
384fs
512fs
768fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Normal
22.5792
24.5760
33.8688
36.8640
-
-
-
-
-
-
-
-
Double
Quad
-
-
22.5792
24.5760
33.8688
36.8640
-
-
-
-
Table 9. DAC System clock example (Auto Setting Mode)
■ DAC Audio Data Control
The DAC1, DAC2 bits select the output data for each DAC.
DAC1 bit
DAC1 Source
Normal Mode
TDM Mode
TDMA bit = “0”
TDMA bit = “1”
(default)
0
1
SDTIA1
SDTIA2
L1, R1
L2, R2
Table 10. DAC1 Source Control
DAC2 Source
DAC2 bit
Normal Mode
TDM Mode
TDMA bit = “0”
TDMA bit = “1”
0
1
SDTIA1
L1, R1
L2, R2
(default)
SDTIA2
Table 11. DAC2 Source Control
MS0610-E-01
2007/07
- 16 -
[AK4682]
■ De-emphasis Filter
The AK4682 includes the digital de-emphasis filter (tc=50/15μs) by IIR filter. This filter corresponds to three sampling
frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis filter is off in Double speed mode and Quad speed mode. De-
emphasis of each DAC can be set individually by register.
Mode
DEM11
DEM10
DEM
(DEM21)
(DEM20)
0
1
2
3
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
(default)
Table 12. De-emphasis control
■ ADC Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz and
scales with sampling rate (fs).
■ Audio Serial Interface Format
Each PORTA/B can select independent audio interface format. The TDMA, DIFA1-0 bits control the audio format for
PORTA and support normal mode and TDM128 mode. The DIFB1-0 bits control the audio format for PORTB and
support only normal mode. The default is mode 2. In all modes the serial data is MSB-first, 2’s complement format. The
SDTOB pins are clocked out on the falling edge of BICKB pins and the SDTIA1-0 pins are latched on the rising edge
of BICKA pins.
1. Setting for the PORTA
1-1.Normal mode: TDMA bit = “0” (default)
The TDMA bit = “0” sets the AK4682 audio serial interface format to the normal mode. The DIFA1-0 bits select
following eight serial data format (Table 13).
Mode
DIFA1
bit
DIFA0
bit
SDTIA1-2
LRCKA
BICKA
L/R
I/O
speed
I/O
0
1
2
3
0
0
1
1
0
1
0
1
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
H/L
H/L
H/L
L/H
I
I
I
I
I
I
I
I
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
(default)
Table 13 Audio Interface Format (Normal mode.)
1-2. TDM 128 mode: TDMA bit = “1”
The TDMA bits = “1” set the AK4682 audio serial interface format to the TDM 128 mode. The four channel serial
data (SDTIA1, 2) is input to the SDTIA1 pin. The data of SDTIA2 pin is not used. The TDM 128 mode is not
available in Quad Speed Mode.
Mode
DIFA1
bit
DIFA0
bit
SDTIA1-2
LRCKA
BICKA
start
I/O
speed
I/O
8
9
10
11
0
0
1
1
0
1
0
1
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
I
I
I
I
128fs
128fs
128fs
128fs
I
I
I
I
↑
↑
↑
↓
(default)
Table 14. Audio Interface Format (TDM 128 mode.)
MS0610-E-01
2007/07
- 17 -
[AK4682]
2. Setting for the PORTB
2-1: Normal mode:
The PORTB supports only the normal mode. The DIFB1-0 bits select following eight serial data format (Table 15).
Mode
MSB pin
MSB bit
DIFB1
DIFB0
SDTOB
LRCKB
BICKB
L/R I/O speed I/O
0
0
0
0
0
24bit, L J
H/L
I
I
≥ 48fs
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
x
x
x
x
1
2
3
4
5
6
7
8
9
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
24bit, L J
24bit, L J
24bit, I2S
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
24bit, L J
24bit, L J
24bit, L J
24bit, I2S
H/L
H/L
L/H
H/L
H/L
H/L
L/H
H/L
H/L
H/L
L/H
I
I
I
I
I
I
≥ 48fs
≥ 48fs
≥ 48fs
64fs
64fs
64fs
64fs
64fs
64fs
64fs
(default)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
10
11
64fs
Table 15. Audio Interface Format (Normal mode, x: Don’t care. L J: Left justified.)
MS0610-E-01
2007/07
- 18 -
[AK4682]
LRCK
0
0
0
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
24
28
25
25
29
31
31
31
31
0
0
0
0
1
1
1
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
12 11 10
19 18
0
23 22
12 11 10
19 18
0
23
Don’t Care
8
7
1
0
Don’t Care
8
7
1
0
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0, 4 Timing
LRCK
1
2
8
9
10
24
25
31
0
1
2
8
9
10
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
23 22
0
23 22
16 15 14
23 22
0
23
Don’t Care
8
7
1
0
Don’t Care
8
7
1
0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1, 5 Timing
LRCK
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
30
BICK(64fs)
SDTO(o)
23 22
23 22
2
2
1
1
0
0
23 22
23 22
2
2
1
1
0
0
23
23
Don’t Care
Don’t Care
SDTI(i)
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3.Mode 2, 6 Timing
LRCK
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
23 22
2
2
1
1
0
0
23 22
23 22
2
2
1
1
0
0
Don’t Care
Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3, 7 Timing
MS0610-E-01
2007/07
- 19 -
[AK4682]
128 BICK
LRCKA
(mode 8)
BICKA(128fs)
18
0
18
0
19
0
0
19
19
19
18
19 18
SDTIA1(i)
SDTIA2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
(Don’t Care)
Figure 5. Mode 8 Timing
128 BICK
LRCKA
(mode 9)
BICKA(128fs)
22
0
22
0
23
0
0
19
23
23
22
23 22
SDTIA1(i)
SDTIA2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
(Don’t Care)
Figure 6. Mode 9 Timing
128 BICK
LRCKA
(mode 10)
BICKA(128fs)
22
23 22
0
23
22
23
0
23 22
0
0
23 22
SDTIA1(i)
SDTIA2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
(Don’t Care)
Figure 7. Mode 10 Timing
MS0610-E-01
2007/07
- 20 -
[AK4682]
128 BICK
LRCKA
(mode 11)
BICKA(128fs)
22
0
22
0
23
0
23
23
23
22
23 22
0
SDTIA1(i)
SDTIA2(i)
L2
L1
R1
R2
32 BICK
32 BICK
32 BICK
32 BICK
(Don’t Care)
Figure 8. Mode 11 Timing
MS0610-E-01
2007/07
- 21 -
[AK4682]
■ Digital Volume Control
The AK4682 has channel-independent digital volume control (256 levels, 0.5dB step). The IATL7-0, IATR7-0 bits set
the volume level of each ADC channel (Table 16). The OAT1L7-0, OAT1R7-0, OAT2L7-0 and OAT2R7-0 bits set
each DAC channel (Table 17).
IATL7-0,
Attenuation Level
IATR7-0
00H
01H
02H
:
+24dB
+23.5dB
+22.0dB
:
2FH
30H
31H
+0.5dB
0dB
-0.5dB
:
(default)
FEH
FFH
-103dB
MUTE (-∞)
Table 16.ADC Digital Volume (IATT)
OAT1L7-0,
OAT1R7-0,
OAT2L7-0,
OAT2R7-0
00H
Attenuation Level
+12dB
+11.5dB
+11.0dB
:
01H
02H
:
17H
18H
+0.5dB
0dB
(default)
19H
-0.5dB
:
FEH
FFH
-115dB
MUTE (-∞)
Table 17.DAC Digital Volume (OATT)
ATSAD (ATSDA) bits (Table 18, Table 19) control the transition time of attenuation. The transition between each
attenuation level is the soft transition. Therefore, the switching noise does not occur in the transition.
Mode
0
1
ATSAD
ATT speed
1061/fs
256/fs
(default)
0
1
Table 18. Transition time of attenuation (ADC)
Mode
0
1
ATSDA
ATT speed
1061/fs
256/fs
(default)
0
1
Table 19. Transition time of attenuation (DAC)
MS0610-E-01
2007/07
- 22 -
[AK4682]
The transition between set values is soft transition of 1061 levels in Mode 0. It takes 1061/fs (22ms@fs=48kHz) from
00H to FFH(MUTE) in mode 0. If PDN pin goes to “L”, the IATL7-0, IATR7-0 (OAT1L7-0, OAT1R7-0, OAT2L7-0,
OAT2R7-0) bits are initialized to 30H(18H). The ATTs goes to their default value when RSTN bit = “0”. When RSTN
bit return to “1”, the ATTs fade to their current value.
■ Soft mute operation
The ADC and DAC have the soft mute function. The soft mute operation is performed at digital domain. When the
SMAD/SMDA bits go to “1”, the output signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 18,
Table 19) from the current ATT level. When the SMAD/SMDA bits are returned to “0”, the mute is cancelled and the
output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is
cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and returned to ATT level
by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMAD/SMDA bits
(1)
(1)
ATT Level
Attenuation
(3)
-
∞
GD
GD
(2)
AOUT
Notes:
(1) ATT_DATA×ATT transition time (Table 18, Table 19). For example, in Normal Speed Mode, this time is
1061/fs cycles (256/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
Figure 9. Soft Mute Function
MS0610-E-01
2007/07
- 23 -
[AK4682]
■ Stereo Matrix Control
The AK4682 has independent stereo matrix control for DAC1 and DAC2. The PL23-20 and PL13-10 bits control each
matrix.
PL13
PL12
PL11
PL10 DAC1 Lch Output DAC1 Rch Output
Note
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
R
L
(L+R)/2
MUTE
R
R
R
R
R
L
L
L
L
L
REVERSE
STEREO
(L+R)/2
MUTE
R
(default)
L
(L+R)/2
MUTE
R
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
L
(L+R)/2
MONO
Table 20. PL13-10: DAC1 Stereo Matrix Control
PL23
PL22
PL21
PL20 DAC2 Lch Output DAC2 Rch Output
Note
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
R
L
(L+R)/2
MUTE
R
R
R
R
R
L
L
L
L
L
REVERSE
STEREO
(L+R)/2
MUTE
R
(default)
L
(L+R)/2
MUTE
R
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
L
(L+R)/2
MONO
Table 21. PL23-20: DAC2 Stereo Matrix Control
STEREO: Normal stereo output
REVERSE: L/R Reverse output
MONO: Monaural output
MUTE: Mute operation
MS0610-E-01
2007/07
- 24 -
[AK4682]
The stereo matrix control has the four channel independent soft transition using soft muting function.
DAC1 Lch Setting
(Control Register)
L
(L+R)/2
R
L
R
R
(1)
(1)
(1)
(3)
(3)
(1)
ATT Level
Attenuation
-
∞
GD
(2)
GD
(2)
GD (2)
DAC1 Lch OUT
L
(L+R)/2
L
R
Notes:
(1) ATT_DATA×ATT transition time (Table 18, Table 19). For example, in Normal Speed Mode, this time is
1061/fs cycles (256/fs) at ATT_DATA=00H. ATT transition of the soft-mute is from 00H to FFH
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
Figure 10. Soft Mute Function for Stereo Matrix Control
MS0610-E-01
2007/07
- 25 -
[AK4682]
■ Input Selector, Input Attenuator
The AK4682 includes 8:4 stereo input/output selectors. The AIN2-0, AOUT12-10, AOUT22-20, AOUT32-30 bits set
each input channel (Table 22, Table 23, Table 24, Table 25). To select the DAC1 or DAC2, set PWAD bit = PWDA bit
= PWANA bit = “1”.
AIN3 bit
AIN2 bit
AIN1 bit
AIN0 bit
Input Selector
LIN1 / RIN1
LIN2 / RIN2
LIN3 / RIN3
LIN4 / RIN4
LIN5 / RIN5
LIN6 / RIN6
DAC1L/DAC1R
DAC2L/DAC2R
Mute
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
(default)
Table 22. Input Selector (for ADC, x: Don’t care)
AOUT13 bit AOUT12 bit AOUT11 bit AOUT10 bit
Input Selector
LIN1 / RIN1
LIN2 / RIN2
LIN3 / RIN3
LIN4 / RIN4
LIN5 / RIN5
LIN6 / RIN6
DAC1L/DAC1R (default)
DAC2L/DAC2R
Mute
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
Table 23. Input Selector (for L/ROUT1, x: Don’t care)
AOUT23 bit AOUT22 bit AOUT21 bit AOUT20 bit
Input Selector
LIN1 / RIN1
LIN2 / RIN2
LIN3 / RIN3
LIN4 / RIN4
LIN5 / RIN5
LIN6 / RIN6
DAC1L/DAC1R
DAC2L/DAC2R (default)
Mute
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
Table 24. Input Selector (for L/ROUT2, x: Don’t care)
AOUT33 bit AOUT32 bit AOUT31 bit AOUT30 bit
Input Selector
LIN1 / RIN1
LIN2 / RIN2
LIN3 / RIN3
LIN4 / RIN4
LIN5 / RIN5
LIN6 / RIN6
DAC1L/DAC1R
DAC2L/DAC2R
Mute
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
(default)
Table 25. Input Selector (for L/ROUT3, x: Don’t care)
MS0610-E-01
2007/07
- 26 -
[AK4682]
[Input selector switching sequence]
The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 11).
1. Enable the soft mute before changing channel.
2. Change channel.
3. Disable the soft mute.
SMUTE
(1)
(1)
DATT Level
Attenuation
Channel
(2)
-∞
LIN1/RIN1
LIN2/RIN2
Figure 11. Input channel switching sequence example
The period of (1) varies in the setting value of DATT. It takes 1028/fs to mute when DATT value is +24dB.
When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms
because there is some DC difference between the channels.
MS0610-E-01
2007/07
- 27 -
[AK4682]
■ Power ON/OFF Sequence
The each block of the AK4682 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are
reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the
DAC outputs go to AVDD2 voltage and SDTOB pin goes to “L”. This reset must always be done after power-up.
In slave mode, after exiting reset at power-up etc., the DAC (ADC) starts to operate from the rising edge of LRCKA
(LRCKB) after MLCKA (MCLKB), and then the device is in the power-down mode until MCLKA (MCLKB) and
LRCKA (LRCKB) are input. In slave mode, the DAC (ADC) starts to operate by the input of MLCKA (MCLKB) after
exiting reset.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTOB
becomes available after 522/fs cycles of LRCKB clock. In case of the DAC, an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are AVDD2 voltage during the initialization. Figure 12 shows the
sequences of the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWAD and PWDA bits. These bits don’t initialize the
internal register values. When PWAD bit = “0”, the SDTOB pin goes to “L”. When PWDA bit = “0”, the DAC outputs
go to AVDD2 voltage. Since some click noise may occur, the analog output should muted externally if the click noise
influences system application.
Power
PDN
(1)
522/fs
ADC Internal
State
Init Cycle
Normal Operation
Normal Operation
Power-down
Power-down
516/fs (2)
DAC Internal
State
Init Cycle
(3)
GD
GD
ADC In
(Analog)
ADC Out
(Digital)
(4)
(5)
“0”data
“0”data
“0”data
“0”data
DAC In
(Digital)
(3)
GD
GD
(6)
(6)
(6)
DAC Out
(Analog)
(7)
Clock In
MCLK,LRCK,SCLK
Don’t care
Don’t care
External
Mute
Mute ON
(8)
Mute ON
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(6) Click noise occurs at the rising/falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLKA (MCLKB), BICKA (BICKB), and LRCKA (LRCKB)) are stopped, the AK4682
must be in the power-down mode.
(8) Please mute the analog output externally if the click noise (6) influences system application.
Figure 12. Power-down/up sequence example
MS0610-E-01
2007/07
- 28 -
[AK4682]
■ Reset Function
When RSTN bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The DAC outputs
go to AVDD2 voltage and SDTOB pins go to “L”. Because some click noise occurs, the analog output should muted
externally if the click noise influences system application. The Figure 13 shows the power-up sequence.
RSTN bit
4~5/fs (8)
1~2/fs (8)
Internal
RSTN bit
(1)
516/fs
ADC Internal
State
Digital Block Power-down
Digital Block Power-down
Normal Operation
Normal Operation
Init Cycle
DAC Internal
State
Normal Operation
GD
Normal Operation
(2)
GD
ADC In
(Analog)
(3)
ADC Out
(Digital)
(4)
“0”data
DAC In
(Digital)
“0”data
(2)
GD
GD
(6)
(5)
(6)
DAC Out
(Analog)
(7)
Don’t care
Clock In
MCLK,LRCK,SCLK
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
noise influences system application.
(5) When RSTN bit = “0”, the analog outputs go to AVDD2 voltage.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “0”, and occurs at 1∼2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLKA (MCLKB), BICKA (BICKB), LRCKA (LRCKB)) can be stopped in the reset mode.
When exiting the reset mode, “1” should be written to RSTN bit after the external clocks (MCLKA (MCLKB),
BICKA (BICKB), LRCKA (LRCKB)) are fed.
(8) There is a delay about 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 13. Reset sequence example
MS0610-E-01
2007/07
- 29 -
[AK4682]
■ Serial Control Interface
AK4682 supports the fast-mode I2C-bus system (max: 400kHz).
1. Data transfer
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4682 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave
device pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition
generated by the master device.
1-1. Data validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 14. Data transfer
1-2. START and STOP condition
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start from
the START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All
sequences end by the STOP condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 15. START and STOP conditions
MS0610-E-01
2007/07
- 30 -
[AK4682]
1-3. ACKNOWLEDGE
ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will
release the SDA line (HIGH) after transmitting eight bits. The receiver must pull down the SDA line during the
acknowledge clock pulse so that that it remains stable “L” during “H” period of this clock pulse. The AK4682 will
generates an acknowledge after each byte has been received.
In the read mode, the slave, the AK4682 will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the
STOP condition.
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
Figure 16. Acknowledge on the I2C-bus
1-4. FIRST BYTE
The first byte, which includes seven bits of slave address and one bit of R/W bit, is sent after the START condition. If
the transmitted slave address matches an address for one of the device, the receiver who has been addressed pulls down
the SDA line.
The most significant five bits of the slave address are fixed as “00100”. The next two bits are “10”. These two bits
identify the specific device on the bus. The eighth bit (LSB) of the first byte (R/W bit) defines whether a write or read
condition which the master requests. A “1” indicates that the read operation is to be executed. A “0” indicates that the
write operation is to be executed.
0
0
1
0
0
1
0
R/W
Figure 17. The First Byte
MS0610-E-01
2007/07
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[AK4682]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4682.
After receipt of the start condition and the first byte, the AK4682 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4682. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 18. The Second Byte
After receipt of the second byte, the AK4682 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 19. Byte structure after the second byte
The AK4682 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4682 generates an acknowledge, and awaits the next data again. The master can
transmit more than one words instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next
address automatically. If the address exceeds 0DH prior to generating the stop condition, the address counter will “roll
over” to 00H and the previous data will be overwritten.
S
S
T
O
P
T
A
R
T
Slave
Address
Register
Address(n)
Data(n)
Data(n+1)
Data(n+x)
S
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
Figure 20. WRITE Operation
MS0610-E-01
2007/07
- 32 -
[AK4682]
3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4682.
After transmission of a data, the master can read next address’s data by generating the acknowledge instead of
terminating the write cycle after the receipt of the first data word. After the receipt of each data, the internal 5bits
address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds
0DH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The AK4682 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
3-1. CURRENT ADDRESS READ
The AK4682 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation
would access data from the address “n+1”.
After receipt of the slave address with R/W bit set to “1”, the AK4682 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does
not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues transmission
S
S
T
O
P
T
A
R
T
Slave
Address
Data(n)
Data(n+1)
Data(n+2)
Data(n+x)
S
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
Figure 21. CURRENT ADDRESS READ
3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4682 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues
transmission.
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Slave
Address
Word
Address(n)
Slave
Address
Data(n)
Data(n+1)
Data(n+x)
S
S
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 22. RANDOM READ
MS0610-E-01
2007/07
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[AK4682]
■ Register Map
Addr
00H
01H
02H
Register Name
Powerdown 1
Powerdown 2
D7
0
0
D6
0
0
D5
PWANA
PWDA PWAD
DIFB1 DIFB0
D4
0
D3
0
0
D2
D1
D0
SMAD SMDA RSTN
0
0
0
Audio Data Format
0
0
0
TDMA DIFA1 DIFA0
DAC1 ATSAD ATSDA
03H De-emphasis/ ATT speed DEM21 DEM20 DEM11 DEM10 DAC2
04H
05H
Clock Control
Stereo Matrix Control
0
ACKS
PL22
DFS1
PL21
DFS0
PL20
0
CKSB1 CKSB0
MSB
PL10
AIN0
PL23
PL13
PL12
AIN2
PL11
AIN1
06H Input Selector Control 1 AOUT13 AOUT12 AOUT11 AOUT10 AIN3
07H Input Selector Control 2 AOUT33 AOUT32 AOUT31 AOUT30 AOUT23 AOUT22 AOUT21 AOUT20
08H
09H
0AH
0BH
0CH
0DH
ADC Lch Volume
ADC Rch Volume
DAC1 Lch Volume
DAC1 Rch Volume
DAC2 Lch Volume
DAC2 Rch Volume
IATL7 IATL6
IATR7 IATR6 IATR5
OAT1L7 OAT1L6 OAT1L5 OAT1L4 OAT1L3 OAT1L2 OAT1L1 OAT1L0
OAT1R7 OAT1R6 OAT1R5 OAT1R4 OAT1R3 OAT1R2 OAT1R1 OAT1R0
OAT2L7 OAT2L6 OAT2L5 OAT2L4 OAT2L3 OAT2L2 OAT2L1 OAT2L0
OAT2R7 OAT2R6 OAT2R5 OAT2R4 OAT2R3 OAT2R2 OAT2R1 OAT2R0
IATL5
IATL4
IATR4
IATL3
IATR3
IATL2
IATR2
IATL1
IATR1 IATR0
IATL0
Note: For addresses from 0EH to 1FH, data must not be written.
When PDN pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset, but registers are not initialized to their default values.
Unused bits must contain a “0” data.
MS0610-E-01
2007/07
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[AK4682]
■ Register Definitions
Addr
00H
Register Name
Powerdown 1
Default
D7
0
0
D6
0
0
D5
PWANA
1
D4
0
0
D3
0
0
D2
D1
D0
RSTN
1
SMAD SMDA
0
0
RSTN: Internal timing reset
0: Reset. Registers are not initialized.
1: Normal operation (default)
SMDA: DAC Soft Mute Enable
0: Normal operation (default)
1: All DAC outputs soft-muted
SMAD: ADC Soft Mute Enable
0: Normal operation (default)
1: ADC outputs soft-muted
PWANA: Power management for 2Vrms analog I/O
0: Power OFF
1: Power ON (default)
Addr
01H
Register Name
Powerdown 2
Default
D7
0
0
D6
0
0
D5
D4
D3
0
0
D2
0
0
D1
0
0
D0
0
0
PWDA PWAD
1
1
PWAD: Power-down control of ADC
0: Power-down
1: Normal operation (default)
PWDA: Full-Power-down control of DAC1-2
0: Power-down
1: Normal operation (default)
Addr
02H
Register Name
Audio Data Format
Default
D7
0
0
D6
0
0
D5
D4
D3
0
0
D2
D1
D0
DIFB1 DIFB0
TDMA DIFA1 DIFA0
1
1
0
1
1
DIFA1-0, TDMA: Audio format control for PORTA
Refer Table 13, Table 14.
DIFB1-0: Audio format control for PORTB
Refer Table 15.
MS0610-E-01
2007/07
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[AK4682]
D0
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
03H De-emphasis/ ATT speed DEM21 DEM20 DEM11 DEM10 DAC2
DAC1 ATSAD ATSDA
Default
0
1
0
1
1
0
0
0
ATSDA: DAC digital Attenuator transition time control
ATSAD: ADC digital Attenuator transition time control
Refer Table 18, Table 19.
DAC2-1: DAC Data control
Refer Table 10, Table 11
DEM11-10: DAC1 De-emphasis filter control
DEM21-20: DAC2 De-emphasis filter control
Refer Table 12.
Addr
04H
Register Name
Clock Control
Default
D7
0
0
D6
ACKS
0
D5
DFS1
0
D4
DFS0
0
D3
0
0
D2
D1
D0
MSB
0
CKSB1 CKSB0
0
0
MSB: ADC Master/Slave control
Refer Table 1.
CKSB1-0: ADC Clock control for Master mode.
Refer Table 2.
DFS1-0: DAC Sampling Speed Control
These settings are ignored in Auto Setting Mode. Refer Table 4.
ACKS: DAC Auto Setting Mode
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the DFS1-0 bits are
ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode.
Addr
05H
Register Name
Stereo Matrix Control
Default
D7
PL23
1
D6
PL22
0
D5
PL21
0
D4
PL20
1
D3
PL13
1
D2
PL12
0
D1
PL11
0
D0
PL10
1
PL13-10: DAC1 Stereo Matrix Control.
Refer Table 20.
PL23-20: DAC2 Stereo Matrix Control.
Refer Table 21.
MS0610-E-01
2007/07
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[AK4682]
Addr
06H
Register Name
D7
D6
D5
D4
D3
D2
AIN2
0
D1
AIN1
0
D0
AIN0
0
Input Selector Control 1 AOUT13 AOUT12 AOUT11 AOUT10 AIN3
Default
0
1
1
0
0
AIN3-0: ADC input selector control
0000: LIN1/RIN1 (default)
0001: LIN2/RIN2
0010: LIN3/RIN3
0011: LIN4/RIN4
0100: LIN5/RIN5
0101: LIN6/RIN6
0110: DAC1L/DAC1R
0111: DAC2L/DAC2R
1xxx: Mute (x: don’t care)
AOUT13-10: L/ROUT1 input selector control
0000: LIN1/RIN1
0001: LIN2/RIN2
0010: LIN3/RIN3
0011: LIN4/RIN4
0100: LIN5/RIN5
0101: LIN6/RIN6
0110: DAC1L/DAC1R (default)
0111: DAC2L/DAC2R
1xxx: Mute (x: don’t care)
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
07H Input Selector Control 2 AOUT33 AOUT32 AOUT31 AOUT30 AOUT23 AOUT22 AOUT21 AOUT20
Default
0
0
0
0
0
1
1
1
AOUT23-20: L/ROUT2 input selector control
0000: LIN1/RIN1
0001: LIN2/RIN2
0010: LIN3/RIN3
0011: LIN4/RIN4
0100: LIN5/RIN5
0101: LIN6/RIN6
0110: DAC1L/DAC1R
0111: DAC2L/DAC2R (default)
1xxx: Mute (x: don’t care)
AOUT33-30: L/ROUT3 input selector control
0000: LIN1/RIN1 (default)
0001: LIN2/RIN2
0010: LIN3/RIN3
0011: LIN4/RIN4
0100: LIN5/RIN5
0101: LIN6/RIN6
0110: DAC1L/DAC1R
0111: DAC2L/DAC2R
1xxx: Mute (x: don’t care)
MS0610-E-01
2007/07
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[AK4682]
Addr
08H
09H
Register Name
ADC Lch Volume
ADC Rch Volume
Default
D7
D6
D5
D4
D3
D2
D1
D0
IATL0
IATL7 IATL6 IATL5 IATL4 IATL3 IATL2 IATL1
IATR7 IATR6 IATR5 IATR4 IATR3 IATR2 IATR1 IATR0
0
0
1
1
0
0
0
0
IATL7-0, IATR7-0: ADC Volume level control
Refer Table 16.
Addr
0AH
0BH
0CH
0DH
Register Name
DAC1 Lch Volume
DAC1 Rch Volume
DAC2 Lch Volume
DAC2 Rch Volume
Default
D7
D6
D5
D4
D3
D2
D1
D0
OAT1L7 OAT1L6 OAT1L5 OAT1L4 OAT1L3 OAT1L2 OAT1L1 OAT1L0
OAT1R7 OAT1R6 OAT1R5 OAT1R4 OAT1R3 OAT1R2 OAT1R1 OAT1R0
OAT2L7 OAT2L6 OAT2L5 OAT2L4 OAT2L3 OAT2L2 OAT2L1 OAT2L0
OAT2R7 OAT2R6 OAT2R5 OAT2R4 OAT2R3 OAT2R2 OAT2R1 OAT2R0
0
0
0
1
1
0
0
0
OAT1L7-0, OAT1R7-0, OAT2L7-0, OAT2R7-0: DAC Volume level control
Refer Table 17.
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[AK4682]
SYSTEM DESIGN
Figure 23 shows the system connection diagram. The evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
3.3V to 5V
5V Digital
Analog in
Digital
+
10u
0.1u
1
DVSS1
MCLKB
TVDD
RIN2 36
LIN2
35
2
+
Analog in
5V Analog
3
NC
RIN1
34
33
32
31
30
29
28
27
26
25
10u 0.1u
LRCKB
4
5
BICKB
LIN1
0.1u 10u
+
6
AVDD1
AVSS1
VCOM3
VCOM36
AVSS2
AVDD2
ROUT3
SDTOB
7
PDN
8
LRCKA
BICKA
MCLKA
9
+
+
10
11
12
10u
+
5V Analog
SDTIA1
SDTIA2
0.1u
+
+
9V to 12V
Analog
Digital Ground
Analog Ground
5V Digital
Analog out
Figure 23. Typical Connection Diagram (Master Mode)
Notes:
- DVSS1, AVSS1, DVSS2, AVSS2 and PVSS must be connected the same analog ground plane.
MS0610-E-01
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[AK4682]
1. Grounding and Power Supply Decoupling
The AK4682 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2, DVDD1,
DVDD2, TVDD and PVDD are usually supplied from analog supply in system. If AVDD1, AVDD2, DVDD1, DVDD2
and TVDD are supplied separately, the power up sequence is not critical. AVSS1, DVSS1, AVSS2, DVSS2 and PVSS
of the AK4682 must be connected to analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should
be as near to the AK4682 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The voltage of AVDD1 sets the ADC input range, AVDD2 sets the DAC analog output range. VCOM3 and VCOM36
are signal grounds of this chip. An electrolytic capacitor 10μF parallel with a 0.1μF ceramic capacitor attached between
these VCOM pins and AVSS1 pin eliminates the effects of high frequency noise. No load current may be drawn from
these VCOM pins. All signals, especially clocks, should be kept away from the AVDD1, AVDD2, VCOM3 and
VCOM36 pins in order to avoid unwanted coupling into the AK4682.
3. Analog Inputs
The AK4682 receives the analog input through the single-ended Pre-amp using external resistors. The input range is 2.2
x AVDD1/5 Vrms (typ. fs=48kHz) at each analog input pins. Each input pins are biased internally. The ADC output
data format is 2’s complement. The internal digital HPF removes the DC offset.
The AK4682 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples
of 64fs. The AK4682 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Analog Outputs
The analog outputs are also single-ended and centered on around the AVDD2 voltage. The output signal range scales
with the supply voltage and nominally 2 x AVDD2/5 Vrms at each analog output pins. The DAC input data format is 2’s
complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for
800000H(@24bit). The ideal output is AVDD2 voltage for 000000H(@24bit). The internal analog filters remove most
of the noise generated by the delta-sigma modulator of DAC beyond the audio passband.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets a few mV.
5. Attention to the PCB Wiring
Attention should be given to avoid coupling with other signals on each analog input/output pins. Unused input pins
among LIN1-6 and RIN1-6 pins should be left open.
MS0610-E-01
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[AK4682]
PACKAGE
48pin LQFP(Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
1.40 ± 0.05
36
25
37
24
13
48
1
12
0.145 ± 0.05
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.5 ± 0.2
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0610-E-01
2007/07
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[AK4682]
MARKING
AK4682EQ
XXXXXXX
1
1) Pin #1 indication
2) Asahi Kasei Logo
3) Marking Code: AK4682EQ
4) Date Code: XXXXXXX (7 digits)
REVISION HISTORY
Date (YY/MM/DD)
07/04/24
Revision Reason
Page
12
Contents
00
First Edition
Audio Interface Timing (Normal and TDM128
mode) were changed.
07/07/02
01
Error Correct
MS0610-E-01
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[AK4682]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application
or use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support,
or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the
use approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from
any and all claims arising from the use of said product in the absence of such notification.
MS0610-E-01
2007/07
- 43 -
相关型号：
AKD4683-B
24bit CODEC that has two channels of ADC and four channels of DAC with internal DIR, DIT
AKM
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