ALD500R-50PE [ALD]
PRECISION INTEGRATING ANALOG PROCESSOR WITH PRECISION VOLTAGE REFERENCE; 具有精密电压基准精密积分模拟处理器
| 型号： | ALD500R-50PE |
| 厂家： | 
ADVANCED LINEAR DEVICES |
| 描述： | PRECISION INTEGRATING ANALOG PROCESSOR WITH PRECISION VOLTAGE REFERENCE |
| 文件： | 总12页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED
LINEAR
DEVICES, INC.
ALD500RAU/ALD500RA/ALD500R
PRECISION INTEGRATING ANALOG PROCESSOR
WITH PRECISION VOLTAGE REFERENCE
BENEFITS
APPLICATIONS
• Low cost, simple functionality
• Wide dynamic signal range
• Very high noise immunity
• 4 1/2 digits to 5 1/2 digits plus sign measurements
• Precision analog signal processor
• Precision sensor interface
• Automatic compensation and cancellation
of error sources
• Easy to use to acquire bipolar signals
• Up to 19 bit (18 bit + sign bit) single conversion
or 21 bit (20 bit + sign bit) multiple conversion
and noise performance
• High accuracy DC measurement functions
• Portable battery operated instruments
• Computer peripheral
• PCMCIA
• Inherently linear and stable with temperature
and component variations
FEATURES
• Resolution up to 18 bits plus sign bit and over-range bit
• Accuracy independent of input source impedances
• Accurate on-chip voltage reference
PIN CONFIGURATION
ALD500R
• Tempco as low as 10 ppm/°C guaranteed
• Chip select - power down mode
• High input impedance of 1012
Ω
I
1
2
3
4
5
20
19
18
17
16
15
14
13
12
11
C
V
B
S
• Inherently filters and integrates any external noise spikes
• Differential analog input
• Wide bipolar analog input voltage range ±3.5V
• Automatic zero offset compensation
• Low linearity error - as low as 0.001% typical
• Fast zero-crossing comparator - 1µs
• Low power dissipation - 6mW typical
• Automatic internal polarity detection
• Low input current - 2pA typical
+
C
INT
-
V
DGND
C
C
OUT
AZ
B
B
A
UF
6
7
AGND
-
+
C
V
V
REF
REF
N/C
N/C
IN
+
C
-
8
IN
+
9
V
REF
REF
-
10
• Optional digital control from a microcontroller, an ASIC, or
V
a dedicated digital circuit
• Flexible conversion speed vs. resolution trade-off
QE, PE, SE PACKAGE
N/C pin is connected internally. Connect to V .
-
*
Ordering Information
Resolution Endpoint Voltage Reference
Linearity Accuracy/Tempco
Package Type
Operating
Temperature
20L PDIP
20L SOIC
20L QSOP
ALD500R-50QE
20LCDIP
16 bit
17 bit
18 bit
17 bit
18 bit
17 bit
18 bit
18 bit
0.015%
0.01%
0.5% 50ppm/C
0.3% 20ppm/C
ALD500R-50PE
ALD500R-50SE
0°C to 70°C
0°C to 70°C
ALD500RA-20PE
ALD500RAU-20PE
ALD500RA-10PE
ALD500RAU-10PE
ALD500RA-20PEI
ALD500RA-20SE
ALD500RAU-20SE
ALD500RA-10SE
ALD500RAU-10SE
ALD500RA-20SEI
ALD500RA-20QE
ALD500RAU-20QE
ALD500RA-10QE
ALD500RAU-10QE
ALD500RA-20QEI
0.005%
0.01%
0.2% 10ppm/C
0.3% 20ppm/C
0.3% 20ppm/C
0°C to 70°C
0.005%
0.01%
-40°C to +85°C
0.005%
0.005%
ALD500RAU-20PEI ALD500RAU-20SEI ALD500RAU-20QEI
ALD500RAU-20DE -55°C to +125°C
* Contact factory for customized voltage reference voltage levels, accuracy and tempco specifications.
Rev. 1.01 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706Tel: (408) 747-1155, Fax: (408) 747-1286
http://www.aldinc.com
FIGURE 1. ALD500R Functional Block Diagram
C
REF
R
INT
C
INT
-
V
+
REF
(11)
V
REF
(12)
C
AZ
R
REF
C
INT
(2)
+
-
C
R
C
= 100KΩ
= 0.1µF
C
BUF
(5)
C
AZ
(4)
REF
B
REF
(8)
REF
(7)
REF
INT
SW
SW
R
R
+
-
SW
IN
Buffer
+
Integrator
-
+
V
IN
(14)
+
-
SW
SW
R
R
+
-
Comp1
-
Level
Shift
Comp2
+
C
(17)
OUT
SW
Az
SW
AZ
+
-
SW
SW
SW
R
R
S
Polarity
Detection
DGND
(18)
AGND
(6)
SW
SW
IN
G
-
V
Analog
IN
(13)
Phase
Decoding
Logic
Switch
Control
Signals
REF
Control
Bias
A
B
V
V
N/C N/C
SS DD
(3) (19) (10) (9)
C
B
C
S
(20)
(15) (16)
Control Logic
I
B
(1)
GENERAL THEORY OF OPERATION
GENERAL DESCRIPTION
The ALD500RAU/ALD500RA/ALD500R are integrating
dual slope analog processors, designed to operate on ±5V
power supplies for building precision analog-to-digital
converters. The ALD500RAU/ALD500RA/ALD500R
feature specifications suitable for 18 bit/17 bit/16 bit
resolution conversion, respectively. Together with three
capacitors, tworesistors, andadigitalcontroller, aprecision
Analog to Digital converter with auto zero can be
implemented. The digital controller can be implemented
by an external microcontroller, under either hardware
(fixed logic) or software control. For ultra high resolution
applications, up to 23 bit conversion can be implemented
with an appropriate digital controller and software.
Dual-Slope Conversion Principles of Operation
The basic principle of dual-slope integrating analog to digital
converter is simple and straightforward. A capacitor, CINT, is
charged with the integrator from a starting voltage, VX, for a
fixed period of time at a rate determined by the value of an
unknown input voltage, which is the subject of measurement.
Then the capacitor is discharged at a fixed rate, based on an
external reference voltage, back to VX where the discharge
time, or deintegration time, is measured precisely. Both the
integration time and deintegration time are measured by a
digital counter controlled by a crystal oscillator. It can be
demonstrated that the unknown input voltage is determined
by the ratio of the deintegration time and integration time, and
isdirectlyproportionaltothemagnitudeoftheexternalreference
voltage.
The ALD500R series of analog processors accept
differential inputs and the external digital controller first
counts the number of pulses at a fixed clock rate that a
capacitor requires to integrate against an unknown analog
input voltage, then counts the number of pulses required
to deintegrate the capacitor against a known internal
reference voltage. This unknown analog voltage can then
be converted by the microcontroller to a digital word, which
is translated into a high resolution number, representing
an accurate reading. This reading, when ratioed against
the reference voltage, yields an accurate, absolute voltage
measurement reading.
The major advantages of a dual-slope converter are:
a. Accuracy is not dependent on absolute values of
integration time tINT and deintegration time tDINT, but is
dependent on their relative ratios. Long-term clock frequency
variations will not affect the accuracy. A standard crystal
controlledclockrunningdigitalcountersisadequatetogenerate
very high accuracies.
b. Accuracy is not dependent on the absolute values of
R
INT and CINT, as long as the component values do not vary
The ALD500R analog processors consist of on-chip digital
control circuitry to accept control inputs, integrating buffer
amplifiers, analog switches, and voltage comparators and
a highly accurate, ultra-stable voltage reference. It
functions in four operating modes, or phases, namely auto
zero, integrate, deintegrate, and integrator zero phases.
At the end of a conversion, the comparator output goes
from high to low when the integrator crosses zero during
deintegration. ALD500R analog processors also provide
direct logic interface to CMOS logic families.
through a conversion cycle, which typically lasts less than 1
second.
c. Offset voltage values of the analog components, such
as VX, are cancelled out and do not affect accuracy.
d. Accuracyofthesystemdependsmainlyontheaccuracy
and the stability of the voltage reference value.
2
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
e. Very high resolution, high accuracy measurements
can be achieved simply and at very low cost.
reference voltage is integrated
VREF = Reference Voltage
CINT = Integrating Capacitor value
RINT = Integrating Resistor value
Aninherentbenefitofthedualslopeconvertersystemisnoise
immunity. The input noise spikes are integrated (averaged to
near zero) during the integration periods. Integrating ADCs Actual data conversion is accomplished in two phases: Input
are immune to the large conversion errors that plague SignalIntegrationPhaseandReferenceVoltageDeintegration
successiveapproximationconvertersandotherhighresolution Phase.
converters and perform very well in high-noise environments.
The integrator output is initialized to 0V prior to the start of
Theslowconversionspeedoftheintegratingconverterprovides InputSignalIntegrationPhase. DuringInputSignalIntegration
inherentnoiserejectionwithatleasta20dB/decadeattenuation Phase, internal analog switches connect VIN to the buffer
rate. Interferencesignalswithfrequenciesatintegralmultiples input where it is maintained for a fixed integration time period
oftheintegrationperiodare,theoretically,completelyremoved. (tINT). This fixed integration period is generally determined by
Integrating converters often establish the integration period to a digital counter controlled by a crystal oscillator. The
reject 50/60Hz line frequency interference signals.
application of VIN causes the integrator output to depart 0V at
a rate determined by VIN and a direction determined by the
polarity of VIN.
The relationship of the integrate and deintegrate (charge
and discharge) of the integrating capacitor values are
shown below:
The Reference Voltage Deintegration Phase is initiated
immediately after tINT, within 1 clock cycle. During
ReferenceVoltage Deintegration Phase, internal analog
switchesconnectareferencevoltagehavingapolarityopposite
that of VIN to the integrator input. Simultaneously the same
digital counter controlled by the same crystal oscillator used
above is used to start counting clock pulses. The Reference
VoltageDeintegrationPhaseismaintaineduntilthecomparator
output inside the dual slope analog processor changes state,
indicating the integrator has returned to 0V. At that point the
digital counter is stopped. The Deintegration time period
(tDINT), as measured by the digital counter, is directly
proportional to the magnitude of the applied input voltage.
. .
tINT / RINT CINT)
VINT = VX - (VIN
(integrate cycle)
(1)
(2)
(3)
. .
tDINT / RINT CINT)
VX = VINT - (VREF
(deintegrate cycle)
Combining equations 1 and 2 results in:
IN / VREF = -tDINT / tINT
where:
V
After the digital counter value has been read, the digital
counter, the integrator, and the auto zero capacitor are all
reset to zero through an Integrator Zero Phase and an Auto
Zero Phase so that the next conversion can begin again. In
practice, this process is usually automated so that analog-to-
digital conversion is continuously updated. The digital control
Vx = An offset voltage used as starting voltage
VINT = Voltage change across CINT during tINT and
during tDINT (equal in magnitude)
VIN = Average, or an integrated, value of input voltage
to be measured during tINT (Constant VIN)
tINT = Fixed time period over which unknown voltage is ishandledbyamicroprocessororadedicatedlogiccontroller.
integrated
The output, in the form of a binary serial word, is read by a
microprocessor or a display adapter when desired.
tDINT = Unknown time period over which a known
C
INT
INTEGRATOR
-
R
INT
V
INT
COMPARATOR
-
C
ANALOG
INPUT
OUT
+
(V
)
IN
+
S1
POLARITY
DETECTION
PHASE
CONTROL
SWITCH DRIVER
POLARITY CONTROL
VOLTAGE
REFERENCE
REF
SWITCHES
CONTROL
LOGIC
A
B
V
= 4.1V MAX
INT
V
V
IN ≈ FULL SCALE
MICROCONTROLLER
(CONTROL LOGIC
+ COUNTER)
V
V
IN ≈ 1/2 FULL SCALE
V
x
≈
0
t
DINT
t
t
INT
DINT
Figure 2. Basic Dual-Slope Converter
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
3
ABSOLUTE MAXIMUM RATINGS
+
Supply voltage, V
13.2V
-0.3V to V +0.3V
600 mW
+
Differential input voltage range
Power dissipation
Operating temperature range PE, SE package
Operating temperature range QE package
Storage temperature range
0°C to +70°C
-55°C to +125°C
-65°C to +150°C
+260°C
Lead temperature, 10 seconds
OPERATING ELECTRICAL CHARACTERISTICS
+
-
T
= 25°C V = +5V V = -5V (V supply ± 5V) unless otherwise specified; C = C = 0.47µf
AZ REF
A
500RAU
Typ
500RA
Typ
500R
Typ
Parameter
Symbol
Min
15
Max
Min
30
Max
Min
60
Max
Unit
Test Conditions
Notes 1, 7
Resolution
µV
Zero-Scale
Error
Z
0.0025
0.003
0.003
0.005
0.005
0.008
%
%
0°C to 70°C
SE
End Point
Linearity
E
0.001
0.005
0.007
0.003 0.010
0.015
0.005 0.015
0.020
%
%
Notes 1, 2
0°C to +70°C
NL
Best Case
Straight Line
Linearity
N
0.0025
0.004
0.6
0.003 0.005
0.008
0.003 0.008
0.015
Notes 1, 2
L
0°C to +70°C
0°C to +70°C
Notes 1, 7
Zero-Scale
Temperature
Coefficient
TC
ZS
0.3
0.15
0.3
0.15
0.7
0.3
0.15
0.01
0.012
1.3
0.7
µV/°C
ppm/°C
%
0.3
0.35
0.35
Full-Scale
Symmetry Error
(Rollover Error)
S
0.005
0.008
1.3
0.008
0.010
1.3
0°C to 70°C
YE
%
Full-Scale
TC
FS
ppm/°C
0°C to +70°C
Temperature
Coefficient
Note 7
Input
Current
I
2
2
2
pA
V
V
= 0V
IN
IN
Common-Mode CMVR
Voltage Range
V
+1.5
+0.9
+1.5
V
V
V
-1.5
DD
-0.9
DD
-1.5
DD
V
V
V
+1.5
SS
+0.9
SS
+1.5
SS
V
V
V
-1.5 V +1.5
SS
V
V
V
-1.5
SS
DD
DD
DD
DD
DD
DD
Integrator
Output Swing
VINT
V
SS
-0.9 V +0.9
SS
-0.9
-1.5
V
Analog Input
Signal Range
VIN
V
SS
-1.5 V +1.5
SS
V
AGND = 0V
Voltage
Reference
Range
VREF
V
+1
SS
V
-1
DD
V
SS
+1
V
-1 V + 1
V
-1
DD
V
DD SS
4
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
DC & AC ELECTRICAL CHARACTERISTICS
= 25°C V supply = ±5.0V unless otherwise specified; C = C = 0.47µf
REF
T
A
AZ
500RAU
Typ
500RA
Typ
500R
Typ
0.6
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Test Conditions
+
Supply Current
I
S
0.6
1.0
0.6
1.0
1.0
mA
V
= 5V , A =1,B=1
Power Dissipation
P
10
10
10
mW
V
V supply= ±5V
D
Positive Supply Range
V
+S
4.5
-4.5
4
5.5
4.5
-4.5
4
5.5
4.5
5.5
Note 4
Negative Supply Range
V
-S
-5.5
0.4
1
-5.5
0.4
1
-4.5
4
-5.5
0.4
1
V
V
V
V
V
Note 4
Comparator Logic 1,
Output High
V
OH
I
I
= 400µA
SOURCE
Comparator Logic 0,
Output Low
V
OL
= 1.1mA
SINK
Logic 1, Input High
Voltage
V
IH
3.5
3.5
3.5
Logic 0, Input Low
Voltage
V
IL
Logic Input Current
Comparator Delay
I
t
0.01
1
0.01
1
0.01
1
µA
L
µsec
Note 5
D
Figure 3. ALD500R TIMING DIAGRAM
1 Conversion Cycle
123,093
Clock Pulses
123,093
Clock Pulses
0.5416 µs
~
~
1.8432 MHz Clock
A INPUT
66.667 msec.
66.667 msec.
B INPUT
COUT
NOT VALID
NOT VALID
Positive Input Signal
COUT
Negative Input Signal
Auto Zero
Phase
Input Signal
Integration
Phase
Reference
Voltage
Deintegration
Phase
Integrator Zero
Phase
Auto Zero
Phase
Clock data in
or clock data out
of counters within the
the microcontroller
or fixed logic controller,
as needed.
Fixed period of
approx.1 msec.
Variable
number of
clock pulses.
Fixed number
of clock pulses
by design.
At VIN MAX,
max. number of
clock pulses
Stop counter upon
detection of comparator
output going from high
to low state.
START
REPEAT
CONVERSION
CYCLE
CONVERSION
CYCLE
~
= 246,185
START INTEGRATION CYCLE
START DEINTEGRATION CYCLE
START INTEGRATOR ZERO CYCLE
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
5
DC ELECTRICAL CHARACTERISTICS
T
= 25°C V supply = +5.0V unless otherwise specified; C = C
= 0.47µf, R
= 100KΩ(1% metal film)
A
AZ REF
REF
Parameter
Symbol
500RAU-10
500RA-10
500RAU-20
500RA-20
500RAU-50
Unit
Test Conditions
500RA-50
500R-50
Typ
Min
Typ
Max
Min
Typ
Max
Min
Max
Voltage Reference
V
R
0.998 1.000 1.002 0.997 1.000
1.003 0.995
1.000
1.005
V
Supply Voltage
Rejection Ratio
V
95
3
95
7
95
dB
RSR
Temperature
Coefficient
V
10
20
15
-0.08
10
50 ppm/C°
RTC
Long Term Drift
Warm Up Time
∆V
∆t
/
-0.08
10
-0.08
10
ppm/
1000hrs
Note 7
Note 7
REF
min.
Positive Supply
Operating Voltage Range
V+
V-
I
4.5
5.5
4.5
5.5
4.5
5.5
V
V
Negative Supply
Operating Voltage Range
-5.5
-4.5
-5.5
-4.5
-5.5
-4.5
Power Down Supply
Current
25
25
25
µA
Note 7
PD
NOTES:
1. Integrate time ≥ 66 msec., Auto Zero time ≥ 66 msec., V
= 4V, V = 2.0V Full Scale
IN
INT
Resolution = V
INT
/integrate time/clock period
2. End point linearity at ±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.
3. Rollover Error also depends on C , C , C characteristics.
INT REF AZ
~
4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ±2.5V.
5. Recommended selection of clock periods of one of the following:
t clk = 0.27µsec, 0.54µsec, or 1.09µsec
which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.
6.
R
REF
is 100K Ω 1% metal film, 50 ppm/C.
7. Sample tested parameter.
6
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
PIN DESCRIPTION
Pin No.
Symbol
Description
-
1
I
Bias circuit pin. Connect a 0.1µF capacitor from this pin to V to minimize noise.
B
2
C
INT
Integrator capacitor connection.
-
V
3
Negative power supply.
4
C
The Auto-zero capacitor connection.
The Integrator resistor buffer connection.
This pin is analog ground.
AZ
5
BUF
6
AGND
-
7
C
Negative reference capacitor connection.
Positive reference capacitor connection.
REF
+
C
8
REF
-
Internally connected. Connect to V for normal operation.
9
N/C
N/C
-
10
11
12
13
14
15
16
17
Internally connected. Connect to V for normal operation.
-
V
External voltage reference (-) connection. High impedance load (≥100MΩ) only.
External voltage reference (+) connection. High impedance load (≥100MΩ) only.
Negative analog input.
REF
+
V
REF
-
V
IN
+
V
Positive analog input.
IN
A
B
C
Converter phase control MSB Input.
Converter phase control LSB Input.
Comparator output. C
OUT
is LOW when a negative input voltage is being integrated. A HIGH-to-LOW transition on C
that the Deintegrate phase is completed. C
time the Integrator Zero phase.
is HIGH during the Integration phase when a positive input voltage is being integrated and
signals the processor
is undefined during the Auto-Zero phase. It should be monitored to
OUT
OUT
OUT
18
19
20
DGND
Digital ground.
+
V
Positive power supply.
C
S
Chip select - power down pin. Logic 1 = power on. Logic 0 = power down.
Table 1. Conversion Phase and Control Logic Internal Analog Switch Functions
Switch Functions
Input
Connect
Reference Input Auto Zero
Polarity
Reference
Sample
V
=AGND
IN
System
Offset
Conversion Control
Phase
Logic
+
-
SW
R
SW
SW
SW
SW
SW
SW
S
IN
R or
AZ
R
G
Auto Zero
A = 0, B = 1
A = 1, B = 0
Open
Open
Open
Closed
Open
Closed
Open
Closed
Open
Open
Open
Input Signal
Integration
Closed
Reference Voltage A = 1, B = 1
Deintegration
Open
Open
Closed*
Open
Open
Open
Open
Closed
Closed
Open
Integrator
A = 0, B = 0
Closed
Closed
Output Zero
+
-
R
*SW would be closed for a positive input signal. SW would be closed for a negative input signal.
R
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
7
ALD500RAU/ALD500RA/ALD500RCONVERSIONCYCLE
time and depends on system parameters and component
value selections. The total number of clock pulses or clock
The ALD500RAU/ALD500RA/ALD500R conversion cycle counts, during integration phase determine the resolution of
takes place in four distinct phases, the Auto Zero Phase, the the conversion. For high resolution applications, this total
Input Signal Integration Phase, the Reference Voltage number of clock pulses should be maximized. The basic unit
Deintegration Phase, and the Integrator Zero Phase. A typical
of resolution is in µV/count. Before the end of this phase,
measurementcycleusesallfourphasesinanordersequence comparator output is sampled by the microcontroller. This
as mentioned above. The internal analog switch status for phaseisterminatedbychanginglogicinputsABfrom10to11.
each of these phases is summarized in Table 1.
Reference Voltage Deintegration Phase (DINT Phase)
The following is a detailed description of each one of the four
phases of the conversion cycle.
At the end of the Input Signal Integration Phase, Reference
Voltage Deintegration Phase begins. The previously charged
reference capacitor is connected with the proper polarity to
ramp the integrator output back to zero. The ALD500RAU/
ALD500RA/ALD500Ranalogprocessorsautomaticallyselects
Auto Zero Phase (AZ Phase)
The analog-to-digital conversion cycle begins with the Auto
Zero Phase, when the digital controller applies low logic level the proper logic state to cause the integrator to ramp back
to input A and high logic level to input B of the analog toward zero at a rate proportional to the reference voltage
processor. During this phase, the reference voltage is stored stored on the reference capacitor. The time required to return
on reference capacitor CREF, comparator offset voltage and to zero is measured by the counter in the digital processor
the sum of the buffer and integrator offset voltages are stored
using the same crystal oscillator. The phase is terminated by
on auto zero capacitor CAZ. During the Auto Zero Phase, the the comparator output after the comparator senses when the
comparator output is characterized by an indeterminate integrator output crosses zero. The counter contents are then
waveform.
transferred to the register. The resulting time measurement
is proportional to the magnitude of the applied input voltage.
During the Auto Zero Phase, the external input signal is
disconnected from the internal circuitry of the ALD500RAU/ The duration of this phase is precisely measured from the
ALD500RA/ALD500R by opening the two SWIN analog transition of AB from 10 to 11 to the falling edge of the
switches and connecting the internal input nodes internally to comparator output, usually with a crystal controlled digital
analogground. Afeedbackloop,closedaroundtheintegrator counter chain. The comparator delay contributes some error
and comparator, charges the CAZ capacitor with a voltage to
compensate for buffer amplifier, integrator and comparator comparator delay and overshoot will result in error timing,
in this phase. The typical comparator delay is 1µ . The
sec
offset voltages.
which translates into error voltages. This error can be zeroed
and minimized during Integrator Output Zero Phase and
This is the system initialization phase, when a conversion is corrected in software, to within ±1 count of the crystal clock
ready to be initiated at system turn-on. In practice the
converter can be operated in continuous conversion mode, LSB).
(which is equivalent to within ± 1 LSB, when 1 clock pulse = 1
whereAZphasemustbelongenoughforthecircuitconditions
to settle out any system errors. Typically this phase is set to Integrator Zero Phase ( INTZ Phase)
be equal to tINT
.
This phase guarantees the integrator output is at 0V when the
Auto Zero phase is entered, and that only system offset
voltages are compensated. This phase is used at the end of
Input Signal Integration Phase (INT Phase)
During the Input Signal Integration Phase (INT), the thereferencevoltagedeintegrationandisusedforapplications
ALD500RAU/ALD500RA/ALD500Rintegratesthedifferential with high resolutions. If this phase is not used, the value of the
+
-
voltage across the (V IN) and (V IN) inputs. The differential
Auto-Zero capacitor (CAZ) must be much greater than the
voltage must be within the device's common-mode voltage value of the integration capacitor (CINT) to reduce the effects
range CMVR. The integrator charges CINT for a fixed period of charge-sharing. The Integrator Zero phase should be
of time, or counts a fixed number of clock pulses, at a rate programmed to operate until the Output of the Comparator
determined by the magnitude of the input voltage. During this
phase, the analog inputs see only the high impedance of the
returns "HIGH". A typical Integrator Zero Phase lasts 1msec.
noninverting operational amplifier input of the buffer. The The comparator delay and the controller's response latency
integratorrespondsonlytothevoltagedifferencebetweenthe may result in Overshoot causing charge buildup on the
analog input terminals, thus providing true differential analog integrator at the end of a conversion. This charge must be
inputs.
removed or performance will degrade. The Integrator Output
Zero phase should be activated (AB = 00) until COUT goes
The input signal polarity is determined by software control at high. Atthispoint,theintegratoroutputisnearzero. AutoZero
the end of this phase: COUT = 1 for positive input polarity; Phase should be entered (AB = 01) and the ALD500RAU/
C
OUT = 0 for negative input polarity. The value is, in effect, the ALD500RA/ALD500R is held in this state until the next
sign bit for the overall conversion result.
conversion cycle.
The duration of this phase is selected by design to be a fixed
8
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
+
-
Differential Inputs (V IN,V IN)
(+) or (-) input voltages will cause a roll-over error. This error
can be minimized by using a large reference capacitor in
The ALD500RAU/ALD500RA/ALD500R operates with comparison to the stray capacitance.
differential voltages within the input amplifier common-mode
voltage range. The amplifier common-mode range extends Phase Control Inputs (A, B)
from 1.5V below positive supply to 1.5V above negative
supply. Within this common-mode voltage range, common- The A and B logic inputs select the ALD500RAU/ALD500RA/
mode rejection is typically 95dB.
ALD500R operating phase. The A and B inputs are normally
driven by a microprocessor I/O port or external logic, using
The integrator output also follows the common-mode voltage. CMOS logic levels. For logic control functions of A and B logic
When large common-mode voltages with near full-scale inputs, see Table 1.
differential input voltages are applied, the input signal drives
the integrator output to near the supply rails where the Comparator Output (COUT
)
integrator output is near saturation. Under such conditions,
linearity of the converter may be adversely affected as the By monitoring the comparator output during the Input Signal
integrator swing can be reduced. The integrator output must Integration Phase, which is a fixed signal integrate time
notbeallowedtosaturate. Typically, theintegratoroutputcan period, the input signal polarity can be determined by the
swing to within 0.9V of either supply rails without loss of microcontroller controlling the conversion. The comparator
linearity.
output is HIGH for positive signals and LOW for negative
signals during the Input Signal Integration Phase. The state of
the comparator should be checked by the microcontroller at
the end of the Input Signal Integration Phase, just before
Analog Ground
AnalogGroundisV-IN duringAutoZeroPhaseandReference transition to the Reference Voltage Deintegration Phase. For
Voltage Deintegration Phase. If V- is different from analog very low level input signals noise may cause the comparator
ground, a common-mode voltage exists at the inputs. This output state to toggle between positive and negative states.
common mode signal is rejected by the high common mode For the ALD500RAU/ALD500RA/ALD500R, this noise has
rejection ratio of the converter. In most applications, V
set at a fixed known voltage (i.e., power supply ground). All
other ground connections should be connected to digital At the start of the Reference Voltage Deintegration Phase,
IN
-
is been minimized to typically within one count.
IN
ground in order to minimize noise at the inputs.
comparator output is set to HIGH state. During the Reference
VoltageDeintegrationPhase,themicrocontrollermustmonitor
the comparator output to make a HIGH-to-LOW transition as
the integrator output ramp crosses zero relative to analog
+
-
Differential Reference (V REF, V REF
)
The reference voltage can be anywhere from 1V of the power ground. This transition indicates that the conversion is
supply voltage rails of the converter. Roll-over error is caused complete. The microcontroller then stops and records the
by the reference capacitor losing or gaining charge due to the pulsecount. Theinternalcomparatordelayis1µsec,typically.
straycapacitanceonitsnodes. Thedifferenceinreferencefor The comparator output is undefined during the Auto Zero
Phase.
Positive Input Signal (VIN
)
0V
Negative Input Signal (VIN
)
ANALOG INPUT
REFERENCE
DEINTEGRATE
INTEGRATE
ANALOG INPUT
INTEGRATE
REFERENCE
DEINTEGRATE
INTEGRATOR
OUTPUT
INTEGRATOR
OUTPUT
(V
)
INT
ZERO
CROSSING
ZERO
CROSSING
(V
)
INT
EXTERNAL INPUT
EXTERNAL INPUT
POLARITY DETECTION
POLARITY DETECTION
COMPARATOR
OUTPUT
COMPARATOR
OUTPUT
(C
)
(C
)
OUT
OUT
Figure 4. Comparator Output
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
9
where:
APPLICATIONS AND DESIGN NOTES
VIN MAX = Maximum input voltage desired
(full count voltage)
= Integrating Resistor value
Determination and Selection of System Variables
RINT
Theprocedureoutlinedbelowallowstheusertodeterminethe
values for the following ALD500RAU/ALD500RA/ALD500R
system design variables:
For minimum noise and maximum linearity, RINT should be in
the range of between 50kΩ to 150kΩ .
Integrating Capacitor (CINT
)
(1) Determine Input Voltage Range
(2) Clock Frequency and Resolution Selection
(3) Input Integration Phase Timing
(4) Integrator Timing Components (RINT, CINT
(5) Auto Zero and Reference Capacitors
(6) Voltage Reference
The integrating capacitor should be selected to maximize
integrator output voltage swing VINT, for a given integration
time, without output level saturation. For +/-5V supplies,
recommended VINT range is between +/- 3 Volt to +/-4 Volt.
Using the 20µA buffer maximum output current, the value of
the integrating capacitor is calculated as follows:
)
System Timing
-6
.
CINT = (tINT) (20 x 10 ) / VINT
Figure 3 and Figure 4 show the overall timing for a typical
system in which ALD500RAU/ALD500RA/ALD500R is
interfaced to a microcontroller. The microcontroller drives the
A, B inputs with I/O lines and monitors the comparator output,
COUT, using an I/O line or dedicated timer-capture control pin.
It may be necessary to monitor the state of the comparator
output in addition to having it control a timer directly during the
Reference Deintegration Phase.
where: tINT
VINT
=
=
Input Integration Phase Period
Maximum integrator output
voltage swing
It is critical that the integrating capacitor must have a very low
dielectricabsorption, aschargelossorgainduringconversion
directlyconvertsintoanerrorvoltage. Polypropylenecapacitors
are recommended while Polyester and Polybicarbonate
capacitors may also be used in less critical applications.
There are four critical timing events: sampling the input
polarity;capturingthedeintegrationtime;minimizingovershoot
and properly executing the Integrator Output Zero Phase.
Reference (CREF) and Auto Zero (CAZ) Capacitors
Selecting Input Integration Time
CREF and CAZ must be low leakage capacitors (e.g.
polypropylene types). The slower the conversion rate, the
larger the value CREF must be. Recommended capacitor
values for CREF and CAZ are equal to CINT. Larger values for
CAZ and CREF may also be used to limit roll-over errors.
For maximum 50/60 cycle noise rejection, Input Integration
Time must be picked as a multiple of the period of line
frequency. For example, tINT times of 33msec, 66msec and
100 msec maximize 60Hz line rejection, and 20msec, 40
msec, 80msec, and 100 msec maximize 50Hz line rejection.
Note that tINT of 100 msec maximizes both 60 Hz and 50Hz
line rejection.
Calculate VREF
The reference deintegration voltage is calculated using:
.
.
VREF = (VINT) (CINT) (RINT) / 2(tINT
)
INT and DINT Phase Timing
The ALD500RAU/ALD500RA/ALD500R requires an external
in order to operate properly. This R should be a 1%
metal film 100KΩ resistor, 50 ppm/C. Any other loading must
be high impedance (≥100MΩ).
The duration of the Reference Deintegrate Phase (DINT) is a
function of the amount of voltage charge stored on the
R
REF
REF
integrator capacitor during INT phase, and the value of VREF
.
The DINT phase must be initiated immediately following INT
phaseandterminatedwhenanintegratoroutputzero-crossing
is detected. In general, the maximum number of counts
chosenforDINT phaseistwicetothreetimesthatofINTphase
with VREF chosen as a maximum voltage relative to VIN. For
example, VREF = VIN(max)/2 would be a good reference
voltage.
Converter Noise
The converter noise is the total algebraic sum of the integrator
noise and the comparator noise. This value is typically 14 µV
peak to peak. The higher the value of the reference voltage,
the lower the converter noise. Such sources of noise errors
canbereducedbyincreasedintegrationtimes,whicheffectively
filter out any such noise. If the integration time periods are
selected as multiples of 50/60Hz frequencies, then 50/60Hz
noise is also rejected, or averaged out. The signal-to-noise
ratio is related to the integration time (tINT) and the integration
time constant (RINT) (CINT) as follows:
Integrating Resistor (RINT
)
The desired full-scale input voltage and amplifier output
current capability determine the value of RINT. The buffer and
integrator amplifiers each have a full-scale current of 20µA.
The value of RINT is therefore directly calculated as follows:
-6
.
.
S/N (dB) = 20 Log ((VINT / 14 x 10 ) tINT /(RINT CINT))
RINT
= VIN MAX / 20 µA
This converter noise can also be reduced by using multiple
samples and mathematically averaged. For example, taking
16samplesandaveragingthereadingsresultinamathematical
(by software) filtering of noise to less than 4µV.
10
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
DESIGN EXAMPLES
We now apply these equations in the following
design examples.
EQUATIONS AND DERIVATIONS
Dual Slope Analog Processor equations and derivations
are as follows:
t
INT
.
.
1
V
t
(1)
REF DINT
∫
V
(t)dt =
IN
Design Example 1:
.
R
C
INT
0
INT
R
C
INT
INT
For V (t) = V (constant):
IN
IN
1. Pick resolution = 16 bit.
1
2. Pick t
= 4x
= 4 x 16.6667 msec.
= 66.6667ms
INT
.
V
t
1
.
REF DINT
60Hz
(2)
.
t
V
=
IN
INT
.
C
INT
R
.
C
INT
R
INT
INT
= 0.0666667 sec.
t
t
DINT
(2a)
(3)
.
. .
V
= V
REF
IN
3. Pick clock period = 1.08507 µs and number of counts
INT
0.0666667
= 61440
over t
=
INT
.
t
I
INT
B
-6
C
=
1.08507x10
INT
V
INT
4. Pick V MAX value, e.g., V MAX = 2.0 V
IN
I MAX = 20µA
IN
At V MAX, the current I is also at a maximum level,
IN
B
2.0
for a given R
value:
INT
R
INT
=
= 100 kΩ
B
-6
20x10
V
IN
I
B
V
MAX
IN
(4)
R
INT
=
=
5. Applying equation (3) to calculate C
-6
INT:
I MAX
B
C
INT
= (0.0666667)(20x10 )/4 where V
~
= 4.0V
INT
From equation (2a),
0.33 µF
=
.
V
t
IN INT
(5a)
(5b)
~
and C ≥ C : C C
REF AZ
= =
~
V
=
6. Pick C
0.33 µF
REF
REF
AZ
INT
= 133.3333 msec
t
DINT
OR
7. Pick t
= 2 x t
INT
DINT
.
t
V
MAX
IN
INT
MAX
V
=
REF
.
.
R
INT
V
INT
MAX
C
INT
t
DINT
8. Calculate V
=
V
REF
t
MAX
DINT
Rearranging equations (3) and (4):
.
-6
3
C
V
INT
4 x 0.33 x 10 x 100 x 10
INT
t
=
(6)
(7)
INT
=
V
-3
I
133.3333 x 10
B
and
V
MAX
IN
~
=
1.00V
I MAX =
B
R
INT
At V
V
MAX, equation (6) becomes:
INT = INT
.
Design Example 2:
1. Select resolution of 17 bit. Total number of
C
=
V
MAX
INT
INT
t
INT
(6a)
I MAX
B
counts during t
is131,072.
INT
Combining (6a) and (7):
.
.
R
INT
.
C
V
MAX
INT
INT
MAX
. .
(8)
t
=
2. We can pick t
of 16.6667 msec. x 5 = 83.3333 msec.
INT
INT
V
IN
In equation (5b), substituting equation (8) for t
or alternately, pick t
equal
INT
16.6667 msec. x 6 = 100.00 msec.
(for 60 Hz rejection)
:
INT
.
.
R
INT
C
INT
V
INT
MAX
which is t
= 20.00 msec. x 5
INT
.
V
MAX
V
MAX
IN
IN
(9)
= 100.00 msec. (for 50 Hz rejection)
V
=
=
REF
t
MAX
DINT
.
.
Therefore, using t
= 100 msec. would achieve
C
V
INT
MAX
MAX
R
INT
INT
INT
both 50 Hz and 60 Hz cycle noise rejection. For this
example, the following calculations would assume
t
DINT
t
of 100 msec. Now select period equal to
For t
MAX = 2 x t
,
INT
0.5425 µsec. (clock frequency of 1.8432 MHz)
DINT
INT
equation (9) becomes:
.
.
R
INT
C
V
MAX
INT
INT
2t
(10)
V
=
REF
INT
ALD500RAU/ALD500RA/ALD500R
Advanced Linear Devices
11
3. Pick V MAX = ±2V
IN
Design Example 4:
Objective: 5 1/2 digit + sign +over-range measurement.
For I MAX = 20µA, applying equation (4),
B
1. Pick t
= 133.333 msec. for 60Hz noise rejection.
INT
2
R
=
= 100 KΩ
INT
(16.6667 msec. x 8 cycles)
Frequency = 1.8432 MHz
clock period = 0.5425 µsec.
-6
20x10
4. Calculate, using equation (3) for C
-6
:
INT
C
= (0.1) x (20 x 10 /4)
~
INT
During Input Integrate Phase,
(assume V MAX = 4V)
= 0.5 µF
INT
-3
133.333 x 10
total count =
-6
0.5425 x 10
Use C
INT
0.47µF as the closest practical value.
= 245776
5. Pick C
and C = 0.47 µF
AZ
REF
For V
= 4.0V, the basic resolution is
INT
6. Pick t
= 2 x t
= 200 msec.
INT
DINT
4
or 16.276 µV/count
245776
7. Calculate the value for V
, from equation (10):
REF
For V MAX = 2.00V, the input resolution is
IN
.
.
V
REF
=
C
V
MAX
R
INT
V
MAX
INT
INT
IN
16.276
x
= 8.138 µV/count
V MAX
INT
t
MAX
DINT
-6
3
0.5 x 10 x 4 x 100 x 10
2. Pick V range = ± 2V
IN
=
-3
200 x 10
2
= 100 KΩ
For I = 20 µA, R
INT
=
B
= 1.00V
-6
20 x 10
~
-6
= (0.133333) x (20 x 10 )/4 = 0.67 µF
3. Calculate C
INT
Design Example 3:
4. Pick C
REF
= C = 0.67 µF
AZ
1. Pick resolution of 18 bit. Total number of counts during
t
is 262,144.
5. Select t
DINT
= 2 x t
= 266.667 msec.
INT
INT
2. Pick t
= 16.66667 msec. x 10 cycles
= 0.1666667 sec.
6. Calculate V
as shown in Design Example 1,
INT
REF
substituting the appropriate values:
.
.
R
INT
C
V
MAX
INT
INT
MAX
V
=
This t
allows clock period of 0.5425 µsec.
REF
INT
and still achieve 18 bits resolution.
t
DINT
~
= 1.005V
3. Again, as shown from previous example, pick V MAX = ±2V
IN
2
For I MAX = 20 µA,
R
=
INT
= 100 KΩ
B
-6
20x10
4. Next, we calculate C
INT:
-6
C
INT
= (0.1666667) x (20 x 10 )/4
~
(V MAX = 4.0V)
INT
= 0.83 µF
In this case, use CINT = 1.0 µF to keep
V
INT
< 4.0V
5. Pick C
and C = 1.0 µF
AZ
REF
6. Select t
DINT
= 2 x t
= 333.333 msec.
INT
7. Calculate V
as shown in the previous examples
REF
= 1.00V
and V
REF
12
Advanced Linear Devices
ALD500RAU/ALD500RA/ALD500R
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