A119X [ALLEGRO]
Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches;
| 型号： | A119X |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches |
| 文件： | 总22页 (文件大小：815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A119x and A119x-F
Programmable, Chopper-Stabilized, Two-Wire Hall-Effect Switches
FEATURES AND BENEFITS
▪ꢀChoiceꢀofꢀfactory-setꢀtemperatureꢀcoefficientꢀ(TC)ꢀforꢀuseꢀ
with ferrite or rare-earth magnets
▪ꢀFieldꢀprogrammableꢀforꢀoptimizedꢀswitchpoints
▪ꢀAEC-Q100ꢀautomotiveꢀqualified
▫ꢀOn-boardꢀvoltageꢀregulator:ꢀ3ꢀtoꢀ24ꢀVꢀoperation
▪ꢀHigh-speed,ꢀ4-phaseꢀchopperꢀstabilization
▫ꢀLowꢀswitchpointꢀdriftꢀthroughoutꢀtemperatureꢀrange
▫ꢀLowꢀsensitivityꢀtoꢀthermalꢀandꢀmechanicalꢀstresses
▪ꢀOn-chipꢀprotectionꢀ
DESCRIPTION
The A119x and A119x-F comprise a family of two-wire,
unipolar, Hall-effect switches, which can be trimmed by the
user at end-of-line to optimize magnetic switchpoint accuracy
in the application. The latter (-F option) are temperature-
compensated for use with ferrite magnets. These devices are
producedontheAllegro™ advancedBiCMOSwaferfabrication
process,which implementsapatentedhigh-frequency,4-phase,
chopper stabilization technique. This technique achieves
magnetic stability over the full operating temperature range,
and eliminates offsets inherent in devices with a single Hall
element that are exposed to harsh application environments.
▫ꢀSupplyꢀtransientꢀprotection
▫ꢀReverse-batteryꢀprotection
▫ꢀIndustry-leadingꢀISOꢀ7637-2ꢀperformanceꢀthroughꢀuseꢀofꢀ
proprietary,ꢀ40ꢀVꢀclampingꢀstructure
▪ꢀSolid-stateꢀreliability
▪ꢀRobustꢀEMCꢀandꢀESDꢀperformanceꢀ
▪ꢀUBꢀpackageꢀwithꢀintegratedꢀ0.1ꢀµFꢀbypassꢀcapacitor
The A119x and A119x-F family has a number of automotive
applications.Theseincludesensingseattrackposition,seatbelt
bucklepresence,hood/trunklatching,andshiftselectorposition.
Two-wire unipolar switches are particularly advantageous in
cost-sensitive applications because they require one less wire
for operation versus the more traditional open-collector output
switches. Additionally, the system designer inherently gains
diagnostics because there is always output current flowing,
which should be in either of two narrow ranges. Any current
level not within these ranges indicates a fault condition.
Packages
3-pin SOT23-W
2 mm × 3 mm × 1
mm (suffix LH)
3-pin ultramini SIP
1.5 mm × 4 mm × 3
mm (suffix UA)
2-pin ultramini SIP
1.5 mm × 4 mm × 4
mm (suffix UB)
All family members are offered in three package styles. The LH
is a SOT-23Wstyle, miniature, low-profile package for surface-
mount applications. The UA is a 3-pin, ultra-mini, single inline
package(SIP)forthrough-holemounting.TheUBisa2-pinsingle
inline package (SIP) for through-hole mounting that integrates
the power supply decoupling capacitor. All three packages are
lead (Pb) free, with 100% matte-tin leadframe plating.
Not to scale
UB package only
0.1 µF
V+
VCC
Program/Lock
OffsetAdjust
ICC Adjust
Regulator
To all subcircuits
LH & UA
package
only
Clock/Logic
0.01 µF
Polarity
Amp
Schmitt
Trigger
Low-Pass
Filter
GND
UA package only
GND
Functional Block Diagram
A1190-DS, Rev. 7
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
SELECTION GUIDE
Output (ICC) in
South Polarity
Field
Supply Current
at ICC(L)
Magnetic Operate
Point, BOP
(G)
Temperature
Coefficient
Part Number
Package
Packing1
(mA)
A1190LLHLT-T2
A1190LLHLX-T
A1190LUA-T3
LH (3-pin SOT23-W surface-mount)
LH (3-pin SOT23-W surface-mount)
UA (3-pin SIP through-hole)
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel
Bulk, 500 pieces/bag
SmCo
SmCo
SmCo
SmCo
SmCo
Ferrite
SmCo
Ferrite
SmCo
Ferrite
SmCo
Ferrite
SmCo
Ferrite
SmCo
Ferrite
SmCo
Ferrite
SmCo
Ferrite
2 to 5
A1190LUBTN-T
A1192LLHLT-T2
UB (2-pin SIP through-hole)
13-in. reel, 4000 pieces/reel
7-in. reel, 3000 pieces/reel
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel
13-in. reel, 10000 pieces/reel
Bulk, 500 pieces/bag
LH (3-pin SOT23-W surface-mount)
A1192LLHLT-F-T2 LH (3-pin SOT23-W surface-mount)
A1192LLHLX-T LH (3-pin SOT23-W surface-mount)
A1192LLHLX-F-T LH (3-pin SOT23-W surface-mount)
Low
A1192LUA-T3
UA (3-pin SIP through-hole)
UA (3-pin SIP through-hole)
UB (2-pin SIP through-hole)
A1192LUA-F-T3
A1192LUBTN-T
Bulk, 500 pieces/bag
10 to 200
13-in. reel, 4000 pieces/reel
13-in. reel, 4000 pieces/reel
7-in. reel, 3000 pieces/reel
7-in. reel, 3000 pieces/reel
13-in. reel, 10000 pieces/reel
13-in. reel, 10000 pieces/reel
Bulk, 500 pieces/bag
A1192LUBTN-F-T UB (2-pin SIP through-hole)
A1193LLHLT-T2
LH (Surface mount)
A1193LLHLT-F-T2 LH (Surface mount)
A1193LLHLX-T LH (Surface mount)
A1193LLHLX-F-T LH (Surface mount)
5 to 6.9
High
A1193LUA-T3
UA (3-pin SIP through-hole)
A1193LUA-F-T3
A1193LUBTN-T
UA (3-pin SIP through-hole)
UB (2-pin SIP through-hole)
Bulk, 500 pieces/bag
13-in. reel, 4000 pieces/reel
13-in. reel, 4000 pieces/reel
A1193LUBTN-F-T UB (2-pin SIP through-hole)
™
1 Contact Allegro for additional packing options.
2 These variants available only through authorized distributors.
3 Contact factory for availability.
RoHS
COMPLIANT
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
VCC
Notes
Rating
28
Unit
V
Forward Supply Voltage
Reverse Supply Voltage
VRCC
B
–18
V
Magnetic Flux Density
Unlimited
–40 to 150
165
G
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
TA
Range L
ºC
ºC
ºC
TJ(max)
Tstg
–65 to 170
INTERNAL DISCRETE CAPACITOR RATINGS (UB PACKAGE ONLY)
Characteristic
Rated Normal Capacitance
Rated Voltage
Symbol
CSUPPLY
VCSUPPLY
Notes
Rating
0.1
Unit
µF
V
Connected between VCC and GND
50
Rated Capacitor Tolerance
Temperature Designator
±10
%
X7R
–
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
PINOUT DIAGRAMS AND TERMINAL LIST TABLE
Pinout Diagrams
3
NC
2
1
2
2
1
1
3
LH Package
UA Package
UB Package
Terminal List Table
Name
Number
Function
LH package UA package
UB package
Connects power supply to chip;
used to apply programming
signal
1
VCC
VCC
VCC
LH package: no connection, it
is highly recommended that this
pin be tied to GND
2
3
NC
GND
GND
GND
–
UA, UB package: ground
terminal
GND
Ground terminal
PROGRAMMABLE PARAMETERS
Quantity
of Bits
Name
Functional Description
B
OP Trim
Fine trim of Programmable Magnetic Operating Point
Lock access to programming
6
1
Programming Lock
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
ELECTRICAL CHARACTERISTICS: Valid at TA = –40°C to 150°C, TJ < TJ(max), through operating supply voltage range, unless
otherwise noted
Characteristics
Supply Voltage1
Symbol
Test Conditions
Operating, TJ ≤ 165 °C
Min.
3
Typ.
–
Max.
24
5
Unit
V
VCC
A1190
B > BOP
B > BOP
B < BRP
B < BRP
B > BOP
2
–
mA
mA
mA
mA
mA
V
ICC(L)
A1192, A1192-F
A1193, A1193-F
A1190, A1192, A1192-F
A1193, A1193-F
5
–
6.9
6.9
17
17
–
Supply Current
5
–
12
12
28
–
ICC(H)
–
Supply Zener Clamp Voltage
Supply Zener Clamp Current
Reverse Supply Current
VZ(sup)
IZ(sup)
IRCC
ICC = ICC(L)(max) + 3 mA, TA = 25°C
VZ(sup) = 28 V
–
ICC(L)(max)
+ 3 mA
–
–
–
–
–
mA
mA
VRCC = –18 V
–1.6
–
LH, UA package (no bypass capacitor2);
capacitance of probe CS = 20 pF
90
mA/µs
Output Slew Rate
di/dt
fC
UB package (integrated capacitor3);
capacitance of probe CS = 20 pF
–
–
–
0.22
700
–
–
–
mA/µs
kHz
µs
Chopping Frequency
LH, UA packages: A1190,
A1192, A1192-F
CBYP = 0.01 µF,
B >BOP +10 G
25
UB package3: A1190, A1192,
A1192-F
B >BOP +10 G
–
–
–
–
25
25
µs
µs
Power-Up Time4
ton
LH, UA packages: A1193,
A1193-F
CBYP = 0.01 µF,
B < BRP –10 G
UB package3: A1193, A1193-F B < BRP –10 G
ton < ton(max), VCC slew rate > 25 mV/µs
–
–
–
25
–
µs
–
Power-Up State5,6
POS
ICC(H)
1 VCC represents the generated voltage between the VCC pin and the GND pin.
2 Measured without bypass capacitor between VCC pin and the GND pin. Use of a bypass capacitor results in slower current change.
3 Measured with internal bypass capacitor (0.1 µF) between VCC and GND. Additional bypass capacitance results in slower current change.
4 Guaranteed by characterization and design.
5 Power-Up State as defined is true only with a VCC slew rate of 25 mV/µs or greater.
6 For t > ton and BRP < B < BOP, Power-Up State is not defined.
MAGNETIC CHARACTERISTICS1: Valid at TA = –40°C to 150°C, TJ ≤ TJ (max), unless otherwise noted
Characteristics
Initial Operate Point
Symbol
Test Conditions
Min.
Typ.
Max.
Unit2
BOP(init)
–
–14
10
G
Programmable Magnetic
Operating Point
BOP
TA = 25°C
10
–
200
G
Average Magnetic Step Size3
Switchpoint Temperature Drift
Hysteresis
STEPBOP TA = 25°C, VCC = 5 V
3
–
–
5
4.8
±20
–0.25
–
7.5
–
G
G
A1190, A1192, A1193
ΔBOP
A1192-F, A1193-F
10 to 200 G
–
%/°C
G
BHYS
30
1 Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north
magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).
2 1 G (gauss) = 0.1 mT (millitesla).
3 STEPBOP is a calculated average from the cumulative programmed bits.
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
THERMAL CHARACTERISTICS: may require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions*
Value Unit
Package LH, on 1-layer PCB based on JEDEC standard
228
110
165
213
ºC/W
ºC/W
ºC/W
ºC/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side
Package UA, on 1-layer PCB with copper limited to solder pads
Package UB, on 1-layer PCB with copper limited to solder pads
Package Thermal Resistance
RθJA
*Additional thermal information available on the Allegro website.
Power Derating Curve
25
24
23
V
CC(max)
22
21
20
19
18
17
16
15
14
13
12
11
10
9
2-layer PCB, Package LH
(RθJA = 110ºC/W)
1-layer PCB, Package UA
(RθJA = 165ºC/W)
1-layer PCB, Package UB
(RθJA = 213ºC/W)
8
7
6
5
1-layer PCB, Package LH
(RθJA = 228ºC/W)
4
V
CC(min)
3
2
20
40
60
80
100
120
140
160
180
Temperature (ºC)
Power Dissipation vs. Ambient Temperature
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000
900
2-layer PCB, Package LH
(RθJA = 110ºC/W)
1-layer PCB, Package UA
(RθJA = 165ºC/W)
1-layer PCB, Package UB
(RθJA = 213ºC/W)
800
700
600
500
1-layer PCB, Package LH
(RθJA = 228ºC/W)
400
300
200
100
0
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Characteristic Performance
A1190
A1190
Average Supply Current (Low) versus Supply Voltage
Average Supply Current (Low) versus Temperature
5.0
4.5
4.0
5.0
4.5
4.0
T
= 150°C
A
T
= 25°C
A
V
= 24 V
= 3.0 V
CC
3.5
3.0
2.5
2.0
3.5
3.0
2.5
2.0
V
CC
T
= –40°C
A
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Supply Voltage, VCC (V)
Ambient Temperature, TA (°C)
A1192, A1193
A1192, A1193
Average Supply Current (Low) versus Supply Voltage
Average Supply Current (Low) versus Temperature
7.0
7.0
6.5
6.5
T
T
= 150°C
= –40°C
A
V
= 24 V
= 3.0 V
CC
A
6.0
5.5
5.0
6.0
5.5
5.0
T
A
= 25°C
V
CC
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Supply Voltage, VCC (V)
Ambient Temperature, TA (°C)
A1190, A1192, A1193
A1190, A1192, A1193
Average Supply Current (High) versus Supply Voltage
Average Supply Current (High) versus Temperature
17
17
16
16
T
T
= –40°C
= 150°C
= 25°C
A
V
= 24 V
CC
15
14
13
12
15
14
13
12
A
V
= 3.0 V
CC
T
A
2
6
10
14
18
22
26
-60
-40
-20
0
20
40
60
80
100 120 140 160
Supply Voltage, VCC (V)
Ambient Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
A1190, A1192, A1193
Average Switchpoint Hysteresis versus Temperature
30
25
20
15
V
V
= 24 V
= 3.0 V
CC
CC
10
5
-60
-40
-20
0
20
40
60
80
100 120 140 160
Ambient Temperature, T (°C)
A
A1190, A1192, A1193
Average Operate Point versus Code
160
140
120
100
80
Bit #5
Bit #4
60
B
OP(init)
40
Bit #3
20
Bit #2
Bit #1
Bit #0
0
-20
0
4
8
12
16
20
24
28
32
36
Code
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
FUNCTIONAL DESCRIPTION
The A1190, A1192, and A1192-F output, ICC, switches low after
the magnetic field at the Hall sensor IC exceeds the operate point
threshold, BOP. When the magnetic field is reduced to below the
release point threshold, BRPꢀ, the device output goes high. This is
shown in figure 1, panel A.
at the Hall sensor IC exceeds the operate point threshold, BOP
When the magnetic field is reduced to below the release point
threshold, BRP, the device output goes low (panel B).
.
The difference between the magnetic operate and release points
is called the hysteresis of the device, BHYS. This built-in hyster-
esis allows clean switching of the output even in the presence of
In the case of reverse output polarity, as in the A1193 and
A1193-F, the device output switches high after the magnetic field external mechanical vibration and electrical noise.
I+
I+
ICC(H)
ICC(H)
ICC(L)
ICC(L)
0
0
B+
B–
B+
B–
BHYS
BHYS
(A) Hysteresis curve for A1190, A1192, and A1192-F
(B) Hysteresis curve for A1193 and A1193-F
Figure 1. Alternative switching behaviors are available in the A119x device family. On the horizontal axis, the B+ direction indicates
increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the
case of increasing north polarity).
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
V+
VCC
RSENSE
A119x
V+
VCC
CBYP
0.01 µF
CBYP
0.01 µF
A119x
GND
GND
ECU
RSENSE
(A) Low-Side Sensing (LH package)
(B) High-Side Sensing (LH package)
V+
VCC
RSENSE
VCC
A119x
V+
CBYP
0.01 µF
CBYP
0.01 µF
A119x
GND
GND
GND
GND
ECU
RSENSE
(C) Low-Side Sensing (UA package)
(D) High-Side Sensing (UA package)
V+
VCC
RSENSE
A119x
V+
VCC
A119x
0.1 µF
0.1 µF
GND
GND
ECU
RSENSE
(E) Low-Side Sensing (UB package)
(F) High-Side Sensing (UB package)
Figure 2. Typical application circuits
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
itsꢀoriginalꢀspectrumꢀatꢀbaseꢀband,ꢀwhileꢀtheꢀDCꢀoffsetꢀbecomesꢀ
a high-frequency signal. The magnetic-sourced signal then can
passꢀthroughꢀaꢀlow-passꢀfilter,ꢀwhileꢀtheꢀmodulatedꢀDCꢀoffsetꢀisꢀ
suppressed. The chopper stabilization technique uses a 350 kHz
high frequency clock. For demodulation process, a sample and
hold technique is used, where the sampling is performed at twice
the chopper frequency. This high-frequency operation allows
a greater sampling rate, which results in higher accuracy and
faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall out-
put voltages and precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset, low-noise amplifiers
in combination with high-density logic integration and sample-
and-hold circuits.
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges. Chopper stabilization is
a unique approach used to minimize Hall offset on the chip. The
patentedꢀAllegroꢀtechnique,ꢀnamelyꢀDynamicꢀQuadratureꢀOffsetꢀ
Cancellation, removes key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
Regulator
Clock/Logic
Low-Pass
Filter
Hall Element
Amp
Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation)
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
PROGRAMMING GUIDELINES
Overview
Definition of Terms
Programming is accomplished by sending a series of input volt-
ageꢀpulsesꢀseriallyꢀthroughꢀtheꢀVCCꢀ(supply)ꢀpinꢀofꢀtheꢀdevice.ꢀ
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when program-
ming. These levels are referred to as highꢀ(VPH), midꢀ(VPM), and
lowꢀ(VPL) (see figure 1 and table 1).
Register. The section of the programming logic that controls the
choice of programmable modes and parameters.
Bit Field. The internal fuses unique to each register, represented
as a binary number. Changing the bit field selection in a particu-
lar register causes its programmable parameter to change, based
on the internal programming logic.
Key.ꢀAꢀseriesꢀofꢀVPM voltage pulses used to select a register or mode.
The A119x family features two programmable modes, Try mode
and Blow mode.
tACTIVE
tPr
tBLOW
tPf
• In Try mode, programmable parameter values are set and mea-
sured. A parameter value is stored temporarily, and reset after
cycling the supply voltage.
VPH
• In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device.ꢀDeviceꢀlockingꢀisꢀalsoꢀaccomplishedꢀinꢀthisꢀmode.
VPM
VPL
The programming sequence is designed to help prevent the
device from being programmed accidentally; for example, as a
result of noise on the supply line. Although any programmable
variable power supply can be used to generate the pulse wave-
forms, Allegro highly recommends using the Allegro Sensor IC
EvaluationꢀKit,ꢀavailableꢀthroughꢀyourꢀlocalꢀAllegroꢀsalesꢀrepre-
sentative. The manual for the kit provides additional information
on programming these devices, and is available for download on
the Allegro MicroSystems website.
tLOW
tLOW
(Supply
cycled)
0
Programming
pulses
Blow
pulse
Figure 4. Programming pulse definition (see table 1)
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C (refer also to figure 4)
Characteristic
Symbol
VPL
Notes
Min. Typ. Max. Unit
4.5
12.5
21
5
–
–
5.5
14
27
V
V
V
Programming Voltage
VPM
Measured at the VCC pin.
VPH
tPr = 11 µs, VCC = 5 → 26 V, CBLOW = 0.1 µF (min). Minimum supply current
required to ensure proper fuse blowing. CBLOW must be connected between the
VCC and GND pins during programming to provide the current necessary for fuse
blowing.
Programming Current
Pulse Width
IPP
175
–
–
mA
tLOW
tACTIVE
tBLOW
tPr
Duration at VPL separating pulses at VPM or VPH
.
20
20
90
5
–
–
–
–
µs
µs
Duration of pulses at VPM or VPH for key/code selection.
Duration of pulse at VPH for fuse blowing.
100
–
–
µs
Pulse Rise Time
Pulse Fall Time
VPL to VPM, or VPL to VPH
.
100
100
–
µs
tPf
VPH to VPL, or VPM to VPL
.
5
–
µs
Blow Pulse Slew Rate
SRBLOW
375
–
mV/µs
Allegro MicroSystems, LLC
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Code. The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Programming Procedure
Programming involves selection of a register, a mode, and then
setting values for parameters in the register for evaluation or for
fuse blowing. Figure 10 provides an overview state diagram.
Addressing. Setting the bit field code in a selected register by
seriallyꢀapplyingꢀaꢀpulseꢀtrainꢀthroughꢀtheꢀVCCꢀpinꢀofꢀtheꢀdevice.ꢀ
Eachꢀparameterꢀcanꢀbeꢀmeasuredꢀduringꢀtheꢀaddressingꢀprocess,ꢀ
but the internal fuses must be blown before the programming
code (and parameter value) becomes permanent.
Register SelectionꢀEachꢀprogrammableꢀparameterꢀcanꢀbeꢀ
accessed through a specific register. To select a register, a
sequenceꢀofꢀvoltageꢀpulsesꢀconsistingꢀofꢀaꢀVPH pulse, a series of
VPMꢀpulses,ꢀandꢀaꢀVPHꢀpulseꢀ(withꢀnoꢀVCC supply interruptions)
mustꢀbeꢀappliedꢀseriallyꢀtoꢀtheꢀVCCꢀpin.ꢀTheꢀquantityꢀofꢀVPM
pulses is called the key, and uniquely identifies each register. The
pulses for selection of register key 1, is shown in figure 5. No
VPM pulse is sent for key 0. The register selections are shown in
table 2.
Fuse Blowing.ꢀApplyingꢀaꢀVPH pulse of sufficient duration to
permanently set an addressed bit by blowing a fuse internal to the
device. Once a bit (fuse) has been blown, it cannot be reset.
Blow Pulse.ꢀAꢀVPH pulse of sufficient duration to blow the
addressed fuse.
Mode Selection After register selection, the mode is selected,
either Try or Blow mode. Try mode is selected by default. To
select Blow mode, that mode selection key must be sent.
Cycling the Supply. Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the program-
ming settings in Try mode.
Table 2. Programming Logic Table
Register
Bit Field Address (Code)
Description
Binary Format
[MSB → LSB]
Decimal
Equivalent
Key
Name
Try Mode
Initial value (below minimum |BOP| ) (Try mode sequence
starts with code 1); Code corresponds to bit field value (code
1 selects bit field value 000001)
000000
111111
111111
0
63
0
0
BOP Trim Up Counting
Maximum selectable value (above maximum |BOP| )
Initial value (above maximum |BOP| ) (Try mode sequence
starts with code 1); Code is automatically inverted (code 1
selects bit field value 111110)
1
7
BOP Trim Down Counting
000000
000111
001111
63
Minimum selectable value (below minimum |BOP|)
Check integrity of all fuse bits versus low threshold
Check integrity of all fuse bits versus high threshold
7
15
Fuse Check
Blow Mode
Initial value (below minimum |BOP| ); (Only allows selection
of 1 bit per sequence)
000000
0
0
7
BOP Trim
Maximum selectable value (above maximum |BOP| ); (Only
allows selection of 1 bit per sequence)
111111
001000
63
8
Programming Lock
Locks out access to all registers except Fuse Check
Allegro MicroSystems, LLC
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Try Mode In Try mode, bit field addressing is accomplished by
applyingꢀaꢀseriesꢀofꢀVPMꢀpulsesꢀtoꢀtheꢀVCCꢀpinꢀofꢀtheꢀdevice,ꢀasꢀ
shownꢀinꢀfigureꢀ6.ꢀEachꢀpulseꢀincreasesꢀtheꢀbitꢀfieldꢀvalueꢀforꢀtheꢀ
selected parameter, increasing by one on the falling edge of each
additionalꢀVPM pulse. When addressing the bit field in Try mode,
theꢀquantityꢀofꢀVPM pulses is represented by a decimal number
called the code. Addressing activates the corresponding fuse
locations in the given bit field by increasing the binary value of
anꢀinternalꢀDAC,ꢀupꢀtoꢀtheꢀmaximumꢀpossibleꢀcode.ꢀAsꢀtheꢀvalueꢀ
of the bit field code increases, the value of the programmable
parameterꢀchanges.ꢀMeasurementsꢀcanꢀbeꢀtakenꢀafterꢀeachꢀVPM
pulse to determine if the required result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states.
Blow Mode After the required code is determined for a given
parameter, its value can be set permanently by blowing individual
fuses in the appropriate register bit field. Blowing is accom-
plished by selecting the register, then the Blow mode selection
key, followed by the appropriate bit field address, and ending
the sequence with the Blow pulse. The Blow mode selection key
isꢀaꢀsequenceꢀofꢀnineꢀVPMꢀpulsesꢀfollowedꢀbyꢀoneꢀVPH pulse. A
complete example is provided in figure 12.
TheꢀBlowꢀpulseꢀconsistsꢀofꢀaꢀVPH pulse of sufficient duration,
tBLOW, to permanently set an addressed bit by blowing a fuse
internalꢀtoꢀtheꢀdevice.ꢀDueꢀtoꢀpowerꢀrequirements,ꢀtheꢀfuseꢀforꢀ
each bit in the bit field must be blown individually. The A119x
family built-in circuitry allows only one fuse at a time to be
blown.ꢀDuringꢀBlowꢀmode,ꢀtheꢀbitꢀfieldꢀcanꢀbeꢀconsideredꢀaꢀ“one-
hot”ꢀshiftꢀregister.ꢀTableꢀ3ꢀrelatesꢀtheꢀquantityꢀofꢀVPM pulses to
the binary and decimal values for Blow mode bit field address-
ing. It should be noted that the simple relationship between the
quantityꢀofꢀVPMꢀpulsesꢀandꢀtheꢀcorrespondingꢀcodeꢀis:
When setting the BOP Trim parameter, as an aid to programming,
values can be traversed from low to high, or from high to low. To
accommodate this direction selection, the value of the bit field
(and code) defaults to the value 1, on the falling edge of the final
registerꢀselectionꢀVPH pulse (see figure 5). A complete example is
provided in figure 11.
2n = Code,
whereꢀnꢀisꢀtheꢀquantityꢀofꢀVPM pulses. The bit field has an initial
state of decimal code 0 (binary 000000).
VPH
Bit Field Selection
Address Code Format
(Decimal Equivalent)
Code 5
VPM
(Binary)
Code in Binary
1
0 1
Fuse Blowing
Target Bits
Bit 2
Bit 0
VPL
Key
Fuse Blowing
Address Code Format
Code 4
(Decimal Equivalents)
Code 1
0
Figure 5. Register selection pulse sequence
Figure 7. Example of code 5 broken into its binary components
VPH
Table 3. Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary Register
Setting
Equivalent Code
VPM
1
2
3
4
5
6
000001
000010
000100
001000
010000
100000
1
2
VPL
4
8
16
32
0
Figure 6. Try mode bit field addressing pulses
Allegro MicroSystems, LLC
115 Northeast Cutoff
14
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
To correctly address the fuses to be blown, the code represent-
ing the required parameter value must be translated into a binary
number.ꢀForꢀexample,ꢀasꢀshownꢀinꢀfigureꢀ7,ꢀdecimalꢀcodeꢀ5ꢀisꢀ
equivalent to the binary number 101. Therefore bit 2 must be
addressed and blown, the device power supply cycled, and then
bit 0 must be addressed and blown. The order of blowing bits,
however, is not important. Blowing bit 0 first, and then bit 2 is
acceptable.
Setting the fuse threshold high checks that all blown fuses are
properly blown. Setting fuse threshold low checks all un-blown
fusesꢀareꢀproperlyꢀintact.ꢀTheꢀsupplyꢀcurrentꢀincreasesꢀbyꢀ250ꢀµAꢀ
if a marginal fuse is detected. If all fuses are correctly blown or
fully intact, there will be no change in supply current.
Additional Guidelines
The additional guidelines in this section should be followed to
ensureꢀtheꢀproperꢀbehaviorꢀofꢀtheseꢀdevices:
Note:ꢀAfterꢀblowing,ꢀtheꢀprogrammingꢀisꢀnotꢀreversible,ꢀevenꢀ
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
•ꢀAꢀ0.1ꢀμFꢀblowingꢀcapacitor,ꢀCBLOW, must be mounted between
theꢀVCCꢀpinꢀandꢀtheꢀGNDꢀpinꢀduringꢀprogramming,ꢀtoꢀensureꢀ
enough current is available to blow fuses.
• The power supply used for programming must be capable of
deliveringꢀatꢀleastꢀVPHꢀandꢀ175ꢀmA.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
Locking the Device
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters.ꢀToꢀdoꢀso,ꢀperformꢀtheꢀfollowingꢀsteps:
• Lock the device (only after all other parameters have been pro-
grammed and validated) to prevent any further programming of
the device.
1.ꢀ EnsureꢀthatꢀtheꢀCBLOW capacitor is mounted.
2.ꢀ SelectꢀtheꢀProgrammingꢀLockꢀregisterꢀ(keyꢀ7).
3. Select Blow mode (key 9).
BOP Selection
Selecting BOP should be done in two stages. First, Try mode
should be used to adjust BOP and monitor the output state. Then
the optimum BOP is set permanently using Blow mode.
4.ꢀ Addressꢀbitꢀ3ꢀ(001000)ꢀbyꢀsendingꢀfourꢀVPM pulses.
5. Send one Blow pulse, at IPPꢀandꢀSRBLOW, and sustain it for
Use the BOP Trim Up Counting register to increase the BOP selec-
tion by one Magnetic Step Size, StepBOP, increment with each
bit field pulse (see figure 8). Use the BOPꢀTrimꢀDownꢀCountingꢀ
register to decrease the BOP selection by one StepBOPwith each
bit field pulse (see figure 9). As an aid to programming, when
using down-counting method, the A119x automatically inverts
the bit field selection (code 0 in down-counting sets the bit field
value 111111, and the actual bit field value decreases until code
63ꢀsetsꢀbitꢀfieldꢀvalueꢀ000000).ꢀ
tBLOW
.
6.ꢀ DelayꢀforꢀaꢀtLOW interval, then power-down.
7.ꢀ Optionallyꢀcheckꢀallꢀfuses.ꢀ
Fuse Checking
Incorporated in the A119x family is circuitry to simultaneously
check the integrity of the fuse bits. The fuse checking feature is
enabledꢀbyꢀusingꢀtheꢀFuseꢀCheckꢀregisterꢀ(selectionꢀkeyꢀ7),ꢀandꢀ
while in Try mode, applying the codes shown in table 2. The
register is only valid in Try mode and is available before or after
the Programming Lock bit is set.
Note that the release point, BRP, is a value below BOP. The
difference is specified by the Hysteresis, BHYS , which is not
programmable.
Allegro MicroSystems, LLC
115 Northeast Cutoff
15
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
(Code 0,
(Code 63,
Bit value 111111 )
Bit value 111111 )
BOP
BOP
|B (max)|
OP
|B (max)|
OP
BHYS
BHYS
BRP
BRP
(Code 63,
Bit value 000000)
(Code 0,
Bit value 000000 )
|B (min)|
OP
|B (min)|
OP
BOP
BOP
BHYS
BHYS
BRP
BRP
0
31
63
0
31
63
Try Mode, Bit Field Code
Try Mode, Bit Field Code
Figure 8. BOP Selection Up-Counting
Figure 9. BOP Selection Down-Counting
Allegro MicroSystems, LLC
115 Northeast Cutoff
16
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Figure 10. Programming state diagram
Figure 11. Example of Try mode pulse sequence, Register Key = BOP selection down counting
Figure 12. Example of Blow mode pulse sequence, Register Key = BOP selection bit field 2 (code 4)
Allegro MicroSystems, LLC
115 Northeast Cutoff
17
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
Example:ꢀReliabilityꢀforꢀVCC at TA=150°C, package UA, using a
low-KꢀPCB.
Observeꢀtheꢀworst-caseꢀratingsꢀforꢀtheꢀdevice,ꢀspecifically:ꢀꢀ
RθJAꢀ=165ꢀ°C/W,ꢀTJ(max) =165°C,ꢀVCC(max)= 24ꢀV,ꢀandꢀ
ICC(max) = 17 mA.
Calculate the maximum allowable power level, PD(max). First,
invertꢀequationꢀ3:
TheꢀPackageꢀThermalꢀResistance,ꢀRθJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
ItsꢀprimaryꢀcomponentꢀisꢀtheꢀEffectiveꢀThermalꢀConductivity,ꢀK,ꢀ
of the printed circuit board, including adjacent devices and traces.
Radiationꢀfromꢀtheꢀdieꢀthroughꢀtheꢀdeviceꢀcase,ꢀRθJC, is relatively
smallꢀcomponentꢀofꢀRθJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
ΔTmax = TJ(max) – TAꢀ=ꢀ165°C–150°C = 15°C
This provides the allowable increase to TJ resulting from internal
powerꢀdissipation.ꢀThen,ꢀinvertꢀequationꢀ2:
ꢀꢀꢀꢀPD(max) = ΔTmaxꢀ÷ꢀRθJAꢀ=ꢀ15°Cꢀ÷ꢀ165ꢀ°C/Wꢀ=ꢀ91ꢀmW
Finally,ꢀinvertꢀequationꢀ1ꢀwithꢀrespectꢀtoꢀvoltage:
ꢀꢀꢀꢀVCC(est) = PD(max) ÷ ICC(max)=ꢀ91ꢀmWꢀ÷ꢀ17ꢀmA=5ꢀV
Theꢀeffectꢀofꢀvaryingꢀpowerꢀlevelsꢀ(PowerꢀDissipation,ꢀPD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
The result indicates that, at TA, the application and device can
dissipateꢀadequateꢀamountsꢀofꢀheatꢀatꢀvoltagesꢀ≤VCC(est)
.
PDꢀ=ꢀVIN
I
(1)
(2)
×
IN
CompareꢀVCC(est)ꢀtoꢀVCC(max).ꢀIfꢀVCC(est)ꢀ≤ꢀVCC(max), then reli-
ableꢀoperationꢀbetweenꢀVCC(est)ꢀandꢀVCC(max) requires enhanced
RθJA.ꢀꢀIfꢀVCC(est)ꢀ≥ꢀVCC(max),ꢀthenꢀoperationꢀbetweenꢀVCC(est)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀΔT = PD
R
θJA
×
TJ = TAꢀ+ꢀΔTꢀ
ꢀ
(3) andꢀVCC(max) is reliable under these conditions.
Forꢀexample,ꢀgivenꢀcommonꢀconditionsꢀsuchꢀas:ꢀTA= 25°C,
VCC = 12ꢀV, ICC = 4 mA, and RθJA = 140 °C/W, then:
PDꢀ=ꢀVCC
I
=ꢀ12ꢀV 4 mA = 48 mW
×
×
CC
ꢀ
ΔT = PD
R
= 48 mW 140ꢀ°C/Wꢀ=ꢀ7°C
θJA
×
×
TJ = TA + ΔTꢀ=ꢀ25°Cꢀ+ꢀ7°Cꢀ=ꢀ32°C
A worst-case estimate, PD(max), represents the maximum allow-
ableꢀpowerꢀlevelꢀ(VCC(max), ICC(max)), without exceeding
TJ(max),ꢀatꢀaꢀselectedꢀRθJA and TA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
18
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Package LH, 3-Pin SOT23W
+0.12
–0.08
2.98
3
D
1.49
4°±4°
A
+0.020
–0.053
0.180
D
0.96
D
+0.10
2.90
+0.19
–0.06
2.40
1.91
–0.20
0.70
0.25 MIN
1.00
2
1
0.55 REF
0.25 BSC
0.95
PCB Layout Reference View
Seating Plane
Gauge Plane
B
Branded Face
8X 10° REF
1.00 ±0.13
+0.10
NNT
1
0.05
–0.05
C
Standard Branding Reference View
0.95 BSC
0.40 ±0.10
N = Last two digits of device part number
T = Temperature code
For reference only; not for tooling use (reference DWG-2840).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
Active Area Depth, 0.28 mm REF
A
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
D
Branding scale and appearance at supplier discretion
Hall element, not to scale
Allegro MicroSystems, LLC
115 Northeast Cutoff
19
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Package UA, 3-Pin SIP
+0.08
–0.05
4.09
45°
B
C
E
2.05 NOM
1.52 ±0.05
10°
1.44 NOM
E
Mold Ejector
Pin Indent
+0.08
–0.05
E
3.02
45°
Branded
Face
NNN
0.79 REF
A
1.02
MAX
1
Standard Branding Reference View
D
= Supplier emblem
N = Last three digits of device part number
1
2
3
14.99 ±0.25
+0.03
–0.06
0.41
For reference only; not for tooling use (reference DWG-9065).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
+0.05
–0.07
0.43
Dambar removal protrusion (6X)
A
B
C
D
Gate and tie bar burr area
Active Area Depth, 0.50 mm REF
Branding scale and appearance at supplier discretion
Hall element (not to scale)
E
1.27 NOM
Allegro MicroSystems, LLC
115 Northeast Cutoff
20
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Package UB, 2-Pin SIP
+0.06
–0.05
4.00
B
4 X 10°
1.50 0.05
E
2.00
C
E
1.75
Mold Ejector
Pin Indent
+0.06
4.00
–0.07
E
NNN
Branded
Face
45°
YYWW
LLLL
A
0.85 0.07
4 X 2.50 REF
0.25 REF
0.30 REF
0.42 0.10
D
Standard Branding Reference View
= Supplier emblem
2.54 REF
N
Y
W
L
= Last three digits of device part number
= Last 2 digits of year of manufacture
= Week of manufacture
4 X 0.85 REF
= Lot number
1
2
1.00 0.10
For reference only; not for tooling use (reference DWG-9070).
Dimensions in millimeters.
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions.
Exact case and lead configuration at supplier discretion within limits shown.
12.20 0.10
4 X 7.37 REF
+0.07
0.25
–0.03
1.80
0.10
A
B
C
D
E
F
Dambar removal protrusion (8X)
Gate and tie bar burr area
0.38 REF
0.25 REF
Active Area Depth, 0.38 mm REF
4 X 0.85 REF
Branding scale and appearance at supplier discretion
Hall element; not to scale
0.85 0.07
Thermoplastic Molded Lead Bar for alignment during shipment
+0.06
1.80
–0.07
F
+0.06
1.50 0.05
4.00
–0.05
Allegro MicroSystems, LLC
115 Northeast Cutoff
21
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
Two-Wire Hall-Effect Switches
A119x and A119x-F
Revision History
Revision
Revision Date
Description of Revision
4
5
May 24, 2013
Update application information
September 21, 2015 Added AEC-Q100 qualification under Features
and Benefits
6
7
February 3, 2016
February 25, 2016
Added UB package option; added -F part option.
Removed A1190-F part option.
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
22
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
相关型号：
©2020 ICPDF网 联系我们和版权申明