A1245LUA-I2-T [ALLEGRO]

Chopper-Stabilized, Two Wire Hall-Effect Latch;


型号：	A1245LUA-I2-T
厂家：	ALLEGRO MICROSYSTEMS
描述：	Chopper-Stabilized, Two Wire Hall-Effect Latch
文件：	总13页 (文件大小：567K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A1245

Chopper-Stabilized, Two Wire Hall-Effect Latch

FEATURES AND BENEFITS

DESCRIPTION

• High speed, 4-phase chopper stabilization

□ Low switchpoint drift throughout temperature range

□ Low sensitivity to thermal and mechanical stresses

• On-chip protection

□ Supply transient protection

□ Reverse battery protection

• On-board voltage regulator

The A1245 is a two-wire Hall-effect latch. The device is

producedontheAllegro^™advancedBiCMOSwaferfabrication

process,whichimplementsapatentedhighfrequency,4-phase,

chopper-stabilization technique. This technique achieves

magnetic stability over the full operating temperature range,

and eliminates offsets inherent in devices with a single Hall

element that are exposed to harsh application environments.

□ 3.0 to 24 V operation

• Solid-state reliability

• Industry leading ISO 7637-2 performance through use of

proprietary, 40 V clamping structures

Two-wirelatchesareparticularlyadvantageousincost-sensitive

applications because they require one less wire for operation

versus the more traditional open-collector output switches.

Additionally, the system designer inherently gains diagnostics

because there is always output current flowing, which should

be in either of two narrow ranges.Any current level not within

these ranges indicates a fault condition.

PACKAGES:

Not to scale

The Hall-effect latch will be in the high output current state

in the presence of a magnetic south polarity field of sufficient

magnitude and will remain in this state until a sufficient north

polarity field is present.

Approximate

footprints

The device is offered in two package styles. The LH is a

SOT-23W style, miniature low profile package for surface-

mount applications. The UA is a 3-pin ultra-mini single inline

packages (SIP) for through-hole mounting. Both packages are

lead (Pb) free, with 100% matte tin leadframe plating.

3-pin SOT23-W

2 × 3 × 1 mm

(suffix LH)

3-pin ultramini SIP

1.5 × 4 × 3 mm

(suffix UA)

VCC

V+

Regulator

Clock/Logic

Amp

To all subcircuits

Schmitt

Trigger

Low-Pass

Filter

Polarity

GND

UA package only

GND

Functional Block Diagram

A1245-DS, Rev. 1

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

Selection Guide

Operating Ambient Tem-

perature, T_A

Supply Current

at I_CC(L)

Part Number

Packing*

Package

(°C)

(mA)

A1245LLHLX-I1-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount

A1245LLHLX-I2-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount

–40 to 150

5 to 6.9

2 to 5

A1245LUA-I1-T

A1245LUA-I2-T

Bulk, 500 pieces/bag

3-pin SIP through hole

5 to 6.9

2 to 5

*Contact Allegro for additional packing options

SPECIFICATIONS

Absolute Maximum Ratings

Characteristic

Symbol

V_CC

Notes

Rating

Unit

Forward Supply Voltage

Reverse Supply Voltage

Magnetic Flux Density

V_RCC

–18

Unlimited

–40 to 150

165

Operating Ambient Temperature

Maximum Junction Temperature

Storage Temperature

T_A

Range L

ºC

T_J(max)

T_stg

–65 to 170

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

Pin-out Diagrams and Terminal List Table

LH Package, 3-pin

SOT23W Pin-out

UA Package, 3-pin SIP

Pin-out

Terminal List Table

Number

Name

Function

VCC

Connects power supply to chip

N/A

2, 3

No connection (tie to GND; improved thermal characteristics) or float

Ground (Tie both to GND for improved thermal characteristics, or float

unused GND pin)

GND

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

ELECTRICAL CHARACTERISTICS: valid at T_A= –40°C to 150°C; T_J< T_J(max); for LH and UA: C_BYP= 0.01 µF; through oper-

ating supply voltage range; unless otherwise noted

Characteristics

Supply Voltage^1,2

Symbol

Test Conditions

Min.

3.0

Typ.

Max.

6.9

Unit

V_CC

Operating

-I1

–

B < B_RP

I_CC(L)

Supply Current

-I2

I_CC(H)

B > B_OP

–

Supply Zener Clamp Voltage

Supply Zener Clamp Current

Reverse Supply Current

Output Slew Rate³

V_Z(sup)

I_CC(L)(max) + 3 mA, T_A= 25°C

V_Z(sup)= 28 V

I_CC(L)(max)

+ 3 mA

I_Z(sup)

I_RCC

–

V_RCC= –18 V

–1.6

–

No external bypass capacitor, capacitance of

probe C_S= 20 pF

dI/dt

mA/µs

Chopping Frequency⁵

Power-Up Time^2,4,5

Power-Up State^4,6,7

f_c

–

700

–

kHz

µs

–

t_on

V_CC≥ V_CC(min)

POS

t_on< t_on(max), V_CCslew rate > 25 mV/µs

I_CC(H)

¹V_CCrepresents the generated voltage between the VCC pin and the GND pin.

²The V_CCslew rate must exceed 600 mV/ms from 0 to V_CC(min). A slower slew rate through this range can affect device performance.

³Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change.

⁴Power-Up Time is measured with and without an external bypass capacitor of 0.01 µF, B < B_RP– 10 G. Adding a larger bypass capacitor would cause longer Power-Up

Time.

⁵Guaranteed by characterization and design.

⁶Power-Up State as defined is true only with a V_CCslew rate of 25 mV/µs or greater.

⁷Power-Up State is defined during the power-on phase (t < t_ON) until the device has fully powered-on (t_ON), after which the output will correspond to the magnetic field level

seen by the sensor. For t > t_onand B_RP< B < B_OP, Power-Up State is not defined.

MAGNETIC CHARACTERISTICS^1:valid at T_A= –40°C to 150°C; T_J< T_J(max); for LH and UA: C_BYP= 0.01 µF; through oper-

ating supply voltage range; unless otherwise noted

Characteristics

Magnetic Operating Point

Magnetic Release Point

Hysteresis

Symbol

B_OP

Test Conditions

Min.

Typ.

–

Max.

Unit²

B_RP

–40

–

–5

B_HYS

B_OP– B_RP

¹Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore

greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).

²1 G (gauss) = 0.1 mT (millitesla).

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Characteristic

Symbol

Test Conditions*

Value Units

Package LH, 1-layer PCB with copper limited to solder pads

228

110

165

ºC/W

Package LH, 2-layer PCB with 0.463 in.²of copper area each side connected by

thermal vias

Package Thermal Resistance

R_θJA

Package UA, 1-layer PCB with copper limited to solder pads

*Additional thermal information available on Allegro Web site.

Power Derating Curve

CC(max)

LH, 2-layer PCB

(R^qJA= 110 ºC/W)

UA, 1-layer PCB

(R^qJA= 165 ºC/W)

LH, 1-layer PCB

(R^qJA= 228 ºC/W)

CC(min)

100

120

140

160

180

Temperature (ºC)

Maximum Power Dissipation versus Ambient Temperature

1900

1800

1700

1600

1500

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

120

140

160

180

Temperature (°C)

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

CHARACTERISTIC PERFORMANCE

Average Supply Current (Low) vs. Temperature

Average Supply Current (Low) vs. Supply Voltage

7.0

6.8

6.6

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

7.0

6.8

6.6

6.4

6.2

6.0

5.8

5.6

5.4

5.2

5.0

3 V

-40°C

24 V

25°C

150°C

-50

100

150

200

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

Average Supply Current (High) vs. Supply Voltage

Average Supply Current (High) vs. Temperature

17.0

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

12.5

12.0

17.0

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

12.5

12.0

3 V

-40°C

24 V

25°C

150°C

-50

100

150

200

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

Average B_OPvs. Temperature

Average B_OPvs. Supply Voltage

40.0

35.0

30.0

25.0

20.0

15.0

10.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

3 V

-40°C

25°C

24 V

150°C

5.0

-50

100

150

200

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

Average B_RPvs. Supply Voltage

Average B_RPvs. Temperature

-5.0

-10.0

-15.0

-20.0

-25.0

-30.0

-35.0

-40.0

-5.0

-10.0

-15.0

-20.0

-25.0

-30.0

-35.0

-40°C

25°C

3 V

24 V

150°C

-40.0

-50

100

150

200

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

Average B_HYSvs. Supply Voltage

Average B_HYSvs. Temperature

65.0

60.0

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

15.0

65.0

60.0

55.0

50.0

45.0

40.0

35.0

30.0

25.0

20.0

-40°C

25°C

3 V

24 V

150°C

15.0

-50

100

150

200

Ambient Temperature, T_A(°C)

Supply Voltage, V_CC(V)

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

FUNCTIONAL DESCRIPTION

The A1245 output, I_CC, switches high after the magnetic field

at the Hall sensor IC exceeds the operate point threshold, B_OP

When the magnetic field is reduced to below the release point

threshold, B_RP, the device output goes low. This is shown in

Figure 1.

The difference between the magnetic operate and release points

is called the hysteresis of the device, B_HYS. This built-in hyster-

esis allows clean switching of the output even in the presence of

external mechanical vibration and electrical noise.

I+

I_CC(H)

I_CC(L)

B–

B+

B_HYS

Figure 1: Hysteresis for the A1245

On the horizontal axis, the B+ direction indicates increasing south

polarity magnetic field strength, and the B– direction indicates

decreasing south polarity field strength (including the case of

increasing north polarity).

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

R_SENSE

V+

VCC

A1245

C_BYP

0.01 µF

GND

R_SENSE

(A) Low Side Sensing

(B) High Side Sensing

LH and UA Packages

Figure 2: Typical Application Circuits

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for

its original spectrum at base band, while the DC offset becomes

a high-frequency signal. The magnetic-sourced signal then can

pass through a low-pass filter, while the modulated DC offset is

suppressed. The chopper stabilization technique uses a 350 kHz

high frequency clock. For demodulation process, a sample and

hold technique is used, where the sampling is performed at twice

the chopper frequency. This high-frequency operation allows

a greater sampling rate, which results in higher accuracy and

faster signal-processing capability. This approach desensitizes

the chip to the effects of thermal and mechanical stresses, and

produces devices that have extremely stable quiescent Hall out-

put voltages and precise recoverability after temperature cycling.

This technique is made possible through the use of a BiCMOS

process, which allows the use of low-offset, low-noise amplifiers

in combination with high-density logic integration and sample-

and-hold circuits.

switchpoint accuracy is the small signal voltage developed

across the Hall element. This voltage is disproportionally small

relative to the offset that can be produced at the output of the

Hall sensor IC. This makes it difficult to process the signal while

maintaining an accurate, reliable output over the specified oper-

ating temperature and voltage ranges. Chopper stabilization is

a unique approach used to minimize Hall offset on the chip. The

patented Allegro technique, namely Dynamic Quadrature Offset

Cancellation, removes key sources of the output drift induced by

thermal and mechanical stresses. This offset reduction technique

is based on a signal modulation-demodulation process. The

undesired offset signal is separated from the magnetic field-

induced signal in the frequency domain, through modulation.

The subsequent demodulation acts as a modulation process for

the offset, causing the magnetic field-induced signal to recover

Regulator

Clock/Logic

Low-Pass

Filter

Hall Element

Amp

Figure 3: Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation)

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

Power Derating

The device must be operated below the maximum junction tem-

perature of the device, T_J(max). Under certain combinations of

peak conditions, reliable operation may require derating supplied

power or improving the heat dissipation properties of the appli-

cation. This section presents a procedure for correlating factors

affecting operating T_J. (Thermal data is also available on the

Allegro MicroSystems Web site.)

A worst-case estimate, P_D(max), represents the maximum allow-

able power level (V_CC(max), I_CC(max)), without exceeding

T_J(max), at a selected R_θJAand T_A.

Example: Reliability for V_CCat T_A=150°C, package LH, using a

low-K PCB.

Observe the worst-case ratings for the device, specifically:

R_θJA=110 °C/W, T_J(max) =165°C, V_CC(max)= 24 V, and

I_CC(max) = 17 mA.

The Package Thermal Resistance, R_θJA, is a figure of merit sum-

marizing the ability of the application and the device to dissipate

heat from the junction (die), through all paths to the ambient air.

Its primary component is the Effective Thermal Conductivity, K,

of the printed circuit board, including adjacent devices and traces.

Radiation from the die through the device case, R_θJC, is relatively

small component of R_θJA. Ambient air temperature, T_A, and air

motion are significant external factors, damped by overmolding.

Calculate the maximum allowable power level, P_D(max). First,

invert equation 3:

ΔT_max= T_J(max) – T_A= 165°C–150°C = 15°C

This provides the allowable increase to T_Jresulting from internal

power dissipation. Then, invert equation 2:

The effect of varying power levels (Power Dissipation, P_D), can

be estimated. The following formulas represent the fundamental

relationships used to estimate T_J, at P_D.

P_D(max) = ΔT_max÷R_θJA=15°C÷110 °C/W=136mW

Finally, invert equation 1 with respect to voltage:

_CC(est)= P_D(max) ÷ I_CC(max)= 136mW÷17 mA= 8 V

The result indicates that, at T_A, the application and device can

dissipate adequate amounts of heat at voltages ≤V_CC(est)

P_D= V_IN

(1)

(2)

(3)

ꢀ

ΔT = P_D

θJA

T_J= T_A+ ΔT

Compare V_CC(est)to V_CC(max). If V_CC(est)≤ V_CC(max), then reli-

able operation between V_CC(est)and V_CC(max) requires enhanced

R_θJA. If V_CC(est)≥ V_CC(max), then operation between V_CC(est)

and V_CC(max) is reliable under these conditions.

For example, given common conditions such as: T_A= 25°C,

V_CC= 12 V, I_CC= 9 mA, and R_θJA= 110 °C/W, then:

P_D= V_CC

= 12 V 9 mA = 108 mW

ΔT = P_D

= 48 mW 110 °C/W = 11.9°C

θJA

T_J= T_A+ ΔT = 25°C + 11.9°C = 36.9°C

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

Package Outline Drawings

For Reference Only – Not for Tooling Use

(Reference DWG-2840)

Dimensions in millimeters – NOT TO SCALE

Dimensions exclusive of mold ﬂash, gate burrs, and dambar protrusions

Exact case and lead conﬁguration at supplier discretion within limits shown

+0.12

2.98

–0.08

1.49

4° 4°

+0.020

0.180

–0.053

0.96

+0.19

–0.06

+0.10

1.91

2.40

2.90

–0.20

0.70

1.00

0.25 MIN

0.55 REF

0.25 BSC

0.95

Seating Plane

Gauge Plane

Branded Face

PCB Layout Reference View

8X 10°

REF

1.00 0.13

+0.10

NNN

0.05

–0.05

0.95 BSC

0.40 0.10

^CStandard Branding Reference View

= Last three digits of device part number

Active Area Depth, 0.28 mm

Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads;

adjust as necessary to meet application process requirements and PCB layout tolerances

Branding scale and appearance at supplier discretion

Hall elements, not to scale

Figure 4: Package LH, 3-Pin SOT23W

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

For Reference Only – Not for Tooling Use

(Reference DWG-9013)

Dimensions in millimeters – NOT TO SCALE

Dimensions exclusive of mold ﬂash, gate burrs, and dambar protrusions

Exact case and lead conﬁguration at supplier discretion within limits shown

45°

+0.08

–0.05

4.09

1.52 0.05

2.04

2 X 10°

1.44

Mold Ejector

Pin Indent

+0.08

–0.05

3.02

45°

Branded

Face

1.02 MAX

0.79 REF

+0.05

–0.07

+0.03

–0.06

0.43

0.41

1.27 NOM

NNN

14.99 0.25

Standard Branding Reference View

= Supplier emblem

= Last three digits of device part number

Dambar removal protrusion (6X)

Gate and tie bar burr area

Active Area Depth, 0.50 mm REF

Branding scale and appearance at supplier discretion

Hall element, not to scale

Figure 5: Package UA, 3-Pin SIP

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Chopper-Stabilized, Two Wire

Hall-Effect Latch

A1245

Revision History

Revision

Date

December 17, 2014 Initial Release

July 13, 2015 Corrected LH package Active Area Depth value

Change

–

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1245LUA-I2-T [ALLEGRO]

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