A1309LLHLX-RP9-T中文资料_数据手册_规格书

A1308 and A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

FEATURES AND BENEFITS

DESCRIPTION

• 5 V supply operation

New applications for linear output Hall-effect sensors, such

as displacement and angular position, require higher accuracy

and smaller package sizes. The Allegro A1308 and A1309

linear Hall-effect sensor ICs have been designed specifically

to meet both requirements. These temperature-stable devices

areavailableinbothsurface-mountandthrough-holepackages.

• QVO temperature coefficient programmed at Allegro^™for

improved accuracy

• Miniature package options

• High-bandwidth, low-noise analog output

• High-speed chopping scheme minimizes QVO drift across

operating temperature range

• Temperature-stable quiescent voltage output and sensitivity

• Precise recoverability after temperature cycling

• Output voltage clamps provide short-circuit diagnostic

capabilities

The accuracy of each device is enhanced via end-of-line

optimization. Each device features nonvolatile memory to

optimize device sensitivity and the quiescent voltage output

(QVO: output in the absence of a magnetic field) for a given

application or circuit. This A1308 and A1309 optimized

performance is sustained across the full operating temperature

range by programming the temperature coefficient for both

sensitivity and QVO at Allegro end-of-line test.

• Undervoltage lockout (UVLO)

• Wide ambient temperature range:

–40°C to 150°C (SOT-23W), –40°C to 125°C (SIP)

• Immune to mechanical stress

• Enhanced EMC performance for stringent automotive

applications

These ratiometric Hall-effect sensor ICs provide a voltage

output that is proportional to the applied magnetic field. The

quiescent voltage output is adjusted around 50% of the supply

voltage.

3-pin ultramini SIP

PACKAGES:

1.5 mm × 4 mm × 3 mm

3-pin SOT-23W

2 mm × 3 mm × 1 mm

(suffix LH)

(suffix UA)

The features of these linear devices make them ideal for use in

automotiveandindustrialapplicationsrequiringhighaccuracy,

and they operate across an extended temperature range,

–40°C to 150°C (SOT-23W) or –40°C to 125°C (SIP).

Each BiCMOS monolithic circuit integrates a Hall element,

temperature-compensating circuitry to reduce the intrinsic

Continued on the next page…

Not to scale

Functional Block Diagram

V+

VCC

VOUT

Sensitivity and

Sensitivity TC

Offset and

Offset TC

C_BYPASS

GND

A1308-9-DS, Rev. 7

January 4, 2017

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

DESCRIPTION (continued)

sensitivitydriftoftheHallelement,asmall-signalhigh-gainamplifier,

a clamped low-impedance output stage, and a proprietary dynamic

offset cancellation technique.

TheA1308 andA1309 sensor ICs are offered in two package styles.

The LH is a SOT-23W style, miniature, low-profile package for

surface-mount applications. The UA is a 3-pin, ultramini, single

inline package (SIP) for through-hole mounting. Both packages are

lead (Pb) free, with 100% matte-tin leadframe plating.

SELECTION GUIDE

Operating Ambient

Temperature Range

(T_A) (°C)

Output

Polarity

Sensitivity

(typ) (mV/G)

Part Number

Packing^[1]

Package

A1308LLHLX-05-T

A1308KUA-1-T

Forward

Reverse

0.5

1.3

2.5

3.125

5

–40 to 150

–40 to 125

–40 to 150

–40 to 125

–40 to 150

–40 to 125

–40 to 150

–40 to 125

–40 to 150

10,000 pieces per reel

500 pieces per bag

10,000 pieces per reel

500 pieces per bag

10,000 pieces per reel

500 pieces per bag

10,000 pieces per reel

500 pieces per bag

10,000 pieces per reel

3-pin SOT-23W surface mount

3-pin SIP through hole

A1308LLHLX-1-T

A1308LLHLX-2-T

A1308KUA-2-T

3-pin SOT-23W surface mount

3-pin SIP through hole

A1308KUA-3-T

3-pin SIP through hole

A1308LLHLX-3-T

A1308KUA-5-T

3-pin SOT-23W surface mount

3-pin SIP through hole

A1308LLHLX-5-T

A1309LLHLX-9-T

A1309KUA-9-T

5

3-pin SOT-23W surface mount

3-pin SIP through hole

9

A1309LLHLX-RP9-T

–9

3-pin SOT-23W surface mount

¹Contact Allegro for additional packing options.

ABSOLUTE MAXIMUM RATINGS

Characteristic

Forward Supply Voltage

Reverse Supply Voltage

Forward Output Voltage

Reverse Output Voltage

Output Source Current

Output Sink Current

Symbol

Notes

Rating

Unit

V

V_CC

V_RCC

V_OUT

V_ROUT

8

–0.1

V

7

–0.1

V

I_OUT(SOURCE)VOUT to GND

2

mA

°C

I_OUT(SINK)

VCC to VOUT

Range K

10

–40 to 125

–40 to 150

165

Operating Ambient Temperature

T_A

Range L

Maximum Junction Temperature

Storage Temperature

T_J(max)

T_stg

–65 to 170

Allegro MicroSystems, LLC

115 Northeast Cutoff

2

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

PINOUT DIAGRAMS AND TERMINAL LIST TABLE

LH Package

Pinout

UA Package

Pinout

Terminal List Table

Number

Name

Description

LH

UA

3

Input power supply; tie to GND

with bypass capacitor

VCC

1

VOUT

GND

2

3

2

Output signal

Ground

1

2

1

2

3

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions

Value

Units

Package LH, 1-layer PCB with copper limited to solder pads

228

°C/W

2

Package LH, 2-layer PCB with 0.463 in. of copper area each side

connected by thermal vias

Package Thermal Resistance

R_θJA

110

165

°C/W

Package UA, 1-layer PCB with copper limited to solder pads

Allegro MicroSystems, LLC

115 Northeast Cutoff

3

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

OPERATING CHARACTERISTICS: Valid through T_A, C_BYPASS= 0.1 µF, V_CC= 5 V, unless otherwise noted

Characteristics

ELECTRICAL CHARACTERISTICS

Supply Voltage

Symbol

Test Conditions

Min.

Typ.

Max.

Unit ^[1]

V_CC

4.5

–

5.0

–

5.5

3

V

K temp. option tested at T_A= 25°C to 125°C

(device powers on); L temp. option tested at T_A=

25°C to 150°C (device powers on)

V_UVLOHI

Undervoltage Threshold^[2]

K temp. option tested at T_A= 25°C to 125°C

V_UVLOLO(device powers off); L temp. option tested at T_A=

25°C to 150°C (device powers off)

2.5

–

V

Supply Current

I_CC

t_PO

No load on VOUT

T_A= 25°C, C_L(PROBE)= 10 pF

T_A= 25°C

–

9

50

–

11.5

–

mA

µs

Power-On Time^[3][4]

–

V

_CCRamp Time^[3][4]

_CCOff Level^[3][4]

t_VCC

V_CCOFF

t_CLP

V_Z

0.005

100

0.55

–

ms

V

T_A= 25°C

0

–

6

–

Delay to Clamp^[3][4]

T_A= 25°C, C_L= 10 nF

T_A= 25°C, I_CC= 14.5 mA

Small signal –3 dB

T_A= 25°C

30

7.3

20

400

µs

Supply Zener Clamp Voltage

Internal Bandwidth^[3]

–

V

BW_i

f_C

–

kHz

Chopping Frequency^[3][5]

OUTPUT CHARACTERISTICS

–

V_CC= 5 V, T_A= 25°C, C_BYPASS= open,

Sens ≥ 1.3 mV/G, no load on VOUT

–

1.7

2.8

1.5

2.5

–

G

Output Referred Noise^[3][6]

V_N

V_CC= 5 V, T_A= 25°C, C_BYPASS= open,

G

Sens = 0.5 mV/G, no load on VOUT

V_CC= 5 V, T_A= 25°C, C_BYPASS= open,

Sens ≥ 1.3 mV/G, no load on VOUT

mG/√Hz

Input Referred RMS Noise Density^[3]

V_NRMS

V_CC= 5 V, T_A= 25°C, C_BYPASS= open,

Sens = 0.5 mV/G, no load on VOUT

DC Output Resistance^[3]

Output Load Resistance^[3]

Output Load Capacitance^[3]

R_OUT

R_L

–

3

–

Ω

VOUT to GND

4.7

–

kΩ

C_L

–

10

nF

V_CLPHIGHT_A= 25°C, R_L=10kΩ(VOUT to GND)

V_CLPLOWT_A= 25°C, R_L=10kΩ(VOUTto VCC)

A1308LLHLX-05-T

4.35

0.40

0.43

1.17

2.4

4.5

0.55

0.5

1.3

2.5

3.125

5

4.65

0.70

0.57

1.43

2.6

V

Output Voltage Clamp^[7][8]

V

mV/G

V

A1308KUA-1-T

A1308LLHLX-1-T

A1308LLHLX-2-T

A1308KUA-2-T

2.4

2.6

A1308KUA-3-T

3.025

4.85

8.73

–9.27

2.488

3.225

5.15

9.27

–8.73

2.512

Sensitivity

Sens

T_A= 25°C

A1308LLHLX-3-T

A1308KUA-5-T

A1308LLHLX-5-T

A1309LLHLX-9-T

A1309KUA-9-T

A1309LLHLX-RP9-T

T_A= 25°C

5

9

–9

Quiescent Voltage Output (QVO)

Sensitivity Temperature Coefficient

V_OUT(Q)

TC_Sens

2.5

Programmed at T_A= 125°C (K temp. option) or

150°C (L temp. option), calculated relative to

Sens at 25°C

0.08

0.12

0.16

%/°C

Continued on the next page…

Allegro MicroSystems, LLC

115 Northeast Cutoff

4

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

OPERATING CHARACTERISTICS (continued): Valid through T_A, C_BYPASS= 0.1 µF, V_CC= 5 V, unless otherwise noted

Characteristics

ERROR COMPONENTS

Linearity Sensitivity Error

Symmetry Sensitivity Error

Symbol

Test Conditions

Min.

Typ.

Max.

Unit ^[1]

Lin_ERR

–

±1.5

–

%

Sym_ERR

Ratiometry Quiescent Voltage

Output Error^[9]

Rat_VOUT(Q)Across supply voltage range (relative to V_CC= 5 V)

–

±1.5

–

%

Ratiometry Sensitivity Error^[9]

Ratiometry Clamp Error^[10]

DRIFT CHARACTERISTICS

Rat_Sens

Across supply voltage range (relative to V_CC= 5 V)

T_A= 25°C, across supply voltage range (relative

to V_CC= 5 V)

Rat_VOUTCLP

A1308KUA-1-T

A1308KUA-2-T

–15

–10

–20

–15

–20

–30

0

–

15

10

15

0

mV

A1308KUA-3-T

T_A= 125°C

A1308KUA-5-T

A1309KUA-9-T

A1308LLHLX-05-T

A1308LLHLX-1-T

A1308LLHLX-2-T

A1308LLHLX-3-T

A1308LLHLX-5-T

A1309LLHLX-9-T

A1309LLHLX-RP9-T

Typical Quiescent Voltage Output Drift

Across Temperature Range

∆V_OUT(Q)

T_A= 150°C

0

Sensitivity Drift Due to

Package Hysteresis^[11]

∆Sens_PKGT_A= 25°C, after temperature cycling

–

±2

–

%

¹1 G (gauss) = 0.1 mT (millitesla),

²On power-up, the output of the device is held low until V_CCexceeds V_UVLOHI. After the device is powered, the output remains valid until V_CCdrops

below V_UVLOLO, when the output is pulled low.

³Determined by design and characterization, not evaluated at final test.

⁴See the Characteristic Definitions section.

⁵f_Cvaries as much as approximately ±20% across the full operating ambient temperature range and process.

⁶Output Referred Noise is calculated as 6 sigma (6 standard deviations) from characterization of a small sample of devices. Conversion of noise from

gauss to mV_(P-P)can be done by: Noise (G) × Sensitivity (mV/G) = Noise (mV_(P-P)).

⁷V_CLPLOWand V_CLPHIGHscale with V_CCdue to ratiometry.

⁸Parameter is tested at wafer probe only.

⁹Percent change from actual value at V_CC= 5 V, for a given temperature.

¹⁰Percent change from actual value at V_CC= 5 V, T_A= 25°C.

¹¹Sensitivity drift through the life of the part, ΔSens_LIFE, can have a typical error value ±3% in addition to package hysteresis effects.

Allegro MicroSystems, LLC

115 Northeast Cutoff

5

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

CHARACTERISTIC DEFINITIONS

Power-On Time. When the supply is ramped to its operating

voltage, the device output requires a finite time to react to an

input magnetic field. Power-On Time, t_PO, is defined as the time

it takes for the output voltage to begin responding to an applied

magnetic field after the power supply has reached its minimum

specified operating voltage, V_CC(min), as shown in Figure 1.

Quiescent Voltage Output. In the quiescent state (no signifi-

cant magnetic field: B = 0 G), the output, V_OUT(Q), is at a con-

stant ratio to the supply voltage, V_CC, across the entire operating

ranges of V_CCand Operating Ambient Temperature, T_A.

Quiescent Voltage Output Drift Across Temperature

Range. Due to internal component tolerances and thermal

considerations, the Quiescent Voltage Output, V_OUT(Q), may

drift due to temperature changes within the Operating Ambient

Delay to Clamp. A large magnetic input step may cause the

clamp to overshoot its steady-state value. The Delay to Clamp,

t_CLP, is defined as the time it takes for the output voltage to settle Temperature, T_A. For purposes of specification, the Quiescent

within 1% of its steady-state value, after initially passing through Voltage Output Drift Across Temperature Range, ∆V_OUT(Q)(mV),

its steady-state voltage, as shown in Figure 2.

is defined as:

∆V_OUT(Q)

V_OUT(Q)(TA)–V_{OUT(Q)(25°C)}

=

(1)

V

V_CC

Sensitivity. The amount of the output voltage change is propor-

tional to the magnitude and polarity of the magnetic field applied.

This proportionality is specified as the magnetic sensitivity,

Sens (mV/G), of the device and is defined as:

V_CC(typ)

V_OUT

90% V_OUT

V_OUT(B+)– V_OUT(B–)

(2)

Sens

=

V_CC(min)

(B+) – (B–)

t_PO

where B+ is the magnetic flux density in a positive field (south

polarity) and B– is the magnetic flux density in a negative field

(north polarity).

t₁

t₂

t₁= time at which power supply reaches

minimum specified operating voltage

Sensitivity Temperature Coefficient. The device sensitiv-

ity changes as temperature changes, with respect to its Sensitiv-

ity Temperature Coefficient, TC_SENS. TC_SENSis programmed

at 150°C (L temperature device) or at 125°C (K temperature

device), and calculated relative to the baseline sensitivity pro-

gramming temperature of 25°C. TC_SENSis defined as:

t₂= time at which output voltage settles

within ±10% of its steady-state value

under an applied magnetic field

0

+t

Figure 1: Deﬁnition of Power-On Time, t_PO



 



Sens_T2– Sens_T1

1



 



TC_Sens

=

100

)

×

(%/°C

(3)

Sens_T1

T2–T1



 



Magnetic Input Signal

where T1 is the baseline Sens programming temperature of 25°C,

and T2 is the TC_SENSprogramming temperature of 150°C (L

temperature device) or 125°C (K temperature device).

V_CLPHIGH

V_OUT

t_CLP

The ideal value of Sens across the full ambient temperature

range, Sens_IDEAL(TA), is defined as:

t₁

t₂

t₁= time at which output voltage initially

reaches steady-state clamp voltage

Sens_IDEAL(TA)

Sens_T1× [100 (%) + TC_SENS(T_A–T1)]

=

(4)

t₂= time at which output voltage settles to

within 1% of steady-state clamp voltage

Sensitivity Drift Across Temperature Range. Second-

order sensitivity temperature coefficient effects cause the

magnetic sensitivity, Sens, to drift from its ideal value across the

operating ambient temperature range, T_A. For purposes of specifi-

time (µs)

Figure 2: Deﬁnition of Delay to Clamp, t_CLP

cation, the Sensitivity Drift Across Temperature Range, ∆Sens_TC

,

Allegro MicroSystems, LLC

115 Northeast Cutoff

6

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

is defined as:

The output voltage clamps, V_CLPHIGHand V_CLPLOW, limit the

operating magnetic range of the applied field in which the device

provides a linear output. The maximum positive and negative

applied magnetic fields in the operating range can be calculated:

Sens_TA– Sens_IDEAL(TA)

∆Sens_TC

=

100 (%)

×

(5)

Sens_IDEAL(TA)

Sensitivity Drift Due to Package Hysteresis. Package

V_CLPHIGH– V_OUT(Q)

stress and relaxation can cause the device sensitivity at T_A= 25°C

to change during and after temperature cycling. This change in

sensitivity follows a hysteresis curve. For purposes of specifica-



B_MAX(+)



=

(10)

Sens

V_OUT(Q)– V_CLPLOW



B_MAX(–)

tion, the Sensitivity Drift Due to Package Hysteresis, ∆Sens_PKG

,

Sens

is defined as:

Sens_(25°C)(2)– Sens_(25°C)(1)

Symmetry Sensitivity Error. The magnetic sensitivity of the

device is constant for any two applied magnetic fields of equal

magnitude and opposite polarities. Symmetry error, Sym_ERR(%),

is measured and defined as:

∆Sens_PKG

=

(6)

100 (%)

×

Sens_(25°C)(1)

where Sens_(25°C)(1)is the programmed value of sensitivity

at T_A= 25°C, and Sens_(25°C)(2)is the value of sensitivity at

T_A= 25°C after temperature cycling T_Aup to 150°C (L tempera-

ture device) or 125°C (K temperature device), down to –40°C,

and back up to 25°C.



Sens_(B+)

Sens_(B–)







1–

Sym_ERR

=

100 (%)

×

(11)







where Sens_Bxis as defined in equation 10, and B+ and B– are

positive and negative magnetic fields such that |B+| = |B–|.

Linearity Sensitivity Error. The A1308 and A1309 are

designed to provide linear output in response to a ramping

applied magnetic field. Consider two magnetic fields, B1 and B2.

Ideally, the sensitivity of a device is the same for both fields, for

a given supply voltage and temperature. Linearity error is present

when there is a difference between the sensitivities measured at

B1 and B2.

Ratiometry Error. The A1308 and A1309 provide ratiometric

output. This means that the Quiescent Voltage Output, V_OUT(Q)

magnetic sensitivity, Sens, and clamp voltages, V_CLPHIGHand

V_CLPLOW, are proportional to the supply voltage, V_CC. In other

words, when the supply voltage increases or decreases by a

certain percentage, each characteristic also increases or decreases

by the same percentage. Error is the difference between the

measured change in the supply voltage relative to 5 V and the

measured change in each characteristic.

,

Linearity Sensitivity Error, LIN_ERR, is calculated separately for

positive (Lin_ERR+) and negative (Lin_ERR–) applied magnetic

fields. LIN_ERR(%) is measured and defined as:







Sens



The ratiometric error in quiescent voltage output, Rat_VOUT(Q)

(%), for a given supply voltage, V_CC, is defined as:



^(B+)(2)

1–

Lin_ERR+

=

100 (%)

(7)

×



Sens_(B+)(1)





V_OUT(Q)(VCC)/ V





^OUT(Q)(5V)

Sens_(B–)(2)





1–

Rat_VOUT(Q)

=

100 (%)

×

(12)









1–

Lin_ERR–

V_CC/ 5 (V)







Sens

^(B–)(1)

The ratiometric error in magnetic sensitivity, Rat_Sens(%), for a

given supply voltage, V_CC, is defined as:

where:

|V_OUT(Bx)

V

|

–

OUT(Q)

Sens_Bx

=

(8)



Sens_(VCC)/ Sens

V_CC/ 5 (V)



B_x



^(5V)

1–

Rat_Sens

=

100 (%)

(13)

×









and Bx are positive and negative magnetic fields, with respect to

the quiescent voltage output, such that

The ratiometric error in the clamp voltages, Rat_VOUTCLP(%), for

a given supply voltage, V_CC, is defined as:

|B₍₊₎₍₂₎| > |B₍₊₎₍₁₎| and |B_(–)(2)| > |B_(–)(1)

The effective linearity error is:

|



V_CLP(VCC)/ V





^CLP(5V)

1–

Rat_VOUTCLP

=

100 (%)

(14)

×





V_CC/ 5 (V)





Lin_ERRmax(|Lin

| |Lin_ERR–|)

=

,

ERR+

(9)

where V_CLPis either V_CLPHIGHor V_CLPLOW

.

Allegro MicroSystems, LLC

115 Northeast Cutoff

7

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

Undervoltage Lockout. The A1308 and A1309 provide an

undervoltage lockout feature which ensures that the device out-

puts a V_OUTsignal only when V_CCis above certain thresholds.

The undervoltage lockout feature provides a hysteresis of opera-

tion to eliminate indeterminate output states.

V

UVLOHI

V

CC

V

UVLOLO

t

UVLO

The output of the A1308 and A1309 is held low (GND) until

V_CCexceeds V_UVLOHI. After V_CCexceeds V_UVLOHI, the device

VOUT output is enabled, providing a ratiometric output voltage

that is proportional to the input magnetic signal and V_CC. If V_CC

should drop back down below V_UVLOLOfor longer than t_UVLO

after the device is powered up, the output would be pulled low

(see Figure 3) until V_UVLOHIis reached again and VOUT would

be reenabled.

V

OUT

time

Figure 3: Deﬁnition of Undervoltage Lockout

V_CCRamp Time. The time taken for V_CCto ramp from 0 V to

t_VCC

V_CC(typ), 5 V (see Figure 4).

V_CC(typ)

V_CCOff Level. For applications in which the VCC pin of the

A1308 or A1309 is being power-cycled (for example using a

multiplexer to toggle the part on and off), the specification of

V_CCOff Level, V_CCOFF, determines how high a V_CCoff voltage

can be tolerated while still ensuring proper operation and startup

of the device (see Figure 4).

V_CCOFF

0

time

Figure 4: Deﬁnition of V_CCRamp Time, t_VCC

Allegro MicroSystems, LLC

115 Northeast Cutoff

8

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

APPLICATION INFORMATION

A1308

A1309

VOUT

VCC

R_L

4.7 nF

GND

0.1 µF

5 V

Figure 5: Typical Application Circuit

through a low-pass filter, while the modulated DC offset is sup-

pressed. In addition to the removal of the thermal and mechanical

stress-related offset, this novel technique also reduces the amount

of thermal noise in the Hall sensor IC while completely removing

the modulated residue resulting from the chopper operation. The

chopper stabilization technique uses a high-frequency sampling

clock. For demodulation process, a sample-and-hold technique

is used. This high-frequency operation allows a greater sampling

rate, which results in higher accuracy and faster signal-processing

capability. This approach desensitizes the chip to the effects

of thermal and mechanical stresses, and produces devices that

have extremely stable quiescent Hall output voltages and precise

recoverability after temperature cycling. This technique is made

possible through the use of a BiCMOS process, which allows the

use of low-offset, low-noise amplifiers in combination with high-

Chopper Stabilization Technique

When using Hall-effect technology, a limiting factor for

switchpoint accuracy is the small signal voltage developed across

the Hall element. This voltage is disproportionally small relative

to the offset that can be produced at the output of the Hall sensor

IC. This makes it difficult to process the signal while maintain-

ing an accurate, reliable output over the specified operating

temperature and voltage ranges. Chopper stabilization is a unique

approach used to minimize Hall offset on the chip. Allegro

employs a technique to remove key sources of the output drift

induced by thermal and mechanical stresses. This offset reduction

technique is based on a signal modulation-demodulation process.

The undesired offset signal is separated from the magnetic field-

induced signal in the frequency domain, through modulation.

The subsequent demodulation acts as a modulation process for

the offset, causing the magnetic field-induced signal to recover

its original spectrum at baseband, while the DC offset becomes a

high-frequency signal. The magnetic-sourced signal then can pass density logic integration and sample-and-hold circuits.

Regulator

Clock/Logic

Hall Element

Amp

Anti-aliasing Tuned

LP Filter

Filter

Figure 6: Chopper Stabilization Technique

Allegro MicroSystems, LLC

115 Northeast Cutoff

9

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

Package LH, 3-Pin (SOT-23W)

+0.12

–0.08

2.98

3

D

1.49

4°±4°

A

+0.020

–0.053

0.180

D

0.96

D

+0.10

2.90

+0.19

–0.06

2.40

1.91

–0.20

0.70

0.25 MIN

1.00

2

1

0.55 REF

0.25 BSC

0.95

Seating Plane

Gauge Plane

PCB Layout Reference View

B

Branded Face

8X 10° REF

C

Branding Reference View

1.00 ±0.13

+0.10

NNN

0.05

–0.05

0.95 BSC

0.40 ±0.10

1

For Reference Only; not for tooling use (reference DWG-2840)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Part Number

NNN

A1308LLHLX-05-T

A1308LLHLX-1-T

A1308LLHLX-2-T

A1308LLHLX-3-T

A1308LLHLX-5-T

A1309LLHLX-9-T

A1309LLHLX-RP9-T

308

309

09R

Active Area Depth, 0.28 mm REF

A

B

Reference land pattern layout

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

C

D

Branding scale and appearance at supplier discretion

Hall element, not to scale

Allegro MicroSystems, LLC

115 Northeast Cutoff

10

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

Package UA, 3-Pin SIP

+0.08

4.09

–0.05

45°

B

C

E

2.04

1.52 ±0.05

10°

1.44

E

Mold Ejector

Pin Indent

+0.08

3.02

–0.05

45°

Branded

Face

0.79 REF

A

NNN

1.02

MAX

1

Standard Branding Reference View

D

1

2

3

= Supplier emblem

N = Last three digits of device part number

14.99 ±0.25

+0.03

–0.06

0.41

For Reference Only; not for tooling use (reference DWG-9065)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

+0.05

–0.07

0.43

Dambar removal protrusion (6X)

A

B

C

D

Gate and tie bar burr area

Active Area Depth, 0.50 mm REF

Branding scale and appearance at supplier discretion

Hall element (not to scale)

E

1.27 NOM

Allegro MicroSystems, LLC

115 Northeast Cutoff

11

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A1308 and

A1309

Linear Hall-Effect Sensor ICs with Analog Output

Available in a Miniature, Low-Profile Surface-Mount Package

Revision History

Number

Date

Description

–

1

2

3

4

5

6

7

June 27, 2014

Initial release

June 27, 2014

Updated product offerings

November 13, 2015

March 30, 2016

April 19, 2016

September 2, 2016

December 9, 2016

January 4, 2017

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, LLC

115 Northeast Cutoff

12

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

型号	制造商	描述	价格	文档
A1310AG1	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310AG2	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310AS1	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310AS2	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310AT1	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310AT2	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310BG1	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310BG2	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310BS1	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格
A1310BS2	DBLECTRO	DIP PLUG PITCH:2.54mm	获取价格

A1309LLHLX-RP9-T

A1309LLHLX-RP9-T 概述

A1309LLHLX-RP9-T 数据手册

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