A1367LKTTN-2-T [ALLEGRO]
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC;
| 型号： | A1367LKTTN-2-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC |
| 文件： | 总27页 (文件大小：845K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A1367
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
FEATURES AND BENEFITS
DESCRIPTION
• 240 kHz nominal bandwidth achieved via proprietary
packaging and chopper stabilization techniques
• On-board supply regulator with reverse-battery protection
• Proprietary segmented linear temperature compensation
(TC) technology provides a typical accuracy of 1% over
the full operating temperature range
The Allegro™ A1367 programmable linear Hall-effect
current sensor IC has been designed to achieve high accuracy
and resolution without compromising bandwidth. This goal
is achieved through new proprietary linearly interpolated
temperature compensation technology that is programmed
at the Allegro factory and provides sensitivity and offset that
are virtually flat across the full operating temperature range.
Temperature compensation is performed in the digital domain
with integrated EEPROM technology while maintaining a
240 kHz bandwidth analog signal path, making this device
idealforHEVinverter,DC-to-DCconverter,andelectricpower
steering (EPS) applications.
• Customer-programmable, high-resolution offset and
sensitivity trim
• Factory-programmed sensitivity and quiescent
output voltage TC with extremely stable temperature
performance
• High-sensitivity Hall element for maximum accuracy
• Extremely low noise and high resolution achieved via
proprietary Hall element and low-noise amplifier circuits
ThisratiometricHall-effectsensorICprovidesavoltageoutput
thatisproportionaltotheappliedmagneticfield.Thecustomer
can configure the sensitivity and quiescent (zero field) output
voltage through programming on the VCC and output pins,
to optimize performance in the end application. The quiescent
output voltage is user-adjustable, around 50% (bidirectional
configuration) or 10% (unidirectional configuration) of the
supply voltage, VCC, and the output sensitivity is adjustable
within the range of 0.6 to 6.4 mV/G.
Continued on the next page…
PACKAGE:
4-Pin SIP (suffix KT)
Continued on the next page…
Not to scale
VCC
(Programming)
Programming
Regulator
Undervoltage
Detection
Broken
Ground
Detection
Charge Pump
Pulse Generator
Control
To all
subcircuits
CBYPASS
Temperature
Sensor
EEPROM and
Control Logic
Active Temp.
Compensation
Sensitivity Control
Offset Control
Output
Clamps
VOUT
(Programming)
Signal Recovery
Push/Pull
Output Driver
CL
GND
Functional Block Diagram
A1367-DS, Rev. 1
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
FEATURES AND BENEFITS (CONTINUED)
DESCRIPTION (CONTINUED)
• Patented circuits suppress IC output spiking during fast current The sensor IC incorporates a highly sensitive Hall element with
step inputs
a BiCMOS interface integrated circuit that employs a low-noise
small-signal high-gain amplifier, a clamped low-impedance output
stage,andaproprietary,high-bandwidthdynamicoffsetcancellation
technique. These advances in Hall-effect technology work together
to provide an industry-leading sensing resolution at the full 240 kHz
bandwidth. Broken ground wire detection as well as user-selectable
outputvoltageclampsalsoarebuiltintothisdeviceforhighreliability
in automotive applications.
• Open circuit detection on ground pin (broken wire)
• Selectable sensitivity range between 0.6 and 6.4 mV/G
through use of coarse sensitivity program bits
• User-selectable ratiometric behavior of sensitivity, quiescent
voltage, and clamps (ratiometry can be disabled), for simple
interface with application A-to-D converter (ADC)
• Precise recoverability after temperature cycling
• Output voltage clamps provide short-circuit diagnostic
capabilities
• Wide ambient temperature range: –40°C to 150°C
• Immune to mechanical stress
• Extremely thin package: 1 mm case thickness
• AEC-Q100 automotive qualified
Device parameters are specified across an extended ambient
temperaturerange:–40°Cto150°C.TheA1367sensorICisprovided
in an extremely thin case (1 mm thick), 4-pin SIP (single in-line
package, suffix KT) that is lead (Pb) free, with 100% matte-tin
leadframe plating.
Selection Guide
Sensitivity Range2
(mV/G)
Part Number
Package
Packing1
A1367LKTTN-1-T
A1367LKTTN-2-T
A1367LKTTN-2U-T
A1367LKTTN-5-T
4-pin SIP
4-pin SIP
4-pin SIP
4-pin SIP
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
4000 pieces per 13-in. reel
SENS_COARSE 00: 0.6 to 1.3
SENS_COARSE 01: 1.3 to 2.9
SENS_COARSE 01: 1.3 to 2.9
SENS_COARSE 10: 2.9 to 6.4
1 Contact Allegro for additional packing options
2 Allegro recommends against changing Coarse Sensitivity settings when programming devices that will be used in production. Each A1367
has been factory temperature compensated at a specific sensitivity range, and changing the coarse bits setting could cause sensitivity drift
through temperature range (ΔSensTC) to exceed specified limits.
Table of Contents
Specifications
Absolute Maximum Ratings
Thermal Characteristics
Pinout Diagram and Terminal List Table
Operating Characteristics
Characteristic Performance Data
Characteristic Definitions
Functional Description
Programming Sensitivity and Quiescent
Voltage Output
Coarse Sensitivity
Memory-Locking Mechanisms
Power-On Reset (POR) Operation
Detecting Broken Ground Wire
Chopper Stabilization Technique
3
3
3
4
5
8
11
16
Programming Guidelines
20
20
22
22
22
22
24
24
25
Serial Communication
Writing Access Code
Writing to Volatile Memory
Writing to Nonvolatile Memory
Reading from EEPROM or Volatile Memory
Enabling/Disabling Ratiometry
EEPROM Cell Organization
Diagnostic Clamps
EEPROM Error Checking and Correction (ECC) 25
Detecting ECC Error
Package Outline Drawing
16
16
16
17
18
19
25
26
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
SPECIFICATIONS
Absolute Maximum Ratings
Characteristic
Symbol
VCC
Notes
Rating
15
Unit
V
Forward Supply Voltage
Reverse Supply Voltage
Forward Output Voltage
Reverse Output Voltage
Output Source Current
Output Sink Current
VRCC
TJ(max) should not be exceeded
VOUT < VCC + 2 V
–15
16
V
VOUT
V
VROUT
Difference between VCC and output should not exceed 20 V
VOUT to GND
–6
V
IOUT(source)
IOUT(sink)
2.8
10
mA
mA
VCC to VOUT
Maximum Number of EEPROM Write
Cycles
EEPROMw(max)
100
cycle
Operating Ambient Temperature
Storage Temperature
TA
Tstg
L temperature range
–40 to 150
–65 to 165
165
°C
°C
°C
Maximum Junction Temperature
TJ(max)
Thermal Characteristics: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions*
Value
Unit
Package Thermal Resistance
RθJA
On 1-layer PCB with exposed copper limited to solder pads
174
°C/W
*Additional thermal information available on the Allegro website
Power Dissipation versus Ambient Temperature
900
800
700
600
500
400
300
200
(R
qJA
=
174
ºC/W)
100
0
20
40
60
80
100
120
140
160
180
Temperature, TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
Pinout Diagram and Terminal List Table
Terminal List Table
Number
Name
Function
Input Power Supply, use bypass capacitor to connect to ground;
also used for programming
1
VCC
2
3
4
VOUT
NC
Output Signal, also used for programming
No connection; connect to GND for optimal ESD performance
Ground
GND
1
2 3 4
KT Package Pinout Diagram
(Ejector pin mark on opposite side)
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
OPERATING CHARACTERISTICS: Valid through the full operating temperature range, TA, CBYPASS = 0.1 µF, VCC = 5 V, un-
less otherwise specified
Characteristic
ELECTRICAL CHARACTERISTICS
Supply Voltage
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
VCC
ICC
4.5
–
5
5.5
V
Supply Current
No load on VOUT
11
16.25
mA
TA = 25°C, CBYPASS = open, CL = 1 nF,
Sens = 2 mV/G, constant magnetic field
of 400 G
Power-On Time2
tPO
–
–
80
–
–
µs
µs
TA = 150°C, CBYPASS = open, CL = 1 nF,
Sens = 2 mV/G, constant magnetic field
of 400 G
Temperature Compensation
Power-On Time2
tTC
146
VPORH
VPORL
VPORHYS
tPORR
tPORA
Vz
TA = 25°C, VCC rising
TA = 25°C, VCC falling
TA = 25°C
3.75
–
4
4.2
–
V
V
Power-On Reset Voltage2
3.5
500
32
Power-On Reset Hysteresis
Power-On Reset Release Time2
Power-On Reset Analog Delay
Supply Zener Clamp Voltage
Internal Bandwidth
–
–
mV
µs
TA = 25°C, VCC rising
TA = 25°C, VCC rising
TA = 25°C, ICC = 30 mA
Small signal –3 dB, CL = 1 nF, TA = 25°C
TA = 25°C
–
–
–
46
–
µs
6.5
–
7.5
240
1
–
V
BWi
–
kHz
MHz
Chopping Frequency3
fC
–
–
OUTPUT CHARACTERISTICS
TA = 25°C, magnetic field step of 400 G,
CL = 1 nF, Sens = 2 mV/G
Propagation Delay Time2
Rise Time2
tpd
tr
–
–
1.1
2.4
–
–
µs
µs
TA = 25°C, magnetic field step of 400 G,
CL = 1 nF, Sens = 2 mV/G
TA = 25°C, magnetic field step of 400 G,
CL = 1 nF, Sens = 2 mV/G, measurement of
80% input to 80% output
–
1.8
–
µs
Response Time2
tRESPONSE
TA = 25°C, magnetic field step of 400 G,
CL = 1 nF, Sens = 2 mV/G, measurement of
90% input to 90% output
–
–
2.2
10
–
–
µs
µs
TA = 25°C, magnetic field step from 800 to
1200 G, CL = 1 nF, Sens = 2 mV/G
Delay to Clamp2
tCLP
VCLP(HIGH) TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
4.55
0.15
4.7
–
–
–
4.85
0.45
–
V
Output Voltage Clamp4
VCLP(LOW)
VSAT(HIGH)
VSAT(LOW)
TA = 25°C, RL(PULLUP) = 10 kΩ to VCC
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
TA = 25°C, RL(PULLDWN) = 10 kΩ to VCC
V
V
–
Output Saturation Voltage2
Broken Wire Voltage2
–
400
–
mV
VBRK(HIGH) TA = 25°C, RL(PULLUP) = 10 kΩ to VCC
–
VCC
100
1.4
V
VBRK(LOW)
TA = 25°C, RL(PULLDWN) = 10 kΩ to GND
–
–
mV
mG/√(Hz)
TA = 25°C, CL = 1 nF, BWf = BWi
–
–
TA = 25°C, CL = 1 nF, Sens = 2 mV/G,
BWf = BWi
–
–
12.6
2.1
mVp-p
–
Noise5
VN
TA = 25°C, CL = 1 nF, Sens = 2 mV/G,
BWf = BWi
mVRMS
–
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
OPERATING CHARACTERISTICS (continued): Valid through the full operating temperature range, TA, CBYPASS = 0.1 µF,
VCC = 5 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
OUTPUT CHARACTERISTICS (continued)
DC Output Resistance
ROUT
–
4.7
4.7
–
3
–
–
–
Ω
kΩ
RL(PULLUP) VOUT to VCC
RL(PULLDWN) VOUT to GND
Output Load Resistance
–
–
kΩ
Output Load Capacitance6
CL
VOUT to GND
Sens = 2 mV/G, CL = 1 nF
1
10
–
nF
Output Slew Rate7
SR
–
480
V/ms
2
QUIESCENT VOLTAGE OUTPUT (VOUT(Q)
)
VOUT(QBI)init TA = 25°C
VOUT(QU)init TA = 25°C
VOUT(QBI)PR TA = 25°C
VOUT(QU)PR TA = 25°C
2.4
0.45
2.35
0.4
2.5
0.5
–
2.6
0.55
2.65
0.6
V
V
V
V
Initial Unprogrammed Quiescent
Voltage Output2,8
Quiescent Voltage Output
Programming Range2,4,9
–
Quiescent Voltage Output
Programming Bits10
QVO
–
0.95
–
9
–
1.4
–
bit
Average Quiescent Voltage Output
Programming Step Size2,11,12
StepVOUT(Q) TA = 25°C
ErrPGVOUT(Q) TA = 25°C
1.15
mV
mV
Quiescent Voltage Output
Programming Resolution2,13
±0.5 ×
StepVOUT(Q)
SENSITIVITY (Sens)2
SENS_COARSE = 00, TA = 25°C
–
–
1
2.2
4.7
–
–
–
mV/G
mV/G
mV/G
mV/G
mV/G
mV/G
bit
Initial Unprogrammed Sensitivity8
Sensinit
SensPR
SENS_COARSE = 01, TA = 25°C
SENS_COARSE = 10, TA = 25°C
SENS_COARSE = 00, TA = 25°C
SENS_COARSE = 01, TA = 25°C
SENS_COARSE = 10, TA = 25°C
–
–
0.6
1.3
2.9
–
1.3
2.9
6.4
–
Sensitivity Programming Range4,9
–
–
Coarse Sensitivity Programming Bits14
Fine Sensitivity Programming Bits10
2
SENS_COARSE
SENS_FINE
–
9
–
bit
SENS_COARSE = 00, TA = 25°C
SENS_COARSE = 01, TA = 25°C
SENS_COARSE = 10, TA = 25°C
2.4
5
3.2
6.6
14.2
4.1
8.5
18
µV/G
µV/G
µV/G
Average Fine Sensitivity and
Temperature Compensation
Programming Step Size2,14,15
StepSENS
11
±0.5 ×
StepSENS
Sensitivity Programming Resolution2,13
ErrPGSENS TA = 25°C
–
–
–
µV/G
FACTORY-PROGRAMMED SENSITIVITY TEMPERATURE COEFFICIENT
TA = 150°C,TA= –40°C,calculated relative to
25°C
Sensitivity Temperature Coefficient2
TCSENS
0
–
%/°C
TA = 25°C to 150°C
TA = –40°C to 25°C
–2
–
–
2
%
%
Sensitivity Drift Through Temperature
Range2,9,15
ΔSensTC
–3.5
3.5
Average Sensitivity Temperature
Compensation Step Size
StepSENSTC TA = –40°C to 150°C
2 × StepSENS
µV/G
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
OPERATING CHARACTERISTICS (continued): Valid through the full operating temperature range, TA, CBYPASS = 0.1 µF,
VCC = 5 V, unless otherwise specified
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit1
FACTORY-PROGRAMMED QUIESCENT VOLTAGE OUTPUT TEMPERATURE COEFFICIENT
Quiescent Voltage Output
Temperature Coefficient2
TA = 150°C, TA = –40°C, calculated relative
to 25°C
TCQVO
–
0
–
–
mV/°C
mV
TA = 25°C to 150°C; SENS_COARSE = 00
or 01
–10
10
Quiescent Voltage Output Drift
Through Temperature Range2,9,15
ΔVOUT(Q)TC
TA = 25°C to 150°C; SENS_COARSE = 10
TA = –40°C to 25°C
–15
–30
–
–
15
30
mV
mV
Average Quiescent Voltage
Output Temperature Compensation
Step Size
StepQVOTC
EELOCK
–
–
2.3
1
–
–
mV
bit
LOCK BIT PROGRAMMING
EEPROM Lock Bit
ERROR COMPONENTS
Linearity Sensitivity Error2,16
Symmetry Sensitivity Error2
LinERR
–1
–1
< ±0.25
< ±0.25
1
1
%
%
SymERR
Through supply voltage range (relative to
VCC = 5 V ±5%); SENS_COARSE = 00
–0.8
–0.9
–1.2
–1
±0.15
±0.15
±0.25
< ±0.5
< ±1
0.8
0.9
1.2
1
%
%
%
%
%
%
%
Ratiometry Quiescent Voltage Output
Error2,17
Through supply voltage range (relative to
RatERRVOUT(Q)
V
CC = 5 V ±5%); SENS_COARSE = 01
Through supply voltage range (relative to
CC = 5 V ±5%); SENS_COARSE = 10
V
Through supply voltage range (relative to
VCC = 5 V ±5%)
Ratiometry Sensitivity Error2,17
Ratiometry Clamp Error2,18
RatERRSens
RatERRCLP
ΔSensPKG
ΔSensLIFE
Through supply voltage range (relative to
VCC = 5 V ±5%), TA = 25°C
–
–
Sensitivity Drift Due to Package
Hysteresis2
TA = 25°C, after temperature cycling, 25°C to
150°C and back to 25°C
–
±0.6
–
TA = 25°C, shift after AEC Q100 grade 0
qualification testing
Sensitivity Drift Over Lifetime19
–
±1
–
1 1 G (gauss) = 0.1 mT (millitesla).
2 See Characteristic Definitions section.
3 fC varies up to approximately ±20% over the full operating ambient temperature range, TA, and process.
4 Sens, VOUT(Q), VCLP(LOW) , and VCLP(HIGH) scale with VCC due to ratiometry.
5 Noise, measured in mVPP and in mVRMS, is dependent on the sensitivity of the device.
6 Output stability is maintained for capacitive loads as large as 10 nF.
7 High-to-low transition of output voltage is a function of external load components and device sensitivity.
8 Raw device characteristic values before any programming.
9 Exceeding the specified ranges will cause sensitivity and Quiescent Voltage Output drift through the temperature range to deteriorate beyond the specified values.
10 Refer to Functional Description section.
11 Step size is larger than required, in order to provide for manufacturing spread. See Characteristic Definitions section.
12 Non-ideal behavior in the programming DAC can cause the step size at each significant bit rollover code to be greater than twice the maximum specified value of
StepVOUT(Q) or StepSENS
.
13 Overall programming value accuracy. See Characteristic Definitions section.
14 Each A1367 part number is factory programmed and temperature compensated at a different coarse sensitivity setting. Changing coarse bits setting could cause sensitiv-
ity drift through temperature range,ΔSensTC, to exceed specified limits.
15 Allegro will be testing and temperature compensating each device at 150°C. Allegro will not be testing devices at –40°C. Temperature compensation codes will be applied
based on characterization data.
16 Linearity applies to output voltage ranges of ±2 V from the quiescent output for bidirectional devices.
17 Percent change from actual value at VCC = 5 V, for a given temperature, through the supply voltage operating range.
18 Percent change from actual value at VCC = 5 V, TA = 25°C, through the supply voltage operating range.
19 Based on characterization data obtained during standardized stress test for Qualification of Integrated Circuits. Cannot be guaranteed. Drift is a function of customer ap-
plication conditions. Please contact Allegro MicroSystems for further information.
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC PERFORMANCE DATA
Response Time (tRESPONSE
)
400 G Excitation Signal with 10%-90% rise time = 1 µs
Response time (80% input to 80% output) = 2.06 µs, Sensitivity = 2 mV/G, CBYPASS = 0.1 µF, CL = 1 nF
tRESPONSE = 2 µs
Propagation Delay (tPD
)
400 G Excitation Signal with 10%-90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS = 0.1 µF, CL = 1 nF
tPD = 1.1 µs
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC PERFORMANCE DATA (continued)
Rise Time (tr)
400 G Excitation Signal with 10%-90% rise time = 1 µs
Sensitivity = 2 mV/G, CBYPASS = 0.1 µF, CL = 1 nF
tr = 2.3 µs
Power-On Time (tPO
)
400 G Constant Excitation Signal with tPO = 81 µs
Sensitivity = 2 mV/G, CBYPASS = Open, CL = 1 nF
tPO = 71.6 µs
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC PERFORMANCE DATA (continued)
Quiescent Voltage Output Driꢀ Through Temperature Range
versus Ambient Temperature
30
20
10
0
-10
-20
-30
-50
-30
-10
10
30
50
70
90
110
130
150
TA (°C)
Sensiꢀvity Driꢁ Through Temperature Range
versus Ambient Temperature
3
2
1
0
-1
-2
-3
-50
-30
-10
10
30
50
70
90
110
130
150
TA (°C)
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC DEFINITIONS
Power-On Time (tPO)
V
VCC
VCC(typ)
When the supply is ramped to its operating voltage, the device
requires a finite time to power its internal components before
responding to an input magnetic field.
VOUT
90% VOUT
Power-On Time (tPO ) is defined as: the time it takes for the out-
put voltage to settle within ±10% of its steady-state value under
an applied magnetic field, after the power supply has reached
its minimum specified operating voltage (VCC(min)) as shown in
Figure 1.
VCC(min)
tPO
t1
t2
t1= time at which power supply reaches
minimum specified operating voltage
Temperature Compensation Power-On Time
(tTC)
t2= time at which output voltage settles
within ±10% of its steady-state value
under an applied magnetic field
After Power-On Time (tPO ) elapses, tTC is also required before a
valid temperature compensated output.
0
+t
Propagation Delay (tpd)
Figure 1: Power-On Time Definition
The time interval between a) when the applied magnetic field
reaches 20% of its final value, and b) when the output reaches
20% of its final value (see Figure 2).
Applied Magnetic Field
(%)
90
Rise Time (tr)
Transducer Output
The time interval between a) when the sensor IC reaches 10% of
its final value, and b) when it reaches 90% of its final value (see
Figure 2).
Rise Time, t
r
Response Time (tRESPONSE
)
20
10
0
The time interval between a) when the applied magnetic field
reaches 80% of its final value, and b) when the sensor reaches
80% of its output corresponding to the applied magnetic field
(see Figure 3). The 90%-90% is also shown in the Electrical
Characteristics table.
t
Propagation Delay, t
pd
Figure 2: Propagation Delay and Rise Time Definitions
Applied Magnetic Field
(%)
80
Continued on the next page…
Transducer Output
Response Time, t
RESPONSE
0
t
Figure 3: Response Time Definition
Allegro MicroSystems, LLC
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC DEFINITIONS (continued)
Delay to Clamp (tCLP
)
Average Quiescent Voltage Output Program-
ming Step Size (StepVOUT(Q)
)
A large magnetic input step may cause the clamp to overshoot
its steady-state value. The Delay to Clamp (tCLP) is defined as:
the time it takes for the output voltage to settle within ±1% of its
steady-state value, after initially passing through its steady-state
voltage, as shown in Figure 4.
The Average Quiescent Voltage Output Progamming Step Size
(StepVOUT(Q) ) is determined using the following calculation:
VOUT(Q)maxcode – VOUT(Q)mincode
(1)
,
StepVOUT(Q)
=
2n – 1
Quiescent Voltage Output (VOUT(Q)
)
In the quiescent state (no significant magnetic field: B = 0 G),
the output (VOUT(Q) ) has a constant ratio to the supply voltage
(VCC ) throughout the entire operating ranges of VCC and ambient
temperature (TA).
where n is the number of available programming bits in the trim
range, 9 bits, VOUT(Q)maxcode is at decimal code 255, and
VOUT(Q)mincode is at decimal code 256.
Quiescent Voltage Output Programming Res-
Initial Unprogrammed Quiescent Voltage
olution (ErrPGVOUT(Q)
)
Output (VOUT(Q)init
)
The programming resolution for any device is half of its pro-
gramming step size. Therefore, the typical programming resolu-
tion will be:
Before any programming, the Quiescent Voltage Output
(VOUT(Q)) has a nominal value of VCC /2, as shown in Figure 5.
Quiescent Voltage Output Programming
ErrPGVOUT(Q)(typ) = 0.5 × StepVOUT(Q)(typ)
Range (VOUT(Q)PR
)
(2)
The Quiescent Voltage Output (VOUT(Q) ) can be programmed
within the Quiescent Voltage Output Range limits: VOUT(Q)PR(min)
and VOUT(Q)PR(max). Exceeding the specified Quiescent Voltage
Output Range will cause Quiescent Voltage Output Drift Through
Temperature Range (ΔVOUT(Q)TC) to deteriorate beyond the
specified values, as shown in Figure 5.
Quiescent Voltage Output Temperature Coef-
ficient (TCQVO
)
Device VOUT(Q) changes as temperature changes, with respect to
its programmed Quiescent Voltage Output Temperature Coef-
ficient, TCQVO . TCQVO is programmed at 150°C and calculated
relative to the nominal VOUT(Q) programming temperature of
25°C. TCQVO (mV/°C) is defined as:
Magnetic Input
V
VCLP(HIGH)
VOUT
tCLP
TCQVO = [VOUT(Q)T2 – VOUT(Q)T1][1/(T2 – T1)]
(3)
t1
t2
where T1 is the nominal VOUT(Q) programming temperature of
t1= time at which output voltage initially
reaches steady-state clamp voltage
VOUT(Q)PR(max)
value
VOUT(Q)PR(min)
value
VOUT(Q)
t2= time at which output voltage settles to
steady-state clamp voltage ±1% of the
clamp voltage dynamic range, where
clamp voltage dynamic range =
Programming range
(specified limits)
VCLP(HIGH)(min) – VCLP(LOW)(max)
Note: Times apply to both high clamp
(shown) and low clamp.
Distribution of values
resulting from minimum
programming code
(QVO programming bits
set to decimal code 256)
Distribution of values
resulting from maximum
programming code
(QVO programming bits
set to decimal code 255)
Typical initial value before
customer programming
VOUT(Q)init
(QVO programming
bits set to code 0)
0
t
Figure 4: Delay to Clamp definition
Figure 5: Quiescent Voltage Output Range definition
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC DEFINITIONS (continued)
25°C, and T2 is the TCQVO programming temperature of 150°C.
where BPOS and BNEG are two magnetic fields with opposite
The expected VOUT(Q) through the full ambient temperature range polarities.
(VOUT(Q)EXPECTED(TA)) is defined as:
Initial Unprogrammed Sensitivity (Sensinit
)
V
OUT(Q)EXPECTED(TA) = VOUT(Q)T1 + TCQVO(TA – T1)
(4)
Before any programming, Sensitivity has a nominal value that
depends on the SENS_COARSE bits setting. Each A1367 variant
has a different SENS_COARSE setting.
V
OUT(Q)EXPECTED(TA) should be calculated using the actual mea-
sured values of VOUT(Q)T1 and TCQVO rather than programming
target values.
Sensitivity Programming Range (SensPR)
Quiescent Voltage Output Drift Through Tem-
perature Range (ΔVOUT(Q)TC
The magnetic sensitivity (Sens) can be programmed around its
initial value within the sensitivity range limits: SensPR(min) and
SensPR(max). Exceeding the specified Sensitivity Range will
)
Due to internal component tolerances and thermal consider-
ations, the Quiescent Voltage Output (VOUT(Q)) may drift from its
nominal value through the operating ambient temperature (TA).
The Quiescent Voltage Output Drift Through Temperature Range
(ΔVOUT(Q)TC) is defined as:
cause Sensitivity Drift Through Temperature Range (ΔSensTC
)
to deteriorate beyond the specified values. Refer to the Quiescent
Voltage Output Range section for a conceptual explanation of
how value distributions and ranges are related.
Average Fine Sensitivity Programming Step
DVOUT(Q)TC = VOUT(Q)(TA) – VOUT(Q)EXPECTED(TA)
(5)
Size (StepSENS
)
∆VOUT(Q)TC should be calculated using the actual measured
values of ∆VOUT(Q)(TA) and ∆VOUT(Q)EXPECTED(TA) rather than
programming target values.
Refer to the Average Quiescent Voltage Output Programming
Step Size section for a conceptual explanation.
Sensitivity (Sens)
Sensitivity Programming Resolution
(ErrPGSENS
)
The presence of a south polarity magnetic field, perpendicular
to the branded surface of the package face, increases the output
voltage from its quiescent value toward the supply voltage rail.
The amount of the output voltage increase is proportional to the
magnitude of the magnetic field applied.
Refer to the Quiescent Voltage Output Programming Resolution
section for a conceptual explanation.
Sensitivity Temperature Coefficient (TCSENS
)
Device sensitivity changes as temperature changes, with respect
to its programmed sensitivity temperature coefficient, TCSENS
TCSENS is programmed at 150°C and is calculated relative to the
nominal sensitivity programming temperature of 25°C.
TCSENS (%/°C) is defined as:
Conversely, the application of a north polarity field decreases the
output voltage from its quiescent value. This proportionality is
specified as the magnetic sensitivity, Sens (mv/G), of the device,
and it is defined as:
.
VOUT(BPOS) – VOUT(BNEG)
Sens =
,
(6)
SensT2 – Sens
SensT1
1
BPOS – BNEG
TCSENS
=
T1 × 100%
,
(7)
T2–T1
Branded
Face
Mold Ejector
Pin Indent
where T1 is the nominal Sens programming temperature of 25°C,
and T2 is the TCSENS programming temperature of 150°C. The
expected value of Sens over the full ambient temperature range,
SensEXPECTED(TA), is defined as:
Magnetic Flux
Direction Causing the
Output to Increase
TCSENS (T –T1)
A
SensEXPECTED(TA) = SensT1 × 100% +
(8)
100
Figure 6: Magnetic Flux Polarity
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC DEFINITIONS (CONTINUED)
SensEXPECTED(TA) should be calculated using the actual measured where:
values of SensT1 rather than programming target values.
|VOUT(Bx)
V
|
OUT(Q)
–
(12)
SensBx
,
=
Bx
Sensitivity Drift Through Temperature Range
(ΔSensTC
)
and BPOSx and BNEGx are positive and negative magnetic
fields, with respect to the quiescent voltage output such that
|BPOS2| = 2 × |BPOS1| and |BNEG2| = 2 × |BNEG1|.
Second-order sensitivity temperature coefficient effects cause the
magnetic sensitivity, Sens, to drift from its expected value over
the operating ambient temperature range (TA). The Sensitivity
Drift Through Temperature Range (∆SensTC ) is defined as:
Then:
LinERR max(LinERRPOS , LinERRNEG
)
.
=
(13)
SensTA – SensEXPECTED(TA)
∆SensTC
.
100%
=
×
(9) Symmetry Sensitivity Error (SymERR
)
SensEXPECTED(TA)
The magnetic sensitivity of an A1367 device is constant for
Sensitivity Drift Due to Package Hysteresis
(ΔSensPKG
any two applied magnetic fields of equal magnitude and oppo-
site polarities. Symmetry Error, SymERR (%), is measured and
defined as:
)
Package stress and relaxation can cause the device sensitivity at
TA = 25°C to change during and after temperature cycling. The
sensitivity drift due to package hysteresis (∆SensPKG) is defined
as:
SensBPOS
SensBNEG
1–
SymERR
,
100%
=
×
(14)
Sens(25°C)2 – Sens(25°C)1
where SensBx is as defined in equation 12, and BPOSx and
BNEGx are positive and negative magnetic fields such that
|BPOSx| = |BNEGx|.
,
100%
∆SensPKG
=
×
(10)
Sens(25°C)1
where Sens(25°C)1 is the programmed value of sensitivity at TA
= 25°C, and Sens(25°C)2 is the value of sensitivity at TA = 25°C,
after temperature cycling TA up to 150°C and back to 25°C.
Ratiometry Error (RatERR
)
The A1367 device features ratiometric output. This means that
the Quiescent Voltage Output (VOUT(Q)) magnetic sensitivity,
Sens, and Output Voltage Clamp (VCLP(HIGH) and VCLP(LOW)) are
proportional to the Supply Voltage (VCC). In other words, when
the supply voltage increases or decreases by a certain percent-
age, each characteristic also increases or decreases by the same
percentage. Error is the difference between the measured change
in the supply voltage relative to 5 V, and the measured change in
each characteristic.
Linearity Sensitivity Error (LinERR
)
The A1367 is designed to provide a linear output in response to
a ramping applied magnetic field. Consider two magnetic fields,
B1 and B2. Ideally, the sensitivity of a device is the same for both
fields, for a given supply voltage and temperature. Linearity error
is present when there is a difference between the sensitivities
measured at B1 and B2.
Linearity Error
The ratiometric error in Quiescent Voltage Output,
RatERRVOUT(Q) (%), for a given supply voltage (VCC) is defined
as:
Linearity error is calculated separately for the positive
(LinERRPOS) and negative (LinERRNEG) applied magnetic fields.
Linearity Error (%) is measured and defined as:
V
OUT(QBI)(VCC)
VOUT(QBI)(5V)
(15)
Sens
1 –
RatERRVOUT(QBI)
=
100%
×
BPOS2
1–
VCC
LinERRPOS
,
,
=
=
100%
100%
×
×
SensBPOS1
5 V
Sens
BNEG2
(11)
1–
LinERRNEG
Sens
BNEG1
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
14
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
CHARACTERISTIC DEFINITIONS (CONTINUED)
RatERRVOUT(QU) is defined in the same way as RatERRVOUT(QBI)
with a factor of 1/5 multiplied.
Power-On Reset Voltage (VPOR
)
On power-up, to initialize to a known state and avoid current
spikes, the A1367 is held in Reset state. The Reset signal is
disabled when VCC reaches VPORH and time tPORR has elapsed,
allowing the output voltage to go from a high-impedance state
into normal operation. During power-down, the Reset signal is
enabled when VCC reaches VPORL, causing the output voltage to
go into a high-impedance state. (Note that a detailed description
of POR can be found in the Functional Description section).
V
OUT(QU)(VCC)
VOUT(QU)(5V)
1
5
100%
(16)
RatERRVOUT(QU)
1 –
×
×
=
VCC
5 V
This is to scale the ratiometry error of the unidirectional device so
that it can be compared with the bidirectional device.
Power-On Reset Release Time (tPORR
)
The ratiometric error in magnetic sensitivity, RatERRSens (%), for
a given Supply Voltage (VCC) is defined as:
When VCC rises to VPORH , the Power-On Reset Counter starts.
The A1367 output voltage will transition from a high-impedance
state to normal operation only when the Power-On Reset Counter
Sens(VCC) / Sens
VCC / 5 V
(5V)
1–
RatERRSens
.
100%
=
×
(17)
has reached tPORR and VCC has been maintained above VPORH
.
Output Saturation Voltage (VSAT
)
The ratiometric error in the clamp voltages, RatERRCLP (%), for a
given supply voltage (VCC) is defined as:
When output voltage clamps are disabled, the output voltage
can swing to a maximum of VSAT(HIGH) and to a minimum of
VCLP(VCC) / V
CLP(5V)
VSAT(LOW)
.
1–
RatERRCLP
,
=
100%
×
(18)
VCC / 5 V
Broken Wire Voltage (VBRK
)
where VCLP is either VCLP(HIGH) or VCLP(LOW)
.
If the GND pin is disconnected (broken wire event), output volt-
age will go to VBRK(HIGH) (if a load resistor is connected to VCC)
or to VBRK(LOW) (if a load resistor is connected to GND).
Allegro MicroSystems, LLC
115 Northeast Cutoff
15
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
FUNCTIONAL DESCRIPTION
Programming Sensitivity and Quiescent Volt-
age Output
Memory-Locking Mechanisms
The A1367 is equipped with two distinct memory-locking mecha-
nisms:
Sensitivity and VOUT(Q) can be adjusted by programming
SENS_FINE and QVO bits, as illustrated in Figure 7 and Figure 8.
•
Default Lock At power-up, all registers of the A1367 are
locked by default. EEPROM and volatile memory cannot
be read or written. To disable Default Lock, a specific 30 bit
customer access code has to be written to address 0x24 within
Access Code Timeout (tACC = 8 ms) from power-up. After
doing so, registers can be accessed. If VCC is power-cycled,
the Default Lock will automatically be re-enabled. This
ensures that during normal operation, memory content will not
be altered due to unwanted glitches on VCC or the output pin.
Customers should not program sensitivity or VOUT(Q) beyond
the maximum or minimum programming ranges specified in the
Operating Characteristics table. Exceeding the specified limits
will cause the sensitivity and VOUT(Q) drift over the temperature
range (ΔSensTC and ΔVOUT(Q)TC) to deteriorate beyond the speci-
fied values.
Programming sensitivity might cause a small drift in VOUT(Q). As
a result, Allegro recommends programming sensitivity first, then
•
Lock Bit After EEPROM has been programmed by the user,
the EELOCK bit can be set high and VCC power-cycled to
permanently disable the ability to read or write any register.
This will prevent the ability to disable Default Lock using the
method described above. Please note that after the EELOCK
bit is set high and the VCC pin is power-cycled, you will not
have the ability to clear the EELOCK bit or read/write any
register.
VOUT(Q)
.
Coarse Sensitivity
Each A1367 variant is programmed to a different coarse sensitiv-
ity setting. Devices are tested, and temperature compensation is
factory programmed under that specific coarse sensitivity setting.
If the coarse sensitivity setting is changed by programming
SENS_COARSE bits, Allegro cannot guarantee the specified
sensitivity drift through temperature range limits (ΔSensTC).
Quiescent Voltage Output,
VOUT(Q) (mV)
Sensitivity, Sens (mV/G)
Max Specified
VOUT(Q)PR
Max Specified
SensPR
Specified VOUT(Q)
Specified Sensitivity
Programming Range
Programming Range
Mid Range
Mid Range
Min Specified
VOUT(Q)PR
Min Specified
SensPR
255 256
255 256
0
511
0
511
SENS_FINE Code
QVO Code
Figure 7: Device Sensitivity versus SENS_FINE
Programmed Value
Figure 8: Device VOUT(Q) versus QVO Programmed Value
Allegro MicroSystems, LLC
115 Northeast Cutoff
16
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
FUNCTIONAL DESCRIPTION (continued)
Power-On Reset (POR) Operation
The descriptions in this section assume temperature = 25°C, no
output load (RL, CL), and no significant magnetic field is present.
•
Power-Up. At power-up, as VCC ramps up, the output is in a
high-impedance state. When VCC crosses VPORH, the output
will go to VCC/2 after tPORD, where tPORD = POR Release
counter tPORR + POR Analog delay tPORA
.
•
VCC drops below VCC(min) = 4.5 V. If VCC drops below VPORL
the output will be in a high-impedance state. If VCC recovers
and exceeds VPORH, the output will go back to normal
,
operation after tPORD
.
VCC
5 V
VPORH
VPORL
VOUT
tPORD
tPORA
tPORR
tPORD
2.5
Time
Figure 9: POR Operation
Allegro MicroSystems, LLC
115 Northeast Cutoff
17
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
FUNCTIONAL DESCRIPTION (continued)
Detecting Broken Ground Wire
V+
VCC
VOUT
If the GND pin is disconnected, node A becoming open (see
Figure 11), the VOUT pin will go to a high-impedance state.
The output voltage will go to VBRK(HIGH) if a load resistor
RL(PULLUP) is connected to VCC or to VBRK(LOW) if a load resistor
RL(PULLDWN) is connected to GND. The device will not respond
to any applied magnetic field.
A1367
C
GND
C
BYPASS
L
(Recommended)
If the ground wire is reconnected, the A1367 will resume normal
operation.
Figure 10: Typical Application Drawing
V
V
V
CC
CC
CC
R
L(PULLUP)
VOUT
VCC
VCC
VOUT
A1367
A1367
R
L(PULLDWN)
GND
GND
A
A
Connecting VOUT to R
Connecting VOUT to R
L(PULLDWN)
L(PULLUP)
Figure 11: Connections for Detecting Broken Ground Wire
Allegro MicroSystems, LLC
115 Northeast Cutoff
18
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
FUNCTIONAL DESCRIPTION (continued)
to recover its original spectrum at base band, while the DC offset
Chopper Stabilization Technique
becomes a high-frequency signal. The magnetic-sourced signal
can then pass through a low-pass filter, while the modulated
DC offset is suppressed. This high-frequency operation allows
a greater sampling rate that results in higher accuracy and faster
signal-processing capability. This approach desensitizes the chip
to the effects of thermal and mechanical stresses, and produces
devices that have extremely stable quiescent Hall output volt-
ages and precise recoverability after temperature cycling. This
technique is made possible through the use of a BiCMOS pro-
cess, which allows the use of low-offset, low-noise amplifiers in
combination with high-density logic integration and a proprietary,
dynamic notch filter. The new Allegro filtering techniques are far
more effective at suppressing chopper-induced signal noise com-
pared to the previous generation of Allegro chopper-stabilized
devices.
When using Hall-effect technology, a limiting factor for total
accuracy is the small signal voltage developed across the Hall
element. This voltage is disproportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal while maintaining an accu-
rate, reliable output over the specified operating temperature and
voltage ranges. Chopper stabilization is a unique approach used
to minimize Hall offset on the chip.
The patented Allegro technique removes key sources of the out-
put drift induced by thermal and mechanical stresses. This offset
reduction technique is based on a signal modulation-demodula-
tion process. The undesired offset signal is separated from the
magnetic field-induced signal in the frequency domain through
modulation. The subsequent demodulation acts as a modulation
process for the offset, causing the magnetic field-induced signal
Regulator
Clock/Logic
Hall Element
Amp
Anti-Aliasing Tuned
LP Filter
Filter
Figure 12: Concept of Chopper Stabilization
Allegro MicroSystems, LLC
115 Northeast Cutoff
19
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
PROGRAMMING GUIDELINES
Serial Communication
ming Levels table on page 22. Note that the external controller
The serial interface allows an external controller to read and write must avoid sending a Command frame that overlaps a Read
registers, including EEPROM, in the A1367 using a point-to-
point command/acknowledge protocol. The A1367 does not initi-
ate communication; it only responds to commands from the exter-
nal controller. Each transaction consists of a command from the
controller. If the command is a write, there is no acknowledging
from the A1367. If the command is a read, the A1367 responds
by transmitting the requested data.
Acknowledge frame.
The serial interface uses a Manchester-encoding-based protocol
per G.E. Thomas (0 = rising edge, 1 = falling edge), with address
and data transmitted MSB first. Four commands are recognized
by the A1367: Write Access Code, Write to Volatile Memory,
Write to Non-Volatile Memory (EEPROM) and Read. One frame
type, Read Acknowledge, is sent by the A1367 in response to a
Read command.
Serial interface timing parameters can be found in the Program-
Read/Write
Memory Address
Data
CRC
0/1
Synchronize
0
0 0/1
V
MAN(H)
V
MAN(L)
0 V
0
0
1
0
Bit boundaries
Figure 13: General Format for Serial Interface Commands
Allegro MicroSystems, LLC
115 Northeast Cutoff
20
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
PROGRAMMING GUIDELINES (continued)
The A1367 device uses a three-wire programming interface,
where VCC is used to control the program enable signal, data
is transmitted on VOUT, and all signals are referenced to GND.
This three-wire interface makes it possible to communicate with
multiple devices with shared VCC and GND lines.
back to normal operating level. Also, the output is enabled and
responds to magnetic input.
When performing a Write to EEPROM transaction, the A1367
requires a delay of tw to store the data into the EEPROM. The
device will respond with a high-to-low transition on VOUT to
indicate the Write to EEPROM sequence is complete.
The four transactions (Write Access, Write to EEPROM, Write
to Volatile Memory, and Read) are show in the figures on the
following pages. To initialize any communication, VCC should
be increased to a level above VprgH(min) without exceeding
VprgH(max). At this time, VOUT is disabled and acts as an input.
When sending multiple command frames, it is necessary to
toggle the program enable signal on VCC. After the first com-
mand frame is completed, and VCC remains at VprgH , the device
will ignore any subsequent pulses on the output. When the pro-
gram enable signal is brought below VprgL(max) , the output will
respond to the magnetic input. To send the next command, the
After program enable is asserted, the external controller must
drive the output low in a time less than td. This prevents the
device interpreting any false transients on VOUT as data pulses.
After the command is completed, VCC is reduced below VprgL
,
program enable signal is increased to VprgH
.
Read/Write
Memory Address
Data
CRC
Synchronize
0
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1
MSB
MSB
Quantity of Bits
Name
Values
Description
Used to identify the beginning of a serial interface command
[As required] Write operation
2
Synchronization
Read / Write
Address
00
0
1
6
1
[As required] Read operation
0/1
[Read/Write] Register address (volatile memory or EEPROM)
24 data bits and 6 ECC bits. For a read command frame the data consists of 30 bits: [29:26]
Don’t Care, [25:24] ECC Pass/Fail, and [23:0] Data. Where bit 0 is the LSB. For a write
command frame the data consists of 30 bits: [29:24] Don’t Care and [23:0] Data. Where bit 0 is
the LSB.
30
3
Data
CRC
0/1
0/1
Bits to check the validity of frame.
Figure 14: Command Frame General Format
VprgH
VCC
VprgL
VOUT
Command
Frame 1
Command
Frame 2
Command
Frame 3
Figure 15: Format for Sending Multiple Transactions
Allegro MicroSystems, LLC
115 Northeast Cutoff
21
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
PROGRAMMING GUIDELINES (continued)
Programming Parameters, CBYPASS = 0.1 µF, VCC = 5 V
Characteristics
Program Enable Voltage (High)
Program Enable Voltage (Low)
Symbol
Note
Min.
8
Typ.
8.25
–
Max.
8.5
6
Unit
V
VprgH
Program enable signal high level on VCC
Program enable signal low level on VCC
VprgL
VCC
V
External capacitance (CLX) on VOUT may
increase the Output Enable Delay
Output Enable Delay
te
–
125
–
µs
Program Time Delay
Program Write Delay
Manchester High Voltage
Manchester Low Voltage
Bit Rate
td
tw
–
–
15
20
5
–
–
µs
ms
V
VMAN(H)
VMAN(L)
tBITR
tBIT
Data pulses on VOUT
Data pulses on VOUT
Communication rate
4
VCC
1
0
–
V
0.3
–
80
(10)
100
–
kbps
µs
Bit Time
Data bit pulse width at 100 kbps
VprgH
VprgH
VprgL
VprgL
VCC
5 V
VCC
5 V
Normal
Output
Normal
Output
High Z
Normal
Output
Normal
Output
High Z
VOUT (Output)
VOUT (Output)
0 V
5 V
0 V
0 V
5 V
0 V
VOUT (Input)
External Control
VOUT (Input)
External Control
Write
Command
High Z
High Z
Data
High Z
Access Code
High Z
td
te
td
te
Figure 17: Write Volatile Memory
Figure 16: Write Access Code
VprgH
VprgH
VprgL
VprgL
VCC
5 V
VCC
VCC
5 V
VCC
Normal
Output
Normal
Output
Normal
Output
Normal
Output
High Z
Data
High Z
VOUT (Output)
VOUT (Output)
0 V
5 V
0 V
0 V
5 V
0 V
VOUT (Input)
External Control
VOUT (Input)
External Control
Write
Command
Read
Command
Data
High Z
tw
High Z
High Z
High Z
td
te
td
td
te
td
Figure 18: Write Non-Volatile Memory
Figure 19: Read
Allegro MicroSystems, LLC
115 Northeast Cutoff
22
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
PROGRAMMING GUIDELINES (continued)
Figure 22 shows the sequence for a Write command. Bits [29:24]
Read (Controller to A1367)
are Don’t Care because the A1367 automatically generates 6 ECC
bits based on the content of bits [23:0]. These ECC bits will be
stored in EEPROM at locations [29:24].
The fields for the Read command are:
• Sync (2 zero bits)
• Read/Write (1 bit, must be 1 for read)
• CRC (3 bits)
Read/Write
Synchronize
Data
(30 bits)
Memory Address
CRC
Figure 20 shows the sequence for a Read command.
0
0
0
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1
MSB MSB
Read/Write
Memory Address
CRC
Synchronize
Figure 22: Write Sequence
0
0
1
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
MSB
Write Access Code (Controller to A1367)
The fields for the Access Code command are:
Figure 20: Read Sequence
• Sync (2 zero bits)
Read Acknowledge (A1367 to Controller)
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits, address 0x24 for Customer Access)
• Data (30 bits, 0x2C413737 for Customer Access)
• CRC (3 bits)
The fields for the data return frame are:
• Sync (2 zero bits)
• Data (30 bits):
Figure 23 shows the sequence for an Access Code command.
□ [29:26] Don’t Care
□ [25:24] ECC Pass/Fail
□ [23:0] Data
Read/Write
Synchronize
Data
(30 bits)
Memory Address
CRC
Figure 21 shows the sequence for a Read Acknowledge. Refer to
the Detecting ECC Error section for instructions on how to detect
Read/Write Synchronize Memory Address Data (30 bits) and
ECC failure.
0
0
0
1
0
0
1
0
0
0/1 0/1 0/1 . . . 0/1 0/1 0/1 0/1
MSB
MSB
Figure 23: Write Access Code
The controller must open the serial communication with the
A1367 device by sending an Access Code. It must be sent within
Access Code Timeout, tACC, from power-up, or the device will be
disabled for read and write access.
Data
(30 bits)
CRC
Synchronize
0/1 0/1 0/1 0/1 . . .
0
0
0/1 0/1 0/1 0/1 0/1
MSB
Access Codes Information
Figure 21: Read Acknowledgement Sequence
Name
Serial Interface Format
Register Address
Data (Hex)
Write (Controller to A1367)
(Hex)
The fields for the Write command are:
Customer
0x24
0x2C413737
• Sync (2 zero bits)
• Read/Write (1 bit, must be 0 for write)
• Address (6 bits, ADDR[5] is for EEPROM, 1 for register; refer
to the address map)
• Data (30 bits):
□ [29:24] Don’t Care
□ [23:0] Data
• CRC (3 bits)
Allegro MicroSystems, LLC
115 Northeast Cutoff
23
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
PROGRAMMING GUIDELINES (CONTINUED)
Memory Address Map
Address
Register Name
Parameter Name
CUST_ID
Description
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Bits
24
9
Location
23:0
8:0
0x02
ID_C
SENS_FINE
SENS_COARSE1
POL
Sensitivity, fine adjustment
Coarse sensitivity
2
10:9
11
Reverses output polarity
1
0x03
SENSE_C
RESERVED
RESERVED
RESERVED
QVO_FINE
UNI
Reserved scratch pad for SENS_FINE
Reserved scratch pad for SENS_COARSE
Reserved scratch pad for SENS polarity
Quiescent Output Voltage (QVO), fine adjustment
Unidirectional bit
9
20:12
22:21
23
2
1
9
8:0
1
9
CLAMP_EN
RATIOM_DIS
RESERVED
RESERVED
DEV_LOCK
Unused
Enables output clamps high and low
Ratiometry disable
1
10
0x04
0x06
QVO_C
1
11
Reserved scratch pad for QVO_FINE
9
20:12
23:21
0
3
Bit to set the EELOCK (for new lock sequence)
1
COMCFG_C
11
23:1
1 SENS_COARSE[0..1] = 11 is factory reserved. Only 00, 01, and 10 are valid entries.
Enabling/Disabling Ratiometry
EEPROM Cell Organization
By default, this device has an output that is ratiometric, meaning
that Quiescent Voltage Output (VOUT(Q)) magnetic sensitivity,
Programming coefficients are stored in non-volatile EEPROM,
which is separate from the digital subsystem, and accessed by the
Sens, and Output Voltage Clamp (VCLP(HIGH) and VCLP(LOW) ) are digital subsystem EEPROM Controller module. The EEPROM
proportional to the Supply Voltage (VCC). There is an EEPROM
bit (RATIOM_DIS) that can be used to disable the ratiometry
of the output, making the above mentioned components of the
output no longer proportional to VCC. This bit can be found in the
QVO_C register (0x04). Writing a 1 to this bit disables ratiom-
etry; writing a 0 to this bit enables ratiometry.
is organized as 30 bit wide words, each word is made up of 24
data bits and 6 ECC (Error Checking and Correction) check bits,
stored as shown in table below.
EEPROM Bit
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Contents
C5
C4
C3
C2
C1
C0 D23 D22 D21 D20 D19 D18 D17 D16 D15
14
D14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
External EEPROM Word Bit Sequence; C# – Check Bit, D# – Data Bit
Allegro MicroSystems, LLC
115 Northeast Cutoff
24
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
PROGRAMMING GUIDELINES (CONTINUED)
Detecting ECC Error
Diagnostic Clamps
Diagnostic clamps can be enabled in EEPROM for this device.
By writing a 1 to CLAMP_EN (bit 10 in QVO_C register
(0x04)), the output voltage hits a maximum and minimum volt-
age that correspond to the specification Output Voltage Clamp in
the above tables. Writing a 0 to this bit disables the clamps and
allows the output to swing to the Output Saturation Voltage.
If an uncorrectable error has occurred, bits 25:24 are set to 10,
the VOUT pin will go to a high-impedance state, and the device
will not respond to the applied magnetic field. To detect this
high-impedance state, the circuit connection with RL(PULLDWN)
shown in Figure 11 must be used and the output voltage will go
to VBRK(LOW). The connection with RL(PULLUP) should not be
used to detect this error.
EEPROM Error Checking and Correction (ECC)
Hamming code methodology is implemented for EEPROM
checking and correction. The device has ECC enabled after
power-up.
The device always returns 30 bits.
The message received from controller is analyzed by the device
EEPROM driver and ECC bits are added. The first 6 received bits
from device to controller are dedicated to ECC.
EEPROM ECC Errors
Bits
Name
Description
29:26
–
No meaning
00 = No Error
01 = Error detected and message corrected
10 = Uncorrectable error
11 = No meaning
25:24
23:0
ECC
D[23:0]
EEPROM data
Allegro MicroSystems, LLC
115 Northeast Cutoff
25
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
PACKAGE OUTLINE DRAWING
For Reference Only - Not for Tooling Use
(Reference DWG-9202)
Dimensions in millimeters - NOT TO SCALE
Dimensions exclusive of mold flash, gate burs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
B
10°
+0.08
–0.05
+0.08
–0.05
1.00
5.21
E
2.60
F
1.41
F
F
Mold Ejector
Pin Indent
+0.08
3.43
–0.05
Branded
Face
1
2
3
4
0.89 MAX
0.54 REF
A
NNNN
YYWW
+0.08
–0.05
+0.08
0.41
0.20
–0.05
12.14 0.05
D
Standard Branding Reference View
1.27 NOM
N
Y
= Device part number
= Last two digits of year of manufacture
W = Week of manufacture
A
Dambar removal protrusion (16X)
Gate and tie burr area
0.54 REF
B
C
Branding scale and appearance at supplier discretion
0.89 MAX
D
E
F
Molded Lead Bar for preventing damage to leads during shipment
Active Area Depth, 0.37 mm REF
+0.08
1.50
–0.05
D
Hall element, not to scale
+0.08
–0.05
+0.08
–0.05
1.00
5.21
Figure 24: Package KT, 4-Pin SIP
Allegro MicroSystems, LLC
115 Northeast Cutoff
26
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Low-Noise, High-Precision, Programmable Linear Hall-Effect Sensor IC
with Regulated Supply, Advanced Temperature Compensation,
and High-Bandwidth (240 kHz) Analog Output
A1367
Revision History
Revision
Date
Description
–
March 9, 2016
Initial release
Updated Description (page 1), Features and Benefits (page 2), Noise (page 5), Quiescent Voltage
Output Programming Range (page 6), Sensitivity Drift Due to Package Hysteresis (page 7), and
Character Performance Data plots (page 8-9).
1
May 31, 2016
Copyright ©2016, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
27
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
相关型号：
©2020 ICPDF网 联系我们和版权申明