A3932 [ALLEGRO]
THREE PHASE POWER MOSFET CONTROLLER; 三相功率MOSFET控制器
| 型号： | A3932 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | THREE PHASE POWER MOSFET CONTROLLER |
| 文件： | 总8页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Page 1 of 8
3932
ADVANCED DATASHEET - 03/02/99
(Subject to change without notice)
THREE PHASE POWER
MOSFET CONTROLLER
The A3932SEQ is a three-phase brushless DC motor controller. The
A3932’s high current gate drive capability allows driving of a wide range of
power MOSFETs and can support motor supply voltages from 12 to 50V.
The A3932 integrates a bootstrapped high side driver to minimize the
external component count required to drive N-channel MOSFET drivers.
29 SENSE
28 RC
GHC
CC
5
6
7
8
9
27 PWM
26 TACH
25 SR
GLB
SB
A3932SEQ
GHB
Internal fixed off time PWM current control circuitry can be used to
regulate the maximum load current to a desired value. The peak load current
limit is set by the user’s selection of an input reference voltage and external
sensing resistor. The fixed off time pulse duration is set by a user-selected
external RC timing network. For added flexibility, the PWM input can be
used to provide speed/torque control, allowing the internal current control
circuit to set a maximum current limit.
24 BRAKE
23 DIR
CB 10
GLA 11
SA 12
22 H2
21 H3
GHA 13
The A3932 includes optional synchronous rectification. This feature
will short out the current path through the power MOSFETs intrinsic body
diodes during PWM off cycle current decay. This can minimize power
dissipation in the MOSFETs, eliminate the need for external power clamp
diodes, and potentially allow a more economical choice for the MOSFET
drivers.
ABSOLUTE MAXIMUM RATINGS
at T = +25°C
A
Load Supply Voltage, VBB ............................50 V
VREG (Transient) .........................................15 V
Logic Input Voltage Range,
The A3932 provides commutation logic for Hall sensors configured
for 120-degree spacing. The Hall input pins are pulled up to an internally
generated 5V reference. Power MOSFET protection features includes gate-
source voltage monitor, bootstrap capacitor charging current monitor,
undervoltage monitor, motor lead short to supply or ground, and thermal
shutdown.
VIN...................-0.3 V to VLCAP + 0.3 V
Sense Voltage, VSENSE ........................ -5 to 1.5 V
Pins SA/SB/SC, ................................... -5 to 50 V
Pins GHA/GHB/GHC ................-5 to VBB + 17 V
Pins CA/CB/CC .........................SA/SB/SC+17 V
FEATURES
n Drives Wide Range of N-channel
Package Power Dissipation (T = +25°C)
n PWM Torque Control Input
n Motor Lead Short to Supply
and Ground Protection
n Internal 5V Regulator
n Direction Control
A
RØJA ..................................... 52.4 °C/W
RØJC ..................................... 22.7 °C/W
PD ................................................2.4 W
Operating Temperature Range,
TA ................................-20°C to +85°C
Junction Temperature, TJ .........................+150°C
Storage Temperature Range,
MOSFETs
n Sources 1.25A for Gate Turn-On
n Sinks 2.5A for Gate Turn-Off
n Synchronous Rectification
n Power MOSFET Protection
n Adjustable Dead Time for Cross
Conduction Protection
n Brake Input
n Fault Diagnostic Output
n Tachometer Output
n Thermal Shutdown
n Undervoltage Protection
n 32L PLCC Package
TS...............................-55°C to +150°C
n Fast/Slow Current Decay Modes
n Internal PWM current Control
Always order by complete part number: A3932SEQ
Page 2
3932
THREE-PHASE POWER MOSFET CONTROLLER
Functional Block Diagram (1 of 3 outputs shown)
VREG
VBB
LCAP
Regulator
H1
H2
Undervoltage
Detect
Bootcap
Monitor
CA
CBOOT
H3
To Phase C
High
Side
Driver
High Side Protection
Logic
PWM
DIR
Turn-on
Delay
GHA
Control
Logic
RESET
SR
Gate-Source
Monitor
SA
VREG
BRAKE
Low
Side
Driver
Turn-on
Delay
Low Side Protection
MODE
TACH
GLA
Logic
To Phase B
RC Blanking
Fixed - Off
Time
RC
PGND
SENSE
FAULT
AGND
CT
RT
-
RS
+
to LCAP
REF
Bootstrap low
Vgs Low
Motor Lead Short
Invalid Hall
Undervoltage
Dead-Time
Adjust
DEAD
Page 3
3932
THREE-PHASE POWER MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS at T = +25°C, VBB = 50 V, CBOOT= .1µf, CLOAD=1000pf (unless noted otherwise)
A
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
IVBB
RESET Low
6.5
8.5
mA
Quiescent current
IVBB
RESET High
6.5
5.250
50
mA
V
LCAP Regulator
VLCAP
4.75
18
5
–
Motor Supply Voltage Range
V
VREG shorted to VBB
VBB 18 to 50V
10.8
12.4
–
–
13.2
13.6
–
V
VREG Output Voltage
VREG Line Regulation
Control Logic
VREG
13
40
V
VREGLIN
mV
Logic Input Voltage
Logic Input Current
Gate Drive
VIN(1)
VIN(0)
IIN(1)
2.0
–
–
–
–
.8
V
V
VIN = 2.0 V
VIN = 0.8 V
–
<1.0
–
10
µA
µA
IIN(0)
-70
-130
Low side drive, output high
High side drive, output high
Pull Up Switch Resistance
Pull Down Switch Resistance
Low side switching, rise time
Low side switching, fall time
High side switching, rise time
High side switching, fall time
Dead time maximum
VHGL
VHGH
RDS(ON)
RDS(ON)
trGL
12.3
13
11.6
9
13.7
12.8
12
4
V
10.5
6
V
-1A transient
2.5A transient
10% to 90%
W
W
ns
ns
ns
ns
ns
ns
2
3
–
25
–
tfGL
–
10
–
trGH
–
40
–
tfGH
–
10
–
tDEAD
tDEAD
IDEAD = 9mA
–
5500
100
–
Dead time minimum
IDEAD = 780mA
–
–
NOTES:
1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device pin.
Page 4
3932
THREE-PHASE POWER MOSFET CONTROLLER
ELECTRICAL CHARACTERISTICS at T = +25°C, VBB = 50 V, CBOOT= .1µf, CLOAD=1000pf (unless noted otherwise)
A
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Bootstrap Capacitor
Bootstrap Capacitor Voltage
Bootstrap Charge Threshold
Bootstrap Capacitor ROUT
Charge Current
VCAP
IBOOTCHG
RCAP
10.4
9
11.6
13
5
12.8
18
8
V
mA
W
ICX
100
mA
µA
CAP Leakage Current
ICAP
High Side switched ON
15
0
25
Current Limit Circuitry
Offset Voltage
VIO
IB
-5
-5
5
mV
µA
V
Input Bias Current
0
Comparator Common Mode Range
RC Charge Current
VCMR
IRC
0
1.5
1.1
1.2
3.3
.9
1
µA
V
RC Voltage Threshold
VRCL
VRCH
1.0
2.7
1.1
3.0
V
Protection Circuitry
Gate Source Monitor
UVLOGS
UVLODS
VCAP-VGHX, High Side Switched ON
VBB- VSX, High Side ON
2.7
1.6
3.3
2.0
3.9
2.4
V
V
Short to Ground, Drain-Source
Monitor
Undervoltage Threshold
UVLO
UVLO
VFAULT
VTACH
TJ
VREG low to High
VREG High to Low
IOL = 1mA
9.4
8.8
9.9
9.3
10.4
9.8
.5
V
V
Fault Output
V
Tach Output
IOL= 500 µA
.5
V
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
–
–
165
10
–
°C
°C
DTJ
–
NOTES: 1. Typical Data is for design information only.
2. Negative current is defined as coming out of (sourcing) the specified device pin.
Page 5
3932
THREE-PHASE POWER MOSFET CONTROLLER
Pin Descriptions
RESET. A logic input that enables the device, internally
pulled up to LCAP. Logic HIGH will disable the device and
turn off MOSFETs, coasting the motor. Logic LOW will
enable gate drive to follow commutation logic. This input
will override BRAKE.
FAULT. Open drain output to indicate fault condition. Will
go active high for any of the following fault conditions:
1) Invalid HALL input code.
2) High side gate-source undervoltage.
3) Bootstrap capacitor not sufficiently charged.
4) Undervoltage condition detected at VREG.
5) Thermal Shutdown.
GLC/GLB/GLA. Low side gate drive outputs for external
MOSFET drivers. External series gate resistors can be used
to control slew rate seen at the power driver gate, thereby
controlling the di/dt and dv/dt of S outputs. The outputs will
source 1.25A for turn-on and sink 2.5A for gate discharge.
6) Motor lead (SA/SB/SC) connected to ground.
Any fault will force a COAST condition, which turns all
power MOSFETs off. The fault state for gate-source and
bootstrap monitors is cleared at each commutation. If the
motor has stalled, the fault must be cleared by toggling the
RESET pin or repeating a power up sequence.
SC/SB/SA. Directly connected to the motor terminals,
these pins sense the voltages switched across the load. The
pin is also connected to the negative side of the bootstrap
capacitor and negative supply connection for the floating
high side drive.
BRAKE. Logic input for braking function. Logic LOW will
turn on sink side MOSFETs, turn off the source side
MOSFETs. This will effectively short the BEMF in the
windings and brake the motor. Internally pulled up to logic
LCAP.
GHC/GHB/GHA. High side gate drive outputs for n-
channel MOSFET drivers. External series gate resistors can
be used to control slew rate seen at the power driver gate,
thereby controlling the di/dt and dv/dt of S outputs. The
outputs will source 1.25A for turn-on and sink 2.5A for gate
discharge.
SR. Synchronous rectification input. Logic LOW disables
the feature forcing current decay through flyback diodes.
Logic HIGH will result in the opposite pair of drivers to
switch in response to a PWM “off” command. Internally
pulled up to LCAP.
CC/CB/CA. High side connection for bootstrap capacitor,
positive supply for high side gate drive. The bootstrap
capacitor is charged to approximately VREG when the
output Sx terminal is low. When the output swings high, the
voltage on this pin rises with the output to provide the
boosted gate voltage needed for N-channel power
MOSFETs.
TACH. Digital output to indicate speed of rotation. A 3µs
pulse appears at every Hall transition.
PWM. Speed control input. Logic HIGH will turn on
MOSFETs selected by Hall input logic. Logic LOW turns
off the selected MOSFETs. The PWM input held high to
utilize internal current control circuitry. Internally pulled up
to logic LCAP.
MODE. Logic input to set current decay method. Slow
decay mode (logic HIGH) switches off the high side FET in
response to PWM Off command. Fast decay mode (logic
LOW) switches off the source and sink MOSFET’s. Mode
pin is internally pulled up to LCAP.
RC. Analog input. Connection for RT and CT to set the fixed
off time. The CT will also set the BLANK time. (see
applications information). It is recommended that the fixed
off time should not be less than 10ms. The resistor should be
in the range 10k to 500k.
H1/H2/H3. Hall sensor inputs, internally pulled up to
LCAP. Configured for 120-degree electrical spacing.
SENSE. Analog input to the current limit comparator.
Voltage representing load current appears on this pin.
Voltage transients seen at this pin when the drivers turn on
DIR. Logic input to reverse rotation, see commutation logic
table. Internally pulled up to LCAP.
are ignored for time Tblank
.
Page 6
3932
THREE-PHASE POWER MOSFET CONTROLLER
PIN DESCRIPTIONS (continued)
VREG. Regulated 13 V output supply for low side gate
drive and bootstrap capacitor charge circuit. It is good
practice to connect a decoupling capacitor from this pin to
AGND, as close to the device pins as possible. Pin should be
shorted to VBB for 12V applications.
DEAD. Analog input. A resistor between DEAD and LCAP
is selected to adjust turn-off to turn-on time. This delay is
needed to prevent shoot-thru in the external power FET’s.
The resistor allowable range is 5.6k to 470k, which converts
to deadtime of 100ns to 5500ns.
TDEAD @ 11e-12 * RDEAD
VBB. Motor power supply connection for A3932 and power
MOSFETs. Pin should be shorted to VREG for 12V
applications.
AGND. Analog reference.
REF. Analog input to current limit comparator. Voltage
applied here sets the peak load current according to the
equation:
PGND. Return for low side gate drive. This should be
connected to PCB power ground.
ITRIP = VREF/RSENSE
LCAP. 5V reference to power internal logic, connection for
decoupling cap. This pin requires 1nF external capacitor for
decoupling and should not be used to power any external
circuitry.
Commutation Truth Table
H1
1
1
1
0
0
0
1
1
1
0
0
0
H2
0
0
1
1
1
0
0
0
1
1
1
0
H3
1
0
0
0
1
1
1
0
0
0
1
1
DIR
1
1
1
1
1
1
0
0
0
0
0
0
GLA
0
0
1
1
0
0
1
0
0
0
0
1
GLB
0
0
0
0
1
1
0
1
1
0
0
0
GLC
1
1
0
0
0
0
0
0
0
1
1
0
GHA
1
0
0
0
0
1
0
0
1
1
0
0
GHB
0
1
1
0
0
0
0
0
0
0
1
1
GHC
0
0
0
1
1
0
1
1
0
0
0
0
SA
HI
Z
LO
LO
Z
HI
LO
Z
HI
HI
Z
SB
Z
HI
HI
Z
LO
LO
Z
LO
LO
Z
SC
LO
LO
Z
HI
HI
Z
HI
HI
Z
LO
LO
Z
HI
HI
LO
INPUT LOGIC
MODE
PWM
S/R
0
0
0
0
1
1
1
1
RESET
Quadrant
Fast decay
Fast Decay
Slow decay
Mode of Operation
PWM chop– current decay, all drivers off
Peak Current limit – selected drivers ON
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
1
PWM chop – current decay, selected Low side ON
Slow Decay Peak Current limit mode – selected drivers ON
Fast decay
Fast Decay
Slow decay
PWM chop – current decay with opposite of selected drivers ON
Peak Current limit – selected drivers ON
PWM chop – current decay with both Low side drivers ON
Slow Decay Peak Current limit – selected drivers ON
All gate drive outputs to 0V – Clear fault logic
X
X
Page 7
3932
THREE-PHASE POWER MOSFET CONTROLLER
APPLICATION INFORMATION
3) Undervoltage. VREG supplies the low side gate
Synchronous Rectification. To reduce power
consumption in the external MOSFETs, the 3932 control
logic will turn on the appropriate driver during the load
current recirculation, PWM “off” cycle. The intrinsic body
diode of the power MOSFET will only conduct during the
dead time required at each PWM transition.
driver and the bootstrap charge current. It is critical to
ensure that the voltages are at a proper level before
enabling any of the outputs. The undervoltage circuit is
active during power up and will force a motor coast
condition until VREG is greater than approximately
10V.
Decoupling. The internal reference VREG supplies
current for the gate drive circuit. As the gates are driven high
they will require current from an external decoupling
capacitor to support the transients. This capacitor should be
placed as close as possible to the VREG pin. The value of
the capacitor should be at least 20 times larger than the
bootstrap capacitor. Additionally, a 1nF ceramic monolithic
capacitor should be connected between LCAP and AGND as
close to the device pins as possible.
4) Hall Invalid. Illegal codes for the hall inputs (000/111)
will force a fault and coast the motor.
5) Thermal Shutdown. Junction temperature greater
than 165°C will signal a fault and coast the motor.
6) Motor Lead. The 3932 will signal a fault if the motor
lead is shorted to ground or supply. The status is
checked after any high side has turned on.
Protection Circuitry. The A3932 will protect the
external MOSFETs by turning off all MOSFETs if any of the
following fault conditions are detected.
Faults are cleared at the beginning of each commutation. If a
stalled motor results from a fault, the fault can only be
cleared by toggling the RESET pin or by a power up
sequence.
1) Gate Source Monitor (high side only). The
voltage on GHx pins must stay within 3.3V of the
bootstrap capacitor voltage during an ON cycle. If this
voltage droops below this threshold the high side turns
off, and the low side gate will turn on in an attempt to
recharge the bootstrap capacitor. When the bootstrap
capacitor has been properly charged, the high side is
turned back on. The circuit will allow three faults of this
type within one commutation cycle before signaling a
fault and coast the motor.
2) Bootstrap Monitor. The bootstrap capacitor is
charged whenever a sink side FET is on, Sx output goes
low, and load current recirculates. This happens
constantly during normal operation. A 170µs timer is
started at the beginning of this cycle and the capacitor is
charged with typically 100 mA. If the charge current
remains higher than 13mA or the Sx node remains
higher than 2V for longer than the 170µs a fault will be
signaled and the motor will coast.
Page 8
3932
THREE-PHASE POWER MOSFET CONTROLLER
Braking. The 3932 will dynamically brake by forcing all
sink side MOSFETs on, and all source side MOSFETs off.
This will effectively short out the BEMF and brake the
motor. During braking the load current can be approximated
by:
Current Regulation. Load current is regulated by an
internal fixed off time PWM control circuit. When the
outputs of the MOSFETs are turned on, current increases in
the motor winding until it reaches a value given by:
ITRIP = VREF /RSENSE
IBRAKEPEAK = VBEMF/RLOAD
At the trip point, the sense comparator resets the source
enable latch, turning off the source driver. At this point, load
inductance causes the current to recirculate for the fixed off
time period. The current path during recirculation is
As the current does not flow through the sense resistor
during a dynamic brake, care should be taken to ensure that
the power MOSFETs maximum ratings are not exceeded.
determined by the configuration of the MODE and SR input
pins. The fixed off time is determined by an external resistor
(RT) and capacitor (CT) connected in parallel from the RC
terminal to AGND. The fixed off time is approximated by:
The RESET pin overrides the BRAKE input. RESET will
always drive all gate outputs Low.
tOFF = RT * CT
TOFF should be in the range 10ms to 50ms. Larger values for
TOFF could result in audible noise problems.
Torque control can be implemented by varying the REF
input voltage as long as the PWM input stays high. If direct
control of the torque/current is desired by PWM input, a
voltage can be applied to the REF pin to set an absolute
maximum current limit.
PWM Blank. The capacitor (CT) also serves as the means
to set the BLANK time duration. At the end of a PWM off
cycle, a high side gate selected by the commutation logic will
turn on. At this time, large current transients can occur
during the reverse recovery time (trr) of the intrinsic body
diodes of the power MOSFETs. To prevent false tripping of
the sense comparator, the blank function will disable the
comparator for a time defined by:
TBLANK = (1.9 * CT )/(1mA-2/ RT)
The user must ensure that the CT is large enough to cover the
current spike duration.
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