A3944KLPTR-T_技术文档

A3944

Automotive, Low-Side FET Pre-Driver

Description

Features and Benefits

• 6 channels

• Drives logic-level N-channel MOSFETs

• 40 mA gate drive current

• Short and open detection

• High voltage (50 V) drain feedback inputs

The A3944 is a programmable 6 channel low-side MOSFET

pre-driver suitable for use in automotive applications. Each

channel is controllable by a combination of parallel and serial

inputs and provides sufficient gate drive current to allow

PWM control up to 10 kHz, depending on the MOSFET gate

• Programmable fault timers and thresholds per channel

• UVLO and thermal warning circuitry

charge.

Each channel provides independent fault diagnostics for short

to ground and open load when in the off-state, and short to

battery when in the on-state. A short to battery can disable

the output until reset or for a programmable retry time. Each

channelprovidesindependentlyprogrammablefaultthresholds

and blanking times.

• Serial or parallel gate drive control

• Highly configurable, through SPI compatible interface

• Compact TSSOP package

Applications:

• Automotive ECU

• Automotive high-side actuators

Inadditiontochannelstatecontrol,channelfaultmasking,fault

thresholds and fault timers are programmed through the SPI

compatible serial interface. The serial interface also provides

read back of the fault status for each channel.

Package: 28-pin TSSOP with exposed

thermal pad (suffix LP)

Digital inputs and outputs are compatible with 3.3 V and 5 V

supplies.

The A3944 is supplied in a 28 lead TSSOP package (suffix

LP) with an exposed thermal pad. The package is lead (Pb)

free with 100% matte-tin leadframe plating.

Not to scale

Typical Application Diagram

Parallel

Controller

A3944

SPI

A3944-DS, Rev. 1

A3944

Automotive, Low Side FET Pre-Driver

Selection Guide

Part Number

Packing*

A3944KLPTR-T

4000 pieces per reel

™

*Contact Allegro for additional packing options

Absolute Maximum Ratings with respect to ground at T_A= 25°C

Characteristic

Analog Supply Voltage

Symbol

V_BB

Notes

Rating

–0.3 to 40

–0.3 to 6.5

–0.3 to 20

–0.3 to 6.5

–0.3 to 50

–0.3 to 6.5

10

Unit

V

Logic Supply Voltage

Gate Drive Supply Voltage

Terminal VREG

V_DD

V

V_DR

V

V_REG

V

Terminals GATx

V

Terminals DRNx

V

Terminals INx

V

Terminals SI, SCK, CSN

Terminal SO

V

Terminal RESETN

V

Drain Feedback Clamp Energy^*

Drain Feedback Clamp Current^*

Drain Feedback Clamp Power^*

Junction Temperature

E_DRNC

I_DRNC

Single pulse less than 2 ms

μJ

mA

mW

°C

Single pulse not exceeding E_DRNor P_DRN

Average power over any 2 ms period

100

P_DRNC

T_J(max)

100

150

Overtemperature event not exceeding 10 s,

lifetime duration not exceeding 10 hours

Transient Junction Temperature^*

T_tJ

175

°C

Storage Temperature Range

T_stg

T_A

–55 to 150

–40 to 150

°C

Operating Temperature Range

^*Guaranteed by design characterization.

Range K

Thermal Characteristics may require derating at maximum conditions, see application information

Characteristic

Symbol

Test Conditions*

Value

Unit

4-layer PCB based on JEDEC standard

28

ºC/W

Package Thermal Resistance,

Junction to Ambient

R_θJA

2-layer PCB with 3.8 in.²of copper area each side

32

2

ºC/W

Package Thermal Resistance,

Junction to Pad

R_θJP

*Additional thermal information available on the Allegro website

Allegro MicroSystems, LLC

115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A3944

Automotive, Low Side FET Pre-Driver

Pin-out Diagram

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VDR

GAT0

DRN0

GAT1

DRN1

GAT2

DRN2

GAT3

DRN3

GAT4

DRN4

GAT5

DRN5

VREG

VDD

RESETN

SO

1

2

3

SCK

SI

4

5

CSN

IN0

6

PAD

7

IN1

8

IN2

9

IN3

10

11

12

13

14

IN4

IN5

GND

VBB

Terminal List Table

Name

Number

Function

Serial interface chip select

Name

IN1

Number

Function

Gate drive 1 control input

Gate drive 2 control input

Gate drive 3 control input

CSN

DRN0

DRN1

23

3

21

20

19

Gate drive 0 drain sense input

Gate drive 1 drain sense input

IN2

5

IN3

DRN2

DRN3

DRN4

DRN5

GAT0

GAT1

GAT2

GAT3

GAT4

GAT5

GND

7

9

Gate drive 2 drain sense input

Gate drive 3 drain sense input

Gate drive 4 drain sense input

Gate drive 5 drain sense input

Gate drive 0 output

IN4

IN5

18

17

–

Gate drive 4 control input

Gate drive 5 control input

Exposed thermal pad, connect to ground

Chip reset input

11

13

2

PAD

RESETN

SCK

SI

27

25

24

26

15

28

1

Serial clock

4

Gate drive 1 output

Serial data input

6

Gate drive 2 output

SO

Serial data output

8

Gate drive 3 output

VBB

VDD

VDR

VREG

Analog supply (Battery)

Logic Supply

10

12

16

22

Gate drive 4 output

Gate drive 5 output

Gate drive supply

Power ground

14

Voltage regulator

IN0

Gate drive 0 control input

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A3944

Automotive, Low Side FET Pre-Driver

Functional Block Diagram

IN5 IN4 IN3 IN2 IN1 IN0

VBB

Regulator

VDR

VREG

GND

Config

Register

DRN0

GAT0

VDD

Control

Registers

Gate Drive Channel

VDD

Config

Register

DRN1

GAT1

CSN

SO

Gate Drive Channel

SPI

SI

SCK

Config

DRN2

GAT2

Register

Fault

Register

GND

Gate Drive Channel

Config

Register

Fault Logic

DRN3

GAT3

Gate Drive Channel

POR

RESETN

UVLO

Config

Register

DRN4

GAT4

Gate Drive Channel

Retry Timer

Clock

Config

Register

DRN5

GAT5

Gate Drive Channel

GND

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A3944

Automotive, Low Side FET Pre-Driver

V_BAT

V_OCL

Off

Blanking

+

Fault

Filter

Load

I_DPU

65 μA

-

V_OL

Off-State

Fault

Detect

+

-

Fault

Filter

V_STG

Fault

DRNx

Decode

R_DX

50 V

On-State

Fault

Detect

+

-

Fault

Filter

V_STB

I_DPD

65 μA

On

Blanking

V_OCL

Disable

Retry

on STB

t_RE

V_DR

GATx

RESETN

POR

INx

R_Gx

Gx

V_STBV_STGV_OL

Channel

Configuration

Register

Threshold

Generator

VREG

Figure 1. Gate Drive Channel functional block diagram (shows 1 channel of 6)

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A3944

Automotive, Low Side FET Pre-Driver

ELECTRICAL CHARACTERISTICS Valid at T_J= –40°C to 150°C, V_DD= 3.3 V, V_DR= 5 V, V_BB= 6 to 40 V; unless

otherwise specified

Characteristics

Supply and Reference

Logic Supply Voltage

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_DD

V_BB

V_DR

I_DDQ

3.0

6

–

2

5.5

40

6.0

3

V

Analog Supply Voltage

Gate Drive Supply Voltage

VDD Quiescent Current

3.0

–

V

mA

μA

mA

V

–

4

VBB Quiescent Current

I_BBQ

V_DD= 0, V_BB≤ 30 V

–

10

4

VDR Quiescent current

Regulator Voltage

I_DRQ

V_REG

V_DO

t_RST

–

V_BB> 19.5 V

17.5

0

18.5

0.6

–

Regulator Dropout

V

RESETN Pulse Width

RESETN Glitch Filter

Oscillator Frequency

Digital Inputs and Outputs

Input High Voltage

1

μs

ns

t_RGF

f_OSC

–

200

2.6

1.4

MHz

V_IH

V_IL

70

–

30

–

%V_DD

mV

kΩ

Input Low Voltage

Input Hysteresis

V_Ihys

R_PU

R_PD

V_OH

V_OL

I_L

300

–

500

50

Input Pull-Up Resistor

Input Pull-Down Resistor

SO Output High Voltage*

SO Output Low Voltage

SO Output Leakage*

Gate Output Drive

CSN to VDD

–

INx, SI, SCK to GND

SO, I_OH= –2 mA

SO, I_OL= 2 mA

CSN = VDD

–

kΩ

V_DD- 0.4 V_DD- 0.2

–

V

–

0.2

–

0.4

1

V

–1

μA

T_J= 25°C, I_GHx= –20 mA

T_J= 150°C, I_GHx= –20 mA

T_J= 25°C, I_GLx= 20 mA

T_J= 150°C, I_GLx= 20 mA

GATx off, V_GATx= V_DR

GATx on, V_GATx= 0 V

C_LOAD= 400 pF, 20% to 80% V_DR

C_LOAD= 400 pF, 80% to 20% V_DR

At INx input

25

50

25

50

20

–

50

75

50

75

–

70

125

70

125

–

Ω

Pull-Up On-Resistance*

Pull-Down On-Resistance

R_DS(on)UP

Ω

R_DS(on)DN

Ω

Output Sink Current

Output Source Current*

Output Rise Time

I_GL

I_GH

t_r

mA

ns

μs

ns

μs

–

–40

–

180

–

Output Fall Time

t_f

–

Minimum On-Time

Minimum Off-Time

t_on

t_off

t_P(on)

–

1

At INx input

–

1

Turn-On Propagation Delay

INx to GATx

–

200

0.5

–

INx to GATx

–

Turn-Off Propagation Delay

t_P(off)

RESETN to GATx

–

1

Continued on the next page…

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115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A3944

Automotive, Low Side FET Pre-Driver

ELECTRICAL CHARACTERISTICS (continued) Valid at T_J= –40°C to 150°C, V_DD= 3.3 V, V_DR= 5 V, V_BB= 6 to 40 V; unless

otherwise specified

Characteristics

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Fault Detection (On-State)

I_DRNx= 10 μA

I_DRNx= 10 mA

V_DRNx< 32 V

45

–

V

Drain Clamp Voltage

Drain Clamp Leakage

V_DCL

I_DC

54

–

1

μA

GATx driven high, SB[2:0] = 111

GATx driven high, SB[2:0] = 110

GATx driven high, SB[2:0] = 101

GATx driven high, SB[2:0] = 100

GATx driven high, SB[2:0] = 011

GATx driven high, SB[2:0] = 010

GATx driven high, SB[2:0] = 001

GATx driven high, SB[2:0] = 000

RT0 = 1

30

17

15

13

11

9

31

18

16

14

12

10

8

32

19

17

15

13

11

9

%V_REG

ms

Short to Battery Threshold

V_STB

7

5

6

7

40

7

55

10

2

72

13

2.75

72

36

18

7

Retry Timer

t_RE

RT0 = 0

ms

Fault Filter Time

t_FF(on)

1.25

40

20

10

4

μs

GATx driven high, TON[1:0] = 11

GATx driven high, TON[1:0] = 10

GATx driven high, TON[1:0] = 01

GATx driven high, TON[1:0] = 00

56

28

14

5

μs

Fault Blank Timer

t_BL(on)

μs

Fault Detection (Off-State)

DRNx Pull-Up Diagnostic Current*

DRNx Pull-Down Diagnostic Current

I_DPU

I_DPD

GATx low, V_DRNx< (V_OCL– 200 mV)

GATx low, NPD = 0, V_DRNx>(V_OCL+ 200 mV)

GATx driven low, SG = 1

–80

50

–65

65

–50

80

μA

65

66

67

%V_REG

μs

Short to Ground Threshold

V_STG

GATx driven low, SG = 0

44

45

46

Open Load Threshold

Open Load Clamp Voltage

Fault Filter Time

V_OL

V_OCL

t_FF(off)

GATx driven low

75

76

77

70

71

72

1.25

3000

200

100

60

2

2.75

5000

360

180

100

GATx driven low, TOF[1:0] = 11

GATx driven low, TOF[1:0] = 10

GATx driven low, TOF[1:0] = 01

GATx driven low, TOF[1:0] = 00

4000

280

140

80

μs

Fault Blank Timer

t_BL(off)

μs

Continued on the next page…

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115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

A3944

Automotive, Low Side FET Pre-Driver

ELECTRICAL CHARACTERISTICS (continued) Valid at T_J= –40°C to 150°C, V_DD= 3.3 V, V_DR= 5 V, V_BB= 6 to 40 V; unless

otherwise specified

Characteristics

Serial Interface Timing

Clock High Time

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

t_SCKH

t_SCKL

t_CSS

A in figure 2

B in figure 2

C in figure 2

D in figure 2

E in figure 2

F in figure 2

G in figure 2

50

30

300

–

ns

Clock Low Time

CSN Set-up to SCK Low

CSN Hold after SCK High

CSN High Time

–

t_CSHD

t_CSH

–

Data Out Enable Time

Data Out Disable Time

t_SOE

40

30

t_SOD

–

Data Out Valid Time from

Clock Falling

t_SOV

t_SOH

H in figure 2

I in figure 2

–

5

–

40

–

ns

Data Out Hold Time from

Clock Falling

Data In Set-up Time to Clock Rising

Data In Hold Time from Clock Rising

CSN High to Output Change

t_SIS

t_SIH

t_PCS

J in figure 2

K in figure 2

15

10

–

ns

200

Chip Diagnostics Protection

VDD Undervoltage Lockout

V_DDUV

V_DDUVhys

V_REGUV

Decreasing V_DD

2.6

50

2.75

100

4.8

2.9

150

5.1

V

mV

V

VDD Undervoltage Lockout

Hysteresis

VREG Undervoltage Lockout

Decreasing V_REG

4.5

100

VREG Undervoltage Lockout

Hysteresis

V_REGUVhys

200

300

mV

Overtemperature Warning Threshold

Overtemperature Hysteresis

T_JW

Temperature increasing

Recovery = T_JW– T_JWhys

145

–

160

15

175

–

ºC

T_JWhys

*For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device terminal.

CSN

. . .

C

A

B

D

E

SCK

SI

J

K

. . .

X

D15

X

D14

X

D0

X

F

I

G

SO

Z

D15

D14

D0

Z

H

X = Don’t care, Z = High impedance (tri-state)

Figure 2. Serial Interface Timing Diagram. Letter keys refer to the Serial Interface Timing section of the Electrical

Characteristics table.

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A3944

Automotive, Low Side FET Pre-Driver

Functional Description

The A3944 provides a programmable interface between an ECU

and 6 low-side MOSFET switches in automotive applications.

Each channel provides all the features necessary to drive and

monitor the external FET and load.

than the minimum reset pulse width: forces outputs low, resets

the configuration, sets the LR bit, and resets all other channel

faults.

SI: Active high digital input with pull-down resistor. Data on SI is

clocked into the serial register on the rising edge of SCK.

The gate of the external FET is driven by a 50 Ω (typ) push-pull

driver capable of sourcing and sinking at least 40 mA under all

conditions. This is sufficient to allow most typically used FETs to

be switched with a PWM input at up to 10 kHz. The state of each

channel is determined by a combination of parallel and serial

inputs.

SO: Push-pull digital output. Data from the fault register is output

on SO, changing on the falling edge of SCK.

SCK: Digital clock input with pull-down resistor. See SI and SO

for action.

CSN: Active low digital input with pull-up resistor. When CSN

is low SO becomes active and data is accepted on SI. Data is

latched in the serial register when CSN goes high. When CSN is

high SO is high impedance and SI and SCK are ignored.

When the FET is active its drain is monitored for a short to

battery. When the FET is inactive, internal current sources are

activated and the drain voltage is monitored to check for shorts to

ground or open loads.

INx: Active high digital inputs with pull-down resistors. When

INx is high GATx is allowed to go high, depending the contents

of the serial control register and any active faults. When INx is

low GATx is held off.

The serial, SPI compatible interface provides access to control

and configuration registers. Each channel has a dedicated fault

configuration register that allows independent fault thresholds,

fault timing, and fault configuration for each channel.

GATx: Gate drive outputs. Drive between GND and VDR. Con-

nected through a resistor or directly to the gate of the external

MOSFETs.

The output state of each channel is determined by the logic con-

trol input for the channel and a dedicated bit in the single output

control register. Channels can therefore be controlled by parallel

input, by serial input, or by a combination of the two. All chan-

nels can be switched at the same time with a single serial write.

DRNx: Analog, high-voltage inputs. Drain monitor connection

used to determine the status of the drive to the load.

A single fault mask register can be used to ignore the fault detect

output for any channel combination.

Gate Drive Channels

The serial interface also provides read back of the fault status for

each channel.

Each gate drive channel has independent control logic, gate drive

output, fault detection circuitry, fault threshold generators, fault

timers, and fault configuration register. The fault configuration

register and reference generation provides two short to ground

thresholds and eight short to battery thresholds, plus four turn-on

blank times and four turn-off blank times independently select-

able per channel.

Digital inputs and outputs are compatible with 3.3 V and 5 V

supplies.

Terminal Functions

VDD: Positive supply for digital input, output, and logic.

The gate drive channel block diagram (figure 1) shows the func-

tional circuit for one gate drive channel, which is duplicated in

each gate drive channel. A retry timer, common to all channels,

allows automatic retry for short to battery faults.

VBB: Positive supply for voltage regulator. Can be connected to

battery voltage through reverse polarity protection.

VREG: Regulated voltage for analog and reference functions.

VDR: Positive supply for gate drive outputs.

Control and Enable

GND: Ground return. Connect to common return point for all

external MOSFET source connections.

A gate drive output, GATx, is turned-on when: RESETN is high,

no short to battery fault is present, and either the direct digital

input, INx, or the relevant bit in the serial control register, Gx, is

RESETN: Active low digital input. When held low for longer

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A3944

Automotive, Low Side FET Pre-Driver

high, in other words the logical OR of the INx input and the Gx

bit for each channel x. If the GATx output is to be controlled by

the serial interface, then the corresponding INx logic input should

be held low. Internal pull-down resistors from each INx terminal

to GND ensure that any unconnected input will be pulled low.

Conversely, if the GATx output is to be controlled by the INx

logic input, then the corresponding Gx bit in the control register

should be set to 0, which is its default power-on and reset state.

Channel Fault Diagnostics

All channel faults are determined by monitoring the voltage at the

drain of the external FET through the DRNx terminal. Each chan-

nel has independent bias current generators, programmable fault

comparators, fault decode logic, and programmable fault timers.

The serial interface provides a dedicated fault configuration reg-

ister for each channel to select these features and thresholds per

channel. A single fault mask register provides a fault mask bit for

each channel. Fault detection is disabled when RESETN is low or

when the fault mask bit is set. Fault reporting through the serial

interface is fully described in the Serial Interface section below.

Gate Drive Output

A short to battery (short across the load to the load supply) can be

detected when the channel is active, GATx is high, and the FET

is on (on-state). A short to battery fault always attempts to protect

the FET by pulling GATx low.

Each gate drive output is designed to provide symmetrical charge

current from the VDR supply terminal and discharge current to

the GND return terminal. The maximum source and sink imped-

ance provides peak charge and discharge currents of at least

50 mA when connected directly to the gate of the external FET.

This current can be limited, in order to limit the FET turn-on

switching speed, by using a resistor between the GATx output

and the gate of the FET. Although the GATx drive is designed to

be symmetrical, the actual drive performance will be affected by

the FET parameters and the resistance between the GATx output

and the gate of the FET.

A short to ground or open load can be detected when GATx is

low and the FET is off (off-state). A short to ground fault or

open load fault does not interfere with the operation of the GATx

output.

Each channel fault detected is latched as a fault state, and remains

latched until the diagnostic circuits can determine that the fault

has been removed for that channel. This determination can only

occur at the end of a fault blank time. For short to battery this is

at the end of the on-state fault blank time following a transition

from off to on. For a short to ground or open load this is at the

end of the off-state fault blank time following a transition from

on to off.

The VDR supply is used only to supply the GATx output. The

voltage at VDR can therefore be varied to provide voltage limited

drive to the FET gate. Undervoltage detection is not provided for

this supply.

When a fault is detected, a dedicated bit in one of the two fault

registers is set for each fault on each channel. This requires 3 bits

per channel over 6 channels or 18 fault bits in total. The fault bits

in the fault registers remain latched until the first serial transfer

after the associated fault state has been reset. All latched fault

states and all latched channel fault bits can also be cleared either

by a power-on reset or by taking the RESETN terminal low.

Reset Function

If RESETN is held low for more than the minimum reset pulse

width, then all registers are reset to their power-on state, and all

GATx outputs are held low. Any latched channel faults and cor-

responding bits in the fault register are reset, the logic reset (LR)

bit is set, and the UV and OT bits reflect the status of the under-

voltage and overtemperature detectors.

Practical limits for load resistance, and voltage conditions to

provide effective determination of the load status, are discussed

in the Applications Information section below.

The RESETN input uses a glitch filter to reduce the susceptibility

to transients and noise on the RESETN input. This glitch filter

is guaranteed to ignore any pulses shorter than the minimum

Note that each DRNx terminal has an internal Zener clamp which

limits the voltage at the terminal to V_DCL. If the voltage at the

drain of the FET is likely to be higher than V_DCL, even dur-

ing a transient, then a current limit resistor, R_Dx, must be added

RESETN glitch filter time, t_RGF

.

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115 Northeast Cutoff

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Worcester, Massachusetts 01615-0036 U.S.A.

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A3944

Automotive, Low Side FET Pre-Driver

between the drain connection to the FET and the DRNx terminal. TON0 and TON1 bits (bits 4 and 5 of the fault configuration

This resistor should be selected such that the energy dissipated by register for the channel).

the clamp diode is less than the absolute maximum drain clamp

To avoid false fault detection during supply transients, when the

energy, E_DRN. This is necessary to avoid excessive heat genera-

FET is active an additional fault filter will mask faults that are

tion in the silicon; otherwise permanent damage to the chip is

present for less than the on-state fault filter time, t_FF(on). This

likely. Selecting a value for R_Dxis described in the Applications

fault filter is only active after the fault blank time.

Information section, below.

The result is that directly after switch-on, a short to battery fault

On-State Diagnostics: Short to Battery

will not be detected until t_BL(on)after the GATx output is com-

manded to drive high. If a short occurs after t_BL(on)from switch-

on, then it must be present for at least t_FF(on)before it is detected.

When a channel is in the on-state the voltage at the drain monitor

terminal, V_DRNx, is compared to a threshold level derived from

the voltage at the REF terminal. A short to battery fault is present

if V_DRNxis higher than V_STB(see figure 3). Note that an open

FET also would be detected as a short to battery.

When a short to battery is detected the GATx output is automati-

cally commanded to drive low and to switch-off the FET. Two

alternative modes are then available depending on the status of

the RT0 and RT1 bits (bits 10 and 11 of the fault configuration

register for the channel).

The threshold voltage, V_STB, is selected per channel as a percent-

age of the voltage at the REF terminal. The voltage selection is

determined by the SB0, SB1, and SB2 bits (bits1, 2, and 3 of the

fault configuration register for the channel).

If RT1 is 0, the FET will be held off until the fault is reset by

pulsing RESETN low for longer than t_RSTor by toggling the

channel off then on, through the serial interface. In this mode,

toggling the input terminal for the channel has no effect until

after a reset.

When a FET is switched-on there is a finite time before the drain

voltage reaches a steady state. To avoid false fault detection at

switch-on, the output from the short to battery comparator is

ignored during the on-state fault blank time, t_BL(on), after the

GATx output is commanded to drive high. One of four possible

on-state fault blank times is selected, per channel, through the

If RT1 is 1, the channel will be held off until one of the two

common retry timers completes a time-out. The timer selection is

made by the state of the RT0 bit. The channel control bits, both

serial and logic input, are ignored during this time. At the end of

the retry time-out the channel will be switched-on again if the

state of the control logic commands the channel to be on. In the

retry mode the fault can be reset also by pulsing RESETN low for

longer than t_RSTor by toggling the channel off then on, through

the serial interface. This resets the channel fault and re-enables

the channel from the control logic.

On-State

Off-State

Diagnostics

V_DRNx

V_BB

Normal

Operation

V_OL

Short to Battery

Detected

Note that, if the common retry timer has already been activated

by another channel, then the first retry time-out for the second

channel may be shorter that the full time. Subsequent retry

sequences will run for the full time-out period minus the short

detection time.

Open Load

Detected

V_OCL

V_STG

V_STB

Normal

Operation

Short to Ground

Detected

Off-State Diagnostics: Open Load and Short to Ground

Two current generators and two comparators per channel provide

off-state diagnostic capability. If the voltage at the DRNx termi-

nal, V_DRNx, is greater than the open load clamp voltage, V_OCL

,

then one of the current generators sinks current to V_OCLthrough

the DRNx terminal. If V_DRNxis less than V_OCL,then one of the

current generators sources current from V_OCLthrough the DRNx

Figure 3. Diagnostic Threshold Voltages

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terminal. The voltage output capability of the current sources is

V_DRNxwill then be greater than the open load threshold, V_OL,

limited such that they cannot source current when the output volt- and no fault is detected (see figure 3). If the NPD bit is zero then

age is greater than V_OCLor sink current when the output voltage

is less than V_OCL. The equivalent circuit is shown in figure 4a.

The typical sink and source currents are shown graphically in

figure 4b.

the current sink will pull I_DPDfrom the supply through the load,

through the DRNx terminal, to V_OCL

The open load threshold, V_OL, and the open load clamp voltage,

V_OCL, are a both a fixed percentage of the voltage at the VREG

terminal and are common to all channels.

When a channel is in the off-state the current generators source or

sink current through the DRNx terminal in an attempt to pull the

voltage at the terminal to the open load clamp voltage, V_OCL. The

resulting voltage at the DRNx terminal, V_DRNx, is measured to

test for a short to ground or an open load.

Short to Ground

If a short to ground is present, then V_DRNxwill be pulled low by

the short circuit. V_DRNxwill be less than the short detect thresh-

old, V_STG, and a short to ground fault is reported (see figure 3).

Normal Operation

If a load is present, the load supply is active, and there are no

shorts to ground, then the load will pull V_DRNxabove V_OCL

The short detect threshold voltage, V_STG, is selected, per channel,

as a percentage of the voltage at the VREG terminal. The voltage

selection is determined by the SG bit (bit 0 of the fault configura-

tion register for the channel).

.

I_DPD

Open Load

I_DRNx

DRNx

If there is no short to ground or to supply, and the load is not con-

nected, then the current sources will pull V_DRNxtowards the open

load clamp voltage, V_OCL. V_DRNxwill then be greater than V_STG

but less than V_OLand an open load is reported (see figure 3).

V_DRNx

V_OCL

I_DPU

GND

The time taken for V_DRNxto reach the correct value for an open

fault condition depends on the current sourced from the DRNx

terminal and on the capacitance connected to the drain of the

FET. To avoid false fault detection at switch-off, the outputs

from the short to ground and open load comparators are ignored

during the off-state fault blank time, t_BL(off), after the GATx out-

put drives low. One of four possible off-state fault blank times is

selected, per channel, through the TOF0

Figure 4a. Diagnostic Current Source Circuit

100

80

NPD = 0

NPD = 1

I

DPD

60

40

and TOF1 bits (bits 6 and 7 of the fault configuration register

for the channel).

20

To avoid false fault detection during supply transients, an addi-

tional fault filter masks faults that are present for less than the

off-state fault filter time, t_FF(off). This fault filter is only active

after the fault blank time.

0

–20

–40

–60

–80

–100

The result is that directly after switch-off, a short to ground or

open load fault will not be detected until t_BL(off)after the GATx

output is commanded to drive low. If a fault occurs after t_BL(off)

from switch-off then it must be present for at least t_FF(off)before it

is detected.

I

DPU

0

2

4

6

8

10

12

V

DRNx

(V)

In some applications, for example when driving high efficiency

LEDs, the load may be sensitive to the pull down current used to

Figure 4b. Diagnostic Currents

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ensure open load detection. In these cases this pull-down current

can be disabled by setting the NPD bit (bit 8 in the fault con-

figuration register for the channel). If the NPD bit is set then it is

possible that V_DRNxwill reach the correct value for an open fault

condition when the load is connected, resulting in a false open

load detection.

warning level T_JW. It is incumbent upon the user to take any nec-

essary action to limit dissipation to reduce the temperature.

Serial Interface

The inputs CSN, SCK, and SI provide a three wire synchronous

serial interface, compatible with SPI, that can be used to control

all features of the A3944. The output, SO, can be used to provide

a fourth interface connection for detailed diagnostic feedback.

If this is likely, there are two options:

• Set the fault mask bit for the channel. This will mask all faults

on that channel and may not be a suitable option.

The serial interface timing requirements are specified in the Elec-

trical Characteristics table, and illustrated in the Serial Interface

Timing diagram, figure 2. Data is received on the SI terminal and

clocked through a shift register on the rising edge of the clock

signal input on the SCK terminal. CSN is normally held high, and

is only brought low to initiate a serial transfer. No data is clocked

through the shift register when CSN is high, allowing multiple

slave units to use common SI, SCK, and SO connections. Each

slave then requires an independent CSN connection.

• Set the open load fault mask bit, OLM (bit 6 in the fault mask

register). This will disable open load detection on any channel

where NPD is set to 1.

Chip Diagnostics

The chip temperature and the supply voltage levels at VDD and

VREG are monitored to ensure correct and safe operation of the

circuit.

VDD is monitored to ensure that power-up and power-down does

not cause incorrect operation. All outputs will be switched to high

impedance, the VREG regulator will be disabled and all faults

reset when the voltage at VDD, V_DD, falls below the undervolt-

age level, V_DDUV. The outputs will be reactivated when V_DD

rises above the undervoltage turn-on level plus the hysteresis

voltage, defined as V_DDUV+ V_DDUVhys. When V_DDrises above

this threshold, all registers will be reset to their power-on state,

and all GATx outputs will be low. In the fault register any latched

channel faults will be reset, the logic reset (LR) and undervoltage

(UV) bits will be set, and the OT bit will reflect the status of the

overtemperature monitor.

When 16 data bits have been clocked into the shift register, CSN

must be taken high to latch the data into the selected register.

When this occurs, the internal control circuits act on the new data

and the fault register is reset.

If there is either: more than 16 rising edges on SCK, or at least

one but fewer than 16 rising edges on SCK and CSN goes high,

then the write will be cancelled without writing data to the regis-

ters or resetting the diagnostic registers. The FF bit will be set to

indicate a data transfer error.

Configuration and Control Registers

The serial data word is 16 bits, input MSB first. The first four bits

are defined as the register address. This provides sixteen write-

able registers:

VREG is monitored to ensure correct operation of the fault

detection and control circuits. All channel faults will be reset

when the voltage at VREG, V_REG, falls below the undervoltage

level, V_REGUV. They will be held reset until V_REGrises above the

undervoltage lockout level plus the hysteresis voltage, V_REGUV

+ V_REGUVhys. The outputs will remain active irrespective of the

Address 1: Gate Select Register

The six least significant bits of this register are the control bits

for each of the six channels. G0 corresponds to channel 0, G1 to

channel 1, and so forth. If RESETN is high and no faults are pres-

ent on the channel, then when the Gx bit for a channel is set to 1

the GATx output will be high.

value of V_REG

.

The chip temperature is monitored by the thermal warning cir-

cuit. An overtemperature fault will be indicated but no action will

be taken when the chip temperature exceeds the overtemperature

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case the fault registers will continue to alternate between Fault0

Address 5: Fault Mask Register

and Fault1.

The six least significant bits of this register are the fault mask bits

for each of the six channels. K0 corresponds to channel 0, K1 to

channel 1, and so forth. When the K bit for a channel is set to 1

all faults on that channel are ignored and no faults are reported

for that channel. Bit 6 is an open load fault mask bit, OLM, that

disables the open load detection on any channel where NPD is

set to 1.

The next three most significant bits, after FF, in each fault regis-

ter are the system diagnostic bits: UV (bit 14), LR (bit 13), and

OT (bit 12). These provide an indication of undervoltage, logic

reset, and overtemperature faults.

Bit 11 (FR) indicates which of the two fault registers is being

output on SO. This bit is a zero for the Fault0 register and a one

for the Fault1 register.

Addresses 8 to 13: Channel Fault Configuration Registers

These six registers, one per channel, determine the fault threshold

levels, fault blank times, and fault features for each channel. The

MSB is always set to 1. The next three bits, bits 12,13, and 14,

are the channel address bits.

The least significant 9 bits in each fault register provide three

bits per channel, one bit for each of the three possible fault states:

short to battery, short to ground, and open load. Fault0 con-

tains the fault data for channels 0, 1, and 2. Fault1 contains the

fault data for channels 3, 4, and 5. The bits naming convention

indicates the channel and fault allocation. The format is “ccff,”

where “cc” is C0, C1, C2, C3, C4, or C5 (indicating the channel)

and “ff” is SG, SB, or OL (indicating the faults: short-to-ground,

short-to-battery and open-load respectively).

The remaining register addresses are unused. Writing to these

addresses will have no effect on the operation but will still report

the fault register on SO.

Fault Register

In addition to the writable registers there are two fault registers,

Fault0 and Fault1. The register being output is identified by bit

11, which contains a zero for Fault0 and a one for Fault1. Each

time any register is written through the serial interface, one of

the fault registers can be read, MSB first, on the serial output

terminal, SO (see the Serial Interface Timing diagram, figure 2).

Fault0 is output: on the first write after a power-on-reset, after a

RESETN low input, or after a serial fault poll (described in the

next paragraph). Fault1 is then read on the next write. The two

registers then alternate on each successful serial write sequence.

The contents of the fault register that is being read cannot change

when CSN is low and a serial read is in progress. Any faults

detected during a serial read do affect the read in progress but the

fault will be latched in the fault register when CSN goes high at

the end of a serial read. The fault bits can only be cleared after:

either the diagnostic circuits have confirmed that the fault that

has been reported is no longer present, or there is a low level on

the RESETN input.

In the case of undervoltage or overtemperature faults, which are

not latched, the fault bits will be reset at the end of a serial read if

the fault is not detected at that time.

The first, most significant, bit in both fault registers is the fault

register flag, FF (bit 15). This bit is set to one, if any faults have

been detected since the last fault reset. The state of FF appears

on SDO as soon as CSN goes low, allowing the fault status to be

determined without a change in the level of SCK. A serial trans-

fer may be terminated when CSN goes low then high, without

generating a serial read fault, by ensuring that SCK remains high

while CSN is low. This allows the main controller to poll the

A3944 through the serial interface to determine if a fault has been

detected. When this occurs the fault register pointer is reset to the

Fault0 register, so the next full write sequence outputs the Fault0

register. The fault status can also be read, without disturbing any

For channel faults, which are latched, the fault bits will be reset at

the end of a serial read if the diagnostic circuits have previously

determined that the fault that has been reported is no longer pres-

ent. This determination can only occur at the end of a fault blank

time and therefore requires: either an on-to-off transition (for

short to ground and open load faults), or an off-to-on transition

(for short to battery faults) on the faulty channel before the start

of a serial read. Any changes to the fault state when a read is in

progress are ignored until the end of the serial read. If a fault is

cleared when a serial read is in progress, then the fault bits will

settings, by writing to one of the unused register addresses. In this be cleared when CSN goes high.

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Figures 5 through 10 are channel fault timing diagrams, which

the relative voltage, DRNx, at the drain of the external MOSFET.

show fault conditions applied to a channel and the results of the

fault latches and the state of the fault register after serial reads

and channel state changes. Each diagram shows the state of

the channel control signal, INx, and the state of the gate drive

output, GATx, for the channel, as well as an approximation of

Beneath this is the latched fault state and the contents of the fault

register bits for the channel. The sequence of serial reads are

shown at the bottom of each figure as the state of the CSN input

and the resulting data bits read for the channel.

Output

Disabled

t_RE

IN_X

GATx

DRNx

Short

Applied

Short

Removed

t_BL(on)

V_STB

t_BL(on)

Fault None

Short to Battery

1

None

0

Fault register bit

CxSB

0

CSN

Serial Read

Serial Read Data

Cxff=0

CxSB=1

CxSB=1 CxSB=1 Cxff=0

Figure 5. Fault Sequence: Short to battery during off-state (RT1=1)

IN_X

GATx

Short

Applied

Short

Removed

t_BL(off)

DRNx

V_STG

t_BL(off)

Fault None

Short to Ground

None

Fault register bit

CxSG

0

1

0

CSN

Serial Read

Serial Read Data

Cxff=0

CxSG=1

CxSG=1 CxSG=1 Cxff=0

Figure 6. Fault Sequence: Short to ground during on-state

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IN_X

GATx

DRNx

t_BL(off)

V_OL

V_OCL

V_STG

Load

Connected

Load

Removed

t_BL(off)

Fault None

Open Load

None

Fault register bit

CxOL

0

1

0

CSN

Serial Read

Serial Read Data

Cxff=0

CxOL=1

CxOL=1 CxOL=1 Cxff=0

Figure 7. Fault Sequence: Open load during on-state

Output

Disabled

t_RE

IN_X

GATx

t_FF(on)

Short

Removed

Short

Applied

V_STB

DRNx

t_BL(on)

Fault None

Short to Battery

1

None

0

Fault register bit

CxSB

0

CSN

Serial Read

Serial Read Data

Cxff=0

CxSB=1

CxSB=1 CxSB=1 Cxff=0

Figure 8. Fault Sequence : Short to battery during on-state (RT1=1)

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Short

Applied

Removed

IN_X

GATx

DRNx

V_STG

t_BL(off)

t_FF(off)

Fault None

Short to Ground

None

Fault register bit

CxSG

0

1

0

CSN

Serial Read

Serial Read Data

Cxff=0

CxSG=1

CxSG=1 CxSG=1 Cxff=0

Figure 9. Fault Sequence: Short to ground during off-state

Output

Disabled

IN_X

GATx

t_FF(on)

t_BL(on)

V_OCL

V_STB

Short

Applied

DRNx

Load

recovers

Load goes

open circuit

t_BL(off)

None

Short to Battery

Open Load

None

Faults

Fault register bits

CxSB

CxOL

0

1

0

1

0

CSN

Serial Read

CxSB=1

CxSB=0 CxSB=0

Cxff=0

Serial Read Data

Cxff=0

Figure 10. Fault Sequence: Short to battery during on-state followed immediately by open load (RT1=0)

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V_DDUV+Hys

V_DDUV

V_DD

V_BB

V_REG

V_BB/V_REG

V_REGUV+Hys

V_REGUV

Outputs

Z

Enabled

Z

Enabled

Z

Fault register bits

U

1

0

1

0

U

1

0

1

U

LR

UV

0

CSN

Serial Read

LR=1

UV=1

LR=0

UV=1

LR=0

UV=0

LR=1

UV=1

LR=0

UV=1

Serial Read Data

Where Z=high impedance, U=undefined

Figure 11. Power Sequence Timing- V_DDbefore V_BB

V_DDUV+Hys

V_DDUV

V_DD

V_BB

V_REG

V_BB/V_REG

RESETN

Outputs

X

Z

Enabled

Off

Enabled

Fault register bits

LR

UV

U

1

0

1

0

U

CSN

Serial Read

X

LR=1

UV=1 UV=0

LR=0

LR=1

UV=0

LR=1

UV=0

LR=0

UV=0

Serial Read Data

Where Z=high impedance, U=undefined, X=don’t care

Figure 12. Power Sequence Timing- V_DDafter V_BB- with RESET

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Serial Register Definition*

15

14

0

13

0

12

1

11

10

9

8

7

6

0

5

4

3

2

1

0

G5

0

G4

0

G3

0

G2

0

G1

0

G0

0

Gate Select

0

1

0

OLM

0

K5

0

K4

0

K3

0

K2

0

K1

0

K0

0

Fault Mask

1

0

1

RT1

0

RT0

0

NPD TOF1 TOF0 TON1 TON0 SB2

SB1

0

SB0

0

SG

0

Channel Fault Config

ADR2 ADR1 ADR0

0

FF

1

UV

LR

1

OT

FR

0

C2SG C2SB C2OL C1SG C1SB C1OL C0SG C0SB C0OL

Fault0

Fault1

0

FF

1

UV

LR

1

OT

FR

1

0

C5SG C5SB C5OL C4SG C4SB C4OL C3SG C3SB C3OL

0

*Power on reset value shown below each input register bit.

Gate Select Register

Fault0/Fault1 Registers

G[5..0]

Control bits for each of the six channels.

G0 corresponds to channel 0, G1 to channel 1 etc.

If RESETN is high and no faults are present on

the channel then when the Gx bit for a channel is

set to 1 the GATx output will be high

FF

UV

LR

Logic 1 if any faults have been detected since the

last fault reset.

Logic 1 if any VDD or VREG undervoltage faults

have been detected since the last fault reset.

Fault Mask Register

Logic 1 if a logic reset has occurred since the last

register read. A logic reset is caused by a power-

on-reset or by taking the RESETN input low.

K[5..0]

Fault mask bits for each of the six channels.

K0 corresponds to channel 0, K1 to channel 1 etc.

When the Kx bit for a channel is set to 1 all faults

on that channel are ignored and no faults are

reported for that channel.

OT

FR

Logic 1 if an overtemperature fault has been

detected since the last fault reset.

Fault register identifier.

Logic 0 for Fault0 register,

logic 1 for Fault1 register.

OLM

Open load fault mask for all channels where

NPD=1. If the NPD bit is set to 1 on a channel

and OLM is set to 1 then the open load diagnostic

is disabled for that channel.

CxSG

CxSB

CxOL

Logic 1 if channel short to ground detected.

Where x is channel number.

Logic 1 if channel short to battery detected.

Where x is channel number.

Logic 1 if channel open load detected.

Where x is channel number.

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Serial Register Definition*

15

14

13

12

11

10

9

0

8

7

6

5

4

3

2

1

0

RT1

0

RT0

0

NPD TOF1 TOF0 TON1 TON0 SB2

SB1

0

SB0

0

SG

0

Channel Fault Config

1

ADR2 ADR1 ADR0

0

*Power on reset value shown below each input register bit.

Channel Fault Config Register

ADDR[2..0]

Channel address

TON[1..0] Turn-on blank time select.

ADR2

ADR1

ADR0

Address

TON1

TON0

Turn-on blank time (nominal)

0

1

0

1

0

1

0

1

0

1

Channel 0

Channel 1

Channel 2

Channel 3

Channel 4

Channel 5

0

1

0

1

0

1

5μs

14μs

28μs

56μs

SB[2..0] Short to battery threshold select

SB2

SB1

SB0

Threshold (nominal)

0

6% V_REG

RT[1..0] Retry select

RT1

RT0

Fault

0

1

8% V_REG

0

X

Lockout until reset

0

1

0

10% V_REG

1

0

Short retry timer. Nominally 10ms

Long retry timer. Nominally 55ms

0

1

12% V_REG

1

0

14% V_REG

1

0

1

16% V_REG

NPD

Disable diagnostic pull-down

Action

1

0

18% V_REG

NPD

1

31% V_REG

0

1

Enable diagnostic pull-down

Disable diagnostic pull-down

SG

Short to ground threshold select.

Threshold (nominal)

45% V_REG

SG

0

TOF[1..0] Turn-off blank time select.

TOF1

TOF0

Turn-off blank time (nominal)

1

66% V_REG

0

1

0

1

0

1

80μs

140μs

280μs

4ms

For tolerances on selected parameters refer to the Electrical

Characteristics Table.

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Applications Information

These values would typically apply to a remote load which is

primarily resistive. The load inductance will be due to a combina-

tion of the wiring and any parasitic inductance in the load. In this

example, the DC on-state current will be 13 V/26Ω = 0.5 A.

Drain Feedback Clamp Resistor Selection

The drain feedback input, DRNx, for each channel is clamped

internally with a 50 V (nominal) Zener diode. If the voltage

applied to this terminal is likely to exceed 50 V then an external

current limit resistor will be required to limit the current, power,

and energy to less than the Absolute Maximum specifications in

this document.

When the load is switched off, the inductance attempts to keep

the current flowing by increasing the voltage at the end connect

to the FET switch. This voltage increases up to the breakdown

voltage of the FET. At that point, the voltage across the load

amounts to the difference between the FET breakdown voltage

and the supply voltage, and it acts to reduce the current. With the

parameters in this example, the current would decay to zero in

less than 1 μs. This is less than the 1.85 μs limit for maximum

current, so the drain resistor will be based only on the maximum

current. The value of the drain resistor, R_Dx, in this case is simply

the voltage across the resistor divided by the maximum current:

Note that the internal drain clamp in the A3944 is not intended to

dissipate the energy from any external load. The internal clamp

is provided to protect the internal circuits of the A3944 from any

high voltage that would otherwise cause permanent damage.

If the voltage at DRNx, V_DRNx, will never exceed the minimum

drain clamp voltage, V_DCL, then no external resistor is required

and DRNx can be connected directly to the drain of the external

MOSFET switch.

Three Absolute Maximum specifications apply to the A3944,

none of which may be exceeded:

V_FET– V_DCL

(1)

R_Dx

=

I_DRNC

• The maximum clamp current, I_DRNC, applies to very short

pulses, typically less than 1.85 μs. Any current pulse less than

1.85 μs and less than I_DRNC, will never exceed the maximum

power or energy limits.

where

V_FETis the FET breakdown voltage,

V_DCLis the A3944 drain clamp voltage, and

I_DRNCis the A3944 drain clamp max current.

• The maximum clamp energy, E_DRNC, applies to pulses between

1.85 μs and 2 ms. Above 2 ms the heat produced by the clamp

energy dissipates through the silicon and the package; in that

case, the maximum clamp power applies. Note that for pulse

lengths between about 500 μs and 2 ms the energy starts to dis-

sipate during the pulse, so the maximum current that is possible

will actually be higher than that calculated using the maximum

energy limit.

Substituting into equation 1:

80 V – 54 V

R_Dx

=

= 260 Ω

100 mA

• The maximum clamp power, P_DRNC, applies to pulses lasting

longer than 2 ms up to continuous operation.

The energy injected into the A3944 drain clamp is:

E_DRNC= V_DCL× I_DRNC× t_PULSE

where t_PULSEis the duration of the current pulse.

Substituting into equation 2:

(2)

Maximum current example:

• Load resistance: 26 Ω

• Load inductance: 130 μH

• Load current: 0.5 A

E_DRNC= 54 V × 100 mA × 0.9 μs = 4.86 μJ (per pulse)

• Load supply voltage: 13 V

• FET clamp voltage: 80 V

As expected, based on the pulse length, this is less than half the

clamp energy limit, given in the Absolute Maximum table.

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The maximum repetition rate of this pulse is derived from the

Substituting into equation 4:

maximum average clamp power dissipation limit. The minimum

time between pulses, t_REP, is:

10 μJ

I_DRNC

=

= 18.5 mA

54 V × 10 μs

E_DRNC

(3)

t_REP

=

P_DRNC

As given in equation 1, the value of the drain resistor is the volt-

age across the resistor divided by the maximum current:

where P_DRNCis the A3944 drain clamp maximum power.

V_FET– V_DCL

R_Dx

=

Substituting into equation 3:

I_DRNC

4.86 μJ

t_REP

=

= 48.6 μs

100 mW

80 V – 54 V

18.5 mA

R_Dx

= 1.4 kΩ

resulting in a repetition rate of just over 20 kHz.

As given in equation 3, the maximum repetition rate of this pulse

is derived from the maximum average clamp power dissipation

limit as:

Maximum energy example:

• Load resistance: 18 Ω

• Load inductance: 1 mH

• Load current: 0.72 A

E_DRNC

P_DRNC

t_REP

=

• Load supply voltage: 13 V

• FET clamp voltage: 80 V

10 μJ

t_REP

= 100 μs

100 mW

These values would typically apply to a small inductive load

such as a solenoid or relay. When the load is switched off, the

inductance attempts to keep the current flowing by increasing

the voltage at the end connected to the FET switch. This voltage

increases up to the breakdown voltage of the FET. At that point,

the voltage across the load amounts to the difference between

the FET breakdown voltage and the supply voltage, and it acts to

reduce the current. With the parameters in this example, the cur-

rent would decay to zero in about 10 μs. This is greater than the

1.85 μs pulse time defining the maximum current but less than

the 2 ms time constant for maximum average clamp power, so

the drain resistor will be selected to limit the energy injected into

the drain clamp in the A3944. The maximum current, the A3944

drain clamp maximum current, I_DRNC, will be:

:

resulting in a repetition rate of 10 kHz.

Maximum power example:

• Load resistance: 5 Ω

• Load inductance: 80 mH

• Load current: 2.6 A

• Load supply voltage: 13 V

• FET clamp voltage: 60 V

These values would typically apply to a large inductive load

such as a coil or actuator. When the load is switched off, the

inductance attempts to keep the current flowing by increasing

the voltage at the end connected to the FET switch. This voltage

increases up to the breakdown voltage of the FET. At that point,

the voltage across the load amounts to the difference between

the FET breakdown voltage and the supply voltage, and it acts

to reduce the current. With the parameters in this example, the

current would decay to zero in about 4 ms. This is greater than

the 2 ms time constant for maximum average clamp power, so

the drain resistor will be selected to limit the power dissipated by

E_DRNC

(4)

I_DRNC

=

V_DCL× t_PULSE

where

E_DRNCis the A3944 drain clamp maximum energy,

V_DCLis the A3944 drain clamp voltage, and

t_PULSEis the duration of the current pulse.

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the drain clamp in the A3944. The maximum current, the A3944

drain clamp maximum current, I_DRNC, will be:

Note that this equation is only valid for normal load and open

load conditions when:

V_DRNx> V_OCL

P_DRNC

(5)

I_DRNC

=

where V_OCLis the open load clamp voltage.

V_DCL

Ideally an open load would mean an infinite or at least a very

large (>1 MΩ) resistance. In practice this is not necessarily the

case, and the limit of open-load resistance values for correct

detection will be determined by: the threshold voltages, the diag-

nostic currents, and the load voltage.

where

P_DRNCis the A3944 drain clamp maximum power and

_DCLis the A3944 drain clamp voltage.

Substituting into equation 5:

V

An open load is detected when:

V_DRNx< V_OL

100 mW

54 V

I_DRNC

=

= 1.8 mA

where V_OLis the open load detect voltage, then:

⇒ V_OL> V_DRNx

⇒ V_OL> V_L– I_DPD( R_L+ R_D) ,

R_L> [(V_L– V_OL) / I_DPD] + R_D.

,

As given in equation 1, the value of the drain resistor is the volt-

age across the resistor divided by the maximum current:

(from 6)

(7)

∴

V_FET– V_DCL

R_Dx

=

There are two open-load resistance values to consider. The first is

the minimum resistance at which an open load detection is always

guaranteed. The second is the maximum resistance that a load can

present without ever causing an open load to be detected. Both

cases, described below, assume that the load is connected to the

load supply and that the load supply is higher than the open load

I_DRNC

60 V – 54 V

1.8 mA

R_Dx

= 3.3 kΩ

The maximum repetition rate is irrelevant in this case because the

A3944 will sustain the maximum clamp dissipation indefinitely.

clamp voltage, V_OCL

.

V_L

Practical Open Load Limits

An open load is detected, when the external FET is off, if the

voltage at the DRNx terminal is less than the open load threshold,

V_OL, but greater than the short to ground threshold, V_STG. The

voltage at the DRNx terminal in the off-state is defined as (refer-

ring to figure 13):

R_L

DRNx

+

R_D

V_DRNx= V_L– I_DPD( R_L+ R_D)

(6)

-

V_OL

where

I_DPD

V_DRNxis the voltage at the DRNx terminal,

V_Lis the load supply voltage,

I_DPDis the diagnostic pull-down current,

R_Lis the load resistance, and

V_OCL

Figure 13. Open load detection condition

R_Dis the DRNx current limit resistor.

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For a 6 V supply this gives a maximum value of 19 kΩ for the

Minimum guaranteed open load resistance

The minimum value of R_Lthat will always be detected as an open

is given by the maximum value of R_Lthat could be detected as a

load, R_Lmax. This is defined by:

sum of the open load resistance and the DRNx current limit resis-

tor. This means, for example, that under all conditions, with a

DRNx current limit resistor of up to 7 kΩ, a load resistance less

than 12 kΩ will never cause an open load detection.

V_Lmax– V_OLmax

(8)

R_Lmax

=

– R_Dmin

I_DPDmin

The two limiting values are shown in figure 14 for load volt-

ages from 6 to 36 V. Note that the load resistance value includes

the DRNx current limit resistor. In this figure, a load resistance

greater than the upper line is guaranteed to be detected as an open

load and a load resistance less than the lower line is guaranteed

not to be detected as an open load.

For an 18 V supply this gives a minimum guaranteed open load

resistance value of 79 kΩ. This means that under all conditions,

with a load voltage of up to 18 V, a load resistance greater than

79 kΩ will always be detected as an open load. For a 36 V supply

the minimum guaranteed open load resistance value increases to

379 kΩ.

Practical Short to Ground Limits

Maximum load resistance

A short to ground is detected, when the external FET is off, if

the voltage at the DRNx terminal is less than the short to ground

threshold, V_STG. Under ideal conditions a short circuit would be

zero resistance and the short would be to ground at zero volts.

However in practical systems the short will have a finite resis-

tance and the power ground voltage may be higher than the refer-

ence ground of the detection circuit. The equivalent circuit during

a short to ground is shown in figure 15.

The maximum value of R_Lthat will always be detected as a load

is given by the minimum value of R_Lthat could be detected as a

open, R_Lmin. This is defined by:

V_Lmax– V_OLmax

(9)

R_Lmax

=

– R_Dmin

I_DPDmin

V_L

V_OCL

I_DPU

R_L

DRNx

+

-

R_Dx

V_STG

R_SG

V_G

Figure 14. Open load detection limits

Figure 15. Short to ground detection condition

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The voltage at the DRNx terminal, V_DRNx, in the off-state when a

short to ground is present is defined as:

short detection criterion, R_Lmax., defined by:

V_L– V_Gmax

(12)

– 1

R_SGmax

R_Lmax

=

(V_L– V_G) R_SG

V_STGmin– V_Gmax– I_DPUmaxR_Dmax

(10)

V_DRNx

=

+ V_G+ I_DPUR_D

R_L+ R_SG

Assuming worst case conditions of a maximum ground voltage

offset of +1 V and a maximum short resistance of 0.5 Ω allows

the minimum load resistance to be calculated for different load

voltages. This will be maximum at either V_Lmaxor V_Lmindepend-

ing on the relative values of R_Dmaxand V_L.

where

V_Lis the load supply voltage,

V_Gis the ground (offset) voltage,

R_SGis the resistance of the short to ground (offset),

R_Lis the load resistance,

For example, at a load voltage of 6 V and R_Dset to 5 kΩ, a short

will be detected with a load resistance greater than 0.75 Ω when

SG = 0, or at 2.63 Ω when SG = 1. At a load voltage of 18 V the

same conditions give 0.9 Ω for SG = 0 and 0.34 Ω for SG = 1.

I_DPUis the diagnostic pull-up current, and

R_Dis the DRNx current limit resistor.

The limiting values for SG = 0 and SG = 1 are shown in figure 16

for load voltage from 6 to 36 V and with a DRNx current limit

resistor (R_Dmax) of 7 kΩ. In this figure, a load resistance above

the line is guaranteed to allow detection of a 0.5 Ω short to a

+1 V offset ground. An increase in R_Draises the line.

Note that this equation is only valid for short to ground condi-

tions when:

V_DRNx< V_OCL

where V_OCLis the open load clamp voltage.

A short to ground is detected when:

V_D< V_STG

where V_STGis the short to ground detect voltage, then:

(V_L– V_G) R_SG

+ V_G+ I_DPUR_D< V_STG

R_L+ R_SG

Note that R_Dmust be less than:

(V_STG– V_G)

I_DPU

(V_L– V_G) R_SG

< V_STG– V_G– I_DPUR_D

R_L+ R_SG

V_L– V_G

(11)

– 1

<

R_L>

R_SG

V_STG– V_G– I_DPUR_D

Minimum load resistance

The minimum value of R_Lthat will always allow a short to be

detected is given by the maximum value of R_Lthat satisfies the

Figure 16. Short to ground detection limits

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This will be at a minimum when

Practical Short to Battery Limits

A short to battery is detected, when the external FET is on, if the

voltage at the DRNx terminal is greater than the short to battery

threshold, V_STB. Under ideal conditions a short circuit would be

zero resistance. However in practical systems the short will have

a finite resistance. The equivalent circuit during a short to battery

is shown in figure 17.

(V_L– V_STB

)

V_STBR_L– (V_L– V_STB) R_ON

is at its minimum. This occurs when V_L–V_STBis at its minimum

and V_STBis at its maximum. This is the condition that is present

when V_Lis just high enough to provide the minimum drop-out

voltage above the maximum value of V_REG, (that is, when V_L=

V_REGmax+ V_DOmin) and V_STBis at the maximum tolerance value.

The voltage at the DRNx terminal in the on-state when a short to

battery is present is defined as:

V_LR_ON

Placing these limits into the expression for R_SBgives the expres-

sion for the minimum short resistance, defined by:

V_DRNx

=

R_LR_SB

(13)

+ R_ON

R_L+ R_SB

(V_REGmax+V_DOmin+V_STBmax) R_ONR_L

where

R_SBmax(min)

=

(16)

V_STBmax(R_L+ R_ON) – (V_REGmax+V_DOmin)R_ON

V_DRNxis the voltage at the DRNx terminal,

V_Lis the load supply voltage,

The maximum short resistance at any load voltage is given by:

R_ONis the FET switch on-resistance,

R_Lis the load resistance, and

(V_L– V_STBmax) R_ONR_L

R_SBmax

=

(17)

R_SBis the resistance of the short across the load.

V_STBmax(R_L+ R_ON) – V_LR_ON

A short to ground is detected when:

V_DRNx> V_STB

where V_STBis the short to ground detect voltage, then:a

V_L

V_LR_ON

> V_STB

R_LR_SB

(14)

+ R_ON

R_L+ R_SB

R_L

R_SB

For short to battery diagnostics there are two limiting resistance

values to consider. The first is the maximum value of R_SBthat

will always cause a short to be detected. The second is the mini-

mum value of R_Lthat will not cause a short to battery detection

under normal operating conditions.

DRNx

+

-

V_STB

R_ON

Maximum short resistance

The maximum value of the short resistance, R_SB, that will always

cause a short to be detected is given by the minimum value of

R_SBthat satisfies the short detection criterion defined by:

Figure 17. Short to battery detection condition

(V_L– V_STB) R_ONR_L

R_SB

<

(15)

V_STB(R_L+ R_ON) – V_LR_ON

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The variation of R_SBmaxwith load voltage is shown as the lower

line (Maximum Short Resistance) in figure 18. This example

shows the maximum possible resistance of a short to battery

that will always be detected as a short with a 2.8 Ω load and a

100 mΩ MOSFET using short to battery threshold level 5.

This allows a lower threshold to be used for V_STB, resulting in a

faster short to battery detection and a lower short circuit current.

Minimum load resistance

For normal operation:

As R_Lincreases, R_SBbecomes the dominant resistance and:

(20)

V_LR_ON

V_DRNx

=

V_D=

R_L+ R_ON

R_LR_SB

+ R_ON

R_L+ R_SB

and:

V_LR_ON

V_DRNx< V_STB

V_D=

(18)

R_SB+ R_ON

Rearranging gives:

The expression for R_SB(from equation 15) becomes:

(V_L– V_STB)R_ON

R_L>

(21)

V_STB

(V_L– V_STB)R_ON

(19)

R_SB

<

V_STB

The minimum value of the load resistance, R_L, that will not cause

a short to battery detection under normal operating conditions is

given by:

(V_Lmax– V_STBmin)R_ONmax

(22)

R_Lmin

=

V_STBmin

The variation of R_Lminwith load voltage is shown as the upper

line (Minimum Load Resistance) in figure 18. This example

shows the minimum possible load resistance that will always

allow a short to battery to be detected with a 0.5 Ω short and a

100 mΩ MOSFET using short to battery threshold level 5.

Power Dissipation Estimation

The A3944 supply currents have very little dependency on the

state of the internal circuits. In addition, the internal operation

is essentially low speed so the power dissipation has almost no

dependency on operating frequency other than dissipation due

to channel switching and diagnostics that are proportional to

PWM frequency. It is therefore possible to estimate the maximum

power dissipated within the A3944 by summing the contribution

from the three quiescent supply currents with the dissipation due

to channel switching and diagnostics associated with turning each

external MOSFET on and off.

Figure 18. Short to battery detection limits

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As an example, the maximum likely switching losses can be

Quiescent Dissipation

The quiescent dissipation for each supply is the simply product of

the supply current and the supply voltage:

estimated by using a reasonably large MOSFET total charge of

100 nC and a PWM frequency of 10 kHz. With no gate resistor

the dissipation in the A3944 due to switching losses for a single

channel will be approximately 5 mW.

P_DD= V_DD× I_DDQ

P_BB= V_BB× I_BBQ

P_BR= V_DR× I_DRQ

Channel Diagnostic Dissipation

Each channel has three current generators that are used to deter-

mine the state of the load during the off-state for the channel.

Under normal load conditions the power dissipated is limited to

the product of the pull-down current source and the difference

between the load supply and the open load clamp voltage. For

example, with a 24 V load supply, this would contribute a maxi-

mum of 80 μA × 9.2 V = 0.8 mW. At 12 V this drops to 0.2 mW.

From the Electrical Characteristics table specification this gives

the total maximum quiescent dissipation of 131 mW when V_DD

and V_DRare 5 V and V_BBis 24 V. At 12 V this drops to 83 mW.

Channel Switching Dissipation

The dissipation produced by switching each channel on or off is

calculated by summing the energy passing through the gate drive

output to and from the gate of the external MOSFET over time.

The energy transferred to the gate is given by:

However, the worst case dissipation will occur when the load

is not connected and a capacitor is attached to the diagnostic

feedback terminal for the channel, DRNx. As for the switching

losses, the dissipation can be calculated by summing the energy

transferred to the capacitor over time. In this case the energy

transferred is:

Q_gV_G

(23)

E_SW

=

2

where

Q_gis the total MOSFET gate charge and

V_Gis the MOSFET gate voltage when on.

C_DV²

OCL

(26)

E_D=

2

This is the energy transferred through the gate drive each time

a MOSFET is switched on or off. The total power due to this

energy transfer is calculated by multiplying the energy by the

number of switching events per second. The number of switching

events per second is twice the PWM frequency, so the dissipation

due to switching losses becomes:

where

C_Dis the value of the DRNx capacitor and

V_OCLis the offset clamp voltage.

This is the energy transferred through the current source each

time a MOSFET is switched off. The total power due to this

energy transfer is calculated by multiplying this energy by the

number of switching events per second. The number of switching

events per second is the PWM frequency, so the dissipation due

to switching losses becomes:

P_SW= Q_gV_Gf_PWM

(24)

where f_PWMis the PWM frequency for the channel.

If there is no gate resistor then this is the total dissipation that will

occur inside the A3944. If a gate resistor is used then the dissipa-

tion will be shared proportionally by the gate resistor and by the

on-resistance of the A3944 gate drive. This gives the equation for

internal dissipation as:

C_DV²

f_PWM

OCL

(27)

P_D=

2

where f_PWMis the PWM frequency for the channel.

R_ON

(25)

P_SW= Q_gV_Gf_PWM

As an example, a 10 nF capacitor and a PWM frequency of

R_ON+ R_G

10 kHz will produce a dissipation in the A3944 for a single chan-

nel of approximately 4.3 mW. This is the worst case dissipation.

It will not be present if a load is attached and will be reduced by

any DRNx current limit resistor.

where

R_ONis the on-resistance of the gate drive and

R_Gis the gate resistor value.

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Total Dissipation Example

The total dissipation is the sum of the quiescent dissipation and

the dissipation due to switching and diagnostic currents in each of

the six channels:

P_max= P_DD+ P_BB+ P_DR+ 6 (P_SW+ P_diag

)

(28)

The worst case maximum dissipation occurs at maximum supply

voltage and all loads open circuit. Assuming: a channel PWM fre-

quency of 10 kHz on each channel, a 10 nF capacitor attached to

each DRNx terminal, 10 nC MOSFETs, no DRNx resistors, and

no gate resistors, then the maximum dissipation will be 275 mW.

This is a conservative maximum dissipation showing that the

A3944 can easily be used in high ambient temperatures without

requiring derating.

This worst case dissipation will drop to 227 mW with a 24 V sup-

ply and to 139 mW with a 12 V supply.

The maximum typical dissipation, with all loads connected and

the same conditions, will be 219 mW at 36 V, 165 mW at 24 V

,and 114 mW at 12 V (see figure 19).

Figure 19. Power dissipation all loads connected

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Package LP, 28-Pin TSSOP

with Exposed Thermal Pad

0.45

0.65

9.70±0.10

28

8º

0º

28

1.65

0.20

0.09

B

6.10

3.00

3 NOM 4.40±0.10 6.40±0.20

0.60 ±0.15

A

2

1.00 REF

1

5.08 NOM

1

2

0.25 BSC

Branded Face

5.00

SEATING PLANE

C

28X

GAUGE PLANE

SEATING

PLANE

0.10

C

PCB Layout Reference View

0.30

0.19

0.65 BSC

For Reference Only; not for tooling use (reference MO-153 AET)

Dimensions in millimeters

1.20 MAX

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

0.15

0.00

Terminal #1 mark area

A

B

C

Exposed thermal pad (bottom surface); dimensions may vary with device

Reference land pattern layout (reference IPC7351

SOP65P640X120-29CM);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as

necessary to meet application process requirements and PCB layout

tolerances; when mounting on a multilayer PCB, thermal vias at the

exposed thermal pad land can improve thermal dissipation (reference

EIA/JEDEC Standard JESD51-5)

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Revision History

Revision

Revision Date

May 18, 2012

Description of Revision

Update R_DS(on), I_BBQ, and I_GL

Rev. 1

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

For the latest version of this document, visit our website:

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Allegro MicroSystems, LLC

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1.508.853.5000; www.allegromicro.com


型号：	A3944KLPTR-T
厂家：	ALLEGRO MICROSYSTEMS
描述：	Buffer/Inverter Based MOSFET Driver, PDSO28, LEAD FREE, TSSOP-28 驱动光电二极管接口集成电路
文件：	总31页 (文件大小：602K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A3944KLPTR-T [ALLEGRO]

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