A4952ELYTR-T
更新时间：2024-09-18 18:09:38
品牌：ALLEGRO
描述：Brush DC Motor Controller, 2A, DMOS, PDSO10, LEAD FREE, MO-187BA-T, MSOP-10
概述
规格参数
数据手册A4952ELYTR-T 概述
Brush DC Motor Controller, 2A, DMOS, PDSO10, LEAD FREE, MO-187BA-T, MSOP-10 运动控制电子器件
A4952ELYTR-T 规格参数
| 是否无铅： | 不含铅 | 是否Rohs认证： | 符合 |
| 生命周期： | Active | 零件包装代码： | TSSOP |
| 包装说明： | HTSSOP, TSSOP10,.19,20 | 针数： | 10 |
| Reach Compliance Code： | compliant | HTS代码： | 8542.39.00.01 |
| 风险等级： | 1.67 | Samacsys Description： | Allegro Microsystems A4952ELYTR-T Motor Driver IC 2A 10-Pin, MSOP |
| 模拟集成电路 - 其他类型： | BRUSH DC MOTOR CONTROLLER | JESD-30 代码： | S-PDSO-G10 |
| JESD-609代码： | e3 | 长度： | 3 mm |
| 湿度敏感等级： | 2 | 功能数量： | 1 |
| 端子数量： | 10 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 最大输出电流： | 2 A |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | HTSSOP |
| 封装等效代码： | TSSOP10,.19,20 | 封装形状： | SQUARE |
| 封装形式： | SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 8/40 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.06 mm | 子类别： | Motion Control Electronics |
| 最大供电电压 (Vsup)： | 40 V | 最小供电电压 (Vsup)： | 8 V |
| 表面贴装： | YES | 技术： | DMOS |
| 温度等级： | INDUSTRIAL | 端子面层： | Matte Tin (Sn) |
| 端子形式： | GULL WING | 端子节距： | 0.5 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 40 |
| 宽度： | 3 mm | Base Number Matches： | 1 |
A4952ELYTR-T 数据手册
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PDF下载A4952 and A4953
Full-Bridge DMOS PWM Motor Drivers
Description
Features and Benefits
• Low RDS(on) outputs
Designed for pulse width modulated (PWM) control of DC
motors, the A4952 and A4953 are capable of peak output
currents to ±2 A and operating voltages to 40 V.
• Overcurrent protection (OCP)
▫ꢀMotorꢀshortꢀprotection
▫ꢀMotorꢀleadꢀshortꢀtoꢀgroundꢀprotection
▫ꢀMotorꢀleadꢀshortꢀtoꢀbatteryꢀprotection
• Low Power Standby mode
Inputterminalsareprovidedforuseincontrollingthespeedand
direction of a DC motor with externally applied PWM control
signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
• Adjustable PWM current limit
• Synchronous rectification
• Internal undervoltage lockout (UVLO)
• Crossover-current protection
• Fault output (A4952 only)
Internal circuit protection includes overcurrent protection,
motor lead short to ground or supply, thermal shutdown with
hysteresis, undervoltage monitoring of VBB, and crossover-
current protection.
• Selectable retry (A4952 only)
Packages:
TheA4952 is provided in a low-profile 10-pin MSOPpackage
(suffix LY) and the A4953 is provided in a low-profile
10-pin MSOP
with exposed thermal pad
8-pin SOICN package (suffix LJ). Both packages have an
exposedthermalpad,andarelead(Pb)free,with100%mattetin
leadframe plating.
(LY package)
8-pin SOICN
with exposed thermal pad
(LJ package)
Not to scale
Functional Block Diagram
Load
Supply
VBB
V
INT
Charge
Pump
A4952 only
RTRY
OSC
IN1
Control
Logic
Disable
OUT1
OUT2
IN2
TSD
UVLO
7V
GND
A4952 only
FLTn
LSS
VREF
÷
10
(Optional)
A4952-DS, Rev. 3
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Selection Guide
Part Number
Packing
4000 pieces per 13-in. reel
3000 pieces per 13-in. reel
A4952ELYTR-T
A4953ELJTR-T
Absolute Maximum Ratings
Characteristic
Symbol
VBB
Notes
Rating
40
Unit
V
Load Supply Voltage
Logic I/O Voltage Range
FLTn Sink Current
VIN
–0.3 to 6
10
V
IFLTN
VREF
VS
mA
V
VREF Input Voltage Range
Sense Voltage (LSS pin)
Motor Outputs Voltage
Output Current
–0.3 to 6
–0.5 to 0.5
–2 to 42
2
V
VOUT
IOUT
iOUT
V
Duty cycle = 100%
TW < 500 ns
A
Transient Output Current
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
6
A
TA
Temperature Range E
–40 to 85
150
°C
°C
°C
TJ(max)
Tstg
–55 to 150
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Value Unit
LJ package, on 4-layer PCB based on JEDEC standard
35
62
48
60
ºC/W
ºC/W
ºC/W
ºC/W
LJ package, on 2-layer PCB with 0.8 in2. 2-oz. copper each side
LY package, on 4-layer PCB based on JEDEC standard
Package Thermal Resistance
RθJA
LY package, (estimate) on 2-layer PCB with 1 in2. 2-oz. copper each side
*Additional thermal information available on the Allegro website.
Terminal List Table
Number
Pin-out Diagrams
Name
Function
A4952
A4953
GND
IN2
OUT2
LSS
1
2
3
4
8
7
6
5
FLTn
GND
IN1
1
10
4
–
1
3
2
7
6
8
–
–
5
4
Fault output, active low
Ground
PAD
IN1
OUT1
VBB
Logic input 1
Logic input 2
VREF
IN2
3
LJ Package (A4953)
LSS
8
Power return – sense resistor connection
DMOS full bridge output 1
OUT1
OUT2
PAD
7
FLTn
10
9
GND
OUT2
LSS
1
2
3
4
5
9
DMOS full bridge output 2
RTRY
IN2
8
PAD
–
Exposed pad for enhanced thermal dissipation
Logic input
IN1
7
OUT1
VBB
RTRY
VBB
2
VREF
6
6
Load supply voltage
VREF
5
Analog input
LY Package (A4952)
Allegro MicroSystems, LLC
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
ELECTRICAL CHARACTERISTICS Valid at TJ = 25°C, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
General
Load Supply Voltage Range
VBB
8
–
–
–
–
–
–
–
0.8
1.3
10
–
40
1.0
1.6
–
V
Ω
IOUT = |1.5 A|, TJ = 25°C
RDS(on) Sink + Source Total
RDS(on)
IOUT = |1.5 A|, TJ = 125°C
fPWM < 30 kHz
Ω
mA
µA
V
Load Supply Current
IBB
Low Power Standby mode
Source diode, If = –1.5 A
Sink diode, If = 1.5 A
10
1.5
1.5
–
Body Diode Forward Voltage
Vf
–
V
Logic I/O Inputs
VIN(1)
VIN(0)
INx pins
2.0
–
–
–
–
V
V
Logic Input Voltage Range
INx pins
0.8
0.4
–
VIN(STANDBY)
INx pins, Low Power Standby mode
–
–
V
Logic Input Pull-Down Resistance
Logic Input Current
R
R
R
V
=
0
V
=
I
N
1
=
I
N
2
–
50
40
16
250
kΩ
µA
µA
mV
L
O
G
I
C
(
P
D
)
I
N
IIN(1)
IIN(0
INx pins, VIN = 2.0 V
INx pins, VIN = 0.8 V
–
100
40
)
–
Input Hysteresis
VHYS
–
550
Logic I/O Inputs (A4952 only)
Retry Input Voltage
VRTRY
RTRY pin = valid
–
–
–
3
200
–
mV
V
Retry Overcurrent Protection Pullup
Voltage
VRTRY(OC) RTRY pin = open
Retry Short Circuit Current
Fault Output Voltage
Fault Output Leakage Current
Timing
IRTRY
VRST
ILK
RTRY pin = GND
–
–
–
10
–
–
0.5
1
µA
V
FLTn pin, IOUT = 1 mA
FLTn pin, no fault, pull-up to 5 V
–
µA
Crossover Delay
tCOD
50
0
400
–
500
5
ns
V
VREF Input Voltage Range
VREF
VREF / ISS, VREF = 5 V
VREF / ISS, VREF = 2.5 V
VREF / ISS, VREF = 1 V
9.5
9.0
8.0
2
–
10.5
10.0
10.0
4
V/V
V/V
V/V
µs
Current Gain
AV
–
–
Blank Time
tBLANK
toff
3
Constant Off-time
16
–
25
1
34
µs
Standby Timer
tst
IN1 = IN2 < VIN(STANDBY)
1.5
30
ms
µs
Power-Up Delay
tpu
–
–
Protection Circuits
UVLO Enable Threshold
UVLO Hysteresis
VBBUVLO VBB increasing
VBBUVLOhys
7
–
7.5
500
160
20
–
7.95
–
V
mV
°C
°C
A
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Overcurrent Protection Limit
Overcurrent Protection Pulse Width
TJTSD
TTSDhys
IOCP
Temperature increasing
Recovery = TJTSD – TTSDhys
–
–
–
–
2.5
1
6.5
4
tOCP
–
µs
Allegro MicroSystems, LLC
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Characteristic Performance
PWM Control Timing Diagram
VIN(1)
IN1
IN2
GND
VIN(1)
GND
+IREG
IOUT(x)
0 A
-IREG
Forward/
Reverse/
Forward/
Reverse/
Fast Decay
Fast Decay
Slow Decay
Slow Decay
PWM Control Truth Table
IN1
0
IN2
1
10×VS > VREF
OUT1
OUT2
Function
False
False
True
L
H
H
L
Reverse
Forward
1
0
0
1
H/L
L
L
Chop (mixed decay), reverse
1
0
True
H/L
L
Chop (mixed decay), forward
Brake (slow decay)
1
1
False
False
L
0
0
Z
Z
Coast, enters Low Power Standby mode after 1 ms
Note: Z indicates high impedance.
Allegro MicroSystems, LLC
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Functional Description
Device Operation
Overcurrent Protection
The A4952 and A4953 are designed to operate DC motors. The
output drivers are all low-RDS(on) , N-channel DMOS drivers
that feature internal synchronous rectification to reduce power
dissipation. The current in the output full bridge is regulated with
fixed off-time pulse width modulated (PWM) control circuitry.
The IN1 and IN2 inputs allow two-wire control for the bridge.
In the A4952, a current monitor will protect the IC from damage
due to output shorts. The internal Overcurrent Protection (OCP)
has the following features:
• Fault Output (FLTn pin). If a short is detected, the open drain
FLTn output signal goes low.
• Retry Input (RTRY pin). Sets the action taken by the IC to re-
spond to an OCP fault. If the RTRY pin is tied to GND, then the
outputs will be turned-on again after a 2-ms timeout, to check
if a fault condition remains. If the RTRY pin is left open, then
the fault will be latched, and the IC will disable the outputs. The
fault latch can only be cleared by coming out of Low Power
Standby mode or by cycling the power to VBB.
Protection circuitry includes internal thermal shutdown, and pro-
tection against shorted loads, or against output shorts to ground
or supply. Undervoltage lockout prevents damage by keeping the
outputs off until the driver has enough voltage to operate nor-
mally.
Standby Mode
Low Power Standby mode is activated when both input (INx)
pins are low for longer than 1 ms. Low Power Standby mode
disables most of the internal circuitry, including the charge pump
and the regulator. When the A4952/A4953 is coming out of
standby mode, the charge pump should be allowed to reach its
regulated voltage (a maximum delay of 30 µs) before any PWM
commands are issued to the device.
Note: The A4953 overcurrent protection behaves in the same
manner but the fault is latched and can only be reset by putting
the device into standby mode or by cycling the power to VBB.
During OCP events, Absolute Maximum Ratings may be
exceeded for a short period of time before the device latches.
Shutdown
Internal PWM Current Control
If the die temperature increases to approximately 160°C, the full
bridge outputs will be disabled until the internal temperature falls
below a hysteresis, TTSDhys , of 20°C. Internal UVLO is present
on VBB to prevent the output drivers from turning-on below the
UVLO threshold.
Initially, a diagonal pair of source and sink FET outputs are
enabled and current flows through the motor winding and the
optional external current sense resistor, RS. When the voltage
across RS equals the comparator trip value, then the current sense
comparator resets the PWM latch. The latch then turns off the
sink and source FETs (Mixed Decay mode).
Braking
VREF
The braking function is implemented by driving the device in
Slow Decay mode, which is done by applying a logic high to both
inputs, after a bridge-enable Chop command (see PWM Control
Truth Table). Because it is possible to drive current in both direc-
tions through the DMOS switches, this configuration effectively
shorts-out the motor-generated BEMF, as long as the Chop com-
mand is asserted. The maximum current can be approximated by
VBEMF / RL. Care should be taken to ensure that the maximum
ratings of the device are not exceeded in worse case braking situ-
ations: high speed and high-inertia loads.
The maximum value of current limiting is set by the selection of
RSx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by:
VREF
ITripMAX
=
AV
RS
where VREF is the input voltage on the VREF pin (V) and RS is
theꢀresistanceꢀofꢀtheꢀsenseꢀresistorꢀ(Ω)ꢀonꢀtheꢀLSSꢀterminal.ꢀꢀ
Allegro MicroSystems, LLC
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Synchronous Rectification
Mixed Decay Operation
When a PWM off-cycle is triggered by an internal fixed off-time
cycle, load current will recirculate. The A4952/A4953 synchro-
nous rectification feature turns-on the appropriate DMOSFETs
during the current decay, and effectively shorts out the body
diodes with the low RDS(on) driver. This significantly lowers
power dissipation. When a zero current level is detected, syn-
chronous rectification is turned off to prevent reversal of the load
current.
The bridges operate in Mixed Decay mode. Referring to the
lower panel of the figure below, as the trip point is reached, the
device goes into fast decay mode for 50% of the fixed off-time
period. After this fast decay portion the device switches to slow
decay mode for the remainder of the off-time. During transitions
from fast decay to slow decay, the drivers are forced off for the
Crossover Delay, tCOD . This feature is added to prevent shoot-
through in the bridge. During this “dead time” portion, synchro-
nous rectification is not active, and the device operates in fast
decay and slow decay only.
Mixed Decay Mode Operation
V
PHASE
+
0
–
See Enlargement A
I
OUT
Enlargement A
Fixed Off-Time, t = 25 µs
off
0.50 × t
0.50 × t
off
off
ITrip
I
OUT
Fast Decay
Slow Decay
t
t
t
COD
COD
COD
Allegro MicroSystems, LLC
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Application Information
thermal pad of the device makes a good location for the star
Sense Pin (LSS)
ground point. The exposed pad can be connected to ground for
this purpose.
In order to use PWM current control, a low-value resistor is
placed between the LSS pin and ground for current sensing pur-
poses. To minimize ground-trace IR drops in sensing the output
current level, the current sensing resistor should have an indepen-
dent ground return to the star ground point. This trace should be
as short as possible. For low-value sense resistors, the IR drops in
the PCB can be significant, and should be taken into account.
Layout
The PCB should have a thick ground plane. For optimum electri-
cal and thermal performance, the A4952/A4953 must be soldered
directly onto the board. On the underside of the A4952/A4953
package is an exposed pad, which provides a path for enhanced
thermal dissipation. The thermal pad must be soldered directly to
an exposed surface on the PCB in order to achieve optimal ther-
mal conduction. Thermal vias are used to transfer heat to other
layers of the PCB.
When selecting a value for the sense resistor be sure not to
exceed the maximum voltage on the LSS pin of ±500 mV at
maximum load. During overcurrent events, this rating may be
exceeded for short durations.
Ground
The load supply pin, VBB, should be decoupled with an electro-
lyticꢀcapacitorꢀ(typicallyꢀ100ꢀμF)ꢀinꢀparallelꢀwithꢀaꢀlowerꢀvaluedꢀ
ceramic capacitor placed as close as practicable to the device.
A star ground should be located as close to the A4952/ A4953
as possible. The copper ground plane directly under the exposed
Layout for the A4952 (LY package)
Solder
A4952
GND
GND
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.
OUT2
Thermal Vias
RS
OUT1
VBB
C1
A4952
GND
1
OUT2
LSS
FLTn
RTRY
IN2
C2
BULK
RS
C1
PAD
CAPACITANCE
OUT1
VBB
IN1
VREF
VBB
C2
GND
GND
Bill of Materials
Item
Reference
Value
Units
Description
0.25
2512, 1 W, 1% or better,
carbon film chip resistor
1
RS
Ω
(for VREF = 5 V, IOUT = 2 A)
2
3
C1
C2
0.22
100
µF
µF
X5R minimum, 50 V or greater
Electrolytic, 50 V or greater
Allegro MicroSystems, LLC
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Layout for the A4953 (LJ package)
Solder
A4953
GND
GND
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
OUT2
Thermal Vias
RS
A4953
OUT1
C1
1
GND
OUT2
LSS
C2
VBB
RS
C1
PAD
IN2
BULK
CAPACITANCE
OUT1
VBB
IN1
VREF
VBB
C2
GND
GND
Bill of Materials
Item
Reference
Value
Units
Description
0.25
2512, 1 W, 1% or better,
carbon film chip resistor
1
RS
Ω
(for VREF = 5 V, IOUT = 2 A)
2
3
C1
C2
0.22
100
µF
µF
X5R minimum, 50 V or greater
Electrolytic, 50 V or greater
Allegro MicroSystems, LLC
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Package LJ, 8-Pin SOICN
with exposed thermal pad
4.90 ±0.10
0.65
1.75
8°
0°
8
1.27
8
0.25
0.17
B
2.41 NOM
3.90 ±0.10 6.00 ±0.20
2.41 5.60
1.04 REF
A
1
2
2
1
1.27
0.40
3.30 NOM
3.30
PCB Layout Reference View
0.25 BSC
C
SEATING PLANE
GAUGE PLANE
Branded Face
C
8X
SEATING
PLANE
0.10
C
For Reference Only; not for tooling use (reference MS-012BA)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1.70 MAX
0.51
0.31
0.15
0.00
Terminal #1 mark area
A
B
1.27 BSC
Exposed thermal pad (bottom surface); dimensions may vary with device
C
Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, LLC
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Package LY, 10-Pin MSOP
with exposed thermal pad
0.50
0.30
1.65
10
3.00 ±0.10
0° to 6°
10
0.15 ±0.05
3.00 ±0.10
4.88 ±0.20
1.73 4.60
A
0.53 ±0.10
1
1
2
2
1
0.25
1.98
Seating Plane
1.98 MIN
Gauge Plane
C
For Reference Only; not for tooling use (reference JEDEC MO-187BA-T)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
B
1.73
A
B
C
Terminal #1 mark area
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351 SOP50P490X110-11M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
10
0.86 ±0.05
SEATING
PLANE
0.27
0.18
0.50
REF
0.05
0.15
Allegro MicroSystems, LLC
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Revision History
Revision
Revision Date
Description of Revision
Rev. 3
March 12, 2014
Update Electrical Characteristics table
Copyright ©2010-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
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1.508.853.5000; www.allegromicro.com
A4952ELYTR-T CAD模型
引脚图
封装焊盘图
A4952ELYTR-T 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| A4953 | ALLEGRO | Designed for pulse width modulated (PWM) control of DC motors, the A4952 and A4953 are capable of peak output currents to ±2 A and operating voltages to 40 V. | 获取价格 |
|
| A4953ELJ | SANKEN | Brush DC Motor Controller, PDSO8, SOP-8 | 获取价格 |
|
| A4953ELJTR-T | ALLEGRO | Brush DC Motor Controller, 2A, DMOS, PDSO8, LEAD FREE, MS-012BA, SOIC-8 | 获取价格 |
|
| A4954 | ALLEGRO | Dual Full-Bridge DMOS PWM Motor Driver | 获取价格 |
|
| A4954ELP-T | ALLEGRO | Dual Full-Bridge DMOS PWM Motor Driver | 获取价格 |
|
| A4954ELPTR-T | ALLEGRO | Dual Full-Bridge DMOS PWM Motor Driver | 获取价格 |
|
| A4957 | ALLEGRO | The A4957 is a full-bridge controller for use with external N-channel power MOSFETs and is specifically designed for applications with high-power inductive loads such as brush DC motors. | 获取价格 |
|
| A495P1 | ETC | TO CHANGE WITHOUT NOTICE ACCESSORIES | 获取价格 |
|
| A495P2 | ETC | TO CHANGE WITHOUT NOTICE ACCESSORIES | 获取价格 |
|
| A4960 | ALLEGRO | The A4960 is a three-phase, sensorless, brushless DC (BLDC) motor controller for use with external N-channel power MOSFETs and is specifically designed for automotive applications. | 获取价格 |
|
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