概述
规格参数
数据手册
替代型号A4983SET-T 概述
DMOS Microstepping Driver with Translator DMOS细分驱动器与翻译 电机驱动器 运动控制电子器件
A4983SET-T 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Obsolete |
| 零件包装代码： | QFN | 包装说明： | 5 X 5 MM, 0.90 MM HEIGHT, LEAD FREE, MO-220VHHD, QFN-28 |
| 针数： | 28 | Reach Compliance Code： | compliant |
| ECCN代码： | EAR99 | HTS代码： | 8542.39.00.01 |
| 风险等级： | 5.36 | Is Samacsys： | N |
| 模拟集成电路 - 其他类型： | STEPPER MOTOR CONTROLLER | JESD-30 代码： | S-XQCC-N28 |
| JESD-609代码： | e3 | 长度： | 5 mm |
| 湿度敏感等级： | 2 | 功能数量： | 1 |
| 端子数量： | 28 | 最高工作温度： | 85 °C |
| 最低工作温度： | -20 °C | 最大输出电流： | 2.5 A |
| 封装主体材料： | UNSPECIFIED | 封装代码： | HVQCCN |
| 封装等效代码： | LCC28,.2SQ,20 | 封装形状： | SQUARE |
| 封装形式： | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE | 峰值回流温度（摄氏度）： | 260 |
| 电源： | 35 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1 mm | 子类别： | Motion Control Electronics |
| 最大供电电流 (Isup)： | 5 mA | 最大供电电压 (Vsup)： | 5.5 V |
| 最小供电电压 (Vsup)： | 3 V | 标称供电电压 (Vsup)： | 35 V |
| 表面贴装： | YES | 技术： | BCDMOS |
| 温度等级： | COMMERCIAL EXTENDED | 端子面层： | Matte Tin (Sn) |
| 端子形式： | NO LEAD | 端子节距： | 0.5 mm |
| 端子位置： | QUAD | 处于峰值回流温度下的最长时间： | 40 |
| 宽度： | 5 mm | Base Number Matches： | 1 |
A4983SET-T 数据手册
通过下载A4983SET-T数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载A4983
DMOS Microstepping Driver with Translator
Features and Benefits
▪ Low RDS(ON) outputs
Description
The A4983 is a complete microstepping motor driver with
▪ Automatic current decay mode detection/selection
▪ Mixed and Slow current decay modes
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO
▪ Crossover-current protection
▪ 3.3 and 5 V compatible logic supply
▪ Very thin profile QFN package
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, eighth, and
sixteenth-step modes, with an output drive capacity of up to
35 V and ±2 A. The A4983 includes a fixed off-time current
regulator which has the ability to operate in Slow or Mixed
decay modes.
The translator is the key to the easy implementation of the
A4983. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
highfrequencycontrollines,orcomplexinterfacestoprogram.
The A4983 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
▪ Thermal shutdown circuitry
The chopping control in the A4983 automatically selects the
current decay mode (Slow or Mixed). When a signal occurs at
the STEP input pin, the A4983 determines if that step results
in a higher or lower current in each of the motor phases. If
the change is to a higher current, then the decay mode is set
to Slow decay. If the change is to a lower current, then the
current decay is set to Mixed (set initially to a fast decay for
a period amounting to 31.25% of the fixed off-time, then to a
Package: 28-pin QFN (suffix ET)
Continued on the next page…
Approximate size
Typical Application Diagram
VDD
0.22 μF
0.1 μF
0.1 μF
VBB
VREG
VDD
VCP CP1
CP2
VBB
VBB
OUT1A
MS1
Microcontroller or
Controller Logic
OUT1B
RS1
MS2
A4983
MS3
SLEEP
STEP
DIR
OUT2A
OUT2B
RS2
RESET
ENABLE
REF
ROSC
4983DS
A4983
DMOS Microstepping Driver with Translator
Description (continued)
slow decay for the remainder of the off-time). This current decay
control scheme results in reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
lockout (UVLO), and crossover-current protection. Special power-
on sequencing is not required.
The A4983 is supplied in a 5 mm × 5 mm × 0.90 nominal surface
mount QFN package with exposed thermal pad (suffix ET). The
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation. Internal circuit
protectionincludes:thermalshutdownwithhysteresis,undervoltage
package is lead (Pb) free (suffix –T), with 100% matte tin plated
leadframe.
Selection Guide
Part Number
A4983SET-T
A4983SETTR-T
Pb-free
Yes
Package
Packing
73 pieces per tube
28-pin QFN with exposed thermal pad
28-pin QFN with exposed thermal pad
Yes
1500 pieces per 7-in. reel
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
35
Units
V
Load Supply Voltage
VBB
±2
A
Output Current
IOUT
Duty Cycle < 20%
±2.5
A
Logic Input Voltage
Sense Voltage
V
–0.3 to 7
0.5
V
IN
VSENSE
VREF
V
Reference Voltage
4
V
Operating Ambient Temperature
Maximum Junction
TA
TJ(max)
Tstg
Range S
–20 to 85
150
ºC
ºC
ºC
Storage Temperature
–55 to 150
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.1 MF
0.22 MF
CP1
CP2
VREG
ROSC
VDD
REF
Current
Regulator
Charge
Pump
OSC
VCP
0.1 MF
DMOS Full Bridge
VBB1
DAC
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
SENSE1
VBB2
STEP
DIR
Gate
Drive
DMOS Full Bridge
RS1
RESET
Control
Logic
Translator
MS1
MS2
MS3
OUT2A
OUT2B
PWM Latch
Blanking
Mixed Decay
ENABLE
SLEEP
SENSE2
RS2
DAC
VREF
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
2
Characteristics
Output Drivers
Symbol
Test Conditions
Min.
Max.
Units
Typ.
Operating
8
0
–
–
–
35
35
V
V
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
VBB
VDD
During Sleep Mode
Operating
3.0
–
5.5
0.450
0.370
1.2
1.2
4
V
Source Driver, IOUT = –1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = –1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
0.350
Ω
RDSON
–
0.300
Ω
–
–
–
–
–
–
–
–
–
V
Body Diode Forward Voltage
Motor Supply Current
VF
–
V
–
mA
mA
μA
mA
mA
μA
IBB
Operating, outputs disabled
Sleep Mode
–
2
–
10
fPWM < 50 kHz
–
8
Logic Supply Current
IDD
Outputs off
–
5
Sleep Mode
–
10
Control Logic
VIN(1)
–
–
V
VDD×0.7
–
Logic Input Voltage
VIN(0)
IIN(1)
IIN(0)
–
V
VDD×0.3
–20
<1.0
<1.0
20
ꢀA
ꢀA
VIN = VDD×0.7
VIN = VDD×0.3
Logic Input Current
–20
20
Microstep Select 2
Microstep Select 3
Input Hysteresis
Blank Time
RMS2
RMS3
–
–
100
100
300
1
–
–
kΩ
kΩ
mV
μs
μs
μs
V
VHYS(IN)
tBLANK
150
0.7
20
23
0
500
1.3
40
37
4
OSC > 3 V
30
30
–
Fixed Off-Time
tOFF
ROSC = 25 kΩ
Reference Input Voltage Range
Reference Input Current
VREF
IREF
–3
–
0
3
μA
%
VREF = 2 V, %ITripMAX = 38.27%
VREF = 2 V, %ITripMAX = 70.71%
VREF = 2 V, %ITripMAX = 100.00%
–
±15
±5
±5
800
Current Trip-Level Error3
–
–
%
errI
tDT
–
–
%
Crossover Dead Time
Protection
100
475
ns
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
TJ
–
165
15
–
–
3
–
°C
°C
V
TJHYS
UVLO
UVHYS
–
VDD rising
2.35
0.05
2.7
0.10
V
1
2
Negative current is defined as coming out of (sourcing from) the specified device pin.
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3errI = (ITrip – IProg) ⁄ IProg, where IProg = %ITripMAX
I
.
×
TripMAX
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic
Symbol
Test Conditions*
Value Units
RθJA
Package Thermal Resistance
Package ET; 4-layer PCB, based on JEDEC standard
32 ºC/W
*In still air. Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
t
t
B
A
STEP
t
t
D
C
MS1, MS2, MS3,
RESET, or DIR
Time Duration
Symbol
Typ.
1
Unit
μs
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
tA
tB
tC
tD
1
μs
200
200
ns
ns
Figure 1. Logic Interface Timing Diagram
Table 1. Microstep Resolution Truth Table
MS1 MS2 MS3 Microstep Resolution Excitation Mode
L
H
L
L
L
L
L
L
L
H
Full Step
2 Phase
Half Step
1-2 Phase
H
H
H
Quarter Step
Eighth Step
Sixteenth Step
W1-2 Phase
2W1-2 Phase
4W1-2 Phase
H
H
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Functional Description
Device Operation. The A4983 is a complete microstepping Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one
increment. The translator controls the input to the DACs and
the direction of current flow in each winding. The size of the
increment is determined by the combined state of inputs MS1,
MS2, and MS3.
motor driver with a built-in translator for easy operation with
minimal control lines. It is designed to operate bipolar step-
per motors in full-, half-, quarter-, and sixteenth-step modes.
The currents in each of the two output full-bridges and all of
the N-channel DMOS FETs are regulated with fixed off-time
PWM (pulse width modulated) control circuitry. At each step,
the current for each full-bridge is set by the value of its external
Microstep Select (MS1, MS2, and MS3). Selects the
microstepping format, as shown in table 1. MS2 and MS3 have a
100 kΩ pull-down resistance. Any changes made to these inputs
current-sense resistor (RS1 and RS2), a reference voltage (VREF), do not take effect until the next STEP rising edge.
and the output voltage of its DAC (which in turn is controlled
If the MSx pins are pulled up to VDD, it is good practice to use a
by the output of the translator).
high value pull-up resistor in order to limit current to these pins,
should an overvoltage event occur.
At power-on or reset, the translator sets the DACs and the phase
current polarity to the initial Home state (shown in figures 2
through 6), and the current regulator to Mixed Decay Mode for
both phases. When a step command signal occurs on the STEP
input, the translator automatically sequences the DACs to the
next level and current polarity. (See table 2 for the current-level
sequence.) The microstep resolution is set by the combined
effect of inputs MS1, MS2, and MS3, as shown in table 1.
Direction Input (DIR). This determines the direction of
rotation of the motor. When low, the direction will be clockwise
and when high, counterclockwise. Changes to this input do not
take effect until the next STEP rising edge.
Internal PWM Current Control. Each full-bridge is
controlled by a fixed off-time PWM current control circuit
that limits the load current to a desired value, ITRIP. Initially, a
diagonal pair of source and sink FET outputs are enabled and
current flows through the motor winding and the current sense
resistor, RSx. When the voltage across RSx equals the DAC out-
put voltage, the current sense comparator resets the PWM latch.
The latch then turns off either the source FETs (when in Slow
Decay Mode) or the sink and source FETs (when in Mixed
Decay Mode).
When stepping, if the new output levels of the DACs are lower
than their previous output levels, then the decay mode for the
active full-bridge is set to Mixed. If the new output levels of
the DACs are higher than or equal to their previous levels, then
the decay mode for the active full-bridge is set to Slow. This
automatic current decay selection improves microstepping
performance by reducing the distortion of the current waveform
that results from the back EMF of the motor.
The maximum value of current limiting is set by the selection
of RSx and the voltage at the VREF pin. The transconductance
function is approximated by the maximum value of current
limiting, ITripMAX (A), which is set by
If the logic circuits are pulled up to VDD, it is good practice to
use a high value pull-up resistor in order to limit current to the
logic inputs, should an overvoltage event occur. Logic inputs
include: MSx, SLEEP, DIR, ENABLE, RESET, and STEP.
ITripMAX = VREF /(8 R )
×
S
where RS is the resistance of the sense resistor (Ω) and VREF is
the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current sense
comparator in precise steps, such that
RESET Input (RESET). The RESET input sets the trans-
lator to a predefined Home state (shown in figures 2 through
6), and turns off all of the FET outputs. All STEP inputs are
ignored until the RESET input is set to high.
Itrip = (%ITripMAX /100)
I
TripMAX
×
(See table 2 for %ITripMAX at each step.)
Allegro MicroSystems, Inc.
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4983 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The one shot off-time, tOFF, is deter-
mined by the selection of an external resistor connected from the
ROSC timing pin to ground. If the ROSC pin is tied to an external
voltage > 3 V, then tOFF defaults to 30 μs. The ROSC pin can be
safely connected to the VDD pin for this purpose. The value of
tOFF (μs) is approximately
Sleep Mode (SLEEP). To minimize power consumption when
the motor is not in use, this input disables much of the internal
circuitry including the output FETs, current regulator, and charge
pump. A logic low on the SLEEP pin puts the A4983 into Sleep
mode. A logic high allows normal operation, as well as start-up
(at which time the A4983 drives the motor to the Home microstep
position). When emerging from Sleep mode, in order to allow the
charge pump to stabilize, provide a delay of 1 ms before issuing a
Step command.
tOFF ≈ ROSC ⁄ 825
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current
control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, tBLANK (μs), is approximately
If the SLEEP pin is pulled up to VDD, it is good practice to use
a high value pull-up resistor in order to limit current to the pin,
should an overvoltage event occur.
tBLANK ≈ 1 μs
Mixed Decay Operation. The bridge can operate in Mixed
Decay mode, depending on the step sequence, as shown in figures
3 through 6. As the trip point is reached, the A4983 initially goes
into a fast decay mode for 31.25% of the off-time. tOFF. After that,
it switches to Slow Decay mode for the remainder of tOFF. A tim-
ing dagram for this feature appears on the next page.
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed–off-time cycle, load current recir-
culates according to the decay mode selected by the control logic.
This synchronous rectification feature turns on the appropriate
FETs during current decay, and effectively shorts out the body
diodes with the low FET RDS(ON). This reduces power dissipation
significantly, and can eliminate the need for external Schottky
diodes in many applications. Synchronous rectification turns off
when the load current approaches zero (0 A), preventing reversal
of the load current. A timing dagram for this feature appears on
the next page.
VREG (VREG). This internally-generated voltage is used
to operate the sink-side FET outputs. The VREG pin must be
decoupled with a 0.22 μF ceramic capacitor to ground. VREG
is internally monitored. In the case of a fault condition, the FET
outputs of the A4983 are disabled.
Enable Input (ENABLE). This input turns on or off all of the
FET outputs. When set to a logic high, the outputs are disabled.
When set to a logic low, the internal control enables the outputs as
required. The translator inputs STEP, DIR, MS1, MS2, and MS3,
as well as the internal sequencing logic, all remain active, indepen-
dent of the ENABLE input state.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Current Decay Modes Timing Chart
VPHASE
+
0
–
See Enlargement A
IOUT
Enlargement A
toff
tFD
tSD
IPEAK
IOUT
t
Symbol
toff
Characteristic
Device fixed off-time
Maximum output current
Slow decay interval
Fast decay interval
IPEAK
tSD
tFD
IOUT
Device output current
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Application Layout
A low impedance ground will prevent ground bounce during
high current operation and ensure that the supply voltage remains
stable at the input terminal. The recommended PCB layout shown
in the diagram below, illustrates how to create a star ground
under the device, to serve both as low impedance ground point
and thermal path.
Layout The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A4983 must be soldered directly onto the board. On the under-
side of the A4983 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB. Thermal vias
should not have any thermal relief and should be connected to
internal layers, if available, to maximize the dissipation area.
Solder
A4983
Trace (2 oz.)
Grounding In order to minimize the effects of ground bounce
and offset issues, it is important to have a low impedance single-
point ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the groundplane directly under the A4983, that area
becomes an ideal location for a star ground point.
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
RS1
RS2
C7
C9
VBB
C2
1
OUT2B
ENABLE
GND
CP1
OUT1B
A4983
PAD
NC
DIR
GND
REF
R3
C3
CP2
C4
R2
VCP
STEP
VDD
NC
VDD
C1
C8
R6
C6
R1
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
STEP
STEP
100.00
70.71
100.00
70.71
Slow
Mixed
Slow
Mixed
Slow
Mixed
Slow
Phase 1
IOUT1A
Phase 1
IOUT1A
0.00
0.00
Direction = H
(%)
Direction = H
(%)
–70.71
–70.71
–100.00
100.00
70.71
–100.00
100.00
70.71
Slow
Slow
Mixed
Slow
Mixed
Slow
Mixed
Phase 2
Phase 2
IOUT2A
IOUT2B
0.00
0.00
Direction = H
(%)
Direction = H
(%)
Slow
–70.71
–70.71
–100.00
–100.00
Figure 2. Decay Mode for Full-Step Increments
Figure 3. Decay Modes for Half-Step Increments
STEP
100.00
92.39
70.71
38.27
Phase 1
Slow
Mixed
Slow
Mixed
Slow
IOUT1A
0.00
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71
38.27
Slow
Phase 2
IOUT2B
Mixed
Slow
Mixed
Slow
Mixed
0.00
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
Figure 4. Decay Modes for Quarter-Step Increments
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
STEP
100.00
92.39
83.15
70.71
55.56
38.27
Phase 1
IOUT1A
19.51
Slow
Mixed
Slow
Mixed
0.00
Direction = H
(%)
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
100.00
92.39
83.15
70.71
55.56
38.27
Phase 2
IOUT2B
19.51
Mixed
Slow
Mixed
Slow
0.00
Direction = H
(%)
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
Figure 5. Decay Modes for Eighth-Step Increments
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
STEP
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
Phase 1
IOUT1A
Slow
Mixed
Slow
Mixed
0.00
–9.8
Direction = H
(%)
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
100.00
95.69
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.8
Slow
Phase 2
IOUT2B
Mixed
Slow
Mixed
Slow
0.00
–9.8
Direction = H
(%)
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–95.69
–100.00
Figure 6. Decay Modes for Sixteenth-Step Increments
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
13
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Phase 1
Current
tripMax
(%)
Phase 2
Current
tripMax
(%)
Phase 2
Current
tripMax
(%)
Phase 1
Current
tripMax
(%)
Full
Half
1/4
1/8
1/16
Step
Angle
(º)
Full
Half
1/4
1/8
1/16
Step
Angle
(º)
Step Step Step Step Step [% I
#
]
[% I
]
Step Step Step Step Step
#
[% I
]
[% I
]
#
#
#
#
#
#
#
#
1
1
1
1
100.00
99.52
98.08
95.69
92.39
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.80
0.00
9.80
0.0
5
9
17
33
–100.00
–99.52
–98.08
–95.69
–92.39
–88.19
–83.15
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.80
0.00
0.00
–9.80
180.0
185.6
191.3
196.9
202.5
208.1
213.8
219.4
225.0
230.6
236.3
241.9
247.5
253.1
258.8
264.4
270.0
275.6
281.3
286.9
292.5
298.1
303.8
309.4
315.0
320.6
326.3
331.9
337.5
343.1
348.8
354.4
2
5.6
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
2
3
3
19.51
29.03
38.27
47.14
55.56
63.44
70.71
77.30
83.15
88.19
92.39
95.69
98.08
99.52
100.00
99.52
98.08
95.69
92.39
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.80
11.3
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–92.39
–95.69
–98.08
–99.52
–100.00
–99.52
–98.08
–95.69
–92.39
–88.19
–83.15
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.80
4
16.9
2
3
4
5
6
7
8
5
22.5
10
11
12
13
14
15
16
6
28.1
4
7
33.8
8
39.4
1
2
3
4
5
9
45.0
3
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
50.6
6
56.3
61.9
7
67.5
73.1
8
78.8
84.4
9
0.00
90.0
–9.80
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–92.39
–95.69
–98.08
–99.52
95.6
9.80
10
11
12
13
14
15
16
101.3
106.9
112.5
118.1
123.8
129.4
135.0
140.6
146.3
151.9
157.5
163.1
168.8
174.4
19.51
29.03
38.27
47.14
55.56
63.44
70.71
77.30
83.15
88.19
92.39
95.69
98.08
99.52
2
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
14
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
Pin-out Diagram
OUT2B
ENABLE
GND
OUT1B
NC
1
2
3
4
5
6
7
21
20
19
18
17
16
15
DIR
CP1
GND
REF
CP2
VCP
STEP
VDD
NC
Terminal List Table
Name
CP1
Number
Description
4
5
Charge pump capacitor terminal
Charge pump capacitor terminal
Reservoir capacitor terminal
Regulator decoupling terminal
Logic input
CP2
VCP
6
VREG
MS1
8
9
MS2
10
11
Logic input
MS3
Logic input
RESET
ROSC
SLEEP
VDD
12
13
14
15
16
17
3, 18
19
21
22
23
24
26
27
28
1
Logic input
Timing set
Logic input
Logic supply
STEP
Logic input
REF
Gm reference voltage input
GND
Ground*
DIR
Logic input
OUT1B
VBB1
DMOS Full Bridge 1 Output B
Load supply
SENSE1
OUT1A
OUT2A
SENSE2
VBB2
Sense resistor terminal for Bridge 1
DMOS Full Bridge 1 Output A
DMOS Full Bridge 2 Output A
Sense resistor terminal for Bridge 2
Load supply
OUT2B
ENABLE
NC
DMOS Full Bridge 2 Output B
Logic input
2
7, 20, 25
–
No connection
PAD
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane
under the device.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
15
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983
DMOS Microstepping Driver with Translator
ET Package, 28-Pin QFN with Exposed Thermal Pad
5.15 .203
4.85 .191
A
B
28
All dimensions reference, not for tooling use
(reference JEDEC MO-220VHHD except contact length and exposed pad length and width)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
1
2
A
5.15 .203
4.85 .191
A
B
Terminal #1 mark area
Exposed thermal pad (terminal #1 identifier appearance
at supplier discretion)
C
Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V3M) except heel extended; adjust as
necessary to meet application process requirements and PCB
layout tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
C
28X
SEATING
PLANE
0.08 [.003]
C
0.30 .012
0.18 .007
28X
1.00 .039
0.80 .031
0.10 [.004] M
0.05 [.002] M
C
C
A B
0.20 .008
REF
0.50 .020
24X0.20 .008
0.05 .002
0.00 .000
MIN
0.30 .012
NOM
0.50 .020
NOM
4X0.20 .008
MIN
28
.008
4X0.20
MIN
1
2
0.56 .022
REF
3.15 .124
NOM
3.15 .124
NOM
B
.010
R0.25
REF
C
4.96 .195
NOM
2
1
5.0 .197
NOM
28
1.09 .043
REF
3.15 .124
NOM
3.15 .124
NOM
5.0 .197
NOM
4.96 .195
NOM
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.The information included herein is be-
lieved to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or
other rights of third parties which may result from its use.
Copyright ©2007, Allegro MicroSystems, Inc.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
16
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A4983SET-T 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| A4983SETTR-T | ALLEGRO | DMOS Microstepping Driver with Translator | 完全替代 |
|
A4983SET-T 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| A4983SETTR | ALLEGRO | Motion Control Electronic, BCDMOS, PQCC28, | 获取价格 |
|
| A4983SETTR-T | ALLEGRO | DMOS Microstepping Driver with Translator | 获取价格 |
|
| A4984 | ALLEGRO | DMOS Microstepping Driver with Translator and Overcurrent Protection | 获取价格 |
|
| A4984S | ALLEGRO | BIPOLAR STEPPING MOTOR DRIVER IC | 获取价格 |
|
| A4984SES-T | ALLEGRO | BIPOLAR STEPPING MOTOR DRIVER IC | 获取价格 |
|
| A4984SESTR-T | ALLEGRO | DMOS Microstepping Driver with Translator and Overcurrent Protection | 获取价格 |
|
| A4984SET-T | ALLEGRO | BIPOLAR STEPPING MOTOR DRIVER IC | 获取价格 |
|
| A4984SETTR-T | ALLEGRO | DMOS Microstepping Driver with Translator and Overcurrent Protection | 获取价格 |
|
| A4984SLP-T | ALLEGRO | BIPOLAR STEPPING MOTOR DRIVER IC | 获取价格 |
|
| A4984SLPLU-T | ALLEGRO | BIPOLAR STEPPING MOTOR DRIVER IC | 获取价格 |
|
A4983SET-T 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 5
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 8
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
