A4984SLPTR-T [ALLEGRO]
DMOS Microstepping Driver with Translator and Overcurrent Protection; DMOS细分驱动器与转换器和过流保护
| 型号： | A4984SLPTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | DMOS Microstepping Driver with Translator and Overcurrent Protection |
| 文件： | 总21页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A4984
DMOS Microstepping Driver with Translator
and Overcurrent Protection
Features and Benefits
▪ Low RDS(ON) outputs
Description
The A4984 is a complete microstepping motor driver with
▪ Automatic current decay mode detection/selection
▪ Mixed and Slow current decay modes
▪ Synchronous rectification for low power dissipation
▪ Internal UVLO
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, and eighth-step
modes. Step modes are selectable by MSx logic inputs. It has
an output drive capacity of up to 35 V and ±2 A. The A4984
includesafixedoff-timecurrentregulatorwhichhastheability
to operate in Slow or Mixed decay modes.
▪ Crossover-current protection
▪ 3.3 and 5 V compatible logic supply
▪ Thin profile QFN and TSSOP packages
▪ Thermal shutdown circuitry
▪ Short-to-ground protection
▪ Shorted load protection
The ET package meets customer requirements for no smoke
no fire (NSNF) designs by adding no-connect pins between
critical output, sense, and supply pins. So, in the case of a
pin-to-adjacent-pin short, the device does not cause smoke
or fire. Additionally, the device does not cause smoke or fire
when any pin is shorted to ground or left open.
▪ Low current Sleep mode, < 10 μA
▪ No smoke no fire (NSNF) compliance (ET package)
Packages:
The translator is the key to the easy implementation of the
A4984. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
highfrequencycontrollines,orcomplexinterfacestoprogram.
The A4984 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
Approximate size
24-contact QFN
with exposed thermal pad
4 mm × 4 mm × 0.75 mm
(ES package)
32-contact QFN
with exposed thermal pad
5 mm × 5 mm × 0.90 mm
(ET package)
During stepping operation, the chopping control in theA4984
automatically selects the current decay mode, Slow or Mixed.
24-pin TSSOP
with exposed thermal pad
(LP Package)
Continued on the next page…
Typical Application Diagram
VDD
0.1 μF
0.1 μF
0.22 μF
VREG ROSC CP1
VDD
CP2 VCP
VBB1
VBB2
0.22 μF
100 μF
5 kΩ
Microcontroller or
Controller Logic
SLEEP
STEP
OUT1A
A4984
OUT1B
SENSE1
MS1
MS2
DIR
OUT2A
ENABLE
RESET
OUT2B
SENSE2
VREF
GND
GND
4984-DS
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Description (continued)
In Mixed decay mode, the device is set initially to a fast decay for
a proportion of the fixed off-time, then to a slow decay for the
remainder of the off-time. Mixed decay current control results in
reduced audible motor noise, increased step accuracy, and reduced
power dissipation.
undervoltage lockout (UVLO), and crossover-current protection.
Special power-on sequencing is not required.
The A4984 is supplied in three surface mount packages: two QFN
packages, the 4 mm × 4 mm, 0.75 mm nominal overall height ES
package, and the 5 mm × 5 mm × 0.90 mm ET package. The LP
package is a 24-pin TSSOP. All three packages have exposed pads
for enhanced thermal dissipation, and are lead (Pb) free (suffix –T),
with 100% matte tin plated leadframes.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation. Internal
circuit protection includes: thermal shutdown with hysteresis,
Selection Guide
Part Number
A4984SESTR-T
A4984SETTR-T
A4984SLPTR-T
Package
Packing
1500 pieces per 7-in. reel
1500 pieces per 7-in. reel
4000 pieces per 13-in. reel
24-pin QFN with exposed thermal pad
32-pin QFN with exposed thermal pad
24-pin TSSOP with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Symbol
VBB
Notes
Rating
35
Units
V
Load Supply Voltage
Output Current
IOUT
±2
A
Logic Input Voltage
Logic Supply Voltage
VBBx to OUTx
V
–0.3 to 5.5
–0.3 to 5.5
35
V
IN
VDD
V
V
Sense Voltage
VSENSE
VREF
0.5
V
Reference Voltage
5.5
V
Operating Ambient Temperature
Maximum Junction
Storage Temperature
TA
Range S
–20 to 85
150
ºC
ºC
ºC
TJ(max)
Tstg
–55 to 150
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Functional Block Diagram
0.1 MF
0.22 MF
CP1
CP2
VREG
ROSC
VDD
REF
Current
Regulator
Charge
Pump
OSC
VCP
0.1 MF
DMOS Full Bridge
VBB1
DAC
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
OCP
SENSE1
VBB2
STEP
DIR
Gate
Drive
DMOS Full Bridge
RS1
RESET
Translator
Control
Logic
MS1
MS2
OUT2A
OUT2B
OCP
PWM Latch
Blanking
Mixed Decay
ENABLE
SLEEP
SENSE2
RS2
DAC
VREF
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
2
Characteristics
Output Drivers
Symbol
Test Conditions
Min.
Max.
Units
Typ.
Operating
8
0
–
–
–
35
35
5.5
430
430
1.3
1.3
4
V
V
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
VBB
VDD
During Sleep Mode
Operating
3.0
–
V
Source Driver, IOUT = –1.5 A
Sink Driver, IOUT = 1.5 A
Source Diode, IF = –1.5 A
Sink Diode, IF = 1.5 A
fPWM < 50 kHz
320
320
–
mꢀ
mꢀ
V
RDSON
–
–
Body Diode Forward Voltage
Motor Supply Current
VF
–
–
V
–
–
mA
mA
ꢁA
mA
mA
ꢁA
IBB
Operating, outputs disabled
Sleep Mode
–
–
2
–
–
10
8
fPWM < 50 kHz
–
–
Logic Supply Current
IDD
Outputs off
–
–
5
Sleep Mode
–
–
10
Control Logic
VIN(1)
–
–
V
VDD0.7
–
Logic Input Voltage
VIN(0)
IIN(1)
IIN(0)
–
V
VDD0.3
–20
<1.0
<1.0
20
μA
μA
VIN = VDD0.7
VIN = VDD0.3
MS1 pin
Logic Input Current
Microstep Select
–20
20
RMS1
RMS2
–
–
100
50
11
1
–
–
kꢀ
kꢀ
%
MS2 pin
Logic Input Hysteresis
Blank Time
VHYS(IN)
tBLANK
As a % of VDD
5
19
1.3
40
37
4
0.7
20
23
0
ꢁs
ꢁs
ꢁs
V
OSC = VDD or GND
30
30
–
Fixed Off-Time
tOFF
ROSC = 25 kꢀ
Reference Input Voltage Range
Reference Input Current
VREF
IREF
–3
–
0
3
ꢁA
%
VREF = 2 V, %ITripMAX = 38.27%
VREF = 2 V, %ITripMAX = 70.71%
VREF = 2 V, %ITripMAX = 100.00%
–
±15
±5
±5
800
Current Trip-Level Error3
–
–
%
errI
tDT
–
–
%
Crossover Dead Time
100
475
ns
Protection
Overcurrent Protection Threshold4
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VDD Undervoltage Lockout
VDD Undervoltage Hysteresis
IOCPST
TTSD
2.1
–
–
–
–
A
°C
°C
V
165
15
TTSDHYS
VDDUVLO
VDDUVLOHYS
–
–
VDD rising
2.7
–
2.8
90
2.9
–
mV
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
3VERR = [(VREF/8) – VSENSE] / (VREF/8).
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic
Symbol
Test Conditions*
Value Units
ES package; estimated, on 4-layer PCB, based on JEDEC standard
37 ºC/W
RθJA
Package Thermal Resistance
ET package; estimated, on 4-layer PCB, based on JEDEC standard
LP package; on 4-layer PCB, based on JEDEC standard
32 ºC/W
28 ºC/W
*In still air. Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, PD(max)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
20
40
60
80
100
120
140
160
180
Temperature (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
t
t
B
A
STEP
t
t
D
C
MSx
RESET, or DIR
Time Duration
Symbol
Typ.
1
Unit
ꢁs
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
Setup time, input change to STEP
Hold time, input change to STEP
tA
tB
tC
tD
1
ꢁs
200
200
ns
ns
Figure 1. Logic Interface Timing Diagram
Table 1. Microstep Resolution Truth Table
MS1 MS2 Microstep Resolution Excitation Mode
L
H
L
L
L
Full Step
2 Phase
Half Step
1-2 Phase
W1-2 Phase
2W1-2 Phase
H
H
Quarter Step
Eighth Step
H
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Functional Description
according to the ROSC configuration and the step sequence, as
shown in figures 8 through 11. During Mixed decay, when the trip
point is reached, the A4984 initially goes into a fast decay mode
for 31.25% of the off-time, tOFF. After that, it switches to Slow
decay mode for the remainder of tOFF. A timing diagram for this
feature appears on the next page.
Device Operation. The A4984 is a complete microstep-
ping motor driver with a built-in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, quarter-, and eighth-step modes.
The currents in each of the two output full-bridges and all of the
N-channel DMOS FETs are regulated with fixed off-time PWM
(pulse width modulated) control circuitry. At each step, the current
for each full-bridge is set by the value of its external current-sense Typically, mixed decay is only necessary when the current in the
resistor (RS1 and RS2), a reference voltage (VREF), and the output
voltage of its DAC (which in turn is controlled by the output of
the translator).
winding is going from a higher value to a lower value as determined
by the state of the translator. For most loads automatically-selected
mixed decay is convenient because it minimizes ripple when the
current is rising and prevents missed steps when the current is falling.
For some applications where microstepping at very low speeds is
necessary, the lack of back EMF in the winding causes the current to
increase in the load quickly, resulting in missed steps. This is shown
in figure 2. By pulling the ROSC pin to ground, mixed decay is set to
be active 100% of the time, for both rising and falling currents, and
prevents missed steps as shown in figure 3. If this is not an issue, it
is recommended that automatically-selected mixed decay be used,
because it will produce reduced ripple currents. Refer to the Fixed
Off-Time section for details.
At power-on or reset, the translator sets the DACs and the phase
current polarity to the initial Home state (shown in figures 8
through 11), and the current regulator to Mixed Decay Mode for
both phases. When a step command signal occurs on the STEP
input, the translator automatically sequences the DACs to the
next level and current polarity. (See table 2 for the current-level
sequence.) The microstep resolution is set by the combined effect
of the MSx inputs, as shown in table 1.
When stepping, if the new output levels of the DACs are lower
than their previous output levels, then the decay mode for the
active full-bridge is set to Mixed. If the new output levels of the
DACs are higher than or equal to their previous levels, then the
decay mode for the active full-bridge is set to Slow. This auto-
matic current decay selection improves microstepping perfor-
mance by reducing the distortion of the current waveform that
results from the back EMF of the motor.
Low Current Microstepping. Intended for applications
where the minimum on-time prevents the output current from
regulating to the programmed current level at low current steps.
To prevent this, the device can be set to operate in Mixed decay
mode on both rising and falling portions of the current waveform.
This feature is implemented by shorting the ROSC pin to ground.
In this state, the off-time is internally set to 30 μs.
Microstep Select (MSx). The microstep resolution is set by
the voltage on logic inputs MSx, as shown in table 1. The MS1 pin
has a 100 kΩ pull-down resistance, and the MS2 pin has a 50 kΩ
pull-down resistance. When changing the step mode the change
does not take effect until the next STEP rising edge.
¯¯¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯¯
Reset Input (RESET). The RESET input sets the translator
to a predefined Home state (shown in figures 8 through 11), and
turns off all of the FET outputs. All STEP inputs are ignored until
If the step mode is changed without a translator reset, and abso-
lute position must be maintained, it is important to change the
step mode at a step position that is common to both step modes in
order to avoid missing steps. When the device is powered down,
or reset due to TSD or an over current event the translator is set to
the home position which is by default common to all step modes.
¯¯¯¯¯¯¯¯¯
the RESET input is set to high.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one incre-
ment. The translator controls the input to the DACs and the direc-
tion of current flow in each winding. The size of the increment is
determined by the combined state of the MSx inputs.
Mixed Decay Operation. The bridge operates in Mixed
decay mode, at power-on and reset, and during normal running
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Slow
Decay
Mixed
Decay
Mixed
Decay
Mixed
Decay
Mixed
Decay
Slow
Decay
Slow
Decay
Slow
Decay
Missed
Step
Voltage on ROSC terminal 2 V/div.
Step input 10 V/div.
t → , 1 s/div.
Figure 2. Missed steps in low-speed microstepping
Mixed Decay
No Missed
Steps
ILOAD 500 mA/div.
t → , 1 s/div.
Step input 10 V/div.
Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Direction Input (DIR). This determines the direction of rota- Blanking. This function blanks the output of the current sense
tion of the motor. Changes to this input do not take effect until the comparators when the outputs are switched by the internal current
next STEP rising edge.
control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, tBLANK (μs), is approximately
Internal PWM Current Control. Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP. Initially, a diagonal pair
of source and sink FET outputs are enabled and current flows
through the motor winding and the current sense resistor, RSx.
When the voltage across RSx equals the DAC output voltage, the
current sense comparator resets the PWM latch. The latch then
turns off either the source FET (when in Slow decay mode) or the
sink and source FETs (when in Mixed decay mode).
tBLANK ≈ 1 μs
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is
shorted to ground, the driver will protect itself by sensing the
overcurrent event and disabling the driver that is shorted, protect-
ing the device from damage. In the case of a short-to-ground, the
The maximum value of current limiting is set by the selection of
¯¯¯¯¯¯¯¯
device will remain disabled (latched) until the SLEEP input goes
RSx and the voltage at the VREF pin. The transconductance func-
high or VDD power is removed. A short-to-ground overcurrent
event is shown in figure 4.
tion is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by
When the two outputs are shorted together, the current path is
through the sense resistor. After the blanking time (≈1 μs) expires,
the sense resistor voltage is exceeding its trip value, due to the
overcurrent condition that exists. This causes the driver to go into
a fixed off-time cycle. After the fixed off-time expires the driver
turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in figure 5.
ITripMAX = VREF /(8 R )
S
where RS is the resistance of the sense resistor (ꢀ) and VREF is
the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current sense
comparator in precise steps, such that
Itrip = (%ITripMAX /100)
I
TripMAX
×
If the driver is operating in Mixed decay mode, it is normal for
the positive current to spike, due to the bridge going in the for-
ward direction and then in the negative direction, as a result of the
direction change implemented by the Mixed decay feature. This
is shown in figure 6. In both instances the overcurrent circuitry is
protecting the driver and prevents damage to the device.
(See table 2 for %ITripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The off-time, tOFF, is determined by the
ROSC terminal. The ROSC terminal has three settings:
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
▪ ROSC tied to VDD — off-time internally set to 30 μs, decay
mode is automatic Mixed decay except when in full step where
decay mode is set to Slow decay
▪ ROSC tied directly to ground — off-time internally set to
30 μs, current decay is set to Mixed decay for both increasing
and decreasing currents, except in full step where decay mode
is set to Slow decay. (See Low Current Microstepping section.)
▪ ROSC through a resistor to ground — off-time is determined
by the following formula, the decay mode is automatic Mixed
decay for all step modes.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
VREG (VREG). This internally-generated voltage is used to oper-
ate the sink-side FET outputs. The VREG pin must be decoupled
with a 0.22 μF ceramic capacitor to ground. VREG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4984 are disabled.
tOFF ≈ ROSC ⁄ 825
Where tOFF is in μs.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
5 A / div.
Fault
latched
¯¯¯¯¯¯¯¯¯¯¯¯
Enable Input (ENABLE). This input turns on or off all of the
FET outputs. When set to a logic high, the outputs are disabled.
When set to a logic low, the internal control enables the outputs
as required. The translator inputs STEP, DIR, and MSx, as well as
the internal sequencing logic, all remain active, independent of the
¯¯¯¯¯¯¯¯¯¯¯¯
ENABLE input state.
t →
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4984 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Figure 4. Short-to-ground event
5 A / div.
¯¯¯¯¯¯¯¯¯¯
Sleep Mode ( SLEEP ). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator,
Fixed off-time
¯¯¯¯¯¯¯¯
and charge pump. A logic low on the SLEEP pin puts the A4984
into Sleep mode. A logic high allows normal operation, as well as
start-up (at which time the A4984 drives the motor to the Home
microstep position). When emerging from Sleep mode, in order
to allow the charge pump to stabilize, provide a delay of 1 ms
before issuing a Step command.
t →
Mixed Decay Operation. The bridge can operate in Mixed
Decay mode, depending on the step sequence, as shown in fig-
ures 8 through 11. As the trip point is reached, the A4984 initially
Figure 5. Shorted load (OUTxA → OUTxB) in
Slow decay mode
goes into a fast decay mode for 31.25% of the off-time, tOFF
.
After that, it switches to Slow Decay mode for the remainder of
tOFF. A timing diagram for this feature appears in figure 7.
5 A / div.
Fixed off-time
Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed-off time cycle, load current recircu-
lates according to the decay mode selected by the control logic.
This synchronous rectification feature turns on the appropriate
FETs during current decay, and effectively shorts out the body
diodes with the low FET RDS(ON). This reduces power dissipation
significantly, and can eliminate the need for external Schottky
diodes in many applications. Synchronous rectification turns off
when the load current approaches zero (0 A), preventing reversal
of the load current.
Fast decay portion
(direction change)
t →
Figure 6. Shorted load (OUTxA → OUTxB) in
Mixed decay mode
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
V
STEP
100.00
70.71
See Enlargement A
I
0
OUT
–70.71
–100.00
Enlargement A
t
off
t
FD
t
SD
I
PEAK
I
OUT
t
Symbol
toff
Characteristic
Device fixed off-time
Maximum output current
Slow decay interval
Fast decay interval
IPEAK
tSD
tFD
IOUT
Device output current
Figure 7. Current Decay Modes Timing Chart
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Application Layout
The two input capacitors should be placed in parallel, and as close
to the device supply pins as possible. The ceramic capacitor (C7)
should be closer to the pins than the bulk capacitor (C2). This
is necessary because the ceramic capacitor will be responsible
for delivering the high frequency current components.The sense
resistors, RSx, should have a very low impedance path to ground,
because they must carry a large current while supporting very
accurate voltage measurements by the current sense comparators.
Long ground traces will cause additional voltage drops, adversely
affecting the ability of the comparators to accurately measure the
current in the windings. The SENSEx pins have very short traces
to the RSx resistors and very thick, low impedance traces directly
to the star ground underneath the device. If possible, there should
be no other components on the sense circuits.
Layout. The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A4984 must be soldered directly onto the board. On the under-
side of the A4984 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A4984, that area becomes an ideal location for
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal.
Solder
A4984
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
OUT2B
OUT2A OUT1A
OUT1B
Thermal Vias
GND
R4
OUT2B
OUT1A
R5
OUT2A
R4
OUT1B
R5
C7
GND
OUT2B
OUT1B
DIR
U1
C7
ENABLE
GND
CP1
PAD
GND
REF
C3
C4
GND
C1
CP2
STEP
VDD
A4984
C6
VCP
C3
C4
C1
BULK
ROSC
GND
C2
CAPACITANCE
C6
C2
ROSC
VDD
VBB
VDD
VBB
ES package configuration shown
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
OUT2B
C6
C3
GND
U1
A4984
GND
CP1
C4
GND
C3
GND
ENABLE
CP2
OUT2A
OUT1A
OUT2B
VCP
C5
R4
R5
C4
C5
VBB2
C6
PAD
VREG
SENSE2
OUT2A
OUT1A
SENSE1
VBB1
ROSC
R4
R5
MS1
MS2
C1
GND
RESET
ROSC
ROSC
SLEEP
OUT1B
OUT1B
DIR
BULK
VDD
STEP
REF
GND
GND
GND
C1
GND
C2
GND
CAPACITANCE
C2
VDD
V
BB
VDD
VBB
LP package typical application and circuit layout
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
13
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Pin Circuit Diagrams
VDD
VBB
V
BB
VCP
CP1
CP2
8 V
40 V
GND
GND
GND
PGND
GND
8 V
GND
GND
GND
V
BB
V
BB
MSx
DIR
OUT
VREG
SENSE
V
REG
VREF
ROSC
SLEEP
DMOS
Parasitic
DMOS
Parasitic
8 V
10 V
GND
DMOS
Parasitic
GND
GND
GND
GND
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
14
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
STEP
STEP
100.00
70.71
100.00
Mixed*
70.71
Slow
Mixed
Slow
Mixed
Slow
Mixed
Slow
Phase 1
IOUT1A
Phase 1
IOUT1A
0.00
0.00
Direction = H
(%)
Direction = H
(%)
–70.71
–70.71
–100.00
100.00
70.71
–100.00
100.00
70.71
Mixed*
Slow
Slow
Mixed
Slow
Mixed
Slow
Mixed
Phase 2
Phase 2
IOUT2A
IOUT2B
0.00
0.00
Direction = H
(%)
Direction = H
(%)
Slow
–70.71
–70.71
–100.00
–100.00
*With ROSC pin tied to GND
DIR= H
DIR= H
Figure 8. Decay Mode for Full-Step Increments
Figure 9. Decay Modes for Half-Step Increments
STEP
100.00
92.39
70.71
Mixed*
38.27
Phase 1
Slow
Mixed
Slow
Mixed
Slow
IOUT1A
0.00
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
100.00
92.39
70.71
38.27
Mixed*
Slow
Phase 2
IOUT2B
Mixed
Slow
Mixed
Slow
Mixed
0.00
Direction = H
(%)
–38.27
–70.71
–92.39
–100.00
*With ROSC pin tied to GND
DIR= H
Figure 10. Decay Modes for Quarter-Step Increments
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
15
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
STEP
100.00
92.39
83.15
70.71
55.56
38.27
Mixed*
Phase 1
IOUT1A
19.51
Slow
Mixed
Slow
Mixed
0.00
Direction = H
(%)
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
100.00
92.39
83.15
70.71
55.56
38.27
Mixed*
Phase 2
IOUT2B
19.51
Mixed
Slow
Mixed
Slow
0.00
Direction = H
(%)
–19.51
–38.27
–55.56
–70.71
–83.15
–92.39
–100.00
*With ROSC pin tied to GND
DIR= H
Figure 11. Decay Modes for Eighth-Step Increments
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
16
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45º; DIR = H
Phase 1
Current
tripMax
(%)
Phase 2
Phase 2
Current
tripMax
(%)
Phase 1
Current
tripMax
(%)
Full
Half
1/4
1/8
Step
Angle
(º)
Full
Half
1/4
1/8
Step
Angle
(º)
Current
tripMax
Step Step Step Step [% I
#
]
[% I
]
Step Step Step Step
#
[% I
]
[% I
]
#
#
#
(%)
#
#
#
1
1
2
100.00
99.52
98.08
95.69
92.39
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.80
0.00
0.0
5
9
17
–100.00
–99.52
–98.08
–95.69
–92.39
–88.19
–83.15
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.80
0.00
0.00
–9.80
180.0
185.6
191.3
196.9
202.5
208.1
213.8
219.4
225.0
230.6
236.3
241.9
247.5
253.1
258.8
264.4
270.0
275.6
281.3
286.9
292.5
298.1
303.8
309.4
315.0
320.6
326.3
331.9
337.5
343.1
348.8
354.4
9.80
19.51
29.03
38.27
47.14
55.56
63.44
70.71
77.30
83.15
88.19
92.39
95.69
98.08
99.52
100.00
99.52
98.08
95.69
92.39
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.80
5.6
2
3
11.3
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–92.39
–95.69
–98.08
–99.52
–100.00
–99.52
–98.08
–95.69
–92.39
–88.19
–83.15
–77.30
–70.71
–63.44
–55.56
–47.14
–38.27
–29.03
–19.51
–9.80
16.9
2
3
4
5
6
7
8
22.5
10
11
12
13
14
15
16
28.1
4
33.8
39.4
1
2
3
4
5
45.0
3
6
7
8
50.6
6
56.3
61.9
7
67.5
73.1
8
78.8
84.4
9
0.00
90.0
–9.80
–19.51
–29.03
–38.27
–47.14
–55.56
–63.44
–70.71
–77.30
–83.15
–88.19
–92.39
–95.69
–98.08
–99.52
95.6
9.80
10
11
12
13
14
15
16
101.3
106.9
112.5
118.1
123.8
129.4
135.0
140.6
146.3
151.9
157.5
163.1
168.8
174.4
19.51
29.03
38.27
47.14
55.56
63.44
70.71
77.30
83.15
88.19
92.39
95.69
98.08
99.52
2
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
17
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
Pin-out Diagrams
ES Package
ET Package
LP Package
24 GND
CP1
CP2
1
2
3
4
5
6
7
8
9
23 ENABLE
22 OUT2B
21 VBB2
VCP
OUT2B
NC
OUT2B
OUT1B
DIR
1
2
3
4
5
6
18
17
16
15
14
13
1
2
3
4
5
6
7
8
24 OUT1B
23 NC
VREG
MS1
ENABLE
GND
CP1
20 SENSE2
19 OUT2A
18 OUT1A
17 SENSE1
16 VBB1
VBB2
NC
22 VBB1
21 NC
GND
REF
PAD
MS2
PAD
PAD
ENABLE
GND
CP1
20 DIR
RESET
ROSC
SLEEP
CP2
STEP
VDD
19 GND
18 REF
17 STEP
VCP
CP2
15 OUT1B
14 DIR
VDD 10
STEP 11
REF 12
13 GND
Terminal List Table
Number
Name
ES
Description
ET*
LP
CP1
CP2
DIR
4
5
7
1
2
Charge pump capacitor terminal
Charge pump capacitor terminal
Logic input
8
17
2
20
14
23
13, 24
5
¯¯¯¯¯¯¯¯¯¯¯¯
ENABLE
5
6, 19
Logic input
GND
MS1
MS2
3, 16
8
Ground
11
Logic input
9
12
6
Logic input
2, 4, 21, 23,
26, 28, 29, 31
NC
–
–
No connection
OUT1A
OUT1B
OUT2A
OUT2B
REF
21
18
22
1
27
24
30
1
18
15
19
22
12
7
DMOS Full Bridge 1 Output A
DMOS Full Bridge 1 Output B
DMOS Full Bridge 2 Output A
DMOS Full Bridge 2 Output B
15
10
11
20
23
12
14
19
24
6
18
13
14
25
32
15
17
22
3
Gm reference voltage input
¯¯¯¯¯¯¯¯¯¯
RESET
Logic input
ROSC
8
Timing set
SENSE1
SENSE2
17
20
9
Sense resistor terminal for Bridge 1
Sense resistor terminal for Bridge 2
Logic input
¯¯¯¯¯¯¯¯¯¯
SLEEP
STEP
VBB1
VBB2
VCP
11
16
21
3
Logic input
Load supply
Load supply
9
Reservoir capacitor terminal
VDD
VREG
PAD
13
7
16
10
–
10
4
Logic supply
Regulator decoupling terminal
–
–
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
18
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
ES Package, 24-Pin QFN with Exposed Thermal Pad
0.30
4.00 ±0.15
0.50
24
24
0.95
1
2
1
2
A
2.70
4.00 ±0.15
4.10
2.70
4.10
D
C
25X
SEATING
PLANE
C
PCB Layout Reference View
0.08
C
+0.05
–0.07
0.25
0.75 ±0.05
For Reference Only; not for tooling use (reference JEDEC MO-220WGGD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.50 BSC
A
B
Terminal #1 mark area
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C
Reference land pattern layout (reference IPC7351
QFN50P400X400X80-25W6M)
0.45 MAX
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
B
2.70
2
1
D
Coplanarity includes exposed thermal pad and terminals
24
2.70
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
19
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
ET Package, 32-Contact QFN with Exposed Thermal Pad
0.30
5.00 ±0.15
0.50
32
32
1.00
1
2
1
2
A
5.00 ±0.15
3.40
5.00
1
3.40
5.00
D
33X
C
SEATING
PLANE
0.08
C
0.25±0.10
0.90 ±0.10
C
PCB Layout Reference View
0.50 BSC
For Reference Only; not for tooling use
(reference JEDEC MO-220VHHD-6)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.50±0.10
A
B
Terminal #1 mark area
3.40
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
B
2
1
C
Reference land pattern layout (reference
IPC7351 QFN50P500X500X100-33V6M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
32
3.40
D
Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
20
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
and Overcurrent Protection
A4984
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
0.65
7.80 ±0.10
0.45
4° ±4
24
+0.05
0.15
–0.06
B
3.00
6.10
3.00 4.40 ±0.10 6.40 ±0.20
0.60 ±0.15
(1.00)
A
1
2
4.32
0.25
1.65
4.32
24X
C
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
C
PCB Layout Reference View
0.10
C
+0.05
–0.06
0.25
0.65
1.20 MAX
0.15 MAX
For Reference Only; not for tooling use
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Terminal #1 mark area
A
B
C
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright ©2008-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
21
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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