A6279EET-T [ALLEGRO]
Serial-Input Constant-Current Latched LED Drivers with Open LED Detection; 串行输入恒流锁存LED驱动器，具有LED开路检测
| 型号： | A6279EET-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Serial-Input Constant-Current Latched LED Drivers with Open LED Detection |
| 文件： | 总18页 (文件大小：652K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A6278 and A6279
Serial-Input Constant-Current Latched
LED Drivers with Open LED Detection
Features and Benefits
▪ 3.0 to 5.5 V logic supply range
Description
The A6278 and A6279 devices are specifically designed for
▪ Schmitt trigger inputs for improved noise immunity
▪ Power-On Reset (POR)
▪ Up to 90 mA constant-current sinking outputs
▪ LED open circuit detection
LED display applications. Each of these BiCMOS devices
includes a CMOS shift register, accompanying data latches,
and NPN constant-current sink drivers. The A6278 contains
8 sink drivers, while there are 16 in the A6279.
▪ Low-power CMOS logic and latches
▪ High data input rate
▪ 20 ns typical staggering delay on the outputs
▪ Internal UVLO and thermal shutdown (TSD) circuitry
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data-input rates can reach up to 25 MHz.
The LED drive current is determined by the user’s selection of
a single resistor.ACMOS serial data output permits cascading
between multiple devices in applications requiring additional
drivelines.OpenLEDconnectionscanbedetectedandsignaled
back to the host microprocessor through the SERIAL DATA
OUT pin.
Packages:
Fourpackagestylesareprovided:anMLP/QFNsurfacemount,
0.90 mm overall height nominal (A6279 only); a DIP(type A)
forthrough-holeapplications;andforleadedsurface-mount,an
SOIC (type LW) and a TSSOPwith exposed thermal pad (type
LP).All package styles for theA6278 are electrically identical
to each other, as are the A6279 package styles. All packages
are lead (Pb) free, with 100% matte tin plated leadframes.
28 pin MLP/QFN (suffix ET)
16 and 24 pin DIP (suffix A)
16 and 24 pin TSSOP (suffix LP)
16 and 24 pin SOIC (suffix LW)
Not to scale
Functional Block Diagram
LOGIC
SUPPLY
UVLO
SERIAL
DATA IN
VDD
CLOCK
VDD
SERIAL
DATA OUT
Serial - Parallel Shift Register
Latches
OUTPUT
ENABLE
Control Logic
Block
LATCH
ENABLE
Output Control Drivers and Open Circuit Detector
REXT
IO
GND
Regulator
Exposed Pad
(ET and LP packages)
OUT7 (A6278)
OUT15 (A6279)
OUT0 OUT1
VLED
6278-DS, Rev. 4
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Selection Guide
Part Number
Packing
25 pieces per tube
96 pieces per tube
4000 pieces per 13-in. reel
47 pieces per tube
Package Type
Terminals LED Drive Lines
A6278EA-T
DIP
A6278ELP-T
A6278ELPTR-T
A6278ELW-T
TSSOP with exposed thermal pad
16
8
SOICW
A6278ELWTR-T 1000 pieces per 13-in. reel
A6279EA-T
15 pieces per tube
DIP
A6279ELP-T
A6279ELPTR-T
A6279ELW-T
65 pieces per tube
TSSOP with exposed thermal pad
4000 pieces per 13-in. reel
31 pieces per tube
24
28
16
16
SOICW
A6279ELWTR-T 1000 pieces per 13-in. reel
A6279EET-T
73 pieces per tube
MLP surface mount
A6279EETTR-T
1500 pieces per 7-in. reel
Absolute Maximum Ratings
Parameter
Symbol
VDD
Conditions
Min. Typ. Max. Units
LOGIC SUPPLY Voltage Range
Load Supply Voltage Range
OUTx Current (any single output)
–
–0.5
–
–
–
–
–
–
7.0
17
V
VLED
IO
V
90
mA
mA
A6278
A6279
–
750
Ground Current
IGND
VI
–
1475 mA
VDD
+ 0.4
Logic Input Voltage Range
–0.4
V
Operating Temperature Range (E)
Junction Temperature
TA
TJ
TS
–40
–
–
–
–
85
°C
°C
°C
150
150
Storage Temperature Range
–55
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Pin-out Diagrams
Package A, LW, LP
24-pin
Package A, LW, LP
16-pin
24
23
22
21
20
19
18
17
16
15
14
13
GND
1
16 LOGIC SUPPLY
GND
SERIAL DATA IN
CLOCK
1
2
LOGIC SUPPLY
REXT
SERIAL DATA IN
CLOCK
2
3
4
5
6
7
8
15 REXT
14 SERIAL DATA OUT
13 OUTPUT ENABLE
12 OUT7
3
SERIAL DATA OUT
OUTPUT ENABLE
OUT15
LATCH ENABLE
OUT0
LATCH ENABLE
OUT0
4
EP
5
OUT1
11 OUT6
OUT1
6
OUT14
EP
10
9
7
OUT2
OUT5
OUT4
OUT2
OUT13
8
OUT3
OUT3
OUT12
9
OUT4
OUT11
10
11
OUT5
OUT10
Package ET
OUT6
OUT9
12
OUT7
OUT8
OUT11
OUT4
22
23
24
25
26
27
28
14
13
12
11
10
9
OUT12
OUT13
OUT3
OUT2
EP
OUT14
OUT1
OUT15
OUT0
OUTPUT ENABLE
NC
LATCH ENABLE
NC
8
Terminal List Table
Number
A, LW, LP
ET
Name
Function
A6278 A6279
A6279
1
2
3
4
1
2
3
4
5
6
7
9
GND
SERIAL DATA IN
CLOCK
Reference terminal for logic ground and power ground
Serial-data input to the shift-register
Clock input terminal; data is shifted on the rising edge of the clock.
Data strobe input terminal; serial data is latched with a high-level input
Current-sinking output terminals
LATCH ENABLE
OUTx
5 TO 12 5 TO 20 10 to 26
(Active low) Set low to enable output drivers; set high to turn OFF
(blank) all output drivers
13
14
21
22
27
1
OUTPUT ENABLE
SERIAL DATA OUT
CMOS serial-data output; for cascading to the next device (to that
device SERIAL DATA IN pin); for reading OCD bits.
An external resistor at this terminal establishes the output current for all
of the sink drivers.
15
16
–
23
24
–
2
3
REXT
LOGIC SUPPLY
(VDD) Logic supply voltage (typically 3.3 or 5.0 V)
No connection
4, 8, 18,
28
NC
EP
–
–
–
LP and ET packages only; exposed thermal pad for heat dissipation
Allegro MicroSystems, Inc.
3
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
OPERATING CHARACTERISTICS
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max
Unit
ELECTRICAL CHARACTERISTICS valid at TA = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
LOGIC SUPPLY Voltage Range
VDD
Operating
VDD = 0.0 → 5.0 V
3.0
2.4
2.15
64.2
34.1
4.25
–
–
5.0
–
–
5.5
2.85
2.55
86.8
45.9
5.75
+6.0
+6.0
+6.0
5.0
V
V
V
mA
mA
mA
%
%
%
μA
V
V
Undervoltage Lockout
VDD(UV)
V
DD = 5.0 → 0.0 V
VCE = 0.7 V, REXT = 225 Ω
VCE = 0.7 V, REXT = 470 Ω
VCE = 0.6 V, REXT = 3900 Ω
VCE(A) = VCE(B) = 0.7 V, REXT = 225 Ω
75.5
40.0
5.0
+1.0
+1.0
+1.0
1.0
–
–
–
–
–
Output Current (any single output)
IO
Output Current Matching (difference between any two
ΔIO
V
CE(A) = VCE(B) = 0.7 V, REXT = 470 Ω
outputs at the same VCE
Output Leakage Current
Logic Input Voltage
)
VCE(A) = VCE(B) = 0.6 V, REXT = 3900 Ω
VOH = 15 V
–
–
ICEX
VIH
VIL
VIhys
VOL
VOH
0.7VDD
GND
200
–
VDD
0.3VDD
400
0.4
Logic Input Voltage Hysteresis
SERIAL DATA OUT Voltage
All digital inputs
IOL = 500 μA
IOH = –500 μA
mV
V
V
VDD–0.4
–
OUTPUT ENABLE input, Pull Up
LATCH ENABLE input, Pull Down
REXT = open, VOE = 5 V
150
100
–
–
–
–
–
–
–
300
200
–
–
–
–
–
–
600
400
1.4
5.0
8.0
kΩ
kΩ
mA
mA
mA
mA
mA
mA
°C
°C
V
Input Resistance
RI
IDD(OFF) REXT = 470 Ω, VOE = 5 V
REXT = 225 Ω, VOE = 5 V
LOGIC SUPPLY Current
REXT = 3900 Ω, VOE = 0 V
3.0
IDD(ON)
REXT = 470 Ω, VOE = 0 V
18.0
32.0
–
–
–
REXT = 225 Ω, VOE = 0 V
Temperature increasing
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Open LED Detection Threshold
TJTSD
TJTSDhys
165
15
0.30
–
–
VCE(ODC) IO > 5 mA, VCE ≥ 0.6 V
SWITCHING CHARACTERISTICS valid at TA = 25°C, VDD = VIH = 3.0 to 5.5 V, VCE = 0.7 V, VIL = 0 V, REXT = 470 Ω, IO = 40 mA, VLED = 3 V, RLED
=
58 Ω, CLED = 10 pF, unless otherwise noted
CLOCK Pulse Width
SERIAL DATA IN Setup Time
SERIAL DATA IN Hold Time
LATCH ENABLE Setup Time
LATCH ENABLE Hold Time
OUTPUT ENABLE Set Up Time
OUTPUT ENABLE Hold Time
OUTPUT ENABLE Pulse Width
CLOCK to SERIAL DATA OUT Propagation Delay Time
OUTPUT ENABLE to OUT0 Propagation Delay Time
Staggering Delay (between consecutive outputs)
Total Delay Time (15 × tD)
CLOCK Pulse Width
SERIAL DATA IN Setup Time
SERIAL DATA IN Hold Time
LATCH ENABLE Setup Time
LATCH ENABLE Hold Time
OUTPUT ENABLE Set Up Time
OUTPUT ENABLE Hold Time
OUTPUT ENABLE Pulse Width*
CLOCK to SERIAL DATA OUT Propagation Delay Time
OUTPUT ENABLE to OUT0 Propagation Delay Time
Staggering Delay (between consecutive outputs)
Total Delay Time (15 × tD)
thigh, tlow
tSU(D)
tH(D)
20
10
10
20
20
40
20
600
30
–
–
–
–
–
–
–
–
–
–
75
20
300
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
40
–
–
–
–
–
–
–
–
–
–
–
40
–
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
tSU(LE)
tH(LE)
tSU(OE)
tH(OE)
tW(OE)
tP(DO)
tP(OE)
tD
Normal Mode
10
–
tDtotal
t
high, tlow
tSU(D)
tH(D)
20
20
20
40
20
40
20
2.0
30
–
tSU(LE)
tH(LE)
tSU(OE)
tH(OE)
tW(OE)
tP(DO)
tP(OE)
tD
Test Mode, VDD = 4.5 to 5.5 V
–
–
75
20
300
75
75
10
–
–
tDtotal
tf
tr
Output Fall Time
Output Rise Time
90% to 10% voltage
10% to 90% voltage
–
*See LED Open Circuit Detection (Test) mode timing diagram.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Truth Table
Serial
Clock
Data
Input
Shift Register Contents
Serial
Data
Out
Latch
Enable
Input
Latch Contents
I0 I1 I2 In-1 In
Output
Enable
Input
Output Contents
I0 I1 I2 In-1 In
Input
I0 I1 I2
…
In-1 In
Rn-2 Rn-1
Rn-2 Rn-1
Rn-1 Rn
…
…
H
H
L
R0 R1
R0 R1
…
Rn-1
Rn-1
Rn
L
…
…
X
R0 R1 R2
X
X
X
…
…
X
X
X
L
R0 R1 R2
P0 P1 P2
…
Rn-1 Rn
Pn-1 Pn
P0 P1 P2
Pn-1 Pn
Pn
H
…
…
L
P0 P1 P2
…
Pn-1 Pn
X
X
X
X
X
H
H
H
H
…
H
H
L = Low logic (voltage) level
H = High logic (voltage) level
X = Don’t care
P = Present state
R = Previous state
n = 7 for the A6278, n = 15 for the A6279
Inputs and Outputs Equivalent Circuits
V
V
V
V
DD
DD
DD
DD
IN
IN
LINE
OUT
OUTPUT ENABLE
(active low)
CLOCK and
SERIAL DATA IN
LATCH ENABLE
SERIAL DATA OUT
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Normal Mode Timing Requirements
0
1
n
CLOCK
thigh
t
low
SERIAL
DATA IN
SDI n
tSU(D) tH(D)
SDI n-1
SDI 0
SERIAL
DATA OUT
SDO n
Don't Care
tp(DO)
LATCH
ENABLE
A6278, n = 7
A6279, n = 15
tSU(LE) tH(LE)
tW(OE)
OUTPUT
ENABLE
tW(OE)
tSU(OE)
OUT0
OUT1
Don't Care
Don't Care
Don't Care
tP( O E )
tP( O E )
Logic Levels: VDD and GND
tD
tD
OUTn
tD(Total)
tD(Total)
LED Open Circuit Detection (Test) Mode Timing Requirements
(A) To enter LED OCD mode, a minimum of one CLOCK pulse is required after LATCH ENABLE is brought back low.
CLOCK
1
thigh tlow
OUTPUT
ENABLE
tSU(OE1)
tH(OE1)
LATCH
ENABLE
tSU(LE1)
tH(LE1)
(B) To output the latched error code, OUTPUT ENABLE must be held low a minimum of 3 CLOCK cycles.
3
2
CLOCK
1
tW(OE1)
OUTPUT
ENABLE
A6278, n = 7
A6279, n = 15
SERIAL
DATA OUT
SDO n
SDO n-1 SDO n-2
SDO 0
Don't Care
(C) When returning to Normal mode, a minimum of three CLOCK pulses is required after OUTPUT ENABLE is brought back high.
1
2
3
CLOCK
thigh tlow
OUTPUT
ENABLE
tSU(OE1)
tH(OE1)
Logic Levels: VDD and GND
LATCH
ENABLE
Allegro MicroSystems, Inc.
6
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Functional Description
Open circuit detection does not take place until the sequence in
Normal Mode
Panel B on page 7 is performed. During this sequence, the OE
pin must be held low for a minimum of 2 μs (tW(OE1)) to ensure
proper settling of the output currents and be given a minimum of
three CLOCK pulses. During the period that the OE pin is low
(active), OCD testing begins. The VCE voltage on each of the
output pins is compared to the Open LED Detection Theshold,
VCE(OCD). If the VCE of an enabled output is lower than VCE(OCD)
an error bit value of 0 is set in the corresponding shift register. A
value of 1 will be set if no error is detected. If a particular output
is not enabled, a 0 will be set. The error codes are summarized in
the following table:
Serial data present at the SERIAL DATA IN input is transferred
to the shift register on the logic 0-to-logic 1 transition of the
CLOCK input pulse. On succeeding CLOCK pulses, the register
shifts data towards the SERIAL DATA OUT pin. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
,
Data present in any register is transferred to the respective latch
when the LATCH ENABLE input is high (serial-to-parallel con-
version). The latches continue to accept new data as long as the
LATCH ENABLE input is held high.
Applications where the latches are bypassed (LATCH ENABLE
tied high) will require that the OUTPUT ENABLE input be high
during serial data entry. When the OUTPUT ENABLE input is
high, the output sink drivers are disabled (OFF).
Output State Test Condition Error Code Meaning
Output State
Test Condition Error Code
Meaning
N/A
OFF
N/A
0
0
1
V
CE < VCE(OCD)
Open/TSD
Normal
ON
The data stored in the latches is not affected by the OUTPUT
ENABLE input. With the OUTPUT ENABLE input active (low),
the outputs are controlled by the state of their respective latches.
VCE ≥ VCE(OCD)
LED Open Circuit Detection (Test) Mode
After the testing process, setting the OE pin high causes the shift
registers to latch the error code data where it can then be clocked
out of the SERIAL DATA OUT pin. The OCD latching sequence
(OE low, 3 CLOCK pulses, OE high as shown in panel B of the
LED OCD timing diagram) can then be repeated if necessary to
look for intermittent contact problems.
The LED Open Circuit Detection (OCD) mode, or Test mode,
is entered by clocking in the LED OCD mode initialization
sequence on the OUTPUT ENABLE (OE) and LATCH ENABLE
(LE) pins. In Normal mode, the OE and LE pins do not change
states while the CLOCK signal is cycling. The initialization
sequence is shown in panel A of the LED OCD timing require-
ments diagram on page 7.
The state of the outputs can be programmed with new data at any
time while in LED OCD mode (the same as in Normal mode).
This allows specific patterns to be tested for open circuits. The
pattern that is latched will then be tested during the OCD latching
sequence and the resulting bit values can be clocked out of the
SERIAL DATA OUT pin.
Note: Each step event during mode sequencing happens on the
leading edge of the CLOCK signal. Five step events (CLOCK
pulses) are required to enter OCD mode and five step events are
required to return to Normal mode.
A pattern, such as all highs, should first be loaded into the reg-
isters and latched leaving LE low. The device is then sequenced
into LED OCD mode. It should be noted that data is still being
sent through the shift registers while entering the LED OCD
mode. However, this data is not latched when the LE pin goes
high and sees a CLOCK pulse during the initialization sequence.
Note: LED Open Circuit Detection will not work properly if the
current is being externally limited by resistors to within the set
current limit for the device.
To return to Normal mode, perform the clocking sequence shown
in panel C of the timing diagram on the OE and LE pins.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
affect LED current. The output current is determined by the value
Constant Current (REXT
)
of an external current-control resistor (REXT). The relationship of
these parameters is shown in figure 1. Typical characteristics for
output current and VCE are shown in figure 2 for common values
The A6278 and A6279 allow the user to set the magnitude of
the constant current to the LEDs. Once set, the current remains
constant regardless of the LED voltage variation, the supply
voltage variation, or other circuit parameters that could otherwise
of REXT
.
Figure 1. Output Current versus Current Control Resistance
TA= 25°C, VCE = 0.7 V
90
80
70
60
50
40
30
20
10
0
1
00
2
0
0
3
0
0
5
0
0
7
0
0
1k
2k
3
k
5k
REXT (Ω)
Figure 2. Output Current versus Device Voltage Drop
TA= 25°C
90
80
70
60
50
40
30
20
10
0
REXT = 225 Ω
REXT = 470 Ω
REXT = 3900 Ω
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
VCE (V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
The 20 ns delays are cumulative across all the outputs. Under any
Undervoltage Lockout
of the above conditions, the state of OUT0 gets set after a typical
propagation delay, tP(OE). OUT1 will get set 20 ns after OUT0,
and so forth. In the A6279, OUT15 will get set after 300 ns (15 ×
The A6278 and A6279 include an internal under-voltage lockout
(UVLO) circuit that disables the outputs in the event that the
logic supply voltage drops below a minimum acceptable level.
This feature prevents the display of erroneous information, a
necessary function for some critical applications.
20 ns) plus tP(OE)
.
Note: The maximum CLOCK frequency is reduced in applica-
tions where both the OUTPUT ENABLE pin is held low and the
LATCH ENABLE pin is held high continuously, and the outputs
change state on the CLOCK edges. The staggering delay could
cause spurious output responses at CLOCK speeds greater than
1 MHz.
Upon recovery of the logic supply voltage after a UVLO event,
and on power-up, all internal shift registers and latches are set
to 0. The A6278/A6279 is then in Normal mode.
Output Staggering Delay
The A6278/A6279 has a 20 ns delay between each output. The
staggering of the outputs reduces the in-rush of currents onto the
power and ground planes. This aids in power supply decoupling
and EMI/EMC reduction.
Thermal Shutdown
When the junction temperature of the A6278/A6279 reaches the
thermal shutdown temperature threshold, TJTSD (165°C typical),
the outputs are shut off until the junction temperature cools down
below the recovery threshold, TJTSD– TJTSDhys (15°C typical).
The shift register and output latches will remain active during
a TSD event. Therefore, there is no need to reset the data in the
output latches.
The output staggering delay occurs under the following condi-
tions:
• OUTPUT ENABLE is pulled low
• OUTPUT ENABLE is held low and LATCH ENABLE is
pulled high
In LED OCD mode, if the junction temperature reaches the Ther-
mal Shut Down threshold, the outputs will turn off, as in Normal
mode operation. However, all of the shift registers will be set
with 0, the error bit value.
• OUTPUT ENABLE is held low, LATCH ENABLE is held high,
and CLOCK is pulled high
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Application Information
Load Supply Voltage (VLED
)
Pattern Layout
These devices are designed to operate with driver voltage
drops (VCE) of 0.7 to 3V, with an LED forward voltage, VF , of
1.2 to 4.0 V. If higher voltages are dropped across the driver,
package power dissipation will increase significantly. To mini-
mize package power dissipation, it is recommended to use the
lowest possible load supply voltage, VLED, or to set any series
voltage dropping, VDROP, according to the following formula:
This device has a common logic ground and power ground
terminal, GND. For the LP package, the GND pin should be tied
to the exposed metal pad, EP, allowing the ground plane copper
to be used to dissipate heat. If the ground pattern layout contains
large common mode resistance, and the voltage between the
system ground and the LATCH ENABLE, OUTPUT ENABLE,
or CLOCK terminals exceeds 2.5 V (because of switching noise),
these devices may not work properly.
VDROP = VLED – VF – VCE,
Package Power Dissipation (PD)
The maximum allowable package power dissipation based on
package type is determined by:
with VDROP = IO×RDROP for a single driver or for a Zener diode
(VZ), or for a series string of diodes (approximately 0.7 V per
diode) for a group of drivers (see figure 3). If the available volt-
age source, VLED, will cause unacceptable power dissipation and
series resistors or diodes are undesirable, a voltage regulator can
be used to provide supply voltages.
PD(max) = (150 – TA) / RθJA
,
where RθJA is the thermal resistance of the package, determined
experimentally. Power dissipation levels based on the package
are shown in the Package Thermal Characteristics section (see
page 14).
For reference, typical LED forward voltages are:
The actual package power dissipation is determined by:
PD(act) = DC ×(VCE ×IO×16) + (VDD×IDD),
LED Type
White
VF (V)
3.5 to 4.0
3.0 to 4.0
where DC is the duty cycle. The value 16 represents the maxi-
mum number of available device outputs for the A6279, used for
the worst-case scenario (displaying all 16 LEDs; this would be 8
for the A6278).
Blue
Green
Yellow
Amber
Red
1.8 to 2.2
2.0 to 2.1
1.9 to 2.65
1.6 to 2.25
1.2 to 1.5
When the load suppy voltage, VLED, is greater than 3 to 5 V, and
PD(act) > PD(max), an external voltage reducer (VDROP) must be
used (see figure 3).
Infrared
Reducing the percent duty cycle, DC, will also reduce power dis-
sipation. Typical results are shown on the following pages.
V
V
V
LED
LED
LED
V
V
V
DROP
DROP
DROP
V
F
V
F
V
F
V
V
V
CE
CE
CE
Figure 3. Typical appplications for voltage drops
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Allowable Output Current versus Duty Cycle, A6278
VDD = 5 V
A Package, T = 25°C
A Package, T = 50°C
A
A Package, T = 85°C
A
A
90
90
90
0
0
0
0
100
0
100
0
100
DC (%)
DC (%)
DC (%)
LP Package, T = 25°C
A
LP Package, T = 50°C
A
LP Package, T = 85°C
A
90
90
90
0
0
0
0
100
0
100
0
100
DC (%)
DC (%)
DC (%)
LW Package, T = 25°C
A
LW Package, T = 50°C
A
LW Package, T = 85°C
A
90
90
90
0
0
0
0
100
0
100
0
100
DC (%)
DC (%)
DC (%)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Allowable Output Current versus Duty Cycle, A6279
VDD = 5 V
A Package, T = 25°C
A Package, T = 50°C
A
A Package, T = 85°C
A
A
90
90
90
0
0
0
0
100
0
100
0
100
DC (%)
DC (%)
DC (%)
LP Package, T = 25°C
A
LP Package, T = 50°C
A
LP Package, T = 85°C
A
90
90
90
0
0
0
0
100
0
100
0
100
DC (%)
DC (%)
DC (%)
LW Package, T = 25°C
A
LW Package, T = 50°C
A
LW Package, T = 85°C
A
90
90
90
0
0
0
0
100
0
100
0
100
DC (%)
DC (%)
DC (%)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package Thermal Characteristics
Characteristic
Symbol
Test Conditions*
Value Unit
A package, 16-pin, measured on 4-layer board based on JEDEC standard
A package, 24-pin, measured on 4-layer board based on JEDEC standard
LP package, 16-pin, measured on 4-layer board based on JEDEC standard
38
26
34
28
48
44
32
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Package Thermal Resistance
RθJA LP package, 24-pin, measured on 4-layer board based on JEDEC standard
LW package, 16-pin, measured on 4-layer board based on JEDEC standard
LW package, 24-pin, measured on 4-layer board based on JEDEC standard
ET package, 24-pin, measured on 4-layer board based on JEDEC standard
*Additional thermal information is available on the Allegro Web site.
A6278
A6279
5.0
5.0
4.0
3.0
2.0
1.0
0
4.0
3.0
2.0
1.0
0
25
50
75
100
125
150
25
50
75
100
125
150
Ambient Temperature, TA (°C)
Ambient Temperature, TA (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
13
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package A, 16-pin DIP (A6278)
.775 19.69
.735 18.67
A
.014 0.36
.008 0.20
B
16
.430 10.92
MAX
.280 7.11
.240 6.10
.300 .7.62
A
1
2
.195 4.95
.115 2.92
C
SEATING
PLANE
.015 0.38
MIN
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 BB)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
.005 0.13
MIN
.100 .2.54
.150 3.81
.115 2.92
.070 1.78
.045 1.14
.022 .056
16X
.014 .036
A
Terminal #1 mark area
.010 [0.25] M
C
Package A, 24-pin DIP (A6279)
1.280 32.51
1.230 31.24
A
.014 0.36
.008 0.20
B
24
.430 10.92
MAX
.280 7.11
.240 6.10
.300 .7.62
A
1
2
.195 4.95
.115 2.92
C
SEATING
PLANE
.015 0.38
MIN
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 AF)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
.005 0.13
MIN
.100 .2.54
.150 3.81
.115 2.92
.070 1.78
.045 1.14
.022 .056
.014 .036
24X
A
Terminal #1 mark area
.010 [0.25] M
C
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
14
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package LP, 16-pin TSSOP with Exposed Thermal Pad (A6278)
5.10 .201
4.90 .193
8º
0º
A
16
B
0.20 .008
0.09 .004
4.5 .177
4.3 .169
B
0.75 .030
0.45 .018
3
.118
NOM
6.6 .260
6.2 .244
A
1
.039
REF
1
2
3
.118
NOM
0.25 .010
C
SEATING PLANE
GAUGE PLANE
16X
SEATING
PLANE
0.10 [.004]
C
0.30 .012
0.19 .007
16X
1.20 .047
MAX
0.10 [.004] M
C
A
B
0.15 .006
0.00 .000
0.65 .026
0.45 .018
NOM
0.65 .026
NOM
1.85 .073
NOM
16
Preliminary dimensions, for reference only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.9 .232
NOM
A
B
C
Terminal #1 mark area
3
.118
C
Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling
0.53 .021
REF
NOM
Reference land pattern layout (reference IPC7351
TSOP65P640X120-17M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
1
2
3
.118
NOM
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
15
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package LP, 24-pin TSSOP with Exposed Thermal Pad (A6279)
7.9 .311
7.7 .303
8º
0º
A
24
B
0.20 .008
0.09 .004
4.5 .177
4.3 .169
B
0.75 .030
0.45 .018
3
.118
NOM
6.6 .260
6.2 .244
A
2
1
.039
REF
1
4.32 .170
NOM
0.25 .010
C
SEATING PLANE
GAUGE PLANE
24X
SEATING
PLANE
0.10 [.004]
C
0.30 .012
0.19 .007
0.65 .026
24X
1.20 .047
MAX
0.10 [.004] M
C
A
B
0.15 .006
0.00 .000
0.45 .018
NOM
0.65 .026
NOM
1.85 .073
NOM
24
Preliminary dimensions, for reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.9 .232
NOM
A
B
C
Terminal #1 mark area
3
.118
C
Exposed thermal pad (bottom surface) U.S. Customary dimensions controlling
0.53 .021
REF
NOM
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
1
2
4.32 .170
NOM
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
16
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package LW, 16-pin SOIC (A6278)
10.63 .419
9.97 .393
0.25 [.010] M B M
10.50 .614
10.10 .598
8º
0º
A
B
16
0.33 .013
0.20 .008
7.60 .299
7.40 .291
A
1.27 .050
0.40 .016
1
2
0.25 .010
SEATING PLANE
GAUGE PLANE
16X
C
SEATING
PLANE
0.10 [.004]
C
Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.51 .020
0.31 .012
16X
2.65 .104
2.35 .093
0.25 [.010] M
C
A
B
1.27 .050
0.30 .012
0.10 .004
A
Terminal #1 mark area
Package LW, 24-pin SOIC (A6279)
10.63 .419
9.97 .393
0.25 [.010] M B M
15.60 .614
15.20 .598
8º
0º
A
B
24
0.33 .013
0.20 .008
7.60 .299
7.40 .291
A
2
1.27 .050
0.40 .016
1
0.25 .010
SEATING PLANE
GAUGE PLANE
24X
C
SEATING
PLANE
0.10 [.004]
C
0.51 .020
0.31 .012
Preliminary dimensions, for reference only
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
(reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
24X
2.65 .104
2.35 .093
0.25 [.010] M
C
A
B
1.27 .050
0.30 .012
0.10 .004
A
Terminal #1 mark area
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
17
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6278 and
A6279
Serial-Input, Constant-Current Latched
LED Drivers with Open LED Detection
Package ET, 28-pin MLPQ (A6279)
5.15 .203
4.85 .191
A
B
28
Preliminary dimensions, for reference only
(reference JEDEC MO-220VHHD)
Dimensions in millimeters
1
2
A
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.15 .203
4.85 .191
A
B
Terminal #1 mark area
Exposed thermal pad (terminal #1 identifier appearance
at supplier discretion)
C
Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
C
28X
SEATING
PLANE
0.08 [.003]
C
0.30 .012
0.18 .007
28X
1.00 .039
0.80 .031
0.10 [.004] M
0.05 [.002] M
C
C
A B
0.20 .008
REF
0.50 .020
0.30 .012
NOM
0.05 .002
0.00 .000
0.50 .020
1.15 .045
NOM
3.15 .124
NOM
NOM
0.65 .026
0.45 .018
C
.008
4X 0.20
MIN
4.8 .189
NOM
3.15 .124
NOM
B
2
1
2
1
R0.30 .012
REF
.008
3
24X 0.20
MIN
28
28
3
.118
.118
NOM
NOM
4.8 .189
NOM
Copyright ©2005, 2007, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
18
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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