A6595KLWTR [ALLEGRO]
SIPO Based Peripheral Driver, 2A, NMOS, PDSO20, PLASTIC, SOIC-20;
| 型号： | A6595KLWTR |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | SIPO Based Peripheral Driver, 2A, NMOS, PDSO20, PLASTIC, SOIC-20 驱动 光电二极管 接口集成电路 |
| 文件： | 总10页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A6595
8-Bit Serial Input DMOS Power Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: May 3, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, refer to your Allegro sales representative.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6595
8-Bit Serial Input DMOS Power Driver
Features and Benefits
▪ 50 V minimum output clamp voltage
Description
The A6595 combines an 8-bit CMOS shift register and
▪ 250 mA output current (all outputs simultaneously)
▪ 1.3 Ω typical rDS(on)
accompanying data latches, control circuitry, and DMOS
power driver outputs. Power driver applications include
relays, solenoids, and other medium-current or high-voltage
peripheral power loads.
▪ Low power consumption
▪ Replacements for TPIC6595N and TPIC6595DW
The serial-data input, CMOS shift register and latches allow
direct interfacing with microprocessor-based systems. Serial-
data input rates are over 5 MHz. Use with TTL may require
appropriate pull-up resistors to ensure an input logic high.
A CMOS serial-data output enables cascade connections in
applications requiring additional drive lines.
The A6595 DMOS open-drain outputs are capable of sinking
up to 750 mA. All of the output drivers are disabled (the
DMOS sink drivers turned off) by the OUTPUT ENABLE
input high.
Package: 20-pin DIP (suffix A)
TheA6595 is furnished in a 20-pin dual in-line plastic package
that is lead (Pb) free, with 100% matte tin leadframe plating.
Copper leadframe base material, reduced supply current
requirements, and low on-state resistance allow the device
to sink 150 mA from all outputs continuously, to ambient
temperatures to 125°C.
Not to scale
Pin-out Diagram
POWER
GROUND
POWER
20
1
2
3
4
GROUND
LOGIC
19
LOGIC
SUPPLY
V
DD
GROUND
SERIAL
18
SERIAL
DATA IN
DATA OUT
OUT
17
16
15
14
13
OUT
OUT
0
7
6
OUT
OUT
5
6
1
2
OUT
OUT
5
4
OUT
7
8
3
REGISTER
CLEAR
CLK
ST
CLOCK
CLR
OE
OUTPUT
ENABLE
9
12
11
STROBE
POWER
GROUND
POWER
GROUND
10
26185.120a
A6595
8-Bit Serial Input DMOS Power Driver
Selection Guide
Part Number
A6595KA-T
Packing
18 pieces per tube
Absolute Maximum Ratings*
Characteristic
Symbol
VDD
VI
Notes
Rating
7.0
Units
V
Logic Supply Voltage
Input Voltage Range
Output Voltage
–0.3 to 7.0
50
V
VO
V
IO
Continuous, each output, all outputs on
250
mA
Pulsed tw ≤100 μs, duty cycle ≤ 2%; each out-
put, all outputs on
Output Drain Current
750
mA
IOM
Pulsed tw ≤100 μs, duty cycle ≤ 2%;
2.0
75
A
mJ
ºC
ºC
ºC
Single-Pulse Avalanche Energy
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
EAS
TA
Range K
–40 to 125
150
TJ(max)
T
stg
–55 to 150
*These CMOS devices have input static protection (Class 3) but are still susceptible to damage if exposed to extremely high static
electrical charges.
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Value Units
Package Thermal Resistance
RθJA
On 4-layer PCB based on JEDEC standard
32
ºC/W
*Additional thermal information available on the Allegro website.
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
25
50
75
100
125
150
AMBIENT TEMPERATURE ꢀoC)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6595
8-Bit Serial Input DMOS Power Driver
Functional Block Diagram
REGISTER
CLEAR
(ACTIVE LOW)
LOGIC
SUPPLY
V
DD
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
D-TYPE LATCHES
STROBE
OUTPUT
ENABLE
(ACTIVE LOW)
LOGIC
GROUND
POWER
GROUND
POWER
GROUND
OUT
OUT
N
0
Dwg. FP-013-5
Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
Device Logic Diagram
9
G3
12
C2
SRG8
C1
8
R
13
3
1D
2
4
5
6
7
14
15
16
17
18
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6595
8-Bit Serial Input DMOS Power Driver
V
OUT
DD
IN
Dwg. EP-063-3
Dwg. EP-0105-1
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
V
DD
RECOMMENDED OPERATING CONDITIONS
OUT
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
Dwg. EP-063-2
SERIAL DATA OUT
TRUTH TABLE
Shift Register Contents
Serial
Data
Output Strobe
Latch Contents
Output Contents
Data Clock
Input Input
Output
Enable
I
I
I
...
…
…
…
…
…
I
I
I
I
I
...
I
I
I
I
I
…
I
I
7
0
1
2
6
7
0
1
2
6
7
0
1
2
6
H
L
H
L
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
1
1
1
2
5
5
6
6
6
7
6
6
7
X
R
0
X
X
X
X
X
X
—
R
R
R
…
R
R
0
1
2
6
7
P
P
P
P
P
P
P
P
P
…
…
P
P
L
P
P
P
…
P
P
6 7
0
1
2
6
7
7
0
1
2
6
7
0
1
2
X
X
X
X
X
H
H
H
H
…
H
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous Stat e
Allegro MicroSystems, Inc.
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6595
8-Bit Serial Input DMOS Power Driver
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
Limits
Characteristic
Symbol Test Conditions
Min.
Typ.
Max.
Units
Output Breakdown
Voltage
V(BR)DSX
IO = 1 mA
50
—
—
V
Off-State Output
Current
IDSX
VO = 40 V
—
—
—
—
—
—
0.05
0.15
1.3
1.0
5.0
2.0
3.2
2.0
—
μA
μA
Ω
VO = 40 V, TA = 125°C
Static Drain-Source
On-State Resistance
rDS(on)
IO = 250 mA, VDD = 4.5 V
IO = 250 mA, VDD = 4.5 V, TA = 125°C
IO = 500 mA, VDD = 4.5 V (see note)
VDS(on) = 0.5 V, TA = 85°C
2.0
Ω
1.3
Ω
Nominal Output
Current
ION
250
mA
Logic Input Current
IIH
IIL
VI = VDD = 5.5 V
—
—
—
4.4
4.1
—
—
—
—
—
—
—
—
—
—
—
1.0
-1.0
—
μA
μA
V
VI = 0, VDD = 5.5 V
Logic Input Hysteresis VI(hys)
1.3
SERIAL-DATA
Output Voltage
VOH
IOH = -20 μA, VDD = 4.5 V
IOH = -4 mA, VDD = 4.5 V
IOL = 20 μA, VDD = 4.5 V
IOL = 4 mA, VDD = 4.5 V
IO = 250 mA, CL = 30 pF
IO = 250 mA, CL = 30 pF
IO = 250 mA, CL = 30 pF
IO = 250 mA, CL = 30 pF
All inputs low
4.49
4.3
—
V
—
V
VOL
0.002
0.2
0.1
0.4
—
V
V
Prop. Delay Time
tPLH
tPHL
650
150
7500
425
15
ns
ns
ns
ns
μA
μA
mA
—
Output Rise Time
Output Fall Time
Supply Current
tr
—
tf
—
IDD(OFF)
IDD(ON)
IDD(fclk)
100
300
5.0
VDD = 5.5 V, Outputs on
fclk = 5 MHz, CL = 30 pF, Outputs off
150
0.6
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤100 μs, duty cycle ≤2%.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6595
8-Bit Serial Input DMOS Power Driver
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
B
SERIAL
DATA NI
DATA
50%
t
p
SERIAL
DATA OUT
50%
DATA
D
E
50%
STROBE
OUTPUT
ENABLE
LOW = ALL OUTPUTS ENABLED
t
p
HGIH=OUTPUTOFF
50%
DATA
OUT
N
LOW = OUTPUTNO
Dwg. WP-029-2
HIGH
= ALL OUTPUTS DISABLED
50%
OUTPUT
ENABLE
t
PLH
t
t
t
r
PHL
f
90%
OUT
N
DATA
10%
Dwg. WP-030-2
Serial data present at the input is transferred to the shift reg-
ister on the rising edge of the CLOCK input pulse. On succeed-
ing CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT.
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) .......................................... 10 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) .............................................. 10 ns
C. Clock Pulse Width, tw(CLK) ............................................. 20 ns
Information present at any register is transferred to the
respective latch on the rising edge of the STROBE input pulse
(serial-to-parallel conversion).
D. Time Between Clock Activation
and Strobe, tsu(ST) ....................................................... 50 ns
E. Strobe Pulse Width, tw(ST) ............................................... 50 ns
F. Output Enable Pulse Width, tw(OE) ................................ 4.5 μs
When the OUTPUT ENABLE input is high, the output
source drivers are disabled (OFF). The information stored in the
latches is not affected by the OUTPUT ENABLE input. With the
OUTPUT ENABLE input low, the outputs are controlled by the
state of their respective latches.
NOTE – Timing is representative of a 12.5 MHz clock.
Higher speeds are attainable.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6595
8-Bit Serial Input DMOS Power Driver
TEST CIRCUITS
+15 V
INPUT
tav
IAS = 1.A0
IO
DUT
OUT
V
V
(BR)DXS
O(ON)
V
O
Dwg. EP-066-1
EAS = IAS x V(BR)DSX x tAV/2
Single-Pulse Avalanche Energy Test Circuit and
Waveforms
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6595
8-Bit Serial Input DMOS Power Driver
TERMINAL DESCRIPTIONS
Terminal No.
Terminal Name
POWER GROUND
LOGIC SUPPLY
SERIAL DATA IN
OUT0-3
Function
1
2
Reference terminal for output voltage measurements (OUT0-3).
(VDD) The logic supply voltage (typically 5 V).
Serial-data input to the shift-register.
3
4-7
8
Current-sinking, open-drain DMOS output terminals.
When (active) low, the registers are cleared (set low).
CLEAR
9
OUTPUT ENABLE
When (active) low, the output drivers are enabled; when high, all output driv-
ers are turned OFF (blanked).
10
11
POWER GROUND
POWER GROUND
STROBE
Reference terminal for output voltage measurements (OUT0-3).
Reference terminal for output voltage measurements (OUT0-7).
Data strobe input terminal; shift register data is latched on rising edge.
Clock input terminal for data shift on rising edge.
12
13
CLOCK
14-17
18
OUT4-7
Current-sinking, open-drain DMOS output terminals.
SERIAL DATA OUT
LOGIC GROUND
POWER GROUND
CMOS serial-data output to the following shift register.
Reference terminal for input voltage measurements.
19
20
Reference terminal for output voltage measurements (OUT4-7).
NOTE — Grounds (terminals 1, 10, 11, 19, and 20) must be connected together externally.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
A6595
8-Bit Serial Input DMOS Power Driver
Package A, 20-Pin DIP
+0.76
–1.27
26.16
20
+0.10
0.38
–0.05
+0.76
–0.25
+0.38
10.92
–0.25
7.62
6.35
A
1
2
C
SEATING
PLANE
5.33 MAX
+0.51
3.30
–0.38
2.54
+0.25
–0.38
1.52
0.46 ±0.12
Preliminary dimensions, for reference only
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
(reference JEDEC MS-001 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A
Terminal #1 mark area
Copyright ©2000-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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