A6811SA [ALLEGRO]
DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER; DABiC -IV 12位串行输入，锁存源极驱动器
| 型号： | A6811SA |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | DABiC-IV, 12-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER |
| 文件： | 总8页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6811
PRELIMINARY INFORMATION
(subject to change without notice)
May 15, 2000
DABiC-IV, 12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
The A6811– devices combine a 12-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar sourcing
outputs and pnp active pull downs. Designed primarily to drive
vacuum-fluorescent displays, the 60 V and -40 mA output ratings also
allow these devices to be used in many other peripheral power driver
applications. The A6811– features an increased data input rate (com-
pared with the older UCN/UCQ5811A) and a controlled output slew
rate.
A6811xA
1
2
3
4
20 OUT
19 OUT
18 OUT
OUT
OUT
10
9
11
12
BLNK
BLANKING
8
SERIAL
DATA OUT
17
16
15
14
OUT
7
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 3.3 V or 5 V logic supply,
typical serial-data input rates are up to 33 MHz.
LOAD
SUPPLY
SERIAL
DATA IN
5
6
V
BB
LOGIC
SUPPLY
V
GROUND
DD
A CMOS serial data output permits cascade connections in applica-
tions requiring additional drive lines. Similar devices are available as
the A6809– and A6810– (10 bits), A6812– (20 bits), and A6818– (32
bits).
OUT
6
7
8
CLOCK
CLK
ST
13 OUT
STROBE
5
4
3
9
OUT
OUT
1
12
The A6811– output source drivers are npn Darlingtons, capable of
sourcing up to 40 mA. The controlled output slew rate reduces electro-
magnetic noise, which is an important consideration in systems that
include telecommunications and/or microprocessors and to meet
government emissions regulations. For inter-digit blanking, all output
drivers can be disabled and all sink drivers turned on with a BLANK-
ING input high. The pnp active pull-downs will sink at least 2.5 mA.
10
OUT
2
11 OUT
Dwg. PP-029-5
Two temperature ranges are available for optimum performance in
commercial (suffix S-) or industrial (suffix E-) applications. Package
styles are provided for through-hole DIP (suffix -A) and surface-mount
SOIC or PLCC (suffix -LW or -EP). Copper lead frames, low logic-
power dissipation, and low output-saturation voltages allow all devices
to source 25 mA from all outputs continuously at up to 83°C.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD ................... 7.0 V
Driver Supply Voltage, VBB ................... 60 V
Continuous Output Current Range,
I
OUT......................... -40 mA to +15 mA
Input Voltage Range,
FEATURES
VIN ....................... -0.3 V to VDD + 0.3 V
I Controlled Output Slew Rate
Package Power Dissipation,
I High-Speed Data Storage
I 60 V Minimum
Output Breakdown
I High Data Input Rate
I PNP Active Pull-Downs
PD ........................................ See Graph
Operating Temperature Range, TA
(Suffix ‘E–’) .................. -40°C to +85°C
(Suffix ‘S–’) .................. -20°C to +85°C
Storage Temperature Range,
TS ............................... -55°C to +125°C
I Low-Power CMOS Logic
and Latches
I Improved Replacements
for SN75512B, UCN5811–,
and UCQ5811–
I Low Output-Saturation Voltages
Caution: These CMOS devices have input
static protection (Class 2) but are still
susceptible to damage if exposed to
extremely high static electrical charges.
Complete part number includes a suffix to identify operating
temperature range (E- or S-) and package type (-A, -EP, or -LW).
Always order by complete part number, e.g., A6811SLW .
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6811xEP
A6811xLW
1
2
3
4
20
19
18
17
16
15
14
13
OUT
OUT
OUT
OUT
OUT
OUT
10
9
11
12
BLNK
BLANKING
8
SERIAL
DATA OUT
4
18 OUT
8
7
SERIAL
DATA OUT
7
SERIAL
DATA IN
17 OUT
5
6
7
LOAD
SUPPLY
SERIAL
DATA IN
5
6
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
V
V
16
DD
BB
LOGIC
SUPPLY
V
GROUND
DD
CLOCK
CLK
ST
15 GROUND
OUT
6
7
8
CLOCK
CLK
ST
14 OUT
STROBE
8
6
OUT
5
STROBE
9
OUT
4
OUT
1
12
11
10
OUT
2
Dwg. PP-059-4
OUT
3
Dwg. PP-029-6
TYPICAL INPUT CIRCUIT
V
DD
2.5
2.0
1.5
1.0
0.5
IN
SUFFIX 'A', R
= 55°C/W
θJA
SUFFIX 'EP', R
= 59°C/W
θJA
Dwg. EP-010-5
TYPICAL OUTPUT DRIVER
V
BB
SUFFIX 'LW', R
= 70°C/W
θJA
OUT
N
0
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-024-5
Dwg. EP-021-19
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
V
DD
CLOCK
SERIAL
DATA IN
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
STROBE
BLANKING
MOS
BIPOLAR
LOAD
SUPPLY
V
BB
GROUND
OUT OUT OUT
OUT
N
Dwg. FP-013-1
1
2
3
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data Clock
Input Input I
Data Strobe
Output Input
I
I
...
I
I
I
I
I
...
I
I
Blanklng
I
I
I
... I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...
...
...
...
...
R
R
R
X
R
R
R
X
R
R
R
X
1
1
2
2
2
3
N-2
N-2
N-1
N-1
N-1
N
N-1
N-1
N
X
R
X
1
L
R
R
R
...
...
...
R
R
1
2
3
N-1
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
L
P
L
P
L
... P
... L
P
L
1
2
3
N-1
N
N
1
2
3
N-1
N
1
2
3
N-1
N
X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
www.allegromicro.com
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
ELECTRICAL CHARACTERISTICS at T = +25°C (A6811S-) or over operating temperature
A
range (A6811E-), V
= 60 V unless otherwise noted.
BB
Limits @ V
= 3.3 V Limits @ V
= 5 V
DD
DD
Characteristic
Symbol
Test Conditions
Mln.
—
Typ.
Max.
-15
—
Min. Typ. Max.
<-0.1 -15
Units
µA
V
Output Leakage Current
Output Voltage
I
V
= 0 V
<-0.1
58.3
1.0
—
CEX
OUT
OUT
OUT
V
V
I
I
= -25 mA
= 1 mA
57.5
—
57.5 58.3
—
1.5
—
OUT(1)
OUT(0)
OUT(0)
1.5
—
—
2.5
3.3
—
1.0
5.0
—
V
Output Pull-Down Current
Input Voltage
I
V
= 5 V to V
2.5
2.2
—
5.0
mA
V
OUT
BB
V
—
—
—
IN(1)
IN(0)
IN(1)
IN(0)
V
—
1.1
1.0
—
1.7
V
Input Current
I
I
V
V
= V
—
<0.01
—
<0.01 1.0
<-0.01 -1.0
µA
µA
V
IN
DD
= 0 V
—
<-0.01 -1.0
—
IN
Input Clamp Voltage
V
I
I
I
= -200 µA
—
-0.8
3.05
0.15
33
-1.5
—
—
-0.8
4.75
0.15
33
-1.5
—
IK
IN
Serial Data Output Voltage
V
V
= -200 µA
= 200 µA
2.8
—
4.5
—
V
OUT(1)
OUT(0)
OUT
OUT
0.3
—
0.3
—
V
Maximum Clock Frequency
Logic Supply Current
f
10
—
10
—
MHz
mA
mA
mA
µA
µs
µs
µs
µs
µs
µs
c
I
All Outputs High
0.25
0.25
1.7
0.2
0.7
1.8
0.7
1.8
—
0.75
0.75
3.5
20
0.3
0.3
1.7
0.2
0.7
1.8
0.7
1.8
—
1.0
1.0
3.5
20
DD(1)
DD(0)
I
All Outputs Low
—
—
Load Supply Current
I
I
All Outputs High, No Load
All Outputs Low
—
—
BB(1)
BB(0)
—
—
Blanking-to-Output Delay
Strobe-to-Output Delay
t
C = 30 pF, 50% to 50%
—
2.0
3.0
2.0
3.0
12
—
2.0
3.0
2.0
3.0
12
dis(BQ)
L
t
C = 30 pF, 50% to 50%
—
—
en(BQ)
L
t
R = 2.3 kΩ, C ≤ 30 pF
—
—
p(STH-QL)
L
L
t
R = 2.3 kΩ, C ≤ 30 pF
—
—
p(STH-QH)
L
L
Output Fall Time
Output Rise Time
t
t
R = 2.3 kΩ, C ≤ 30 pF
2.4
2.4
2.4
2.4
f
L
L
R = 2.3 kΩ, C ≤ 30 pF
—
12
—
12
r
L
L
Output Slew Rate
dV/dt
R = 2.3 kΩ, C ≤ 30 pF
4.0
—
20
4.0
—
20
V/µs
L
L
Clock-to-Serial Data Out Delay t
I
= 200 µA
—
50
—
—
50
—
ns
p(CH-SQX)
OUT
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
B
CLOCK
A
SERIAL
DATA IN
DATA
50%
t
p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
E
50%
STROBE
BLANKING
LOW = ALL OUTPUTS ENABLED
t
p(STH-QH)
t
p(STH-QL)
90%
DATA
OUT
N
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
BLANKING
t
dis(BQ)
t
t
t
f
en(BQ)
r
90%
OUT
N
DATA
10%
Dwg. WP-030
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ......................................... 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................... 25 ns
C. Clock Pulse Width, tw(CH) ............................................... 50 ns
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
D. Time Between Clock Activation and Strobe, tsu(C) ....... 100 ns
E. Strobe Pulse Width, tw(STH) ............................................. 50 ns
NOTE – Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
www.allegromicro.com
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6811EA & A6811SA
Dimensions in Inches
(controlling dimensions)
0.014
0.008
20
11
0.430
MAX
0.280
0.240
0.300
BSC
1
10
0.100
0.070
0.045
0.005
BSC
MIN
1.060
0.980
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
0.355
0.204
20
11
10.92
MAX
7.11
6.10
7.62
BSC
1
10
2.54
1.77
1.15
0.13
BSC
MIN
26.92
24.89
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-20 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6811EEP & A6811SEP
Dimensions in Inches
(controlling dimensions)
13
9
0.021
0.013
8
4
14
0.169
0.141
0.032
0.026
0.395
0.385
INDEX AREA
0.356
0.350
0.050
BSC
0.169
0.141
18
19 20
1
2
3
0.356
0.350
0.020
MIN
0.395
0.385
0.180
0.165
Dwg. MA-005-20A in
Dimensions in Millimeters
(for reference only)
13
9
0.533
0.331
8
14
4.29
3.58
0.812
10.03
0.661
9.78
INDEX AREA
9.042
8.890
1.27
BSC
4.29
3.58
18
4
19 20
1
2
3
9.042
8.890
0.51
MIN
10.03
9.78
4.57
4.20
Dwg. MA-005-20A mm
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
NOTES: 1. Exact body and lead configuration at vendor’s
option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
6811
12-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVER
A6811ELW & A6811SLW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
BSC
0° TO 8°
0.5118
0.4961
0.0926
0.1043
Dwg. MA-008-20 in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
BSC
0° TO 8°
13.00
12.60
2.65
2.35
Dwg. MA-008-20 mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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