A80606KEVJSR-1_技术文档

A80606 and A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

FEATURES AND BENEFITS

DESCRIPTION

The A80606 is a multi-output LED driver for automotive

applicationssuchasexteriorlighting,heads-updisplay,andmid-

size LCD backlighting. It implements a current-mode boost/

SEPICconverterwithgatedriverforexternalN-MOSFET.This

allows greater output power even at minimum supply voltage.

• Automotive AEC-Q100 qualified

• Enhanced fault handling for ASIL B system compliance

• Wide input voltage range of 4.5 to 40 V for start/stop,

cold crank, and load dump requirements

• Operate in Boost or SEPIC mode for flexible output

• Gate driver for external NMOS to deliver higher output power

• Six integrated LED current sinks, up to 180 mA each

• Boost switching frequency synced externally or

programmed from 200 kHz to 2.3 MHz

• Programmable boost frequency dithering to reduce EMI

• Advanced control allows minimum PWM on-time down

to 0.3 µs, and avoids MLCC audible noises

• LED contrast ratio: 15,000:1 at 200 Hz using PWM

dimming alone, 150,000:1 when combining PWM and

analog dimming

The A80606 provides six integrated current sinks driving up

to 180 mAper string. Multiple sinks can be paralleled together

to achieve higher LED currents up to 1.08 A. The IC operates

from single power supply from 4.5 to 40 V; once started, it can

continue to operate down to 4 V. This allows it to withstand

stop/start, cold crank, and load dump conditions encountered

in automotive systems.

TheA80606cancontrolLEDbrightnessthroughexternalPWM

signal.ByusingthepatentedPre-EmptiveBoostcontrol,anLED

brightnesscontrastratioof15,000:1canbeachievedusingPWM

dimmingat200Hz.Ahigherratioof150,000:1ispossiblewhen

using a combination of PWM and analog dimming.

• Excellent input voltage transient response even at lowest

PWM duty cycle

• Gate driver for optional PMOS input disconnect switch

• Extensive fault protection features

Continued on next page...

PACKAGE:

APPLICATIONS

• Automotive infotainment backlighting

48-Pin 7 mm × 7 mm

QFN with Wettable Flank

• Automotive heads-up display

• Automotive interior and exterior lighting

Not to scale

V_IN= 8-16 V

V_OUT≤ 40 V

optional input overcurrent disconnect

L1

R_SENSE

R_ADJ

D1

C_IN2

Q1

D2

C_in

R_OVP

R_CS

C_DRV

R_GDRV

C_OUT

CS

GATE

VDRV GDRV

PGND

OVP

Vsense

VIN

V

c

C_VDD

VDD

R_PU

LED1

FAULT

A80606

Up to 11 WLEDs in series

Up to 180 mA/channel

Combine to drive up to 1.08 A total

LED2

LED3

EN

Enable

PWM

ADIM

PWM t_ON≥ 0.3 µs

LED6

CLKOUT

AGND

i_LED

COMP

PEB

100%

FSET

ISET

DITH

R_Z

ADIM

C_P

R_M

PEB = Pre-Emptive Boost

(R_Dcontrols the delay time)

DITH = Dithering Control

R_ISET

R_FSET

R_D

C_M

C_Z

APWM 100 kHz 0-90%

(Modulation frequency and range)

Figure 1: A80606 in typical Boost conﬁguration where V_OUTis higher than V_IN

A80606-DS

August 27, 2020

MCO-0000926

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

DESCRIPTION (continued)

Switchingfrequencycanbeexternallysynchronizedorprogrammed

between 200 kHz and 2.3 MHz. This allows operation either above

or below the AM band. A programmable dithering feature further

reduces EMI. A clock-out is provided for other converters to sync

to the A80606.

The A80606 provides protection against output short, overvoltage,

open- or shorted-LED pin, and overtemperature. A cycle-by-cycle

current limit protects the external boost switch against high current

overloads. An external P-MOSFET can optionally be used to

disconnect input supply in case of output to ground short fault. The

A80606-1 is similar toA80606 except it adopts ‘One-Out-All-Out’

fault handling (See Fault Table section for details).

SELECTION GUIDE ^[1]

Part Number

A80606KEVJSR

A80606KEVJSR-1

Fault Handling

One-Out-Continue

One-Out-All-Out

LED Driver

Package

Packing

48-pin 7 mm × 7 mm wettable flank QFN

with exposed thermal pad and sidewall plating

4000 pieces

per 13-inch reel

6 × 180 mA

^[1]Contact Allegro for additional packing options.

ABSOLUTE MAXIMUM RATINGS ^[2]

Characteristic

Symbol

Notes

Rating

Unit

LEDx Pin

OVP pin

VIN

V_LEDx

V_OVP

V_IN

x = 1..6

–0.3 to 40

V

–0.3 to 40

Higher of –0.3

and (V_IN– 7.4) to

V_IN+0.4

V_SENSE

V_GATE

,

VSENSE, GATE

V

VDRV, GDRV

CS

V_DRV,V_GDRV

V_CS

–1.0 to 7.5

–0.3 to 7

V

EN, PWM, FAULT, ADIM, COMP,

DITH, PEB, FSET, ISET, VDD

External input signals must not be higher than V_IN+ 0.4 V

–0.3 to 5.5

V

Maximum Junction Temperature

Storage Temperature

T_J(max)

T_stg

150

°C

–55 to 150

^[2]Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions ^[4]

Value

Unit

Package Thermal Resistance

R_θJA

EV package measured on 4-layer PCB based on JEDEC standard

24

°C/W

^[4]Additional thermal information available on the Allegro website.

2

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Table of Contents

LED Current Setting ........................................................ 18

PWM Dimming ............................................................... 18

Pre-Emptive Boost (PEB)................................................. 19

Analog Dimming ............................................................. 20

ADIM Mode ................................................................ 20

APWM Mode .............................................................. 21

Extending LED Dimming Ratio.......................................... 22

Analog Dimming with External Voltage............................... 23

VDD.............................................................................. 24

VDRV............................................................................ 24

Shutdown....................................................................... 24

Fault Detection and Protection............................................. 25

FAULT Status ................................................................. 25

LED String Partial-Short Detect ........................................ 27

Overvoltage Protection .................................................... 28

Boost Switch Overcurrent Protection ................................. 29

Input Overcurrent Protection and Disconnect Switch ........... 30

Setting the Input Current Sense Resistor ........................... 31

Input UVLO.................................................................... 31

Fault Protection During Operation ..................................... 31

Package Outline Drawing.................................................... 34

Appendix A: Design Example............................................... 35

Appendix B: External MOSFET Selection Guide .................... 39

Features and Benefits........................................................... 1

Description.......................................................................... 1

Applications......................................................................... 1

Package ............................................................................. 1

Selection Guide ................................................................... 2

Absolute Maximum Ratings................................................... 2

Thermal Characteristics ........................................................ 2

Typical Application – SEPIC .................................................. 3

Functional Block Diagram ..................................................... 4

Pinout Diagram and Terminal List........................................... 5

Electrical Characteristics....................................................... 6

Application Example........................................................... 10

Functional Description .........................................................11

Enabling the IC................................................................11

Powering Up: LED Detection Phase.................................. 12

Powering Up: Boost Output Undervoltage.......................... 14

Soft Start Function .......................................................... 14

Frequency Selection........................................................ 15

Synchronization.............................................................. 15

Loss of External Sync Signal............................................ 16

Switching Frequency Dithering ......................................... 17

Clock Out Function.......................................................... 17

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A80606

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APꢘM 100ꢏHꢜ 0-90ꢝ

Figure 2: A80606 in typical SEPIC conﬁguration where V_OUTcan be either higher or lower than V_IN

3

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

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AꢏNꢅ

Figure 3: Functional Block Diagram

4

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

PINOUT DIAGRAM AND TERMINAL LIST

Nꢅ

3ꢀ

35

3ꢁ

33

3ꢂ

31

30

ꢂ9

ꢂꢃ

ꢂꢄ

ꢂꢀ

ꢂ5

1

ꢂ

Nꢅ

PꢌNꢍ

ꢐꢉP

ꢇꢋꢍ1

ꢇꢋꢍꢂ

ꢇꢋꢍ3

ꢇꢋꢍꢁ

ꢇꢋꢍ5

ꢇꢋꢍꢀ

Nꢅ

3

Nꢅ

ꢁ

ꢉꢍꢍ

Nꢅ

5

ꢀ

PAꢍ

AꢌNꢍ

ꢅꢐMP

ꢊSꢋꢈ

Pꢋꢑ

ꢍꢊꢈH

Nꢅ

ꢄ

ꢃ

9

10

11

1ꢂ

Nꢅ

Package EV, 48-Pin QFN Pinouts

Subject to Change (contact factory before using)

Terminal List Table

Number

Name

Function

1-4, 6, 12-14,

20-26, 35-39,

47-48

NC

Pins marked "NC" may be connected to GND to improve thermal performance.

5

7

8

9

VDD

AGND

COMP

ISET

Output of internal LDO (bias regulator). Connect a 1 µF decoupling capacitor between this pin and AGND. VDD is regulated at ~4.25 V.

LED current Ground. Also serves as ‘quiet’ ground for analog signals.

Output of the error amplifier and compensation node. Connect a series RZ-CZ network from this pin to AGND for control loop compensation.

Connect R_ISETresistor between this pin and AGND to set the 100% LED current.

Pre-Emptive Boost control: Connect resistor from PEB pin to AGND to fine-tune the delay between boost switch and LED current sinks. Leave pin open for minimum

PEB delay of 1 μs.

10

11

15

16

PEB

DITH

FSET

ADIM

Dithering control: connect a capacitor to AGND to set the dithering modulation frequency (1 to 22 kHz). Connect a resistor between DITH and FSET pins to set the

dithering range (such as ±5% of f_SW).

Frequency/Synchronization pin. A resistor R_FSETfrom this pin to AGND sets the switching frequency f_SW(with dithering superimposed) between 200 kHz and

2.3 MHz. It can also be used to synchronize f_SWto an external frequency between 260 kHz and 2.3 MHz (frequency dithering is disabled in this case).

Analog dimming. Apply a PWM clock (40 to 1000 kHz) to pin and the duty cycle of this clock determines the LED current. Alternatively, apply DC level between 0.2

and 2 V to vary LED current between 10% and 100%. If unused, pull pin above 2 V for 100%.

Controls the on/off state of LED current sinks to reduce the light intensity by using pulse-width modulation. Typical PWM dimming frequency is in the range of 200 Hz

to 2 kHz. EN and PWM pins may be tied together to allow single-wire dimming control.

17

18

19

PWM

EN

Enables the IC when this pin is pulled high. If EN goes low, the IC remains in standby mode for up to 16 ms, then shuts down completely.

Logic output representing the switching frequency of internal boost oscillator. This allows other converters to be synchronized to the same f_SWwith the same dithering

modulation, if applicable. Output is active as long as IC is enabled.

CLKOUT

33

34

40

41

42

43

OVP

PGND

VDRV

CS

Overvoltage Protection. Connect external resistor from VOUT to this pin to adjust the overvoltage protection threshold.

Power Ground for internal Gate Driver. Connect pin to external power GND with shortest path.

Gate driver supply voltage (~6.5 V). Connect a 2.2 µF MLCC to PGND for buffer.

Current Sense for peak current control of power switch. Connect to sense resistor at the Source terminal of external power MOSFET.

Gate driver for power switch. Connect to Gate of external power MOSFET. (External FET must be fully enhanced at V_GS= 5 V).

Output gate driver pin for external P-channel MOSFET (input disconnect switch).

GDRV

GATE

Connect this pin to the negative sense side of the input current sense resistor RSC. The threshold voltage is measured as V_IN– V_SENSE. There is also fixed i_ADJ

current sink to allow for trip threshold adjustment.

44

VSENSE

45

46

VIN

Input power to the IC as well as the positive side of input current sense resistor.

FAULT

This pin is an open drain type configuration that will be pulled low when a fault occurs. Connect a pull-up resistor between this pin and desired logic level voltage.

LED current sinks #6 to #1. Connect the cathode of each LED string to pin. Unused LED pin must be terminated to AGND through a resistor (4.75 kΩ for LEDs 1, 3,

4 and 6, 2.37 kΩ for LEDs 2 and 5).

27-32

–

LED6..LED1

PAD

Exposed pad of the package providing enhanced thermal dissipation. Must be connected to the ground plane(s) of the PCB with at least 8 vias, directly in the pad.

5

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ELECTRICAL CHARACTERISTICS ^[1]: Unless otherwise noted, speciﬁcations are valid at V_IN= 12 V, T_J= 25°C, • indicates speciﬁca-

tions guaranteed over the full operating temperature range with T_J= –40°C to 125°C, typical speciﬁcations are at T_J= 25°C

Characteristics

INPUT VOLTAGE SPECIFICATIONS

Operating Input Voltage Range ^[3]

VIN UVLO Start Threshold

VIN UVLO Stop Threshold

UVLO Hysteresis ^[2]

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_IN

●

4.5

−

–

40

V

V_UVLO(rise)

V_UVLO(fall)

V_{UVLO_HYS}

V_INrising

V_INfalling

4.45

4.05

500

−

–

V

300

400

mV

INPUT CURRENTS

EN and PWM = H, C_GATE= 1 nF from GDRV to

PGND, f_SW= 2 MHz

VIN Pin Operating Current

I_OP

●

−

22

32

mA

VIN Pin Quiescent Current

VIN Pin Sleep Current

I_Q

EN = H and PWM = L, f_CLKOUT= 2 MHz

V_IN= 16 V, V_EN/ V_PWM= V_SYNC= 0 V

●

−

4

1

6

5

mA

µA

I_SLEEP

INPUT LOGIC LEVELS (EN, PWM, ADIM)

Input Logic Level-Low

Input Logic Level-High

V_IL

V_IH

R_EN, R_PWMInput = 5 V

●

−

0.4

−

V

1.5

60

−

100

140

kΩ

kΩ

Input Pull-Down Resistor

R_ADIM

Input = 5 V

OUTPUT LOGIC LEVELS (CLKOUT)

Output Logic Level-Low

V_OL

V_OH

5 V < V_IN< 40 V, i_LOAD= 1 mA

f_SW= 2 MHz, no external sync

External sync = 260 kHz to 2.3 MHz

●

−

1.8

33

−

0.3

−

V

Output Logic Level-High

CLKOUT Duty Cycle

D_CLKOUT

t_CLKNPW

50

200

67

−

%

ns

CLKOUT Negative Pulse Width

ANALOG DIMMING (ADIM)

i_ADIM50

i_ADIM25

f_APWM

DC 1.0 V applied to ADIM pin

DC 0.5 V applied to ADIM pin

Clock signal applied to ADIM pin

−

23

40

0

50

25

−

27

%

Analog Dimming Current Level

(shown as % of full-scale current)

APWM Frequency Range ^[2]

APWM Duty Cycle Range ^[2]

VDD REGULATOR

●

1000

90

kHz

%

D_APWM

−

Regulator Output Voltage

VDD UVLO Start Threshold

VDD UVLO Stop Threshold

ERROR AMPLIFIER

V_DD

V_IN> 6 V, i_LOAD< 1 mA

4.05

−

4.25

3.2

4.45

−

V

V_DDUVLOriseV_DDrising, no external load

V_DDUVLOfallV_DDfalling, no external load

−

2.65

−

Amplifier Gain ^[2]

gm

V_COMP= 1.5 V

−

900

–500

–700

+500

1.4

−

μA/V

μA

V_COMP= 1.5 V, A80606 (symm COMP)

V_COMP= 1.5 V, A80606-1 (asymm COMP)

V_COMP= 1.5 V

Source Current

I_EA(SRC)

μA

Sink Current

I_EA(SINK)

R_COMP

μA

COMP Pin Pull Down Resistance

FAULT = 0, V_COMP= 1.5 V

kΩ

Continued on the next page…

6

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ELECTRICAL CHARACTERISTICS ^[1](continued): Unless otherwise noted, speciﬁcations are valid at V_IN= 12 V, T_J= 25°C, • indi-

cates speciﬁcations guaranteed over the full operating temperature range with T_J= –40°C to 125°C, typical speciﬁcations are at T_J= 25°C

Characteristics

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

OVERVOLTAGE PROTECTION

OVP Pin Voltage Threshold

V_OVP(th)

i_OVP(th)

OVP pin connected to V_OUT

Current into OVP pin at 125°C

Measured over temperature

●

2.2

140

2.5

146.5

150

2.8

153

160

V

µA

OVP Pin Sense Current Threshold

OVP Sense Current Temperature

Coefficient ^[2]

∆i_OVP

Current into OVP pin

V_OUT= 16 V, EN = L

−

−36

−

nA/°C

OVP Pin Leakage Current

I_OVPLKG

●

−

0.1

−

1

4

µA

%

V

OVP Variation at Output

Δ_OVP

Measured at V_OUTwhen R_OVP= 188 kΩ

−

7

Measured at V_OUTwhen R_OVP= 188 kΩ ^[2]

Measured at V_OUTwhen R_OVP= 0 Ω

2.4

0.13

2.55

0.20

2.7

0.25

Undervoltage Detection Threshold

V_UVP(th)

V

BOOST SWITCH GATE DRIVER

Gate Driver Supply Voltage

Gate Driver Pull-Up and Pull-Down

Gate Pull-Down When Disabled

Peak Sink Current ^[2]

V_DRV

Measured at V_IN> 7.5 V

−

6.5

2.5

100

2

−

V

Ω

R_GDRV

Measured at i_GDRV= 100 mA

R_{GDRV_OFF}EN = L, V_IN= 0 V

kΩ

A

i_SINK

Measured at V_GDRV= V_DRV

Peak Source Current ^[2]

i_SOURCE

Measured at V_GDRV= 0 V

2

A

Measured with C_LOAD= 1.5 nF;

V_GDRVbetween 10% and 90% of V_DRV

Gate Rise / Fall Time ^[2]

t_RISE,t_FALL

−

7

−

ns

Minimum Gate Driver On-Time

Minimum Gate Driver Off-Time

BOOST SWITCH CURRENT SENSE

t_SW(ON)

●

−

100

ns

t_SW(OFF)

Exceeding i_CS(LIM1)causes gate driver to

truncate existing cycle, but does not shut down

Primary Current Sense Limit

i_CS(LIM1)

i_CS(LIM2)

t_CSDELAY

●

175

−

210

300

32

245

−

mV

ns

Exceeding i_CS(LIM2)causes gate driver to shut

down and latch off

Secondary Current Sense Limit ^[2]

Secondary Current Sense Limit

Propagation Delay

Overdrive CS threshold by 10%, excluding

leading edge blanking

−

OSCILLATOR FREQUENCY

R_FSET= 10 kΩ

R_FSET= 110 kΩ

R_FSET= 10 kΩ

●

1.95

−

2.15

200

2.35

−

MHz

kHz

V

Oscillator Frequency

f_SW

FSET Pin Voltage

V_FSET

−

1.00

−

SYNCHRONIZATION

V_SYNCL

V_SYNCH

FSET/SYNC pin logic Low

FSET/SYNC pin logic High

●

−

0.4

−

V

Sync Input Logic Level

1.5

260

150

Synchronized PWM Frequency

Synchronization Input Min Off-Time

Synchronization Input Min On-Time

f_SWSYNC

2300

−

kHz

ns

t_PWSYNCOFF

t_PWSYNCON

−

Continued on the next page…

7

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ELECTRICAL CHARACTERISTICS ^[1](continued): Unless otherwise noted, speciﬁcations are valid at V_IN= 12 V, T_J= 25°C, • indi-

cates speciﬁcations guaranteed over the full operating temperature range with T_J= –40°C to 125°C, typical speciﬁcations are at T_J= 25°C

Characteristics

LED CURRENT SINKS

LEDx Accuracy ^[4]

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Err_LED

i_ISET= 120 µA (R_ISET= 8.33 kΩ)

●

−

0.7

0.8

3

2

%

LEDx Matching

Δ_LEDx

i_ISET= 120 µA

Measured individually with all

other LED pins tied to ≥1 V,

i_ISET= 120 µA, V_ADIM> 2.1 V

A80606

●

850

950

1050

mV

LEDx Regulation Voltage

V_LED

A80606-1

●

960

955

1060

978

0.985

−

1160

1000

1.015

185

mV

A/A

V

I_ISETto I_LEDxCurrent Gain

ISET Pin Voltage

A_ISET

V_ISET

i_ISET

i_ISET= 120 µA

V_ADIM> 2.1 V

0.955

20

Allowable ISET Current

●

µA

Sensed from each LED pin to GND while its current

sink is in regulation; all other LED pins tied to 1 V

LED String Partial-Short Detect

V_LEDSD

t_LEDSTG

4.85

5.5

1.5

6.1

V

LED Pin Shorted-to-GND Test

Duration ^[2]

Wait time before proceeding with Soft-Start (if

no LED pin is shorted to GND)

−

ms

Maximum time duration before all LED

channels come into regulation, or OVP is

tripped, whichever comes first

Soft-Start Ramp-Up Time ^[2]

t_SSRU

12.4

16.4

20.5

ms

EN goes from High to Low; exceeding t_EN(OFF)

results in IC shutdown

Enable Pin Shut Down Delay

Minimum PWM On-Time

t_EN(OFF)

t_PWMH

●

10

−

16

0.3

−

22

0.4

315

ms

µs

ns

First and subsequent PWM pulses

Minimum PWM Off-Time

(for PWM ≠ 100%)

Externally pulsing PWM pin (guaranteed by

design)

t_PWMLOW

−

INPUT DISCONNECT GATE PIN

Gate Pin Sink Current

I_GSINK

V_GS= V_IN, no input OCP fault

−

−113

−

µA

Gate Pin Source Current

I_GSOURCE

V_GS= V_IN– 6 V, input OCP fault tripped

6

mA

Gate Shutdown Delay When Over-

Current Fault Is Tripped ^[2]

t_GATEFAULT

V_GS

V_IN– V_SENSE= 200 mV; monitored at FAULT pin

−

3

µs

V

PMOS Gate to source voltage measured when

gate is on

Gate Voltage

−6.7

−

VSENSE PIN

VSENSE Pin Sink Current

VSENSE Trip Point

PEB PIN

i_ADJ

●

16

88

20

98

24

µA

V_SENSETRIPMeasured between V_INand V_SENSE, R_ADJ= 0 Ω

108

mV

i_PEB= 60 µA

3.2

5.6

4.6

8.1

6.0

µs

PEB Delay Time

t_PEB

i_PEB= 100 µA

10.5

FAULT PIN

FAULT Output Pull-Down Voltage

FAULT Pin Leakage Current

External FAULT Input Low

External FAULT Input High

V_FAULT

I_FAULT-LKG

V_FIL

i_FAULT= 1 mA

−

0.5

1

V

µA

V

V_FAULT= 5 V

No internal faults; FAULT pin externally pulled down

No internal faults

●

−

0.8

−

V_FIH

1.5

V

No internal faults; delay (in f_SWcycles) from

FAULT pin externally pulled L to LED off;

ignored if FAULT returns to H before that

External FAULT Deglitch Timer

t_FIL

−

8

−

cycles

Continued on the next page…

8

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ELECTRICAL CHARACTERISTICS ^[1](continued): Unless otherwise noted, speciﬁcations are valid at V_IN= 12 V, T_J= 25°C, • indi-

cates speciﬁcations guaranteed over the full operating temperature range with T_J= –40°C to 125°C, typical speciﬁcations are at T_J= 25°C

Characteristics

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

THERMAL PROTECTION (TSD)

Thermal Shutdown Threshold ^[2]

Thermal Shutdown Hysteresis ^[2]

T_SD

Temperature rising

155

170

20

−

°C

T_SDHYS

−

^[1]For input and output current specifications, negative current is defined as coming out of the node or pin (sourcing);

positive current is defined as going into the node or pin (sinking).

^[2]Ensured by design and characterization; not production tested.

^[3]Minimum V_IN= 4.5 V is only required at startup. After startup is completed, IC can continue to operate down to V_IN= 4 V.

^[4]LED current is trimmed to cancel variations in both Gain and ISET voltage.

9

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

APPLICATION EXAMPLE

ꢁ_ꢂN

ꢃ1

ꢁ_ꢀUꢅ≤ ꢊ0 ꢁ

ꢇ1

ꢓ1

ꢉ_ꢂN

ꢉ_ꢀUꢅ

R_ꢀꢁP1

R_ꢀꢁPꢋ

ꢉ_ꢁꢃRꢁ

ꢁꢂN

ꢄꢃRꢁ

ꢁꢃRꢁ

ꢄAꢅꢆ

PꢄNꢃ

ꢄꢃRꢁ

ꢁꢃRꢁ

ꢄAꢅꢆ

PꢄNꢃ

ꢀꢁP

ꢉS

ꢁSꢆNSꢆ

ꢁꢂN

ꢁSꢆNSꢆ

ꢀꢁP

ꢁ_ꢉ

ꢉ_ꢁꢃꢃ

ꢁꢂN

ꢉ_ꢁꢃRꢁ

ꢁꢃꢃ

R_PU

ꢇꢆꢃ1

A80606-1

ꢀꢁAꢂꢃERꢄ

A80606-1

ꢀꢂLAꢅEꢄ

ꢇꢆꢃꢋ

ꢇꢆꢃ3

ꢇꢆꢃꢋ

ꢇꢆꢃ3

ꢈAUꢇꢅ

ꢆN

ꢈAUꢇꢅ

ꢆN

PꢍM

Uꢐ to 1ꢑ0 mA ꢒ

AꢃꢂM

ꢉꢀMP

Pꢆꢎ

ꢉꢀMP

Pꢆꢎ

ꢉꢇꢏꢀUꢅ

AꢄNꢃ

ꢉꢇꢏꢀUꢅ

AꢄNꢃ

ꢈSꢆꢅ

ꢂSꢆꢅ

ꢃꢂꢅH

ꢈSꢆꢅ

ꢂSꢆꢅ

ꢃꢂꢅH

R_ꢌ

ꢉ_P

R_ꢃꢂꢅH

ꢉ_ꢃꢂꢅH

R_Pꢆꢎ

R_ꢂSꢆꢅ

R_ꢈSꢆꢅ

R_Pꢆꢎ1

R_ꢂSꢆꢅ

R_ꢈSꢆꢅ

ꢉ_ꢌ

Figure 4: Two A80606-1 connected in Master/Slave Conﬁguration to drive 180 mA × 12 LED strings

Remarks on Master-Slave configuration:

• Only one Slave to a Master.

• Master-Slave operation requires asymmetrical COMP (for example: source = –700 µA and

sink = 500 µA). This is available in A80606-1 only.

• Also requires bidirectional FAULT pin of A80606-1, so that the slave can halt the switching of master.

10

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

FUNCTIONAL DESCRIPTION

The A80606 is a multi-string LED regulator with six preci-

sion current sinks and a gate driver for external boost MOSFET

switch. It incorporates a patented Pre-Emptive Boost (PEB)

control algorithm to achieve PWM dimming ratio over 15,000:1

at 200 Hz. PEB control also minimizes output ripple to avoid

audible noise from output ceramic capacitors.

Only if no faults were detected, then the IC can proceed to start

switching.

As long as EN = H, the PWM pin can be toggled to control the

brightness of LED channels by using PWM dimming. Alterna-

tively, EN and PWM can be tied together to allow single-wire

control for both power on/off and PWM dimming. If EN is pulled

low for longer than 16 ms, the IC shuts off.

The switching frequency can be either synchronized to an

external clock or generated internally. Spread-spectrum tech-

nique (with user-programmable dithering range and modulation

frequency) is provided to reduce EMI. A clock-out signal (CLK-

OUT) allows other converters to be synchronized to the switching

frequency of A80606.

Enabling the IC

The A80606 wakes up when EN pin is pulled above logic high

level, provided that VIN pin voltage is over the VIN_UVLO

threshold. The boost stage and LED channels are enabled sepa-

rately by PWM = H signal after the IC powers up.

The IC performs a series of safety checks at power up, to deter-

mine if there are possible fault conditions that might prevent the

system from functioning correctly. Power-up checks include:

• VOUT shorted to GND

Figure 5: Startup showing EN, VDD, CLKOUT, and ISET (PWM = L).

Note that CLKOUT is available as soon as V_DDramps up, even

though Boost stage and LED drivers are not yet enabled.

• LED pin shorted to GND

• FSET pin open/shorted

• ISET pin open/shorted to GND, etc.

11

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Unused LED pin should be terminated with a resistor to GND.

Powering Up: LED Detection Phase

The value of this termination resistor is 4.75 kΩ for channels 1,

3, 4 and 6 or 2.37 kΩ for channels 2 and 5. At the end of LED

detection phase, any channel with pull down resistor is then dis-

abled and will not contribute to the boost regulation loop.

The VIN pin has an undervoltage lockout (UVLO) function that

prevents the A80606 from powering up until the UVLO threshold is

reached. Once the VIN pin goes above UVLO and a high signal is

present on the EN pin, the IC proceeds to power up. At this point, the

A80606 is going to enable the disconnect switch and will try to check

if any LED pins are shorted to GND and/or are not used. The LED

detection phase starts when PWM = H and the GATE voltage of the

input disconnect PMOS switch is pulled down to 3.3 V below V_IN.

ꢅꢆUꢇ

Using

ꢌhannels 1-ꢈ

ꢀꢁꢂ1

ꢀꢁꢂꢋ

ꢀꢁꢂ3

ꢀꢁꢂꢈ

ꢀꢁꢂ5

ꢌhannels 5-ꢃ

are disaꢍled

ꢀꢁꢂꢃ

ꢄNꢂ

ꢈ.ꢉ5 ꢊΩ

ꢋ.3ꢉ ꢊΩ

Figure 7: How to signal an unused LED channel

during startup LED detection phase

Table 1: LED Detection phase voltage threshold levels

LED Pin

Interpretation

Outcome

Voltage Measured

Cannot proceed with

soft-start unless fault

is removed

Figure 6: Startup showing EN+PWM, GATE, LED1, and ISET. Note

that LED Detection Phase starts as soon as GATE pin is pulled

down to 3.3 V below V_IN(provided that PWM = H).

LED pin shorted to

GND fault

< 120 mV

LED channel is

removed from

operation

LED channel not in

use

Once the voltage threshold on VLED pins exceeds ~120 mV, a

delay of approximately 1.5 ms is used to determine the status of

the pins.

~230 mV

> 340 mV

LED channel in use

Proceed with soft-start

12

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

If an LED pin is shorted to ground, the A80606 will not proceed

with soft start until the short is removed from the LED pin. This

prevents the A80606 from ramping up the output voltage and put-

ting an uncontrolled amount of current through the LEDs.

The FAULT pin is pulled low in case of LED pin shorted-to-GND

fault, but the IC continues to retry. Once the fault is removed, the

soft-start process will continue. The same applies in case of FSET

or ISET pin is shorted to GND.

Figure 8: Normal startup showing all channels passed LED Detec-

tion phase (only LED1 and LED2 pin voltages are shown). Total

LED current = 100 mA × 4.

Figure 10: LED1 is shorted-to-GND initially, then released. After the

fault is removed, the IC auto-recovers and proceeds with soft-start.

FAULT is released at the end of LED detection phase.

Figure 9: Normal startup showing LED1 channel is disabled with a

4.75 kΩ resistor to GND. Total LED current = 100 mA × 3

13

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

This is illustrated by the following startup timing diagram (not to

scale):

Power Up: Boost Output Undervoltage

During startup, after the input disconnect switch has been

enabled, the output voltage is checked through the OVP (over-

voltage protection) pin. If the sensed voltage does not rise above

V_UVP(th), the output is assumed to be at fault and the IC will not

proceed with soft start. Output UVP level is linked to the OVP

level programmed according to the equation:

Eꢀ

Pꢁꢂ

ꢀꢁN

3.3 ꢀ

ꢂ.ꢃ ꢀ

ꢃAꢄE

0

V_UVP= V_OVP/ 12

1 ꢀ

LEDꢆ

0

Undervoltage protection may be caused by one of the following

faults:

ꢆꢇꢈ detection

ꢉhase

ꢌ1

ꢌꢍ

ꢄꢀP

93ꢅ ꢄꢀP

1.5 ms

• Output capacitor shorted to GND

• Boost inductor or diode open

• OVP sense resistor open

ꢅOUꢄ

ꢀꢁN

0

After an UVP (undervoltage protection) fault, the A80606 is

immediately shutdown and latched off. To enable the IC again,

the latched fault must be cleared. This can be achieved by

powering-cycling the IC, which means either:

t_SSRU

i_LED

0

Soꢊt-Start

Regꢋlation

A

B

ꢇ

D

E

• V_INfalls below falling UVLO threshold, or

• EN = L for >16 ms.

Figure 11: Complete startup process of A80606

Explanation of Events:

Alternatively, latched fault can be cleared by keeping EN = H but

pulling PWM = L for >16 ms. This method has the advantage that

it does not interrupt the CLKOUT signal.

A: EN = H wakes up the IC. V_DDramps up and CLKOUT

becomes available. IC starts to pull down GATE slowly.

Soft Start Function

B: When GATE is pulled down to 3.3 V below V_IN, I_SETbecomes

enabled. IC is now waiting for PWM = H to startup.

During startup, the A80606 ramps up its boost output voltage

following a fixed slope, as determined by OVP set point and Soft-

Start Timer. This technique limits the input inrush current, and

ensures consistent startup time regardless of the PWM dimming

duty cycle.

C: Once PWM = H, the IC checks each LEDx pins to determine

if it is in use, disabled, or shorted to GND.

D: Soft-Start begins at the completion of LED pin short-detect

phase of ~1.5 ms. V_OUTramps up following a fixed slope set by

OVP and soft-start timer of ~16 ms.

The soft-start process is completed when any one of the follow-

ing conditions is met:

E: Soft-start terminates when all LED currents reached regula-

• All enabled LED channels have reached their regulation

current,

• Output voltage has reached 93% of its OVP threshold, or

• Soft-start ramp time (t_SS) has expired.

tion, V_OUTreached 93% OVP, or soft-start timer expired.

Note when PWM pulse is significant small (depending on the

operating conditions), A80606 is in open loop regulation and the

output voltage will be regulated to OVP level in the steady state

as shown in curve C1; otherwise A80606 will regulate the output

voltage to the expected LED load voltage in the closed loop regu-

lation (as shown in curve C2).

To summarize, the complete startup process of A80606 consists

of:

• Power-up error checking

• Enabling input disconnect switch

• LED pin open/short detection

• Soft-start ramp

14

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Frequency Selection

t _{PꢂSꢃNꢄꢅN}

15ꢁ ns

The switching frequency of the boost regulator is programmed

by a resistor connected to FSET pin. The switching frequency

can be selected anywhere from 200 kHz to 2.3 MHz. The chart

below shows the typical switching frequency verses FSET resis-

tor value.

150 ns

t_{PꢂSꢃNꢄꢅꢆꢆ}

t ꢀ ꢁ5ꢁ ns

Figure 13: Pulse width requirements

for an External Sync clock at 2.2 MHz

Based on the above, any clock with a duty cycle between 33%

and 66% at 2.2 MHz can be used. The table below summarizes

the allowable duty cycle range at various synchronization fre-

quencies.

Table 2: Acceptable Duty Cycle range for External Sync

clock at various frequencies

Sync. Pulse Frequency

2.2 MHz

Duty Cycle Range

33% to 66%

2 MHz

30% to 70%

1 MHz

15% to 85%

600 kHz

9% to 91%

Figure 12: Switching Frequency

as a function of FSET Resistance

300 kHz

4.5% to 95.5%

Alternatively, the following empirical formula can be used:

If it is necessary to switch over between internal oscillator and

external sync during operation, ensure the transition takes place

at least 500 ns after the previous PWM = H rising edge. Alterna-

tively, execute the switchover during PWM = L only. This restric-

tion does not apply if PWM dimming is not being used.

Equation 1:

R_FSET= (21.5 / f_SW) – 0.2

where f_SWis in MHz and R_FSETis in kΩ.

If a fault occurs during operation that will increase the switch-

ing frequency, the internal oscillator frequency is clamped to a

maximum of 3.5 MHz. If the FSET pin is shorted to GND, the

part will shut down. For more details, refer to the Fault Mode

Table section.

Eꢌ

Pꢀꢁ

500 ns

Synchronization

Eꢂtꢃꢄꢅnꢆ

ꢇ ꢈꢄEꢉ

1 ꢀ

The A80606 can also be synchronized using an external clock.

At power up, if the FSET pin is held low, the IC will not start.

Only when the FSET pin is tristated to allow for the pin to rise to

about 1 V, or when a sync clock is detected, the A80606 will then

try to power up.

ꢊLꢋOUꢉ

ꢁnternal oscillator

ꢂꢃternal Sync

Figure 14: Avoid switching over between Internal

Oscillator and External Sync in highlighted region

The basic requirement of the external sync signal is 150 ns

minimum on-time and 150 ns minimum off time. The diagram

below shows the timing restrictions for a synchronization clock at

2.2 MHz.

15

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ꢁꢆternal

Loss of External Sync Signal

Sychroniꢇation

ꢋꢋ0ꢌꢀ

Signal

Suppose the A80606 started up with a valid external SYNC sig-

nal, but the SYNC signal is lost during normal operation. In that

case, one of the following happens:

ꢀSꢁꢂꢃSꢄNꢅ

R_ꢀSꢁꢂ

10kΩ

Schottꢈy

ꢉarrier

ꢊiode

• If the external SYNC signal is high impedance (open), the

IC continues normal operation after approximately 5 μs, at

the switching frequency set by R_FSET. No FAULT flag is

generated.

Figure 15: Countermeasure for

External Sync Stuck-at-Low Fault

• If the external SYNC signal is stuck low (shorted to ground),

the IC will detect an FSET-shorted-to-GND fault. FAULT

pin is pulled low after approximately 10 μs, and switching is

disabled. Once the FSET pin is released or SYNC signal is

detected again, the IC will proceed to soft-start.

It is important to use a small capacitance for the AC-coupling

capacitor (220 pF in the above example). If the capacitance is too

large, the IC may incorrectly declare a FSET-shorted-to-GND

fault and restart.

To prevent generating a fault when the external SYNC signal

is stuck at low, the circuit shown below can be used. When the

external SYNC signal goes low, the IC will continue to operate

normally at the switching frequency set by the R_FSET. No FAULT

flag is generated.

16

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

3 kHz. In practice, using a larger dithering range and/or higher

modulation frequency do not generate any noticeable benefits.

Switching Frequency Dithering

To minimize the peak EMI spikes at switching frequency har-

monics, the A80606 offers the option of frequency dithering, or

spread-spectrum clocking. This feature simplifies the input filters

needed to meet the automotive CISPR 25 conducted and radiated

emission limits.

If dithering function is not desired, it can be disabled by discon-

necting the R_DITHbetween DITH and FSET pins. Connect DITH

pin to VDD if C_DITHis not populated. Dithering is always dis-

abled when f_SWis controlled by external sync. R_DITHand C_DITH

have no effects in this case even if they were populated.

For maximum flexibility, the A80606 allows both dithering range

and modulation frequency to be independently programmable

using two external components.

Clock Out Function

The A80606 allows other ICs to be synchronized to its internal

switching frequency through the CLKOUT pin.

The Dithering Modulation Frequency capacitor value is deter-

mined by using the approximate equation:

The CLKOUT signal is available as soon as the IC is enabled

(EN = H), even when the boost stage is not active (PWM = L).

Its frequency is the same as that of the internal oscillator. Its

duty cycle; however, depends on how the switching frequency is

generated:

Equation 2:

C_DITH(nF) = 25 / f_DM(kHz)

where C_DITHis the value of capacitor connected from DITH

pin to GND.

The resistor that sets the dithering range is calculated using the

approximate equation:

• If f_SWis programmed by FSET resistor, the CLKOUT duty

cycles is approximately 50%.

Equation 3:

R_DITH= (20 × R_FSET) / Range (±%)

• If f_SWis controlled by external sync, the output signal has a

fixed 200 ns negative pulse width (CLKOUT = L), regardless

of the external sync frequency.

where R_FSETis the resistor from FSET pin to GND, R_DITHis

the resistor between DITH and FSET pins.

This is illustrated by the following waveforms:

As an example, by using R_FSET= 10 kΩ, R_DITH= 40.1 kΩ,

and C_DITH= 22 nF, the resulted switching frequency is f_SW

=

2.15 MHz ±5% modulated at 1.1 kHz. This is illustrated by the

following diagram.

ꢄ_DꢃꢂH

i

_ꢀꢁEꢂꢉ 100 ꢋA

ꢊ5 ꢋA

ꢀꢁEꢂ

DꢃꢂH

1.ꢆ ꢍ

1.0 ꢍ

0.ꢌ ꢍ

i_DꢃꢂHꢉ ꢊꢆ0 ꢋA

ꢄ_ꢇSꢈꢂ

R_ꢀꢁꢂH

ꢃ0.1 ꢄΩ

R_ꢇSꢈꢂ

10 ꢄΩ

ꢅ_ꢀꢁꢂH

ꢆꢆ nꢇ

i_DꢃꢂH

ꢆ0 ꢋA

0

ꢀithering Range ꢉ

ꢊ5ꢗ

ꢎꢆ0 ꢋA

Modꢓlation

ꢔreꢕꢓency

ꢉ 1.1 ꢄHꢖ

Period ꢉ 0.ꢌ ꢏ ꢅ ꢐ i

ꢑ0.ꢌꢌ ms when ꢅ ꢉ ꢆꢆ nꢇꢒ

f_ꢁꢅꢆꢇHꢈꢉ

ꢆ.ꢆ5

ꢆ.15

ꢆ.05

ꢂime ꢑmsꢒ

0

0.ꢌꢌ

Figure 17: Without external sync, the CLKOUT signal has a ﬁxed

duty cycle of 50%. Delay from CLKOUT falling edge to SW falling

edge is approximately 50 ns.

Figure 16: How to Program Switching Frequency

Dithering Range and Modulation Frequency

There are no hard limits on dithering range and modulation

frequency. As a general guideline, pick a dithering range between

±5% and 10%, with the modulation frequency between 1 kHz and

17

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

PWM Dimming

When both EN and PWM pins are pulled high, the A80606 turns

on all enabled LED current sinks. When either EN or PWM is

pulled low, all LED current sinks are turned off but critical inter-

nal circuits remain active.

Figure 18: With external sync, the CLKOUT signal has a ﬁxed

negative pulse width of 200 ns. Delay from SYNC rising edge to

CLKOUT falling edge is approximately 60 ns.

LED Current Setting

The maximum LED current can be up to 140 mA per channel,

and is set through the ISET pin. Connect a resistor R_ISETbetween

this pin and GND. The relation between I_LEDand R_ISETis given

below:

Figure 19: PWM dimming operation at 20% 1 kHz. CH1 = PWM (5 V/

div), CH2 = SW (20 V/div), CH3 = V_OUT, CH4 = i_LED(200 mA/div).

By using the patented Pre-Emptive Boost (PEB) control algo-

rithm, the A80606 is able to achieve minimum PWM dimming

on-time down to 300 ns. This translates to PWM dimming ratio

up to 15,000:1 at the PWM dimming frequency of 200 Hz. Tech-

nical details on PEB will be explained in the next section.

Equation 4:

I_LED= I_SET× A_ISET

I_SET= V_ISET/ R_ISET

Note that when PWM pulse duration is decreased to below 500 ns,

the output of the converter may ramp up to the output OV thresh-

old and hysteretically regulate around this threshold. This is accept-

able operation; however, this will cause the fault flag to repeatedly

assert low. Fault must be ignored when operating in this mode.

Therefore R_ISET= (V_ISET× A_ISET) / I_LED

= 963 / I_LED

where I_LEDcurrent is in mA and R_ISETis in kΩ.

This sets the maximum current through the LEDs, referred to

as the ‘100% current’. The average LED current can be reduced

from the 100% current level by using either PWM dimming or

analog dimming.

Table 3: ISET resistor values vs. LED current. Resistances

are rounded to the nearest E-96 (1%) resistor value.

Standard Closest RISET

LED current per channel

Resistor Value

5.36 kΩ

6.49 kΩ

9.53 kΩ

12 kΩ

180 mA

150 mA

100 mA

80 mA

60 mA

40 mA

16 kΩ

24 kΩ

Figure 20: Zoom in view for PWM on-time = 10 µs. Notice that the

LED current is shifted with respect to PWM signal. Ripple at V_OUT

is ~0.2 V when using 2 × 4.7 µF MLCC as output capacitors.

18

Allegro MicroSystems

955 Perimeter Road

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www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Common scope settings:

CH1 (Yellow) = PWM (5 V/div); CH2 (Red) = Inductor current

(500 mA/div); CH3 (Blue) = V_OUT(1 V/div); CH4 (Green) =

LED current (200 mA/div); time scale = 2 µs/div.

Figure 21: Zoom-in view showing A80606 is able to regulate LED

current at PWM on-time down to 300 ns.

The typical PWM dimming frequencies fall between 200 Hz and

1 kHz. There is no hard limit on the highest PWM dimming fre-

quency that can be used. However at higher PWM frequency, the

maximum PWM dimming ratio will be reduced. This is shown in

the following table:

Figure 22: Traditional PWM Dimming operation where boost switch

and LED current are enabled at the same time. Note that V_OUT

shows overall ripple of ~0.5 V

Table 4: Maximum PWM Dimming Ratio that can be achieved

when operating at different PWM Dimming Frequency

When PWM signal goes high, a conventional LED driver turns

on its boost switching at the time with LED current sinks. The

problem is that the inductor current takes several switching cycles

to ramp up to its steady-state value before it can deliver full

power to the output load. During the first few cycles, energy to

the LED load is mainly supplied by the output capacitor, which

results in noticeable dip in output voltage.

Maximum PWM

PWM Frequency

PWM Period

Dimming Ratio

15,000:1

3,000:1

200 Hz

1 kHz

5 ms

1 ms

3.3 kHz

20 kHz

300 µs

50 µs

1,000:1

150:1

While it is possible to operate with very high PWM duty cycle for

subtle dimming, it is important to avoid PWM pulse low periods

that are shorter than the Minimum PWM Off-Time (t_PWMLOW),

which is 315 ns. Driving PWM at 100% is acceptable.

Pre-Emptive Boost

The basic principle of pre-emptive boost (PEB) can be best

explained by the following two waveforms. The first one shows

how a conventional LED driver operates during PWM dimming

operation. The second one shows that of the A80606.

Common test conditions for both cases:

PWM = 1% at 1 kHz (on-time = 10 µs), f_SW= 2.15 MHz,

L = 10 µH, V_IN= 12 V, LED load = 8 series (V_OUT= ~25 V)

at 100 mA × 4. C_OUT= 2 × 4.7 µF 50 V 1210 MLCC.

COMP: R_Z= 280 Ω, C_Z= 68 nF.

Figure 23: A80606 PWM dimming operation with PEB delay set to

3 µs. Note that V_OUTripple is reduced to ~0.2 V.

19

Allegro MicroSystems

955 Perimeter Road

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www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

In the A80606, the boost switch is also enabled when PWM goes

high. However, the LED current is not turned on until after a

short delay of t_PEB. This allows the inductor current to build up

before it starts to deliver the full power to LED load. During the

pre-boost period, V_OUTactually bumps up very slightly, while

the following dip is essentially eliminated. When PWM goes low,

both boost switching and LED remains active for the same delay

of t_PEB. Therefore the PWM on-time is preserved in LED current.

can significantly reduce the output ripple voltage compared to a

conventional LED driver.

A80606

ꢃ_ꢂN

ꢂ_Pꢀꢁ

Pꢀꢁ

R_Pꢄ

PEB delay can be programmed using an external resistor, R_PEB

,

from PEB pin to GND. Their relationship is shown in the follow-

ing chart:

R_Pꢁ

13.0

12.0

11.0

10.0

9.0

Figure 25: PEB delay setup circuit with connection to V_IN

12.0

11.0

10.0

9.0

8.0

7.0

6.0

8.0

5.0

7.0

4.0

6.0

3.0

2.0

5.0

1.0

4.0

0.0

3.0

6

8

10

12

14

R_PEB(kΩ)

16

18

20

22

24

V_IN= 18 V

V_IN= 12 V

V_IN= 6 V

2.0

1.0

0.0

Figure 24: How PEB delay time varies with value of PEB pin resis-

tor to GND.

Ideally, t_PEBis equal to the inductor current ramp up time.

But the latter is affected by many external parameters, such

as switching frequency, inductance, V_INand V_OUTratio, etc.

Therefore, some experimentation is required to optimize the

PEB delay time. A simple guideline is to set PEB delay at

nominal V_INequal to 3 switching cycles (longer at lower V_IN).

In general for switching frequency at 500 kHz, t_PEB= 6 to 12 µs

is a good starting point.

20

30

40

50

60

70

I_PEB(µA)

80

90

100 110 120

Figure 26: PEB delay t_PEBvs. PEB pin current

Analog Dimming

The peak (100%) level of LED current is set by the R_ISETresistor.

The actual peak LED current may also be adjusted continuously

from approximately 10% up to 100%, by using the ADIM pin.

There are two methods to do so:

Additionally, adding a resistor from PEB to VIN (as shown

below) can extend PEB delay when V_INbecomes lower. Refer

to the PEB delay versus PEB pin current below; for example,

at switching frequency 400 kHz, set I_PEB= 80 μA to obtain

~5.88 μs PEB delay at V_IN= 12 V by choosing R_PB= 8.45 kΩ

and R_PT= 604 kΩ (PEB voltage is fixed). When V_INlowers to

6 V, PEB delay becomes longer at 6.8 μs with I_PEB= 90 μA. If

V_INincreases to 18 V, PEB delay will be 5.2 μs.

1. In ADIM mode: apply a DC voltage between 0.2 V and 2 V

at the pin.

2. In APWM mode: apply a clock signal with duty cycle be-

tween 90% and 0% at the pin.

ADIM MODE

An analog voltage is applied at the ADIM/APMW pin. This DC

The advantage of PEB is that even a non-optimized delay time

20

Allegro MicroSystems

955 Perimeter Road

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A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

voltage linearly controls the peak LED current, as illustrated by

the chart below:

Normalized LED Current vs. APWM Duty Cycle

100ꢀ

80ꢀ

60ꢀ

40ꢀ

20ꢀ

0ꢀ

Nꢊꢅꢎꢌꢋꢏꢐꢆꢑ ꢁEꢂ ꢃꢄꢅꢅꢆꢇt ꢒs. ꢈꢂIꢉ Vꢊꢋtꢌꢍꢆ

100ꢀ

ꢊꢆꢎsꢄꢅꢆꢏ

90ꢀ

80ꢀ

70ꢀ

60ꢀ

50ꢀ

ꢐꢑꢆꢒꢅꢆ�ꢌꢎꢍ

ꢈꢂIꢉ ꢂꢆꢓꢅꢆꢌsꢏꢇꢍ

40ꢀ

ꢈꢂIꢉ Iꢇꢓꢅꢆꢌsꢏꢇꢍ

30ꢀ

0ꢀ

20ꢀ

40ꢀ

60ꢀ

80ꢀ

100ꢀ

ꢈPꢉꢊ ꢂꢄtꢋ ꢃꢋꢌꢍꢆ

20ꢀ

10ꢀ

0ꢀ

Figure 28: Showing LED current is inversely proportional to the

APWM duty cycle. Test conditions: V_IN= 12 V, V_OUT= 25 V (8 ×

WLED), total LED current = 100 mA × 4, APWM frequency = 100 kHz

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

ꢈꢂIꢉ Vꢊꢋtꢌꢍꢆ (V)

As an example, a system that delivers a full LED current of

100 mA per channel would deliver 75 mA when an APWM signal

with a duty-cycle of 25% is applied (because analog dimming

level is 100% – 25% = 75%). This is demonstrated by the fol-

lowing waveforms (only LED channels 1 to 4 are enabled).

Figure 27: In analog dimming mode, the LED current is linearly pro-

portional to ADIM voltage between 0.2 V and 2 V approximately

There is an internal pull-down resistor (100 kΩ typical) from

ADIM pin to GND. When this pin is left floating, LED current

is actually being dimmed down to ~10%. Therefore, if analog

dimming is not required, the ADIM pin should be pulled to over

2 V (but below V_DD) to ensure 100% LED current. One simple

technique is to pull up ADIM to VDD through a 30 kΩ resistor.

APWM MODE

When a clock signal is detected at ADIM pin, the A80606 goes

into APWM mode. The typical APWM signal frequency is

between 40 kHz and 1 MHz. The duty cycle of this signal is

inversely proportional to the percentage of current delivered to

the LED. The relationship is shown below:

Figure 29: PWM = H. Total LED current drops from 400 mA (4 ×

100 mA/ch) to 300 mA when APWM of 25% duty cycle is applied.

Note that LED current takes ~1 ms to settle after change in APWM.

21

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

and analog dimming method.

For example, the following approach can be used to achieve a

100,000:1 dimming ratio at 200 Hz:

• Vary PWM duty cycle from 100% down to 0.01% to give

10,000:1 dimming. This requires PWM dimming on-time be

reduced down to 0.5 µs.

• With PWM dimming on-time fixed at 0.5µs, vary APWM duty

from 0% to 90% to reduce peak LED current from 100% down

to 10%. This gives a net effect of 100,000:1 dimming.

Average LED Current vs. PWM Dimming Duty Cycle

100

10

Figure 30: PWM = 10% at 1 kHz. Peak LED current drops from

400 mA (4 × 100 mA/ch) to 300 mA when APWM of 25% duty cycle

is applied

1

0.1

One popular application of analog dimming is for LED brightness

calibration, commonly known as ‘LED Binning’. LEDs from

the same manufacturer and series are often grouped into differ-

ent ‘bins’ according to their light efficacy (lumens per watt). It is

therefore necessary to calibrate the ‘100% current’ for each LED

bin, in order to achieve uniform luminosity.

Pꢏꢐ ꢊꢅꢂꢂꢅꢍꢑ

ꢔPꢏꢐ ꢕ Pꢏꢐ

Iꢈꢇꢃꢄ

0.01

0.001

To use ADIM pin as a trim function, the user should first set the

100% current based on efficacy of LED from the lowest bin.

When using LED with higher efficacy, the required current is then

trimmed down to the appropriate level using APWM duty cycle.

0.001

0.01

0.1

1

10

100

Pꢏꢐ ꢊꢅꢂꢂꢅꢍꢑ ꢊꢌtꢒ ꢋꢒꢓꢄꢇ (ꢎ)

As an example, assume that:

Figure 31: How to achieve 100,000:1 dimming ratio by using both

PWM and APWM. Test conditions: V_IN= 12 V, V_OUT= 25 V (8 ×

WLED), total LED current = 400 mA, PWM frequency = 200 Hz,

APWM frequency = 100 kHz.

• LED from lowest bin has an efficacy of 80 lm/W

• LED highest bin has an efficacy of 120 lm/W

Suppose the maximum LED current was set at 100 mA based

on LEDs from lowest bin. When using LEDs from highest bin,

the current should then be reduces to 67% (80/120). This can be

achieved by sending APWM clock with 33% duty cycle.

Note that the A80606 is capable of providing analog dimming

range greater than 10:1. By applying APWM with 96% duty

cycle, for example, an analog dimming range of 25:1 can be

achieved. However, this requires the external APWM signal

source to have very fine pulse-width resolution. At 200 kHz

APWM frequency, a resolution of 50 ns is required to adjust its

duty cycle by 1%.

Extending LED Dimming Ratio

The dynamic range of LED brightness can be further extended,

by using a combination of PWM duty cycle, APWM duty cycle,

22

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955 Perimeter Road

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A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

In the following application example, the thermistor used is NTC-

Analog Dimming with External Voltage

S0805E3684JXT (680 kΩ @ 25°C). R1 = 336 kΩ, R2 = 20 kΩ,

and R3 = 8.45 kΩ. The LED current per channel is reduced from

97 mA at 25°C to 34 mA at 125°C.

Besides using ADIM pin, the LED current can also be reduced

by using an external voltage source applied through a resistor

to the ISET pin. The dynamic range of this type of dimming is

dependent on the ISET pin current. The recommended i_SETrange

is from 20 µA to 144 µA for the A80606. Note that the IC will

continue to work at i_SETbelow 20 µA, but the relative error in

LED current becomes larger at lower dimming level.

ꢀꢁꢁ

ꢂꢃ.ꢄ5 ꢀꢅ

Aꢉ0ꢊ0ꢊ

Nꢀꢁ

Rꢄ

ꢆSꢇꢈ

ꢂ1.0 ꢀꢅ

Below is a typical application circuit using a DAC (digital-analog

converter) to control the LED current. The ISET current (which

R1

directly controls the LED current) is normally set as V_ISET/R_ISET

.

ꢋNꢁ

R3

The DAC voltage can be higher or lower than V_ISET, thus adjust-

ing the LED current to a lower or higher value.

Figure 33: Thermal foldback of

LED current using NTC thermistor

Aꢃ0ꢄ0ꢄ

Rꢅ

ꢈꢇAꢉ

ꢀSꢁꢂ

R_ꢀSꢁꢂ

ꢆNꢇ

Figure 32: Adjusting LED current

with an external voltage source

Equation 5:

V_ISET

R_ISET

VDAC −V

R2





ISET

i_ISET

=

−









where V_ISETis the ISET pin voltage (typically 1.0 V), and

VDAC is the DAC output voltage.

Figure 34: LED current varies with temperature

when using thermistor NTCS0805E3684JXT

for thermal foldback

When VDAC is higher than 1.00 V, the LED current is reduced.

When VDAC is lower than 1.00 V, the LED current is increased.

Some common applications for the above scheme include:

• LED binning

• Thermal fold-back using external NTC (negative temperature

coefficient) thermistor

23

Allegro MicroSystems

955 Perimeter Road

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www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

There is an alternative way to reset the internal fault status reg-

isters. By keeping EN = H and PWM = L for longer than 16 ms,

the A80606 clears all internal fault registers but does not go into

sleep mode. The next time PWM pin goes high, the IC will still

go through soft start process. The difference is that VDD voltage

and CLKOUT signal are always available as long as EN = H.

VDD

The VDD pin provides regulated bias supply for internal circuits.

Connect a C_VDDcapacitor with a value of 1 μF or greater to this

pin. The internal LDO can deliver up to 2 mA of current with a

typical VDD voltage of about 4.25 V. This allows it to serve as

the pull up voltage for FAULT pin.

VDRV

The VDRV pin provides a regulated gate driver supply for

external boost power MOSFET. Connect a C_VDRVcapacitor with

a typical value of 2.2 μF to this pin. The gate driver can deliver

up to 2 A of peak sink and source current, with a typical V_DRV

voltage of 6.5 V. However, its average output current is limited to

approximately 36 mA. Note that average gate driver current is:

Equation 6:

i_VDRV= f_SW× Q_G

where f_SWis the switching frequency and Q_Gis the total gate

charge of the power MOSFET for V_GS= 0 to 6.5 V.

At higher switching frequency, it is important to select a power

MOSFET with low Q_Gto limit the average gate driver current.

Refer to the appendix section for details on MOSFET selection.

Figure 36: As long as EN = H, the IC does not shut down VDD and

CLKOUT. But internal latched faults are cleared by PWM = L for

~16 ms.

Shutdown

If the EN pin is pulled low for longer than t_EN(OFF)(~16 ms), the

A80606 enters shutdown (sleep mode). The next time the EN pin

goes high, all internal fault registers are cleared. The IC needs to

go through a complete soft start process after PWM goes high.

Figure 35: After EN = L for ~16 ms, the IC completely shuts down

so VDD (Blue).

24

Allegro MicroSystems

955 Perimeter Road

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www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

FAULT DETECTION AND PROTECTION

FAULT Status

ꢃꢄ ꢅꢆꢆ

The FAULT pin is an open-drain output that will be pulled low

when a fault occurs. A pull-up resistor (typically around 10 kΩ) is

required between this pin and desired logic level voltage (typi-

cally 3.3 to 5 V). Multiple devices with open-drain FAULT pins

can be connected in parallel to form a wired-AND configuration.

This way, when any device reports a fault, the system FAULT

signal is pulled low.

ꢎNꢕH ꢖ

ꢉꢃNꢗUꢉꢏꢅ

Power ꢁꢇ

ꢈꢉꢄꢄ, ꢊꢋ readyꢌ ꢋAꢍꢎ

ꢇꢁlled ꢏꢌ ꢀaꢁlt checꢐingꢑ

ꢎNꢕꢏ

ꢀAUꢏꢍ State

ꢈꢀAUꢏꢍ ꢇꢁlled ꢏꢑ

Any ꢀaꢁlt

detectedꢂ

The A80606-1 (One-Out-All-Out option) has a bidirectional

FAULT pin. This means the same pin also serves as an input to

monitor the status of system FAULT signal. When the FAULT

pin is pulled low externally for >8 f_SWcycles by another device,

the A80606-1 disables its own boost switch and all LED current

sinks in response. This feature is required in Master/Slave con-

figuration, for example.

ꢒes

No

ꢎNꢕH ꢖ

PꢙMꢕꢏ

ꢃꢄ Ready

ꢈꢄꢏꢓꢅUꢍ actiꢔe,

ꢀAUꢏꢍ ꢇꢁlled ꢏꢑ

ꢎNꢕꢏ

ꢎNꢕH ꢖ PꢙMꢕH

The following two simplified flow charts demonstrate the differ-

ence between A80606 (unidirectional FAULT pin) and A80606-1

(bidirectional FAULT pin).

Pin shorted

to ꢋNꢚ ꢆaꢁlt

 ꢀAUꢏꢍꢕꢏ

ꢏꢎꢚ Pin ꢄhecꢐ

ꢈꢃn Use, ꢚisaꢘled, or

Shorted to ꢋNꢚꢑ

ꢍime-oꢁt withoꢁt ꢆaꢁlts

 ꢀAUꢏꢍ released

Soꢆt Start

ꢈenaꢘle ꢘoost Sꢙ and

ꢏꢎꢚ cꢁrrent sinꢐsꢑ

Any ꢀaꢁlt

detectedꢂ

ꢒes

No

PꢙM ꢚimming

ꢏꢎꢚꢕon

ꢄlear 1ꢛ ms timer

ꢎN ꢖ PꢙM ꢕ H

ꢎN ꢖ PꢙM ꢕ ꢏ

ꢏꢎꢚꢕoꢆꢆ

Start 1ꢛms timer

ꢍimer eꢜꢇired

Figure 37: Simpliﬁed A80606 Startup Flowchart

25

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

ꢀꢄ ꢅꢆꢆ

ꢎNꢕH ꢖ

ꢉꢀNꢗUꢉꢏꢅ

Power ꢂꢇ

ꢈꢉꢄꢄ, ꢊꢋ readyꢌ ꢋAꢍꢎ

ꢇꢂlled ꢏꢌ ꢁaꢂlt checꢐingꢑ

ꢎNꢕꢏ

ꢁAUꢏꢍ State

ꢈꢁAUꢏꢍ ꢇꢂlled ꢏꢑ

Any ꢀnternal

ꢁaꢂlt detectedꢃ

ꢒes

No

ꢎNꢕH ꢖ

PꢙMꢕꢏ

ꢀꢄ Ready

ꢈꢄꢏꢓꢅUꢍ actiꢔe,

ꢁAUꢏꢍ ꢇꢂlled ꢏꢑ

ꢎNꢕꢏ

ꢎNꢕH ꢖ PꢙMꢕH

Pin shorted

to ꢋNꢚ ꢆaꢂlt

 ꢁAUꢏꢍꢕꢏ

ꢏꢎꢚ Pin ꢄhecꢐ

ꢈꢀn Use, ꢚisaꢘled, or

Shorted to ꢋNꢚꢑ

ꢍime-oꢂt withoꢂt ꢆaꢂlts

 ꢁAUꢏꢍ released

Any ꢎꢜternal

ꢁaꢂlt detectedꢃ

ꢀes

ꢈꢁAUꢏꢍ ꢇꢂlled ꢏ

eꢜternallyꢑ

No

ꢈꢁAUꢏꢍꢕHꢑ

Soꢆt Start

ꢈenaꢘle ꢘoost Sꢙ and

ꢏꢎꢚ cꢂrrent sinꢐsꢑ

Any ꢀnternal

ꢁaꢂlt detectedꢃ

ꢒes

No

Any ꢎꢜternal

ꢀes

ꢁaꢂlt detectedꢃ

ꢈꢁAUꢏꢍ ꢇꢂlled ꢏ

eꢜternallyꢑ

No

PꢙM ꢚimming

ꢏꢎꢚꢕon

ꢄlear 1ꢛ ms timer

ꢎN ꢖ PꢙM ꢕ ꢏ

ꢎN ꢖ PꢙM ꢕ H

ꢏꢎꢚꢕoꢆꢆ

Start 1ꢛms timer

ꢍimer eꢜꢇired

Figure 38: Simpliﬁed startup ﬂow chart for A80606-1, showing responses to both Internal

and External FAULT signals

26

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

For A80606, the FAULT pin is pulled low in case any LED

LED String Partial-Short Detect

string is directly or partially shorted. The suspect LED string is

disabled, while the rest of the LED strings continue to operate.

FAULT pin is latched at low until it is reset by either EN = L or

PWM = L for >16 ms

All LED current sink pins (LED1 to LED6) are designed to with-

stand the maximum output voltage, as specified in the Absolute

Maximum Ratings table. This prevents the IC from being dam-

aged if V_OUTis directly applied to an LED pin due to an output

connector short.

For A80606-1, all LED strings are turned off in case any LED

string has detected a partial short. FAULT pin is latched at low

until the IC is reset.

In case of direct-short or partial-shorted fault in any LED string dur-

ing operation, the LED pin with voltage exceeding V_LEDSDwill be

removed from regulation. This prevents the IC from dissipating too

much power due to large voltage drop across the LED current sink.

Figure 41: A80606-1 startup sequence when LED string#2 has a

partial-short fault (6 × WLED instead of 8). As soon as LED2 pin rises

above V_LEDSD(~5 V), the channel is disabled but FAULT remains High.

Figure 39: A80606 Normal startup sequence showing voltage at LED1 and

At least one LED pin must be at regulation voltage (below

~1.2 V) for the LED string partial-short detection to activate.

In case all of the LED pins are above regulation voltage (this

could happen when the input voltage rises too high for the LED

strings), they will continue to operate normally.

LED2 pins. V_IN= 6 V, output = 8 × WLED in series, current = 4 × 100 mA

Figure 40: A80606 startup sequence when LED string#2 has a partial-

short fault (6 × WLED instead of 8). As soon as LED2 pin rises above

V_LEDSC(~5 V), the channel is disabled and FAULT = Low.

27

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Overvoltage Protection

The A80606 offers a programmable output overvoltage protection

(OVP). The OVP pin has a threshold level of 2.5 V typical. Overvolt-

age protection is tripped when current into this pin exceeds ~150 µA.

A resistor can be used to set the OVP threshold up to 40 V approxi-

mately. This is sufficient for driving 11 white LEDs in series.

The formula for calculating the OVP resistor is shown below:

Equation 7:

R_OVP= (V_OVP– V_OVP(th)) / i_OVP(th)

where V_OVPis the desired OVP threshold, V_OVP(th)= 2.5 V

typical, i_OVP(th)= 150 µA typical.

To determine the desired OVP threshold, take the maximum LED

string voltage at cold and add ~10% margin on top of it.

Figure 42: A80606 startup with LED2 string open. V_OUThits OVP at

~28 V and LED2 is removed from regulation. FAULT pin goes Low

but remaining LED strings continue to operate.

The OVP event is not a latched fault and, by itself, does not pull

the FAULT pin to low. If the OVP condition occurs during a load

dump, for example, the IC will stop switching but not shut down.

For A80606-1, all LED strings are disabled in case any string is

not in regulation when V_OUThits OVP. FAULT pin is pulled low

and switching is stopped. The IC remains in latched off state until

it is reset.

OVP condition is typically caused by an open LED fault, or dis-

connected output connector. It may be detected either at startup or

during normal operation. This is explained separately below.

CASE 1: OVP AT STARTUP

During soft start period, the A80606 tries to boost V_OUTuntil it

becomes high enough for all LED string to come into regulation.

But if any LED string is open, V_OUTwill eventually hit OVP. At

this point, the A80606 will disable any LED string that is still not

in regulation. The FAULT pin is pulled low and boost switching

is stopped to allow V_OUTto fall. Once V_OUTdecreases by approx-

imately V_OVP(th), switching resumes to power the remaining LED

strings.

Figure 43: A80606-1 startup with LED2 string open. V_OUThits

OVP and all LED string are disabled. FAULT pin goes Low and IC

remains latched oﬀ until reset.

28

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

CASE 2: OVP DURING NORMAL OPERATION

Boost Switch Overcurrent Protection

When one LED string becomes open during operation, current

through its LED driver drops to zero. The A80606 responds by

boosting the output voltage higher. When output reaches OVP

threshold, the LED string without current is removed from regu-

lation. The rest of LED strings continue to draw current and drain

The external boost switch is protected with a cycle-by-cycle

primary current limit. When the voltage sensed at CS pin exceeds

V_CS(LIM1)(typically 210 mV), the existing switching cycle is

truncated. That means the peak switching current is limited to:

Equation 8:

i_SW(LIM1)= V_CS(LIM1)/ R_CS

down V_OUT. Once V_OUTdecreases by approximately V_OVP(th)

,

boost will resume switching to power the remaining LED strings.

where R_CSis the sense resistor connected from source of boost

MOSFET to power ground.

As an example, if R_CS= 39 mΩ, then i_SW(LIM1)= 5.4 A approxi-

mately.

The waveform below shows normal switching at V_IN= 6 V, V_OUT

= ~26 V and total LED current 800 mA. Average input current is

around 4.5 A.

Figure 44: An open-LED string faults causes VOUT to ramp up

and trip OVP. The A80606 then disables the open LED string and

continues with remaining strings.

The A80606-1, in contrast, will disable all LED strings in case

any LED string becomes open. The IC remains in latched off

state until it is reset.

Figure 46: Normal 400 kHz switching waveform at V_IN= 6 V. Red

trace is the SW node voltage at 10 V/div. Green trace is the induc-

tor current at 1 A/div.

When the input voltage is reduced further to 5.6 V, input current

increases and peak switch current reaches 5.4 A. Overcurrent

protection is tripped to limit the peak SW current.

Figure 45: An open-LED string faults causes VOUT to ramp up and

trip OVP. The A80606-1 then disables all LED string and remains in

latched oﬀ state until reset.

29

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

If the input current level goes above the preset threshold, the part

will be shut down in less than 3 µs. The FAULT pin is pulled

Low and the IC remains in latched off state until it is reset. This

feature prevents catastrophic failure in the system when there is

a direct short from VOUT to GND (caused by a shorted output

connector or cable, for example).

The waveform below illustrates the input overcurrent fault condi-

tion during startup. As soon as input OCP limit is reached, the

part disables the gate of the disconnect switch Q1 and latches off.

Figure 47: When peak current through the inductor reaches ~5.4 A,

overcurrent protection kicks in to truncate the present switching cycle.

There is also a secondary current sense limit V_CS(LIM2), set at

about 40% higher than the cycle-by-cycle current limit. It is to

protect the external MOSFET from destructive current spikes in

case the boost inductor or boost diode is shorted. Once this limit

is tripped, the A80606 will immediately shut down and latch off.

Input Overcurrent Protection and

Disconnect Switch

Figure 49: Startup into an output shorted-to-GND fault. Input OCP

is tripped when current (Green trace) exceeds ~6.5 A. PMOS Gate

(Red) is turned oﬀ immediately and IC latches oﬀ.

i_SꢆNSꢆ

ꢇꢈN

ꢅo ꢌ1

R_SꢆNSꢆ

During startup when Q1 first turns on, an inrush current flows

through Q1 into the output capacitance. If Q1 turns on too fast

(due to its low gate capacitance), the inrush current may trip

input OCP limit. In this case, an external gate capacitance C_Gis

added to slow down the turn-on transition. Typical value for C_Gis

around 4.7 to 22 nF. Do not make C_Gtoo large, since it also slows

down the turn-off transient during a real input OCP fault.

ꢀ1

ꢁPMꢂSꢃ

R_Aꢉꢊ

ꢋ_ꢄ

i_Aꢉꢊ

ꢄAꢅꢆ

ꢇ_SꢆNSꢆ

ꢇ_ꢈN

A80606

ꢇ_ꢈNꢍ ꢇ_SꢆNSꢆꢎ R_SꢆNSꢆꢏ i_SꢆNSꢆꢐ R_Aꢉꢊꢏ i_Aꢉꢊ

Figure 48: Optional input disconnect switch using a PMOSFET

The primary function of the input disconnect switch is to protect

the system and the device from excessive input currents during a

fault condition.

30

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Setting the Input Current Sense Resistor

Fault Protection During Operation

The input disconnect switch threshold is typically 98 mV, mea-

sured between VIN and VSENSE pins when R_ADJis 0 Ω. This

threshold can be trimmed slightly using the R_ADJresistor.

The A80606 constantly monitors the state of the system to deter-

mine if any fault conditions occur during normal operation. The

response to a triggered fault condition is summarized in the table

below. It is important to note that there are several points at which

the A80606 monitors for faults during operation. The locations are

input current, switch current, output voltage, switch voltage, and

LED pins. Some of the protection features might not be active dur-

ing startup to prevent false triggering of fault conditions.

To avoid false tripping, the input disconnect switch overcurrent

limit should be set higher than the boost switch cycle-by-cycle cur-

rent limit. For example, the boost switch OCP is set at 5.4 A, so the

input disconnect switch OCP may be set 25% higher at 6.75 A. The

input current sense resistor is then calculated as below.

The possible fault conditions that the part can detect include:

When R_ADJis not used:

• Open LED Pin or open LED string

• Shorted or partially shorted LED string

• LED pin shorted to GND

• Open or shorted boost diode

• Open or shorted boost inductor

• VOUT short to GND

V_IN– V_SENSE= R_SENSE× i_SENSE= 98 mV

The desired sense resistor is R_SENSE= 98 mV / 6.75 A =

14.5 mΩ. But this is not a standard E-24 resistor value. Pick the

closest lower value which is 13 mΩ.

When R_ADJis used:

• SW shorted to GND

V_IN– V_SENSE= R_SENSE× i_SENSE+ R_ADJ× i_ADJ

Therefore

• ISET shorted to GND

• FSET shorted to GND

• Input disconnect switch drain shorted to GND

R_ADJ= [(V_IN– V_SENSE) – (R_SENSE× i_SENSE)] / i_ADJ

= [98 mV – 88 mV] / 20 µA = 500 Ω

Pick the closest E-96 resistor value of 499 Ω.

Note that some of these faults will not be protected if the input

disconnect switch is not being used. An example of this is VOUT

short to GND fault.

Input UVLO

When V_INrises above V_UVLOrisethreshold, the A80606 is

enabled. The IC is disabled when V_INfalls below V_UVLOfall

threshold for more than 50 μs. This small delay is used to avoid

shutting down because of momentary glitches in the input power

supply.

31

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Table 5: A80606 Fault Mode Table

Fault Flag

Set

Disconnect

Switch

Fault Name

Type

Active

Description

Boost Switch

LED Sink drivers

This fault condition is triggered when the SW current exceeds the

cycle-by-cycle current limit, I_SW(LIM).The present SW on-time is

truncated immediately to limit the current. Next switching cycle starts

normally.

Primary Switch Overcurrent

Protection (Cycle-By-Cycle Auto-restart

Current Limit)

Off for a single

cycle

Always

NO

ON

When current through boost switch exceeds secondary SW current

limit (i_SW(LIM2)) the device immediately shuts down the disconnect

switch, LED drivers and boost. The Fault flag is set. To reset the fault

the EN or PWM pin needs to be pulled low for ~16 ms.

Secondary Switch Current

Limit

Latched

Off

Always

YES

OFF

The device is immediately shut off if the voltage across the input

sense resistor is above the V_SENSEtripthreshold. To reset the fault the

EN or PWM pin must be pulled low for ~16 ms.

Input Disconnect Current

Limit

Latched

Off

Always

Startup

YES

OFF

ON

OFF

If any of the LED pins is determined to be shorted to GND when PWM

first goes high, soft-start process is halted. Only when the short is

removed, then soft-start is allowed to proceed.

LEDx Pin Shorted to GND

Auto-restart

If an LED string is not getting enough current, the device will first

respond by increasing the output voltage until OVP is reached. Any

LED string that is still not in regulation will be disabled. The device will

then go back to normal operation by reducing the output voltage to

the appropriate voltage level.

LEDx Pin Open

(One-Out-Continue option)

Normal

operation

OFF for open pins.

ON for all others.

YES

ON

If an LED string is not getting enough current, the device will first

respond by increasing the output voltage until OVP is reached. If any

LED string is still not in regulation, all LED strings will be disabled and

the device latched off. To reset the fault the EN or PWM pin must be

pulled low for ~16 ms.

LEDx Pin Open

(One-Out-All-Out option)

Normal

operation

Latched

OFF

Fault occurs when the ISET current goes above 150% of max current.

The boost will stop switching and the IC will disable the LED sinks

until the fault is removed. When the fault is removed, the IC will try to

regulate to the preset LED current.

ISET Short Protection

Auto-restart

Always

YES

OFF

ON

OFF

Fault occurs when the FSET current goes above 150% of max

current. The boost will stop switching, Disconnect switch will turn off

and the IC will disable the LED sinks until the fault is removed. When

the fault is removed, the IC will try to restart with soft-start.

FSET/SYNC Short

Protection

Fault occurs when current into OVP pin exceeds i_OVP(th)(typically

150 µA). The IC will immediately stop switching but keep the LED

drivers active, to drain down the output voltage. Once the output

voltage decreases by approximately V_OVP(th), the IC will restart

switching to regulate the output current.

STOP during

OVP event.

Overvoltage Protection

Undervoltage Protection

Auto-restart

Always

NO

ON

Device immediately shuts off boost and current sinks if the voltage at

VOUT is below V_UVP(th). This may happen if VOUT is shorted to GND,

or boost diode is open before startup. It will auto-restart once the fault

is removed.

YES

OFF

Fault occurs if an LED pin voltage exceeds V_LEDSCwith its current

sink in regulation, while at least one other LED pin is below ~1.2 V.

This may happen when two or more LEDs are shorted within a string.

The LED string exceeding the threshold will be disabled and removed

from operation. Device will re-enable the LED string when its pin

voltage falls below threshold, or at the next PWM = H.

LED String Partial Short

Detection (One-Out-

Continue option)

OFF for shorted

string, ON for all

others.

Auto-restart

Latched

Always

YES

ON

LED String Partial Short

Detection (One-Out-All-Out

option)

If two or more LEDs are shorted within a string, all LED strings will be

disabled and the device latched off. To reset the fault, EN or PWM pin

must be pulled low for ~16 ms.

OFF

Fault occurs when the die temperature exceeds the over-temperature

threshold, typically 170°C. IC will restart after temperatures drops

lower by T_SDHYS

Overtemperature Protection Auto-restart

Always

YES

NO

OFF

Fault occurs when V_INdrops below V_UVLO(fall). This fault resets all

latched faults.

V_INUVLO

Auto-restart

Continued on next page...

32

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Table 5: A80606 Fault Mode Table (continued)

Fault Flag

Set

Disconnect

Switch

Fault Name

Type

Active

Description

Boost Switch

LED Sink drivers

FAULT pin pulled Low

Externally (One-Out-

Continue option)

Always

ignored

In One-Out-Continue mode (with unidirectional FAULT pin), external

status of FAULT pin does not affect the operation of the IC in any way.

Always ignored

No change

In One-Out-All-Out mode (with bidirectional FAULT pin), if FAULT pin

is externally pulled Low, the IC immediately shuts off its boost and

LED current sinks. IC can only restart when external fault status is

cleared AND there is no internal fault status pending. That means

local latching faults cannot be cleared by externally forcing FAULT

pin to High.

FAULT pin pulled Low

Externally (One-Out-All-Out Auto-restart

option)

Always

OFF

ON

OFF

LED ꢀtring Partial-ꢀhort Deteꢁtion in One-Out-ꢂontinue modeꢃA80606ꢄ

ꢄaꢅlt Remoꢆed

No ꢄaꢅlts

ꢀꢁꢂꢃ String Partial-Short

ꢄaꢅlt asserted

Pꢋꢌ

ꢀꢁꢂꢃ

ꢀꢁꢂ1

LED1ꢇ

LEDꢈ

ꢑ_{ꢀꢁꢂSꢂ}

0

ꢃ00 mA

iꢍLED _{100 mA}

0

ꢅAULꢆ

D

H

A

E

ꢉ

B

ꢅ

ꢂ

Eꢊplanation of events ꢇ

Aꢇ PꢈM goes High and all ꢀꢁꢂ driꢆers oꢉerate normally. ꢊꢄor simꢉlicity, assꢅme only ꢀꢁꢂ 1

and ꢀꢁꢂꢃ are in ꢅse, each sinꢋing 100 mA.ꢌ

Bꢇ A ꢉartial-short ꢍaꢅlt is asserted to ꢀꢁꢂ ꢃ string. Nothing haꢉꢉens yet since PꢈM ꢎ ꢀ.

ꢂꢇ At the neꢏt PꢈM ꢎ H, ꢀꢁꢂꢃ ꢉin ꢆoltage stays aꢐoꢆe ꢑ_{ꢀꢁꢂSꢂ}while ꢀꢁꢂ1 ꢉin is at regꢅlation

ꢆoltage.

Dꢇ Aꢍter ꢉartial-short detection time ꢊꢒꢃ ꢓsꢌ, ꢀꢁꢂꢃ string is disaꢐled and ꢄAUꢀꢔ ꢉin ꢉꢅlled

ꢀow. ꢀꢁꢂ1 string continꢅes to oꢉerate.

Eꢇ At sꢅꢐseꢕꢅent PꢈM ꢎ H, ꢖꢗ retries ꢀꢁꢂ1 ꢐꢅt shꢅts it oꢍꢍ again since the ꢍaꢅlt is still

ꢉresent. ꢄAUꢀꢔ ꢍlag remains ꢀow.

ꢅꢇ Partial Short ꢍaꢅlt is remoꢆed ꢍrom ꢀꢁꢂ ꢃ string. Nothing haꢉꢉens yet since PꢈM ꢎ ꢀ.

ꢉꢇ At the neꢏt PꢈM ꢎ H, ꢖꢗ retries ꢀꢁꢂ1 and it ꢉasses. ꢘꢅt ꢄAUꢀꢔ ꢍlag is not cleared

Hꢇ ꢄAUꢀꢔ ꢍlag is cleared at the second PꢈM ꢎ H aꢍter Partial Short ꢍaꢅlt was remoꢆed.

33

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

PACKAGE OUTLINE DRAWING

For Reꢀerence ꢁnly ꢂ Not ꢀor Tooling ꢃse

(Reference DWG-2867)

Dimensions in millimeters

NOT TO SCALE

Exact case and lead conﬁguration at supplier discretion within limits shown

0.30

0.50

7.00 BSC

ꢃ0.0

-0.05

0.05

48

0.10 REF

48

4ꢀ0.20 MIN

1

2

1

2

A

5.15

7.00 BSC

7.0

1.00

5.15

C

D

49ꢀ

7.0

0.08

C

0.90 NOM

SEATING

PLANE

C

PCB Layout Reference View

0.25 ꢁ0.05

0.50 BSC

0.05 REF

0.40 NOM

Terminal ꢂ1 mark area

A

B

Exposed thermal pad (reference only, terminal #1 identiﬁer appearance at supplier discretion)

5.15 ꢁ0.10

Reference land pattern layout (reference IPC7351 QFN50P700X700X100-49M);

all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to

meet application process requirements and PCB layout tolerances; when mounting

on a multilayer PCB, thermal vias at the exposed thermal pad land can improve

thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

C

2

1

48

5.15 ꢁ0.10

Coplanarity includes exposed thermal pad and terminals

D

Figure 50: Package EV, 48-Pin 7 mm × 7 mm QFN with Exposed Thermal Pad and Wettable Flank

34

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

APPENDIX A: DESIGN EXAMPLE

This section provides step-by-step instructions to select compo-

nent values for an A80606 application.

Step 3: Determine the OVP resistor according to Equation 6:

R_OVP= (V_OVP– V_OVP(th)) / i_OVP(th)

For the purposes of this example, the following operating condi-

tions are assumed:

The nominal output voltage is:

V_{OUT_nom}= n × V_f+ V_REG

• V_IN= 12 V nominal (6 V min, 18 V max)

• Number of LED channels, nc = 6

where V_REGis the LED pin regulation voltage. Substitute n = 7,

V_f= 3.2 V and V_REG= 0.85 V to get V_{OUT_nom}= 23.25 V.

• Number of series LEDs per channel, n = 7

• LED current per channel, I_LED= 150 mA

• LED forward drop, V_f= 3.2 V max at cold

• Switching frequency, f_SW= 2.15 MHz

Set the OVP threshold voltage approximately 10% higher, to

account for error margin and component tolerances:

V_OVP= V_{OUT_nom}× 1.1 = 25.6 V

The OVP resistor is therefore:

• Dithering modulation frequency, f_DM= 1 kHz

• Dithering frequency range, ∆f_SW= ±5%

• Max ambient temperature, T_A(max)= 65°C

• PWM dimming frequency, f_PWM= 200 Hz

Step 1: Program the Switching Frequency from Equation 1:

R_OVP= (25.6 V – 2.5 V) / 150 µA

ꢀꢀꢀꢀꢀꢀꢀꢀꢀ=ꢀ154ꢀkΩ

ꢀ

Step 3a: Check to ensure the maximum boost duty cycle is suf-

ficient to achieve the required conversion ratio.

D_MAX(boost)= 1 – t_SW(off)× f_SW(max)

where t_SW(off)is the worst-case minimum SW on-time, and

f_SW(max)is the maximum switching frequency with dithering.

R_FSET= (21.5 / f_SW) – 0.2

where f_SWis in MHz and R_FSETis in kΩ.

Substitute t_SW(off)= 100 ns and f_SW(max)= 2.26 MHz to get

D_MAX(boost)= 0.774.

Substitute f_SW= 2.15 MHz to get R_FSET= 9.8 kΩ (pick 10 kΩ).

Step 1a: Program the Dithering Modulation Frequency from

Equation 2:

Theoretical maximum output voltage at the lowest input voltage is:

V_OUT(max)= V_IN(min)/ (1 – D_MAX(boost)) – V_D

C_DITH(nF) = 25 / f_DM(kHz)

Substitute f_DM= 1 kHz to get C_DITH= 25 nF (pick 22 nF).

Step 1b: Select Dithering Range from Equation 3:

∆f_SWRange (±%) = 20 × R_FSET/ R_DITH

where V_Dis the forward drop of boost Schottky diode.

Substitute V_IN(min)= 6 V, D_MAX(boost)= 0.774, and V_D= 0.4 V to

get V_OUT(max)= 26.15 V.

Theoretical V_OUT(max)has to be greater than V_OVP. If this is not

the case, then switching frequency of the boost converter must be

reduced to meet the maximum duty cycle requirement.

Substitute Range = 5 and R_FSET= 10 kΩ to get R_DITH= 40 kΩ

(pick 40.2 kΩ). The switching frequency now linearly sweeps

between 2.04 and 2.26 MHz.

Step 4 – Inductor selection: The inductor must be chosen

based on ripple current requirement. In most applications due to

stringent EMI requirements, the system also needs to operate in

continuous conduction mode (CCM) throughout the whole input

voltage range. A simple guideline is to start with 30% peak-to-

peak ripple current at nominal input and output voltages.

Step 2: Determine the LED current set Resistor R_ISETfrom

Equation 4:

R_ISET= (V_ISET× A_ISET) / I_LED

Substitute V_ISET= 0.985 V, A_ISET= 978, and i_LED= 150 mA to

get R_ISET= 6.42 kΩ.

Step 4a: Determine the Boost Duty Cycle:

D = 1 – V_IN/ (V_OUT+ V_D)

35

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For nominal operation, substitute V_{IN_nom}= 12 V, V_{OUT_nom}

23.25 V and V_D= 0.4 V to get D_nom= 0.493.

=

Step 5: To verify that there is sufficient slope compensation for

the inductor chosen. The A80606 generates a variable internal

Slope Comp according to f_SWand V_IN.

Step 4b: Calculate the nominal Input Current based on esti-

mated efficiency:

• If V_INis between 9 V and 15 V:

SC = 3 × f_SW× V_IN/ 12

i_IN= V_OUT× i_OUT/ (V_INꢀ×ꢀη)

• If V_IN< 9 V:

where η = efficiency of the converter (typically in the 85% to

90% range).

SC = 3 × f_SW× 9 / 12

• If V_IN> 15 V:

For nominal operation, substitute V_OUT= 23.25 V, i_OUT= 0.9 A,

V_IN= 12 V, and η = 0.9 to get i_IN= 1.94 A.

SC = 3 × f_SW× 15 / 12

where f_SWis in MHz and SC is in A/µs.

Step 4c: Select Boost Inductance based on 30% Ripple Current.

For nominal operation, ∆i_L= 0.3 × i_IN= 0.58 A.

∆i_L= t_ON× V_IN/ L = D × V_IN/ (f_SW× L)

For example, at f_SW= 2.15 MHz and V_IN= 6 V, SC = 4.84 A/µs

The falling slope of inductor current is given as:

di_L/dtꢀ=ꢀ–∆i_L/ t_OFFꢀ=ꢀꢀ–∆i_L× f_SW/(1 – D)

Therefore:

Based on equations from previous section, at V_IN= 6 V and

V_OUT(OVP)= 25.6 V, D = 0.749 and ∆i_L= 0.442 A. Therefore

|di_L/dt| = 4.11 A/µs, which is slower than the internal slope. That

means there is sufficient slope compensation.

L = D × V_IN/ (f_SWꢀ×ꢀ∆i_L)

Substitute D_nom= 0.493, V_{IN_nom}= 12 V, and f_SW= 2.15 MHz to

get L = 4.7 µH.

STEP 4d: Determine the maximum and minimum input current

to the system. The maximum current determines the inductor’s

saturation current rating. The minimum current determines its

critical inductance.

In case the negative slope of inductor current is faster than the

internal slope comp, a higher inductance value must be used.

Step 6: Select External Boost Switch MOSFET.

Refer to Appendix B for more details on how to select the exter-

nal boost MOSFET. For this example, the MOSFET picked is

SVD5867NL with the following key parameters:

Maximum input current occurs at minimum V_INand maximum

V_OUT(OVP).

i_{IN_max}= V_OVP× i_OUT/ (V_{IN_min}ꢀ×ꢀη)

• Breakdown voltage V_(BD)DSS= 60 V min

Substitute V_OVP= 25.6 V, V_{IN_min}= 6 V, and η = 0.85 to get

i_{IN_max}= 4.52 A.

• On-resistance R_DS(on)= 50 mΩ max at V_GS= 4.5 V

• Total Gate Charge Q_G= 10 nC for V_GS= 0 to 6.5 V

Step 7: Select boost switch current sense resistor.

Peak inductor current:

i_{L_peak}= i_{IN_max}ꢀ+ꢀ∆i_L/ 2

From Equation 8:

At minimum V_IN= 6 V, D = 0.746, ∆i_L= 0.442 A, and so i_{L_peak}

= 4.52 + 0.442 / 2 = 4.74 A. Therefore, the inductor should have a

saturation current of at least 5.7 A (20% higher than i_{L_peak}).

R_CS= V_CS(LIM1)/ i_SW(LIM1)

From previous section, i_{L_peak}= 4.74 A at min V_INand max

V_OUT. Set the cycle-by-cycle SW current limit at least 20%

higher, which means ~5.7 A. Therefore:

Minimum input current occurs at maximum V_INand nominal

V_OUT

.

R_CSꢀ=ꢀ210ꢀmVꢀ/ꢀ5.7ꢀAꢀ=ꢀ37ꢀmΩ

i_{IN_min}= V_{OUT_nom}× i_OUT/ (V_{IN_max}ꢀ×ꢀη)

Pick a standard E-12 resistor value of 39 mΩ. This gives cycle-

by-cycle current limit of i_SW(LIM1)= 5.4 A.

Substitute V_{OUT_nom}= 23.25 V, V_{IN_max}= 18 V, and η = 0.9 to get

i_{IN_min}= 1.29 A.

Step 8: Choose the input disconnect switch components.

At maximum V_IN= 18 V, D = 0.239, ∆i_L= 0.426 A, and so

i_{L_valley}= 1.29 – 0.426 / 2 = 1.08 A. Therefore the converter

operates in CCM throughout the input voltage range.

Set the input disconnect switch current limit at least 20% above

the SW cycle-by-cycle current limit:

36

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i_SENSE= 5.4 A × 1.2 = 6.48 A

The biggest contributing factors for total output capacitance are

PWM off-time and leakage current (i_LK). This current is mainly

due to the reverse current of switching diode, plus a small/negli-

gible leakage current into the OVP pin.

R_SC= V_SENSETRIP/ i_SENSEꢀ=ꢀ15.1ꢀmΩꢀwhereꢀV_SENSETRIP= 98 mV.

Pick the closest lower resistance value from E-24 series, which is

15 mΩ.

In this design example, the PWM dimming frequency is 200 Hz

with minimum duty cycle of 0.01%. So the maximum PWM

off-time is essentially t_OFF= 5 ms. A typical goal is to keep the

output voltage variation at 250 mV or less to avoid audible noise.

∆V_OUT= t_OFF× i_LK/ C_OUT

R_ADJ= [V_SENSETRIP– (R_SC× i_SENSE)] / i_ADJꢀ=ꢀ40ꢀΩꢀwhereꢀi_ADJꢀ=ꢀ20ꢀμA.

Select the input disconnect switch P-MOSFET based on its drain-

source breakdown voltage and on-resistance.

The SQJ459EP can be used in this case. It has V_DS= –60 V and

R_DS(ON)= 24 mΩ at V_GS= –4.5 V.

Therefore:

C_OUT= t_OFF× i_LKꢀ/ꢀ∆V_OUT

Step 9: Select the switching diode.

Substitute t_OFF= 5 ms, i_LK= 110 µA, and ∆V_OUT= 0.25 V to get

C_OUT= 2.2 µF.

A Schottky barrier diode (SBD) is typically selected based on its

voltage and current ratings:

A major problem with multilayer ceramic capacitor (MLCC)

is that its actual capacitance drops with respect to DC bias. For

example, the capacitance of a 4.7 µF, 50 V, 0805 MLCC may

be derated by 80% when it is biased at 25 V. That means its real

capacity is less than 1 µF in actual application.

• The reverse voltage rating must be higher than the maximum

voltage stress, which is equal to the OVP threshold in this

case.

• The average forward current rating must be higher than the

total LED current. The peak current through diode is given as:

i_{D_peak}= i_{L_peak}= i_{IN_max}ꢀ+ꢀ∆i_L/ 2

MLCC with larger physical size and higher voltage rating typi-

cally suffers less derating problem. For example, a 4.7 µF, 50 V,

1210 MLCC may retain 3.3 µF of capacitance at 25 V. This is

shown in the table below:

From previous calculation at minimum V_IN, i_{L_peak}= 4.74 A.

However, during transient, this current could reach cycle-by-

cycle SW current limit, i_SW(LIM)

.

Rated

Capacitance

at 0 V (µF)

Actual

Capacitance

at 25 V (µF)

Another critical parameter is the diode’s reverse leakage current

at hot. This is especially important when using PWM dimming.

During PWM off time, the boost converter is not switching, so

voltage at output capacitor decays due to leakage current. This

increases output ripple voltage, which may generate audible noise

from ceramic capacitors.

Derating at

25 V

Part Number

Package

GRM21BC71H475KE11

GRM31CR71H475MA12

GRM32ER71H475KA88

0805

1206

1210

4.7

–80%

–45%

–30%

0.94

2.59

3.29

Make sure to verify the diode’s reverse current at hot (such as

125°C) and at the nominal V_OUT. As a general guideline, look

for a diode with leakage of 100 µA or less. If necessary, consider

using a diode with higher voltage rating (such as 100 V instead

of 50 V). Doing so can significantly reduce the leakage current at

Step 11: Selection of input capacitor.

A combination of MLCC and electrolytic capacitor is recom-

mended. The MLCC provides low ESR to reduce input switching

ripple. The electrolytic capacitor provide larger capacitance to

stabilize input voltage during PWM dimming operation.

nominal V_OUT

.

A good rule of thumb is to set the input voltage ripple ΔV_INto be

1% of the minimum input voltage. The minimum input capacitor

requirements are as follows.

For this design example, a 100 V, 3 A Schottky diode SS3H10 is

selected. It has a very low i_R= 50 µA at T_J= 125°C and V_R= 30 V.

Step 10: Selection of output capacitors.

C_INꢀ=ꢀ∆i_L/ (8 × f_SWꢀ×ꢀΔV_IN)

The use of multilayer ceramic capacitor (MLCC) is recom-

mended. MLCC capacitors have extremely low ESR, which is

necessary to reduce the output switching ripple of the boost con-

verter. In addition, the total output capacitance must be sufficient

to reduce output droop during PWM dimming operation.

Substitute ∆i_L= 0.442 A at V_IN= 6 V (from step 4d), ∆V_IN

=

0.06 V, and f_SW= 2.15 MHz to get C_IN= 0.43 µF. Due to the DC

bias derating, the actual MLCC selected should be rated 1 µF or

higher.

37

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A80606 and

A80606-1

High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

A much larger input capacitance is required to provide the inrush

current during PWM dimming operation. The exact requirement

depends on many external factors, such as length of power cables

and response time of the power supply. As a first-order estimate:

assuming the power supply takes 25 µs to response, and the input

capacitor must keep the V_INdroop under 0.2 V while input cur-

rent ramps up from zero to full load. The following is needed:

C_IN= i_IN× t_PSꢀ/ꢀ(8ꢀ×ꢀ∆V_IN)

Substitute i_IN= 4.52 A at V_IN= 6 V (from step 4d), ∆V_IN= 0.2 V

and t_PS= 25 µs to get C_IN= 71 µF. Use an electrolytic capacitor

of 68 µF in parallel with the MLCC.

The following schematic diagrams shows calculated component

values from the design example:

ꢆ_ꢑNꢒ ꢈ ꢓ 1ꢉ ꢆ

ꢆ_ꢎUꢔꢒ ꢕꢊ3 ꢆ

SS3H10

Sꢂꢃꢄ59ꢅP

ꢄ.ꢐ ꢌH

0.015 Ω

ꢇ_ꢑNꢊ

Nꢆꢖ5ꢉꢈꢐNꢍ

ꢖꢊ

1N4148

ꢈꢉ ꢌꢁ

ꢅꢍꢇꢎ

ꢊ.ꢊ ꢌꢁ

Mꢍꢇꢇ

0.1 ꢌꢁ

ꢄ0 Ω

330 pF

15ꢄ ꢋΩ

2.49 Ω

ꢊ.ꢊ ꢌꢁ

ꢊ ꢏ ꢄ.ꢐ ꢌꢁ

50 ꢆ 1ꢊ10

0.039 Ω

100 Ω

ꢗAꢔꢅ

ꢆꢖRꢆ ꢗꢖRꢆ ꢇS PꢗNꢖ

ꢎꢆP

ꢆsense

ꢆ_ꢇꢇ

ꢆin

1 ꢌꢁ

ꢆ_ꢖꢖ

10 ꢋΩ

ꢍꢅꢖ1

Aꢉ0ꢈ0ꢈ

ꢁAUꢍꢔ

ꢅN

ꢈ ꢍꢅꢖ strings with

ꢐ ꢙꢍꢅꢖs in series

at 150 mAꢘch.

ꢍꢅꢖꢊ

ꢍꢅꢖ3

ꢍꢅꢖꢈ

PꢙM

AꢖꢑMꢘAPꢙM

ꢇꢎMP

ꢇꢍꢚꢎUꢔ

AꢗNꢖ

ꢑSꢅꢔ

ꢁSꢅꢔ

ꢖꢑꢔH

Pꢅꢛ

100 ꢀꢁ

ꢊꢉ0 Ω

ꢄ0.ꢊ ꢋΩ

ꢊꢊ nꢁ

6.42 kΩ

11.3 ꢋΩ

10 ꢋΩ

ꢈꢉ nꢁ

Figure 51: A80606 2.15 MHz Boost schematic for design example

38

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A80606 and

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High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

APPENDIX B: EXTERNAL MOSFET SELECTION GUIDE

The A80606 drives an external MOSFET for the boost stage. This

solution provides maximum flexibility in delivering a wide range

of output voltage and current for different LED panels, compared

to controllers with built-in boost switches. On the other hand,

care must be taken in selection of external MOSFET, to ensure

optimal tradeoff between component size, efficiency, and cost.

Primary Parameters to consider include the following.

ON-RESISTANCE

Device with lower R_DSONcan directly reduce the conduction loss

of the boost converter. This is especially important when the out-

put power is high and input supply voltage is low. Note that most

datasheets typically highlight this parameter at V_GS= 10 V and

T_J= 25°C. It is important to examine how R_DSONvaries with gate

voltage and temperature, as shown in the following charts:

BREAKDOWN VOLTAGE

Pick the device with “Drain to Source Breakdown Voltage” at

least 20% higher than the maximum possible SW voltage.

• For boost configuration, V_SW= V_OUT+ V_F; where V_F= boost

diode forward drop.

The A80606 has a maximum V_OUTof 40 V. Therefore, the

MOSFET should be rated 50 V or higher.

• For SEPIC configuration, V_SW= V_IN+ V_OUT+ V_F.

Note that V_INcan be as high as 40 V during load-dump

conditions. The breakdown voltage needs to be increased

accordingly.

GATE THRESHOLD VOLTAGE

The device must be fully enhanced by the time V_GS= 5 V. Note

that this is not the same as “Gate to Source Threshold Voltage”

in most MOSFET datasheets, which is typically specified at very

small current such as 250 µA. A more reliable way is to consult

the “Gate Charge Characteristics” chart of the device, and make

sure that the ‘plateau’ occurs well before V_GSreaches 5 V. See

example from datasheet of one potential candidate:

Figure 53: Chart showing On-Resistance varies with Darin

Current and Gate Voltage.

Figure 54: Nominalized On-Resistance vs. Junction Tem-

perature at V_GS= 10 V. Note that resistance increases by

100% when temperature rises from 25°C to 150°C.

Figure 52: Gate Charge vs. Gate-Source Voltage for an ex-

ample MOSFET. Note plateau at V_GS= 4.2 V approximately.

39

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A80606 and

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High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

On the other hand, selecting a device with very low Q_Gmay

cause excessive voltage spikes at SW node due to high dV/dt. In

this case, a snubber circuit can be added to dampen the ringing.

The switching speed can be slowed down by adding a series gate

resistance (such as 1-5 ohm) between the driver and the device.

The downside of doing this is higher switching losses.

THERMAL RATING

The thermal resistance (R_θJA) is primarily determined by the

device’s physical size. If the thermal resistance of the device is

too high, or if there is insufficient heat dissipation on the PCB,

the device may enter thermal run-away situation and burn itself

out. For most medium-power (10-30 W) applications, a DPAK

device is generally sufficient. For high-power (>50 W) applica-

tions, a D²PAK device may be required. Depending on power

loss, additional heat sink can be mounted to improve the heat

dissipation from the PCB.

GATE CHARGE

As mentioned earlier, lower R_DSONis desired to reduce conduc-

tion loss. But devices with lower R_DSONtypically also have

higher gate charge (Q_G), which can lead to higher switching loss.

This is especially important when switching at high frequency

(such as 2 MHz) and with high output voltage. Higher gate

charge also results in higher gate driver current and hence higher

power loss for the controller IC.

The A80606 uses an LDO to supply the driver voltage (V_DRV),

which has a current limit of 36 mA typical. Average gate driver

current is:

Figure 56: Gate Charge vs. Gate-Source Voltage chart for

a suitable MOSFET (SVD5867NL). Note that its plateau is

at ~3.5 V, and its total gate charge is about 10 nC as V_GS

ramps up from 0 to 6.5 V.

i_VDRV= f_SW× Q_G

If the MOSFET selected has Q_G= 27 nC, for example, then the

highest switching frequency is limited to 1.33 MHz. See the fol-

lowing chart for relation between maximum switching frequency

and MOSFET gate charge:

ꢂꢆꢍ. ꢎꢁꢏtꢐꢉꢏꢌꢋ ꢑꢊꢇꢒꢓꢇꢌꢐꢔ ꢕs. ꢅꢆtꢇ ꢈꢉꢆꢊꢋꢇ

3.0

2.5

2.0

1.5

1.0

0.5

0.0

10

15

20

25

30

35

40

ꢅꢆtꢇ ꢈꢉꢆꢊꢋꢇ (ꢌꢈ)

Figure 55: Maximum Switching Frequency vs. Gate Charge

(to keep average V_DRVcurrent under 36 mA).

40

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A80606 and

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High Power LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

Revision History

Number

Date

August 27, 2020

Description

–

Initial release

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit

improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor

for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

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型号：	A80606KEVJSR-1
厂家：	ALLEGRO MICROSYSTEMS
描述：	High Power LED Driver with Pre-Emptive Boost
文件：	总41页 (文件大小：5340K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A80606KEVJSR-1 [ALLEGRO]

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