A81407KLVATR-1_技术文档

A81407

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

DESCRIPTION

FEATURES AND BENEFITS

• A²-SIL™ pending—device features for safety-critical

systems

The A81407 is ideal for both automotive and industrial

applications, where high temperature operation, a high level

of integration, and robust solutions are required.

• Automotive AEC-Q100 qualified

• Wide input voltage range, 3.8 to 36 V_INoperating range,

40 V_INmaximum

• 2.2 MHz buck or buck/boost pre-regulator (VREG: 5.35 V)

with low EMI frequency dithering

• Frequency dithering and controlled slew rate help reduce

EMI/EMC

• Four internal linear regulators with foldback short-circuit

protection

The IC integrates a buck or buck/boost pre-regulator, four LDOs,

and four floating gate drivers. The pre-regulator uses a buck or

buck/boost topology to efficiently convert input voltages into a

tightly regulated intermediate voltage. Frequency dithering and

slew control help reduce EMI. The output of the pre-regulator

supplies a 3.3 V / 375 mA linear regulator, a 5 V / 150 mA linear

regulator,andtwo5V/120mAlinearregulators.Alloftheoutputs

are protected against short circuits, and two are further protected

from short-to-supply voltage in case they are used remotely.

□ VUC: selectable output (3.3 V / 5.0 V) regulator for

microcontroller

The independent floating gate drivers can be used for input

supply disconnect or reverse-supply protection. They can

also be used for switched loads such as motor phases, solid

state relays, and solenoid valves. They have the capability of

controlling N-channel MOSFETs through SPI. An integrated

charge pump allows the driver outputs to maintain the power

MOSFETs in the on-state over the full supply range with high

phase-voltage slew rates.

□ V5A: 5 V general purpose LDO regulator

□ V5P1 and V5P2: two LDO regulators with short-to-

battery protection for remote sensors

• OV and UV protection for all output rails provides ability

to monitor health of outputs

• Pulse Width Watchdog (PWWD), Window Watchdog

(WWD), and Q&A Watchdog (QAWD)

• Floating gate drivers (with charge pumps) for external

switched load control

• Analog multiplexor (AMUX) reports operational values

of multiple important parameters

• Safety signal (POE) can disable a separate function (e.g.,

motor driver) due to a Watchdog Failure

Diagnostic outputs from the A81407 include a Watchdog

Fault (WD_Fn), power-on reset (NPOR), and a fault flag

(FFn) to alert the microprocessor that a fault has occurred.

The microprocessor can read fault registers through SPI and

operational status via an analog multiplexor.

Continued on next page...

APPLICATIONS

PACKAGE

38-Pin eTSSOP (suffix LV)

Provides system power (for microcontroller/DSP, CAN,

sensors, etc.) and high-side gate driver control (for motor

phases and other switched loads such as solenoid valves and

SS relays) in:

• Industrial applications

• Electronic power steering (EPS)

Not to scale

2

• Advanced braking systems (ABS)

• Transmission control units (TCU)

• Emissions control modules

-

(pending)

• Other automotive applications

5.35 V

(VREG)

Buck-Boost

Pre-regulator

3.3 V / 5 V

5 V LDO (V5P1)

with Foldback &

Short to V_BAT

Protection

5 LDO (V5P2)

with Foldback &

Short to V_BAT

Protection

5 V LDO (V5A)

with Foldback

Protection

LDO (VUC)

with Foldback

Protection

4ch

Floating

Gate

NPOR,

Pulse-Width,

Window, and

Q&A

Drivers

Thermal

Shutdown

(TSD)

Analog MUX

Output for

Status Monitor

Serial

Interface

(SPI)

WD_Fn,

POE,

FFn

Charge

Pump

Dual

Bandgap

Watchdogs

A81407 Simpliﬁed Block Diagram

A81407-DS, Rev. 2

MCO-0000748

December 1, 2020

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

DESCRIPTION (continued)

FEATURES AND BENEFITS (continued)

• Pin-to-pin and pin-to-ground tolerant at every pin

• Control and diagnostic reporting through “secure” SPI

□ 16-bit Data Transfers □ 5-bit Message ID

Dualbandgaps,oneforregulationandoneforfaultchecking,improve

safety coverage and fault detection of the A81407.

The A81407 contains three types of watchdog timers: Pulse Width

Watchdog (PWWD), Window Watchdog (WWD), and Q & A

Watchdog (QAWD). The watchdog timers can be put into various

operating states via secure SPI commands.

□ 5-bit CRC

□ 3-bit Frame Counter

□ Read-Back Register

□ Chip ID

• Logic enable input (ENB) for microprocessor control

• High-voltage ignition enable input (ENBAT)

• Thermal shutdown protection

TheA81407 is supplied in a 38-lead eTSSOPpackage (suffix “LV”)

with exposed power pad.

• –40°C to 150°C junction temperature range

SELECTION GUIDE

Part Number

A81407KLVATR

A81407KLVATR-1

V_UC(V)

Package

Packing ^[1]

Lead Frame

3.3

5

38-pin eTSSOP with thermal pad 4000 pieces per 7-inch reel

100% matte tin

^[1]Contact Allegro for additional packing options.

ABSOLUTE MAXIMUM RATINGS ^[2]

Characteristic

Symbol

Notes

Rating

−0.3 to 40

Unit

V

VIN

V_VIN

V_ENBAT

I_ENBAT

−0.3 to 40

V

ENBAT

±75

mA

V

−0.3 to V_VIN+ 0.3

−1.5

LX

V_LX

t < 250 ns

t < 50 ns

V

V_VIN+ 3

V

GU, GV, GW, GVBB

SU, SV, SW, SVBB

VCP (Gate Drivers)

CP1 (Gate Drivers)

CP2 (Gate Drivers)

VCP2 (Pre-Regulator)

CP2C1 (Pre-Regulator)

CP2C2 (Pre-Regulator)

V5P1, V5P2

V_GU, V_GV, V_GW, V_GVBB

V_Sz– 0.3 to V_Sz+ 12

–6 to V_VIN+ 5

V_VIN– 0.3 to V_VIN+ 12

V_VIN– 0.3 to V_VIN+ 8

V_VIN– 0.3 to V_VIN+ 12

V_VIN– 0.3 to V_VIN+ 8

−0.3 to V_VIN+ 0.3

V_VIN– 0.3 to V_VIN+ 8

−1.0 to 40

V

V_SU, V_SV, V_SW, V_SVBB

V_VCP

V

V_CP1

V

V_CP2

V

V_VCP2

V

V_CP2C1

V

V_CP2C2

V_V5P1, V_V5P2

Independent of V_VIN

V

All other pins

−0.3 to 7

Junction Temperature

Storage Temperature Range

T_J

−40 to 150

°C

T_stg

−40 to 150

^[2]Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of

the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions

for extended periods may aﬀect device reliability.

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions ^[3]

Value

Unit

Junction to Ambient Thermal Resistance

R_θJA

eTSSOP-38 (LV) package

30

°C/W

^[3]Additional thermal information available on the Allegro website.

2

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Table of Contents

Charge Pump (VCP, VCP2).............................................. 20

Bandgap (BG1, BG2) ...................................................... 20

Enable Inputs (ENB, ENBAT) ........................................... 20

Linear Regulators ........................................................... 21

Fault Detection and Reporting (NPOR, WD_Fn, FFn).......... 21

Safe State Control Signal (POE)....................................... 21

Startup Self-Tests ........................................................... 21

Undervoltage Detect Self-Test .......................................... 21

Overvoltage Detect Self-Test............................................ 21

Overtemperature Shutdown Self-Test ................................ 21

Power-On Enable (POE) Self-Test .................................... 22

Analog Multiplexer Output................................................ 22

Floating MOSFET Gate Drivers ........................................ 22

Watchdog Timers............................................................ 22

Serial Communication Interface ........................................... 30

Register Mapping............................................................ 34

Design and Component Selection ........................................ 51

PCB Layout Recommendations ........................................... 56

Package Outline Drawing.................................................... 57

Features and Benefits........................................................... 1

Description.......................................................................... 1

Applications......................................................................... 1

Package ............................................................................. 1

Simplified Block Diagram ...................................................... 1

Selection Guide ................................................................... 2

Absolute Maximum Ratings................................................... 2

Thermal Characteristics ........................................................ 2

Functional Block Diagram ..................................................... 4

Pinout Diagram and Terminal List Table .................................. 6

Electrical Characteristics....................................................... 7

Timing Diagrams................................................................ 16

Summary of Fault Mode Operation....................................... 19

Functional Description ........................................................ 20

Overview ....................................................................... 20

Pre-Regulator (VREG)..................................................... 20

PWM Switching Frequency .............................................. 20

Bias Supply (VCC) .......................................................... 20

3

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

FUNCTIONAL BLOCK DIAGRAM

1 μꢃ

ꢎ5 ꢀ

0.ꢎꢎ μꢃ

ꢎ5 ꢀ

ꢎ.ꢎ μꢃ

1ꢚ ꢀ

1 μꢃ

1ꢚ ꢀ

A81407

ꢀꢁP

ꢀꢁPꢂ

ꢀRꢇꢋ

ꢂharge Pꢗmꢘ

ꢂharge Pꢗmꢘ ꢎ

1ꢎ ꢀ_ꢛAꢞ

ꢄ_ꢁN

3 A

ꢀꢁN

100 ꢘꢃ,

10 nꢃ,

0.1 µꢃ

50 ꢀ

33 to

100 µꢃ

50 ꢀ

ꢛꢋ1ꢉUꢀ

ꢛꢋ1

ꢖꢄꢅ

ꢀꢁPꢂ

ꢎ ꢣꢌ.ꢍ µꢃ

50 ꢀ

1ꢎ10

ꢛꢋꢎ

ꢛꢋ1

ꢇN

ꢌꢍ μꢃ

ꢎ5 ꢀ ꢏ ꢐꢍR

ꢑꢎ3ꢒ55 μꢃ ꢓ 5.3 ꢀꢔ

ꢖ1 10 µH

35 mΩ ꢒ ꢍ5 mΩ

ꢛꢋꢎꢉUꢀ

ꢛꢋꢎ

ꢀꢂꢂ

ꢛꢋꢎ

ꢖꢐ

ꢖꢋ

1 μꢃ

ꢀRꢇꢋ

5.35 ꢀ

ꢄꢎ

SS3Pꢌ

ꢄ1

SS3Pꢌ

Bꢆꢁꢇ

PRꢈ-RꢈGꢆLAꢉOR

ꢊꢀRꢈGꢋ

ꢅSꢂꢎ

ꢂꢖꢆ ꢓ ꢡ_SꢈS

Q1

ꢑwꢏ Hiccꢗꢘ Modeꢔ

ꢂꢖꢆ ꢓ ꢡ_ꢅSꢂ

ꢅSꢂ1

ꢎ ꢕΩ

ꢛꢋ1

ꢀꢂPꢎ Uꢀ

ꢀRꢇꢋ ꢅN

Rꢇꢃ

SꢞꢅP PꢊM

ꢀRꢇꢋ

ꢀUꢂ

ꢃꢛ

ꢂꢅMP

SS

ꢃꢅꢖꢄꢛAꢂꢆ

0.ꢌꢍ μꢃ

ꢂ_P1

39 ꢘꢃ

R_ꢟ1

MPꢅR

ꢎꢎ.1 ꢕΩ

ꢀRꢇꢋ

3.3 ꢀ

ꢑor 5 ꢀꢔ

ꢖꢄꢅ

ꢂ_ꢟ1

3.3 ꢀ

ꢃ7ꢄ ꢅA

ꢛꢋ1

Soꢡt Start

t_SS

SS ꢅꢆ

ꢞSꢄ

1.5 nꢃ

ꢄ1 MꢁSSꢁNꢋꢢ

ꢁꢖꢁMꢉꢖꢐ ꢢ

ꢖꢄꢅs ꢅN

ꢎ.ꢎ ꢙꢃ

1ꢚ ꢀ

MASꢉꢈR

Iꢁ POR

ꢀꢁNꢉUꢀ

ꢀꢂꢂ Uꢀ

ꢛꢋ1ꢉUꢀ

ꢛꢋꢎꢉUꢀ

ꢃꢅꢖꢄꢛAꢂꢆ

ꢢ ꢁndicates a

latched ꢡaꢗlt

ꢞꢇMP

ꢞHꢇRMAꢖ

SꢇNSꢁNꢋ

ꢀRꢇꢋ

ꢛꢋ1

ꢆꢇꢈꢉSꢊ

5 ꢀ

ꢖꢄꢅ

5 ꢀ

1ꢄ0 ꢅA

ꢀ5A

ꢖꢄꢅs ꢅN

ꢎ.ꢎ ꢙꢃ

1ꢚ ꢀ

3.1 ꢀ_ꢞꢈP

ꢎ.ꢚ ꢀ_ꢞꢈP

↑

↓

ꢝ

3.3 ꢕΩ

ꢃAꢖꢖꢁNꢋ

ꢄꢇꢖAꢈ

td_{ꢖꢄꢅ ,ꢅꢃꢃ}

ꢇN

ꢀRꢇꢋ ꢅN

ꢖꢄꢅs ꢅN

ꢜ

ꢇNꢛAꢞ

SꢞARꢞUPꢏ

SHUꢞꢄꢅꢊN

SꢇꢠUꢇNꢂꢇ

ꢀRꢇꢋ Uꢀ

MPꢅR

ꢚ00 ꢕΩ

0.ꢎꢎ μꢃ

ꢀ5P1_ꢄꢁSꢂ

ꢀRꢇꢋ

Short to ꢀꢛAꢞ

Protection

ꢃꢅꢖꢄꢛAꢂꢆ

µꢂ

ꢇNAꢛꢖꢇ

ꢇNꢛ

ꢚ0 ꢕΩ

5 ꢀ

ꢖꢄꢅ

5 ꢀ

1ꢎ0 mA

ꢀ5P1

ꢖꢄꢅs ꢅN

ꢎ.ꢎ μꢃ

50 ꢀ

V5P1_EN_(1:0)

(default ON)

ꢀ5Pꢎ_ꢄꢁSꢂ

ꢀRꢇꢋ

Short to ꢀꢛAꢞ

Protection

ꢃꢅꢖꢄꢛAꢂꢆ

5 ꢀ

1ꢎ0 mA

ꢀ5Pꢎ

ꢖꢄꢅ

ꢖꢄꢅs ꢅN

V5P2_EN_(1:0)

(default ON)

ꢎ.ꢎ μꢃ

50 ꢀ

4

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

FUNCTIONAL BLOCK DIAGRAM (continued)

ꢁꢃꢃ

ꢊ3.0 ꢁꢍ

ꢁꢃꢃ

ꢊ3.0 ꢁꢍ

ꢁUꢆ

A81407

ꢁUꢆ

MꢑSꢀ

NPꢀRꢇꢈꢄꢉꢊꢋꢌ0ꢍ

ꢆS

SPI

MꢀSꢑ

Sꢆꢈ

NPꢀR

ꢕꢁꢖꢖ ꢊw.r.t. Sꢁꢖꢖꢍ

ꢕU ꢊw.r.t. SUꢍ

ꢕꢁ ꢊw.r.t. Sꢁꢍ

ꢃꢄ-

ꢕꢐꢑꢅꢆH

td_{ꢏꢑꢐꢅ.ꢕꢚ}

μꢆ

RꢄSꢄꢅ

ꢀNꢄ

SHꢀꢅ

1ꢔꢁꢖAꢅ

t_ꢎꢃ

,ꢏAUꢐꢅ

ꢕꢎ ꢊw.r.t. Sꢎꢍ

ꢂꢃP

ꢅo SPꢑ

registers

ꢃꢄ-

ꢕꢐꢑꢅꢆH

td_{ꢏꢑꢐꢅ.ꢁꢖꢖ}

SꢁꢖꢖꢇUꢁ

ꢕate-ꢃriꢝer

ꢄNꢁꢖꢖ

ꢕꢁꢖꢖ

Sꢁꢖꢖ

ꢁUꢆ

ꢀꢁꢂUꢁ

ꢕAꢅꢄ

ꢃRꢑꢁꢄR

ꢄNAꢖꢐꢄ

Sꢁꢖꢖ

Uꢁ

ꢃꢄꢅꢄꢆꢅ

ꢁꢆP1

ꢁꢆPꢔ

ꢁRꢄꢕ

ꢁUꢆ

ꢁ5A

ꢁ5P1

ꢁ5Pꢔ

V_Bridge

ꢃꢄ-

ꢕꢐꢑꢅꢆH

td_ꢀꢁ

Pꢀꢄ

Motor

Phase W

ꢄNꢎ

ꢕꢎ

Sꢎ

td_Uꢁ

Bridge A

ꢁUꢆ

MPꢀR

ꢅSꢃ

Motor

Phase V

ꢄN

RSꢅ

Rꢄꢏ

ꢕate-ꢃriꢝer

ꢖꢕꢔ

ꢆꢐꢈ ꢒ ꢓ_SꢉS

ꢄNꢁ

ꢄNU

ꢕꢁ

Sꢁ

ꢕU

SU

ꢏꢏn

μꢆ

ꢎꢃꢇꢏn

ꢑNꢅꢄRRUPꢅ

ꢏꢏ

Bridge B

Motor

Phase U

PUꢐSꢄ ꢎꢑꢃꢅH

ꢎAꢅꢆHꢃꢀꢕ

ꢅꢑMꢄR

ꢎꢃ_ꢑN

Bridge C

ꢆꢐꢈ_ꢑN

50 ꢙΩ

ꢊPꢎꢎꢃꢍ

ꢁRꢄꢕꢀ 2 ^Ψ

ꢁUꢆꢀ 2

ꢁ5A ꢀ 2

ꢁ5P1 ꢀ 2

ꢁ5Pꢔ ꢀ 2

ꢁꢄNꢖAꢅꢀ 8 ^Ψ

ꢖꢕ1

ꢎꢑNꢃꢀꢎ

ꢎAꢅꢆHꢃꢀꢕ

ꢅꢑMꢄR

WDꢀꢁn

ꢁꢆꢆ

ꢊꢎꢎꢃꢍ

WD_SEL_(1:0)

A-MUꢛ

WD_STATE_(2:0)

AMUꢛꢀ

ꢗꢘA

ꢎAꢅꢆHꢃꢀꢕ

ꢅꢑMꢄR

ꢖꢕꢔ

ꢅꢄMP

ꢁꢑN ꢀ 10 ^Ψ

ꢁꢆPꢔ ꢀ 12 ^Ψ

ꢁꢆP ꢀ 12 ^Ψ

ꢁUꢆ

ꢆꢐꢈ ꢒ ꢓ_SꢉS

ꢊꢗꢘAꢍ

ꢜ

SEL_MUX_(3:0)

ꢕNꢃ

ꢎꢃꢇꢏn

WDSEL(1:0)

PꢕNꢃ

5

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Terminal List Table

Number

Name

VCP

Function

Charge pump reservoir capacitor connection, for phase disconnects

Charge pump reservoir capacitor connection, for buck/boost regulator

Input voltage pin

VCP

VCP2

VIN

1

2

3

4

5

6

7

8

9

38 CP2C2

37 CP2C1

36 LX

1

2

3

4

5

6

7

8

VCP2

VIN

GND

VCC

ENB

Ground

GND

VCC

ENB

POE

NPOR

FFn

35 CP1

Internal voltage regulator bypass capacitor pin

Logic enable input from a microcontroller or DSP

Gate drive enable, latches low to put the system into a safe state

34 CP2

33 PGND

32 LG

POE

NPOR

Active-low, open-drain VUC fault detection output. Using SPI

programming, Watchdog (WD) fault and/or V5A can be added to the

NPOR logic.

31 VREG

30 VUC

29 V5A

9

FFn

ENBAT

GVBB

SVBB

GW

Fault Flag to the microcontroller, open-drain, active low

Ignition enable input from the key/switch via a series resistor

Battery line MOSFET gate drive

ENBAT 10

GVBB

PAD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

–

28 WD_Fn

27 COMP

26 AMUXO

25 WD_IN

24 MOSI

23 MISO

22 CS

11

SVBB 12

GW 13

Battery line MOSFET source reference

W phase MOSFET gate drive

SW

14

SW

W phase MOSFET source reference

GV 15

SV 16

GV

V phase MOSFET gate drive

SV

V phase MOSFET source reference

GU 17

SU 18

GU

U phase MOSFET gate drive

21 SCK

SU

U phase MOSFET source reference

V5P2 19

20 V5P1

V5P2

V5P1

SCK

CS

5 V protected regulator output

Package LV, 38-Pin eTSSOP

Pinout Diagram

SPI clock input from the microcontroller

SPI Chip Select input from the microcontroller

SPI data output to the microcontroller (Master Input, Slave Output)

SPI data input from the microcontroller (Master Output, Slave Input)

Watchdog refresh input from a microcontroller or DSP

MISO

MOSI

WDIN

AMUXO Analog Multiplexer output

COMP

WD_Fn

V5A

Error amplifier compensation network pin for the buck/boost pre-regulator

Open-drain, WD fault output. Latches low if a WD fault is detected.

5 V regulator output

VUC

3.3 V regulator output (or 5V for A81407-1)

Voltage feedback input of the pre-regulator and input to the LDOs

Boost gate drive output for the buck/boost pre-regulator

Power ground

VREG

LG

PGND

CP2

Charge pump capacitor connection

CP1

Charge pump capacitor connection

LX

Switching node for the buck/boost pre-regulator

Charge pump capacitor connection

CP2C1

CP2C2

PAD

Charge pump capacitor connection

Exposed thermal pad

6

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or V_ENBAT= High,

unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

GENERAL SPECIFICATIONS

After V_VIN> V_VIN(START)and VREG in regulating,

Buck-Boost Mode

3.8

5.5

13.5

36

V

Operating Input Voltage ^[2]

V_VIN

After V_VIN> V_VIN(START)and VREG in regulating,

Buck Mode

VIN UVLO Start Voltage

VIN UVLO Stop Voltage

VIN UVLO Hysteresis

V_VIN(START)

V_VIN(STOP)

V_VIN(HYS)

I_Q

V_VINrising

4.55

3.25

–

4.8

3.5

1.3

13

5.05

3.75

–

V

V_VINfalling

V_VIN(START)‒ V_VIN(STOP)

V_VIN= 13.5 V, V_VREG= 5.6 V (no PWM)

V

–

mA

VIN Supply Quiescent Current ^[1][3]

V_VIN= 13.5 V,

V_ENBAT= Low and V_ENB= Low, T_J= 25°C

I_Q(SLEEP)

–

13

µA

PWM SWITCHING FREQUENCY AND DITHERING

Switching Frequency

Frequency Dithering

f_OSC

Dithering off

As a percent of f_OSC

V_VINrising

2.0

–

2.2

±10

9.0

17

2.4

–

MHz

%

V

Δf_OSC

8.5

–

9.5

–

VIN Dithering Start Threshold ^[2]

V_{VIN(DITHER,ON)}

V_VINfalling

V

V_VINfalling

7.8

–

8.3

18

8.8

–

V

VIN Dithering Stop Threshold ^[2]V_{VIN(DITHER,OFF)}

V_VINrising

V

SYSTEM (WATCHDOG) CLOCK

Internal Clock Frequency

f_SYS

–

8

–

MHz

%

Internal Clock Tolerance

f_SYS(TOL)

‒5

+5

CHARGE PUMP (VCP AND VCP2)

V_VCP2– V_VIN, V_VIN≥ 9 V, I_VCP2> –5 mA,

Buck Mode

4.1

3.6

3.0

9

6.6

4.4

3.8

10

–

V

VCP2 Output Voltage

(for Pre-Regulator)

V_VCP2– V_VIN, 5.5 V < V_VIN≤ 9 V, I_VCP2> –5 mA,

Buck Mode

V_VCP2

V_VCP2– V_VIN, 3.8 V < V_VIN≤ 5.5 V,

V_REG= 5.35 V, I_VCP2> –5 mA, Buck-Boost Mode

V_VCP– V_VIN, V_VIN> 9 V, I_VCP> –1 mA,

Buck Mode

VCP Output Voltage

(for Gate Drivers)

V_VCP– V_VIN, 5.5 V < V_VIN≤ 9 V, I_VCP> –1 mA,

Buck Mode

V_VCP

8

10

V_VCP– V_VIN, 3.8 V < V_VIN≤ 5.5 V, V_VREG

5.35 V, I_VCP> –1 mA, Buck-Boost Mode

=

6.6

–

9.5

65

–

V

Switching Frequency

f_CPx

kHz

VCC PIN VOLTAGE

Output Voltage

V_VCC

V_VREG= 5.35 V

T_Jrising

–

4.4

–

V

THERMAL PROTECTION

Thermal Shutdown Threshold ^[2]

Thermal Shutdown Hysteresis ^[2]

T_TSD

T_HYS

165

–

°C

15

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

7

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

OUTPUT VOLTAGE SPECIFICATIONS

Pre-Regulator Output Voltage ^[2]

PULSE-WIDTH MODULATION (PWM)

PWM Ramp Offset

V_VREG

V_VIN= 13.5 V, 0.1 A < I_VREG< 1.2 A

5.25

5.35

5.45

V

V_PWM(OFFS)V_COMPfor 0% duty cycle

SR_LXRISEV_VIN= 13.5 V, 10% to 90%, I_VREG= 1 A

V_VIN= 13.5 V, 90% to 10%, I_VREG= 1 A

–

480

1.4

1.5

85

–

mV

V/ns

ns

LX Rising Slew Rate ^[2]

LX Falling Slew Rate ^[2]

Buck Minimum On-Time

Buck Maximum Duty Cycle

SR_LXFALL

–

t_ON(BUCK,MIN)

160

100

D_BUCK(MAX)V_VIN< 7.8 V

After V_VIN> V_VIN(START), VREG regulating,

%

–

60

–

%

V_VIN= 3.8 V

Boost Duty Cycle

D_BST

V_VIN= 6.5 V

–

29

–

%

COMP to LX Current Gain

Slope Compensation ^[2]

INTERNAL MOSFET

gm_POWER

S_E

4.57

1.62

A/V

A/µs

1.1

2.15

V_VIN= 13.5 V, T_J= ‒40°C ^[2], I_DS= 0.1 A

V_VIN= 13.5 V, T_J= 25°C ^[3], I_DS= 0.1 A

V_VIN= 13.5 V, T_J= 150°C, I_DS= 0.1 A

–

60

95

90

mΩ

MOSFET On Resistance

MOSFET Leakage Current

R_DS(on)

115

190

160

V_ENBAT≤ 2.2 V, V_ENB= Low, V_LX= 0 V,

V_VIN= 16 V, −40°C < T_J< 85°C ^[3]

–

10

µA

I_FET(LKG)

V_ENBAT≤ 2.2 V, V_ENB≤ Low, V_LX= 0 V,

V_VIN= 16 V, −40°C < T_J< 150°C

50

150

ERROR AMPLIFIER

Open Loop Voltage Gain

A_VOL

gm_EA

–

520

260

–

60

720

360

±75

1.52

1.22

–

dB

µA/V

µA

V_SS(internal signal) = 750 mV

V_SS(internal signal) = 500 mV

920

460

–

Transconductance

Output Current

I_O(EA)

V_VIN< 8.5 V

V_VIN> 9.5 V

1.2

0.9

–

2.1

1.7

300

V

Maximum Output Voltage

V_O(EA,MAX)

V

Minimum Output Voltage

V_O(EA,MIN)

R_COMP

mV

HICCUP = 1 or FAULT = 1 or

V_ENBAT= Low and V_ENB= Low

COMP Pull-Down Resistance

–

1

–

kΩ

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

8

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

BOOST MOSFET (LG) GATE DRIVER

LG High Output Voltage

LG Low Output Voltage

LG Source Current ^[1]

LG Sink Current ^[1]

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

V_LG(ON)

V_LG(OFF)

I_LG(ON)

V_VIN= 6 V, V_VREG= 5.35 V

4.6

–

5.35

0.4

–

V

V_VIN= 13.5 V, V_VREG= 5.35 V

0.2

V

V_VIN= 6 V, V_VREG= 5.35 V, V_LG= 1 V

V_VIN=13.5 V, V_VREG= 5.35 V, V_LG= 1 V

–

−300

150

mA

I_LG(OFF)

–

SOFT-START

SS Ramp Time ^[2]

t_SS

–

900

–

µs

–

0 V ≤ V_VREG< 0.67 V typical

0.67 V ≤ V_VREG< 1.34 V typical

1.34 V ≤ V_VREG< 2.68 V typical

V_VREG≥ 2.68 V typical

f_OSC/8

f_OSC/4

f_OSC/2

f_OSC

–

SS PWM Frequency Foldback

f_SW(SS)

–

HICCUP MODE

Hiccup Enable Delay Time ^[2]

Hiccup Recovery Time ^[2]

t_HIC(EN)

–

230

930

–

µs

t_HIC(REC)

PWM

cycles

V_VREG< 1.3 V_TYP, V_COMP= V_O(EA,MAX)

V_VREG> 1.3 V_TYP, V_COMP= V_O(EA,MAX)

–

32

–

Hiccup OCP PWM Counts

t_HIC(OCP)

PWM

cycles

120

CURRENT PROTECTIONS

Pulse-by-Pulse Current Limit

LX Short-Circuit Current Limit

V_VIN< 8.5 V

3.83

2.49

5.3

4.2

2.8

7.1

4.77

3.11

–

A

I_LIM(ton,min)

I_LIM(LX)

V_VIN> 9.5 V

Latched fault after 2^nddetection

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

9

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

MISSING ASYNCHRONOUS DIODE (D1) PROTECTION

Detection Level

Time Filtering ^[2]

V_D(OPEN)

t_D(OPEN)

−1.9

−1.4

−1.0

V

50

–

250

ns

VUC, V5A, V5Px LINEAR REGULATORS

VUC Accuracy and Load Regulation

V_VUC5

10 mA < I_VUC< 375 mA, V_VREG= 5.25 V

4.9

5.0

5.1

V

(5 V_OUT

VUC Accuracy and Load Regulation

(3.3 V_OUT

)

V_VUC33

3.23

3.30

3.37

)

VUC Output Capacitance Range ^[2]

V5A Accuracy and Load Regulation

V5A Output Capacitance Range ^[2]

V5Px Accuracy and Load Regulation

V5Px Output Capacitance Range ^[2]

VUC OVERCURRENT PROTECTION

VUC Current Limit ^[1]

C_OUT(VUC)

V_V5A

C_OUT(V5A)

V_V5Px

1.0

4.9

1.0

4.9

1.0

–

5.0

–

15

5.1

15

µF

V

5 mA < I_V5A< 150 mA, V_VREG= 5.25 V

5 mA < I_V5Px< 120 mA, V_VREG= 5.25 V

µF

V

5.0

–

5.1

15

C_OUT(V5Px)

µF

I_VUC(LIM)

I_VUC(FBK)

–412

–65

–625

–187

–880

–275

mA

VUC Foldback Current ^[1]

V_VUC= 0 V

V_V5A= 0 V

V_V5Px= 0 V

V5A OVERCURRENT PROTECTION

V5A Current Limit ^[1]

I_V5A(LIM)

I_V5A(FBK)

–160

–20

–235

–78

–325

–163

mA

V5A Foldback Current ^[1]

V5Px OVERCURRENT PROTECTION

V5Px Current Limit ^[1]

I_V5Px(LIM)

I_V5Px(FBK)

–135

–20

–230

–60

–350

–125

mA

V5Px Foldback Current ^[1]

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

10

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

VUC, V5A, AND V5Px STARTUP TIMING

[2]

VUC Startup Time (5 V_OUT

)

t_VUC5(START)C_VUC= 2.2 µF ±20%, Load = 15 Ω ±10%

t_VUC33(START)C_VUC= 2.2 µF ±20%, Load = 10 Ω ±10%

–

0.15

0.13

0.22

1.0

0.65

1.2

ms

[2]

VUC Startup Time (3.3 V_OUT

)

V5A Startup Time ^[2]

t_V5(START)

C_V5A= 2.2 µF ±20%, Load = 40 Ω ±10%

V5Px Startup Time ^[2]

t_V5Px(START)C_V5Px= 2.2 µF ±20%, Load = 50 Ω ±10%

1.2

IGNITION ENABLE (ENBAT) INPUT

ENBAT Upper Threshold

ENBAT Lower Threshold

ENBAT Hysteresis

V_ENBAT(H)

V_ENBAT(L)

V_ENBATrising

V_ENBATfalling

2.7

2.2

–

3.1

2.6

500

20

3.5

2.9

–

V

V_ENBAT(HYS)V_ENBAT(H)– V_ENBAT(L)

mV

µA

mA

kΩ

V_ENBAT= 3.5 V

–

50

5.5

–

ENBAT Bias Current ^[1]

I_ENBAT(BIAS)

V_ENBAT= 40 V

–

ENBAT Pulldown Resistance

LOGIC ENABLE (ENB) INPUT

ENB Upper Threshold

ENB Lower Threshold

ENB Bias Current ^[1]

R_ENBAT

V_ENBAT< 1.2 V

–

600

V_ENB(H)

V_ENB(L)

I_ENB(IN)

R_ENB

V_ENBrising

V_ENBfalling

V_ENB= 3.3 V

–

0.8

–

2.0

–

V

–

175

–

µA

kΩ

ENB Resistance

–

60

ENB/ENBAT DELAY

Enable Falling Delay Time

t_dLDO(OFF)

10

15

20

µs

VUC, V5A, AND V5Px UNDERVOLTAGE DETECTION THRESHOLDS

V_V5(UV,H)

V_V5(UV,L)

V_V5rising

V_V5falling

–

4.68

4.65

–

V

VUC (5 V_OUT), V5A, and V5Px

Undervoltage Thresholds

4.50

4.80

VUC (5 V_OUT), V5A, and V5Px

Undervoltage Hysteresis

V_V5(UV,HYS)V_{V5(UV,H) –}V_V5(UV,L)

–

30

–

mV

V_3V3(UV,H)

V_3V3(UV,L)

V_3V3rising

V_3V3falling

–

3.12

3.1

–

V

VUC (3.3 V_OUT

Undervoltage Thresholds

)

2.8

3.19

VUC (3.3 V_OUT

Undervoltage Hysteresis

)

V_3V3(UV,HYS)V_{3V3(UV,H) –}V_3V3(UV,L)

–

20

–

mV

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

11

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

VUC, V5A, V5P1, AND V5P2 OVERVOLTAGE PROTECTION THRESHOLDS

V_V5(OV,H)

V_V5(OV,L)

V_V5Arising

V_V5Afalling

5.15

–

5.33

5.30

5.5

–

V

VUC (5 V_OUT), V5A, and V5Px

Overvoltage Thresholds

VUC (5 V_OUT), V5A, and V5Px

Overvoltage Hysteresis

V_V5(OV,HYS)

V_V5A(OV,H)– V_V5A(OV,L)

–

30

–

mV

V5Px Output Disconnect Threshold

V_V5Px(DISC)

V_3V3(OV,H)

V_3V3(OV,L)

V_V5Pxrising

V_3V3rising

V_3V3falling

–

3.45

–

7.2

–

3.66

–

V

3.51

3.49

VUC (3.3 V_OUT

)

Overvoltage Thresholds

VUC (3.3 V_OUT

Overvoltage Hysteresis

)

V_3V3(OV,HYS)V_3V3(OV,H)– V_3V3(OV,L)

–

20

–

mV

VREG, VCPx, AND BG THRESHOLDS

V_VREG(OV,H)

V_VREG(OV,L)

V_VREGrising, LX PWM disabled

V_VREGfalling, LX PWM enabled

5.70

–

5.95

5.85

6.20

–

V

VREG Non-Latching Overvoltage

Threshold

VREG Non-Latching Overvoltage

Hysteresis

V_VREG(OV,HYS)V_VREG(OV,H)– V_VREG(OV,L)

V_VREGrising, triggers rise of VUC linear

–

100

–

mV

V

V_VREG(UV,H)

4.50

4.75

5.00

regulator

VREG Undervoltage Thresholds

V_VREG(UV,L)

V_VREGfalling

–

4.65

100

–

V

VREG Undervoltage Hysteresis

VCP2 Overvoltage Thresholds

V_VREG(UV,HYS)V_VREG(UV,H)– V_VREG(UV,L)

mV

Detected on CP2C1 pin.

V_VCP2(OV,H)

11.0

12.5

14.0

V

Defined as V_VIN– V_CP2C1, V_VIN≥ 14 V

V_VCP2(UV,H)

V_VCP2(UV,L)

V_VCP2(UV,HYS)V_VCP2(UV,H)– V_VCP2(UV,L)

V_VCP(UV,H)V_VCPrising, PWM enabled (w.r.t. V_VIN

V_VCP(UV,L)

V_VCP2rising, PWM enabled (w.r.t. V_VIN

)

2.78

–

3.1

2.8

400

6.3

5.1

1.2

3.26

–

V

VCP2 Undervoltage Thresholds

(Pre-Regulator)

V_VCP2falling, PWM disabled (w.r.t. V_VIN

)

VCP2 Undervoltage Hysteresis

VCP Undervoltage Thresholds

VCP Undervoltage Hysteresis

–

mV

V

)

5.71

–

6.63

–

V_VCPfalling, PWM disabled (w.r.t. V_VIN

)

V

V_VCP(UV,HYS)V_VCP(UV,H)– V_VCP(UV,L)

–

V

BG1 and BG2 Undervoltage

Thresholds ^[2]

V_BGx(UV)

V_BG1or V_BG2falling

1.00

1.05

1.10

V

OVERVOLTAGE FILTERING/DEGLITCH TIME

Overvoltage Detection Delay ^[2]

t_d(OV)

UNDERVOLTAGE FILTERING/DEGLITCH TIME

Undervoltage Filter/Deglitch Times ^[2]

t_d(UV)

Overvoltage detection delay time

Undervoltage detection delay time

5

–

25

µs

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

12

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

NPOR TURN-ON AND TURN-OFF DELAYS

Time from VUC > V_3V3(UV,H)(or V_V5(UV,H)) to

when the NPOR pin becomes high impedance

NPOR Turn-On Delay

t_d(NPOR,ON)

3.7

5

6.3

ms

NPOR OUTPUT VOLTAGES

I_NPOR= 4 mA

–

150

–

400

200

2

mV

µA

NPOR Output Low Voltage

NPOR Leakage Current ^[1]

V_NPOR(L)

V_VIN= 5.5 V, I_NPOR= 2 mA

I_NPOR(LKG)V_NPOR= 3.3 V

–

NPOR ONE-SHOT TIME (ONLY if enabled via SPI using the NPOR_KEY)

NPOR One-Shot “Low” Time After

t_WD(FAULT)

1.6

2

2.4

ms

Watchdog Fault

FAULT FLAG OUTPUT VOLTAGES (FFn)

FFn Output Voltage

FFn Leakage Current

V_FFn(L)

FFn is tripped, I_FFn= 2 mA

V_FFn= 3.3 V

–

150

–

400

2

mV

µA

I_FFn(LKG)

WD_INVOLTAGE THRESHOLDS AND RESISTANCE

WD_INUpper Threshold

V_WDIN(HI)

V_WDIN(LO)

R_WDIN

V_WDINrising

V_WDINfalling

–

0.8

–

2.0

–

V

WD_INLower Threshold

WD_INPull-Down Resistance ^[2]

WD TIMING SPECIFICATIONS

Watchdog Configuration Time

WD_Fn OUTPUT SPECIFICATIONS

50

–

kΩ

t_CONFIG(WD)Can be bypassed by setting WD_SEL bits

–

1000

–

ms

I_{WD_Fn}= 4 mA

–

150

–

400

200

2

mV

µA

Output Low Voltage

V_{WD_Fn(L)}

V_VIN= 5.5 V, I_{WD_Fn}= 1 mA

Leakage Current

I_{WD_Fn(LKG)}V_{WD_Fn}= 3.3 V

–

GATE DRIVE ENABLE (POE)

V_POE(L)

V_POE(H)

I_POE= 4 mA

–

150

–

400

–

mV

V

POE Output Voltage

I_POE= –1.5 mA

0.8 × V_VUC

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

13

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

SERIAL INTERFACE (STRn, SDI, SDO, SCK)

Input Low Voltage

V_IL

V_IH

–

0.8

–

V

Input High Voltage

All logic inputs

2.0

Input Hysteresis

V_Ihys

250

550

50

–

mV

kΩ

V

MOSI and SCK Input Pull-Down

CS Input Pull-Up to 3.0 V

Output Low Voltage

R_PD

V_MOSIor V_SCK= 3.3 V

–

R_PU

–

V_OL

I_OL= 1 mA ^[1]

–

0.4

–

Output High Voltage

V_OH

I_OL= –1 mA ^[1]

0.8 × V_VUC

–

V

SPI Clock Frequency ^[2]

SPI Frame Rate ^[2]

f_SCK

MISO pins, C_L= 20 pF

0.1

2.94

50

30

300

–

10

294

–

MHz

kHz

ns

t_SPI

–

Clock High Time

t_SCK(H)

t_SCK(L)

t_CS(LD)

t_CS(LG)

t_CS(H)

t_MISO(EN)

t_MISO(D)

A in Figure 1

B in Figure 1

C in Figure 1

D in Figure 1

E in Figure 1

F in Figure 1

G in Figure 1

–

Clock Low Time

–

Chip Select Lead Time

Chip Select Lag Time

Chip Select High Time

Data Out (MISO) Enable Time ^[2]

Data Out (MISO) Disable Time ^[2]

–

40

30

–

Data Out (MISO) Valid Time

From SCK Falling ^[2]

t_MISO(V)

t_MISO(H)

t_MOSI(SU)

t_MOSI(H)

H in Figure 1

J in Figure 1

K in Figure 1

L in Figure 1

–

5

–

40

–

ns

Data Out (MISO) Hold Time

From SCK Falling ^[2]

Data In (MOSI) Set-Up Time

To SCK Rising

15

10

–

Data In (MOSI) Hold Time

From SCK Rising

–

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

ꢀ

ꢂS

ꢂ

A

ꢅ

ꢉ

Sꢂꢃ

MꢋSꢌ

MꢌSꢋ

ꢃ

ꢄ

ꢁ

Dꢀ1

ꢁ

Dꢀ0

ꢁ

D0

ꢁ

ꢆ

ꢇ

ꢈ

ꢊ

D31'

D30'

D0'

H

Figure 1: Serial Interface Timing for Write and Read Cycles

MISO activity assumes the Chip_ID from the previous frame was correct

14

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ELECTRICAL CHARACTERISTICS (continued) ^[1]: Valid at 3.8 V ^[4]≤ V_VIN≤ 36 V, –40°C ≤ T_J≤ 150°C, V_ENB= High or

V_ENBAT= High, unless otherwise speciﬁed

Characteristic

GATE OUTPUT DRIVE (z = U, V, W)

Turn-On Time

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

t_r

C_LOAD= 10 nF, 20% to 80%

C_LOAD= 10 nF, 80% to 20%

–

5

0.5

10

–

μs

mA

μs

μA

Ω

Turn-Off Time

t_f

Turn-On Pulse Current

Turn-On Pulse Time

On Hold Current

I_GP

t_GP

I_GH

8.5

22

–

12.5

42

–

400

5

T_J= 25°C, I_G= 10 mA

–

Pull-Down On Resistance ^[3]

R_DS(on)DN

T_J= 150°C, I_G= 10 mA

–

10

9

–

Ω

V_VIN> 5.5 V (w.r.t. V_S, or VIN if V_S> V_VIN

)

8

12

V

Gz and G_VBBHigh Output Voltage

V_GH

4.5 V < V_VIN≤ 5.5 V (w.r.t. V_S, or VIN if V_S>

V_VIN), Buck-Boost mode

7.2

9

–

V

Gz and G_VBBLow Output Voltage

Gz and G_VBBPassive Pull-Down

Gz and G_VBBExternal Load Resistance ^[2]

V_GL

R_GPD

R_G

–10 μA < I_G< 10 μA

–

950

–

V_S+ 0.3

V

V_G– V_S< 0.3 V

–

kΩ

Between gate and source (using ±1% resistor)

100

GATE DRIVE DIAGNOSTICS AND FILTERING (z = U, V, W)

Gz and G_VBBUV Threshold Rising

Gz and G_VBBUV Threshold Hysteresis ^[2]

Gz and G_VBBOV Threshold Falling

Gz and G_VBBOV Threshold Hysteresis ^[2]

V_G(UV,H)

V_G(UV,HYS)

V_G(OV,L)

V_Grising (w.r.t. V_S)

6.0

–

7.1

–

V

250

–

mV

V

V_Gfalling (w.r.t. V_S)

0.35

–

1.05

–

V_G(OV,HYS)

150

1.4

20

mV

ms

μs

Voltage detection delay, GD_UV_SEL = 0

Voltage detection delay, GD_UV_SEL = 1

–

Gz and G_VBBRising/Falling Filter Time

t_dFILT(Gz)

15

25

GATE DRIVE PROPAGATION DELAYS (z = U, V, W)

EN_VBBEnable/Disable Delay Times,

t_d(EN,VBB)

From “SPI command is written” to G_VBB20%

(enable), to G_VBB80% (disable)

–

1.5

10

–

6

ms

μs

GD_EN_SEL = 0

ENz Enable/Disable Delay Times,

t_d(Enz)

From “SPI command is written” to Gz

20% (enable), to Gz 80% (disable)

GD_EN_SEL = 0

ENVBB and Enz Enable/Disable

Delay Times, GD_EN_SEL = 1

t_d(EN,VBB),

t_d(Enz)

From “SPI command is written” to Gz or G_VBB

20% (enable), to Gz or G_VBB80% (disable)

SVBB DIAGNOSTICS AND FILTERING

SVBB UV Threshold Falling

V_SVBB(UV,L)V_SVBBfalling (w.r.t. GND)

V_SVBB(UV,HYS)

–

2.5

650

0.8

20

3.0

–

V

SVBB UV Threshold Hysteresis

mV

ms

µs

Undervoltage detection delay, GD_UV_SEL = 0

Undervoltage detection delay, GD_UV_SEL = 1

–

1.0

25

SVBB UV Filter/Deglitch Times

t_d(FILT,VBB)

15

^[1]For input and output current speciﬁcations, negative current is deﬁned as coming out of the node or pin (sourcing), positive current is deﬁned as going into the node or

pin (sinking).

^[2]Ensured by design and characterization, not production tested.

^[3]Speciﬁcations at 25°C or 85°C are guaranteed by design and characterization, not production tested.

^[4]The lowest operating voltage is only valid if the conditions V_VIN> V_VIN(START)and V_VCP– V_VIN> V_VCP(UV,H)and V_VREGin regulating are satisﬁed before V_VINis reduced.

15

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

13.5 ꢅ

ꢅꢆN

ꢋNꢐ ꢁR ꢋNꢐAꢑꢒ HꢆꢌH

ꢋN

0.5 ms

3.ꢔ ꢅ

ꢅꢂꢂ

ꢖꢊꢗ0 ꢘs

ꢐꢆSꢑ

ꢅ_{SSꢍꢁꢏꢏSꢎ}

SSꢇ

ꢂꢁMP

ꢀ_ꢁSꢂꢈꢉ

ꢀ_ꢁSꢂꢈꢊ

ꢀ_ꢁSꢂ

ꢃꢄ

ꢅRꢋꢌ

ꢅUꢂ

t_SS

0.ꢉ ms

ꢅ_{ꢅRꢋꢌꢍUꢅ,Hꢎ}

All LDOs turn on siꢀultaneouslꢁ at ꢂ

ꢂRꢃGꢄꢅꢂ,ꢆꢇ

ꢅ_{ꢅUꢂꢍUꢅ,Hꢎ}

ꢅ5A

ꢅ5Pꢕ

ꢅUꢂ ꢁꢓꢇ

NPꢁR

t_{dꢍNPꢁR,ꢁNꢎ}

Bꢁ deꢈault, ꢉPOR onlꢁ depends on ꢂꢅꢊ

Figure 2: Startup Timing Diagram

16

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ꢀꢁN

t_dꢅꢂNꢆ

ꢂNꢃ

and

ꢂNꢃAꢄ

t_{ꢉUꢄꢅꢌAꢇꢇꢆ}

ꢀUꢍ Uꢀ

ꢇꢈꢉ

ꢉꢊtꢋꢊts

t_dꢅUꢀꢆ

NPꢉR

All LDO outputs start to decay t_d(EN)seconds after ENB and ENBAT are low.

The time for an output to decay to zero, t_OUT(FALL), varies for each LDO and depends on load and output capacitance.

NPOR transitions low after VUC crosses its UV threshold

Figure 3: Shutdown Timing Diagram

17

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

TIMING DIAGRAMS (not to scale)

* is for internal signal or threshold

ENB+ENBAT HIGH

EN

V_HIC(EN)

*

V_SS(OFFS)

*

V_SS(RST)

SS*

EN_HIC*

HIC*

32×

OCP

32×

OCP

32×

OCP

OCP*

V_O(EA,MAX)

*

V_PWM(OFFS)

COMP

f_OSC

/4

f_OSC

/4

f_OSC

/4

f_OSC/8

LX

1.3 V

VREG

Figure 4: Hiccup Mode Operation with VREG Shorted to GND (R_LOAD< 50 mΩ)

ENB+ENBAT HIGH

EN

V_HIC(EN)

*

V_SS(OFFS)

*

V_SS(RST)

SS*

EN_HIC*

HIC*

120× OCP

OCP*

V_O(EA,MAX)

V_PWM(OFFS)

COMP

f_OSC/4 f_OSC/2 f_OSC

LX

2.7 V

1.3 V

VREG

Figure 5: Hiccup Mode Operation with VREG Overloaded (R_LOAD≈ 0.5 Ω)

18

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Table 1: Summary of Fault Mode Operation

FAULT

VIN UV

A81407 RESPONSE

VREG

VUC

V5A

V5Px ^[4]

FFn

NPOR

WD_Fn

POE

GVBB

GZ ^[4]

SPI

WD

RESET

Increase VIN

Replace the IC

MPOR,

VCP2_UV & VCP_UV

0 V

Low

High

Low

Off

BG1, BG2 UV

UV by only a small

amount, but VUC OK

VREG UV

UV

–

Low

–

On

VUC UV

V5A UV

V5PX UV ^[4]

VCP2 UV

VCP UV

–

UV

–

UV

–

Low

–

Low

–

Off

–

On ^[9]

–

On

Off

On

[5]

–

UV

0 V

–

Low

–

VCP2_UV & VCP_UV

No external gate drive

GVBB off to protect FET

0 V

–

0 V

–

0 V

–

Low

–

Off

On ^[9]

SVBB_UV

–

G_Z_UV ^[4]or G_VBB_UV

when set to ON

G_Z_OV ^[4]or G_VBB_OV

when set to OFF

Inform the microcontroller

–

Low

–

On

VREG OV

VUC OV

OV

–

OV

–

Low

–

Low

–

Low

–

Off

–

On ^[9]

–

On

Off

On

Off

On

Off

On

V5A OV

V5Px OV/STB ^[3][4]

–

OV

–

Disconnect occurs >7.2 V

–

OV ^[10]

0 V

–

VCP2 OV

0 V

HIC

–

0 V

–

0 V

–

Low

–

Low

–

Off

–

Off

On ^[9]

–

VCC STG ^[3]

VREG STG ^[3]

VUC STG ^[3]

V5A STG ^[3]

V5PX STG ^[3]

LX STG ^[3]

VCC ILIM and MPOR

Hiccup mode

VUC Foldback ILIM

V5A Foldback ILIM

V5PX Foldback ILIM

Latch off after 2×

–

0 V

–

Remove STG

–

0 V

–

Off

–

0 V

–

0 V

–

Low

–

Low

–

Off

–

On ^[9]

V_VIN> 8.5 V, LG off

V_VIN< 8.5 V, LG active

–

LG STG ^[3]

–

Low

–

VCP2 high current and fusing.

Definitely VCP_UV too.

VCP2 STG ^[3]

0 V

Low

–

Low

Off

On or Off

Replace the IC

VCP high current and fusing,

no external gate drive.

Likely VCP2_UV too.

VCP STG ^[3]

0 V

Low

–

Low

Off

On or Off

CP2C1 STG ^[3]

CP2C2 STG ^[3]

VCP2_UV and VCP_UV

0 V

Low

–

Low

Off

On

Remove STG

Replace the IC

VCP2 high current and fusing

VCP high current and fusing,

no external gate drive.

Likely VCP2_UV too.

CP1 STG ^[3]

0 V

Low

–

Low

Off

On or Off

Remove STG

Replace the IC

CP2 STG ^[3]

Watchdog Fault

BIST Fault

VCP high current and fusing

PWWD, WWD, or Q&A

Inform the microcontroller

VREG cannot rise

–

Low

–

Low

–

On

Off

On

Off

On

Off

On

[6]

[7]

[8]

–

Low

–

DBE Fault

–

SE Fault

–

L1 missing

0 V

Off

0 V

–

0 V

–

0 V

–

0 V

–

Low

–

Low

–

Off

On ^[9]

Off

Diode D1 missing

C_CP2C1/CP2C2missing

C_VCP2missing

C_CP1/CP2missing

C_VCPmissing

L1 shorted

Latch off after 2×

–

VCP2_UV and VCP_UV

VCP2_UV & VCP_UV

–

Off

VCP2_UV, No ext. gate drive

LX fault, latch off after 2×

VCP2_UV and VCP_UV

VCP2_UV & VCP_UV

–

Off

Replace missing

component, or

remove short circuit.

–

Off

On ^[9]

Off

0 V

–

0 V

–

0 V

–

0 V

–

Low

–

Low

–

C_CP2C1/CP2C2shorted

C_VCP2shorted

C_CP1/CP2shorted

C_VCPshorted

TSD

–

Off

–

Off

VCP_UV, No ext. gate drive

Stop PWM, maintain SPI

–

Off

–

Off

On ^[9]

0 V

Low

–

Low

IC cooldown

^[1]“–” = No effect, operates normally.

^[2]MPOR = Master Power-On Reset.

^[3]STG = short-to-ground, STB = short-to-battery.

^[4]V5Px where (x = 1 or 2), G_Zwhere (z = U or V or W).

^[5]By default, V5A UV will not affect NPOR. However, there is an option, via SPI programming, to have NPOR transition low if V5A is UV.

^[6]By default, a WD Fault will not affect FFn. However, there is an option, via SPI programming, to have FFn latch low.

^[7]By default, a WD Fault will not affect NPOR. However, there is an option, via SPI programming, to have NPOR momentarily transition low for 2 ms to reset the MCU.

^[8]By default, a WD Fault will not affect the four gate drivers. However, there is an option, via WDF_2_Gz, to have all four gate drivers turn off after a watchdog fault.

^[9]By default, the state of GVBB is off and GU/GV/GW are on after a fault, other than a watchdog fault. However, there is an option, via GD_FLT_ON, to have GU/GV/GW turn off.

^[10]V5Px STB will be reported to SPI diagnostic register (0x05) as both V5Px UV and OV fault.

19

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

FUNCTIONAL DESCRIPTION

Charge Pump (VCP, VCP2)

Overview

The A81407 pre-regulator can be configured as an asynchronous

buck or buck-boost converter. This pre-regulator generates a

fixed 5.35 V (VREG) and can deliver up to 1.2 A to power the

internal post-regulators. The post regulators generate the various

voltage levels for the end system.

Charge pump circuits provide the voltage necessary to drive high-

side N-channel MOSFETs in the pre-regulator, linear regulators,

and floating gate drivers. Four external capacitors are required

for charge pump operation. During the first cycle of the charge

pump, the flying capacitor between pins CP2C1 and CP2C1 is

charged from either VIN or VREG, whichever is highest. During

the second cycle, the voltage on the flying capacitor charges the

VCP2 capacitor and the flying capacitor between CP1 and CP2.

During the last cycle, the voltage on the flying capacitor charges

the VCP capacitor. The charge pump incorporates some safety

features:

Pre-Regulator (VREG)

The pre-regulator incorporates an internal high-side and a boost

switch gate driver. An external free-wheeling diode and LC filter

are required to complete the buck converter. By adding a MOS-

FET and boost diode, the pre-regulator can maintain all outputs

with input voltages down to 3.8 V.

1. Undervoltage and overvoltage detection and reporting

2. Overcurrent safe mode protection

The pre-regulator provides many protection and diagnostic func-

tions:

Bandgap (BG1, BG2)

1. Pulse-by-pulse and hiccup mode current limit

2. Undervoltage and overvoltage detection and reporting

3. Shorted switch node to ground protection

4. Open free-wheeling diode (D1) protection

5. High voltage rating for load dump

Dual band gaps are implemented within the A81407. One band-

gap is dedicated to the voltage regulation loops within each of the

regulators, VCC, VCP, VCP2, VREG, and the four post regula-

tors. The second is dedicated to the undervoltage and overvoltage

monitoring functions of all the regulators. This improves safety

coverage and fault reporting from the A81407.

PWM Switching Frequency

Should the regulation bandgap fail, then the output voltages will be

The switching frequency of the A81407 is fixed at 2.2 MHz, typi- out of specification and the monitoring bandgap will report the fault.

cal. The A81407 includes a frequency foldback scheme that starts

If the monitoring bandgap fails, the output voltages will remain

when V_VINis greater than 18 V. From 18 to 36 V, the switching

in regulation, but the monitoring circuits will report the outputs

as out of specification and trip the fault flag.

frequency will foldback from 2.2 to 1 MHz (typical). The switch-

ing frequency (f_SW) for a given input voltage (V_VIN) above 18 V

and below 36 V is:

The bandgap circuits include two smaller, secondary bandgaps that

are used to monitor the undervoltage state of the main bandgaps.

f_SWin MHz = 3.4 – (1.2 / 18) × V_VIN

Enable Inputs (ENB, ENBAT)

Bias Supply (VCC)

Two enable pins are available on the A81407. A high signal on

either of these pins enables the regulated outputs of the A81407.

One enable (ENB), is logic level compatible. The second enable

(ENBAT), is battery-level rated and can be connected to the igni-

tion switch through a low-pass filter.

The bias supply (V_CC) is generated by an internal linear regulator.

This supply is the first rail to start up. Most of the internal control

circuitry is powered by this supply. The bias supply includes

some unique features to ensure safe operation of the A81407.

These features include:

1. VIN input undervoltage lockout

2. VCC undervoltage detection

3. VCC overcurrent and short-circuit current limit

4. Dual input operation: VIN or VREG, for ultra-low battery

voltage operation

20

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

The POE signal can be used to put the system in a safe state, for

example, by disabling the gate driver in a motor application.

Linear Regulators

The A81407 has four linear regulators: one (VUC) that provides

3.3 V (or 5 V for the A81407-1), and three fixed at 5 V (V5A,

V5P1, V5P2). Two of these regulators (V5P1, V5P2) are high-

voltage tolerant so they are protected from connection to the bat-

tery voltage. This makes these outputs most suitable for powering

remote sensors or circuitry where a short-to-battery is possible.

POE includes some additional safe systems. It is continuously

monitored to ensure the signal output matches the A81407

internal circuit’s demand. It is also powered by a separate internal

power rail for added protection.

Startup Self-Tests

The pre-regulator supplies 5.35 V (VREG) to the linear regulators,

which reduces power dissipation and temperature.

The A81407 includes self-test which is performed during the

startup sequence. This self-test verifies the operation of the

undervoltage and overvoltage detect circuits for the main outputs,

and the overtemperature shutdown circuitry.

All linear regulators provide the following protection features:

1. Current limit with foldback

In the event the self-test fails, the A81407 will report the failure

through SPI.

2. Undervoltage and overvoltage detection and reporting

Fault Detection and Reporting

(NPOR, WD_Fn, FFn)

Undervoltage Detect Self-Test

The undervoltage (UV) detection circuits are verified during

startup of the A81407. A voltage that is lower than the undervolt-

age threshold is applied to each UV comparator; this should cause

the corresponding undervoltage bit in the Diagnostic register to

change state: 0→1, indicating a fault. If a diagnostic UV register

bit does not change state, the corresponding Verify Result bit is

latched high. So, when testing is complete, if any bits in the Verify

Result registers are high, then verification has failed. The following

UV comparators are tested: VREG, VUC, V5A, V5P1, and V5P2.

There is extensive fault detection within the A81407; most have

been discussed previously. There are two fault reporting mecha-

nisms used by the A81407; one through hardwired pins and the

other through serial communications interface (SPI).

Three hardwired pins are used for fault reporting. The first pin,

NPOR (open-drain, active low), reports on the status of the VUC

output. By default, this signal transitions low only if VUC is out

of regulation (undervoltage or overvoltage). However, options are

available to: (1) report a Watchdog Fault by momentarily setting

NPOR low for 2 ms, and (2) indicate if V5A is out of regulation.

These additional NPOR options are selectable through SPI.

Overvoltage Detect Self-Test

The overvoltage (OV) detection circuits are verified during

startup of the A81407.

The second pin, WD_Fn (open-drain, active low), latches low if a

Watchdog Fault is detected.

A voltage that is higher than the overvoltage threshold is applied

to each OV comparator; this should cause the corresponding

overvoltage bit in the Diagnostic register to change state: 0→1,

indicating a fault. If a diagnostic OV register bit does not change

state, the corresponding Verify Result register bit is latched high.

So, when testing is complete, if any bits in the Verify Result

registers are high then verification has failed. The following OV

comparators are tested: VREG, VUC, V5A, V5P1, and V5P2.

A third pin, FFn (open-drain, active low), reports on all other

faults. FFn transitions low when a fault is detected. The FFn out-

put should be connected to an interrupt pin on the processor so it

will check the A81407 status and take appropriate action if a fault

occurs. By default, FFn does not report a Watchdog Fault, but it

may be added to the FFn logic via SPI programming.

Safe State Control Signal (POE)

Overtemperature Shutdown Self-Test

The safe state control signal or power-on enable (POE) is a sig-

nal generated when certain potentially unsafe failures occur. The

A81407 is designed to power a system microcontroller with its VUC

output. It can also monitor this system controller using a watchdog

function. A failure of the system controller may be considered to be

unsafe. The following faults will cause the POE signal to be low:

The overtemperature shutdown (TSD) detector is verified during

startup of the A81407.

A voltage that is higher than the overvoltage threshold is applied to

the TSD comparator; this should cause the overtemperature bit in

the Diagnostic register to change state: 0→1, indicating a fault. If

the TSD register bit does not change state, the TSD Verify Result

register bit is latched high. So, when testing is complete, if the TSD

bit in the Verify Result registers is high, then verification has failed.

1. Watchdog fault

2. VUC fault

21

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

The floating gate-drive outputs for external N-channel MOSFETs

Power-On Enable (POE) Self-Test

are provided on pins GVBB, GU, GV, and GW. When Gz = 1

(or “high”), the upper half of the driver is on and current will be

sourced to the gate of the MOSFET, turning it on. When Gz = 0

(or “low”), the lower half of the driver is on and will sink current

from the external MOSFET’s gate to the respective Sz terminal,

turning it off.

The A81407 incorporates continuous self-testing of the power-

on enable (POE) output. It compares the status of the POE pin

(POE_S) with the internal expected status. If they differ for any

reason, the FFn output pin is set low and POE_OK in the status

register is set low.

Analog Multiplexer Output

The reference points for the floating drives are the load phase

connections, SVBB, SU, SV, and SW. The discharge current from

the floating MOSFET gate capacitance flows through these con-

nections.

The AMUX pin is the output of an analog multiplexer to monitor

the voltages shown in Table 2. The output of the MUX is chosen

through SEL_MUX_(3:0) in register 0x09. The accuracy of the

MUX is ±6%. The driving capability of this output is 1 mA and

the maximum voltage is 3.8 V. Typical response time from writing

SEL_MUX_(3:0) to AMUX output change is 20 μs.

In some applications, it may be necessary to provide a current

recirculation path when the motor load is isolated. This will be

necessary in situations where the motor driver does not reduce the

load current to zero before the isolation MOSFETs are turned off.

The recirculation path can be provided by connecting a suitably

rated power diode to the “motor” side of the isolation MOSFETs

and GND. See the Functional Block Diagram for more details.

Table 2: Analog Multiplexer Output

Node

VREG

VUC

Signal Divide Ratio

Tolerance (reference)

1/2

1/8

1/12

1/1

1/10

–

±6%

V5A

±6%

Watchdog Timers

V5P1

V5P2

VENBAT

VCP

±6%

The A81407 contains three different watchdog timers. This section

will describe each one in detail. The selection and configuration of

each watchdog is done through SPI. After a watchdog is selected

and running, it cannot be reconfigured without going through a

secure SPI procedure. The watchdog circuits are updated/latched

when the state machine leaves the configuration mode. After leav-

ing the CONFIG state, modifications to the watchdog registers will

not take effect unless a CONFIG or RESTART command is issued.

±6%

VCP2

BG1

±6%

BG2

±6%

VIN

±6%

TEMP

Output (mV) = 1440 mV – 3.92 mV/°C × T_J(°C)

The three types of watchdogs are:

1. Pulse Width Watchdog (PWWD) (default)

2. Window Watchdog (WWD)

Floating MOSFET Gate Drivers

The A81407 has four independent floating gate drive outputs to

drive external, low on-resistance, power N-channel MOSFETs.

These MOSFETs should be connected as a single battery line dis-

connect (GVBB) and three motor phase isolators (GU, GV, GW).

The four gate drivers can be controlled independently through the

serial interface by setting the appropriate bit in the control register.

3. Q&A Watchdog (QAWD)

The Pulse Width Watchdog is the default watchdog. It will auto-

matically start with default settings if the following conditions are

met:

1. NPOR transitions high, and

A charge pump (VCP) provides the above-battery supply voltage

necessary to maintain the power MOSFETs in the on-state con-

tinuously when the phase voltage is equal to the battery voltage.

2. No watchdog is selected: WD_SEL_(1:0) = [0,0], and

3. The t_CONFIG(WD)conﬁguration timer expires (1000 ms).

A. The conﬁguration timer can be forced to expire by

selecting a watchdog, including the PWWD, with the

WD_SEL_(1:0) bits.

An internal resistor, R_GPDz, between the Gz and Sz pins plus an

integrated hold-off circuit, ensures the gate source voltage of each

MOSFET is held close to 0 V even with the power disconnected.

This can remove the need for additional gate source resistors

on the isolation MOSFETs. In any case, if external gate source

resistors (R_GSz) are mandatory for the application, then the VCP

regulator can provide sufficient current to maintain the MOSFET

in the on-state with a gate source resistor as low as 100 kΩ.

A watchdog fault sets pins WD_Fn and POE low. By default,

a watchdog fault does not affect NPOR. However, at any time,

the microcontroller can select an alternate mode for NPOR after

a watchdog fault. This is accomplished by writing three secure

words to the NPOR_KEY registers. In the alternate mode, a

22

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

watchdog fault will momentarily set NPOR low for t_WD(FAULT)

(2 ms) in an attempt to reset/restore the microcontroller.

This delay should allow ample time for the microcontroller to

modify the registers via SPI and begin delivering a clock to the

WD_INpin. The t_CONFIG(WD)time is shown in Figure 6, Figure 7,

and Figure 12. Alternatively, if the microcontroller quickly modi-

fies all registers and generates the WD clock, t_CONFIGmay be

too long. In this case, simply setting WD_SEL_(1:0) ≠ [00] will

bypass any remaining t_CONFIGtime and move the state machine

from the CONFIG to the NORMAL state. Both cases are shown

in the watchdog state diagram, Figure 12.

By default, a watchdog fault does not affect FFn. However, at any

time, the microcontroller can modify how FFn behaves after a

watchdog fault. If configuration bit WDF_2_FFn is set, then FFn

will transition low if it detects a watchdog fault.

By default, a watchdog fault has no effect on the state of the four

gate drivers: GVBB, GU, GV, and GW. However, at any time, the

microcontroller can modify how the gate drivers behave after a

watchdog fault. If configuration bit WDF_2_Gz, in register 0x08,

is set, then all four gate drivers will turn off if a watchdog fault

occurs.

Clock pulses from the microcontroller must be applied to WD_IN

before the watchdog is selected (via WD_SEL) or restarted (via the

3-word WD_KEY command). The PWWD error counter can be

preloaded to a value set by PWWD_POE_DLY (default of 2). Pre-

loading the error counter forces the microcontroller to send valid

pulses before POE transitions high, effectively “pre-qualifying” the

performance of the microcontroller. Figure 6 and Figure 7 demon-

strate prequalification with PWWD_POE_DLY set to a value of

10, which requires 5 valid clock pulses (‒2 counts per valid clock

pulse) before POE transitions high.

PULSE WIDTH WINDOW WATCHDOG (PWWD)

The Pulse Width Watchdog circuit monitors an external clock

applied to the WD_INpin. This clock should be generated by the

primary microcontroller or DSP. The PWWD watchdog measures

the time between two clock edges, either rising or falling. So the

watchdog effectively measures both the “high” and “low” pulse

widths, as shown in Figure 6. By default, the nominal WD_IN

pulse width (PWWD_PW) is set to 1 ms, but can be modified to

0.5, 1.5, or 2 ms via SPI.

After moving into NORMAL operation, if no clock edges are

detected at WD_INfor PWWD_EDGE_TO, both WD_Fn and POE

pins transition low. By default, PWWD_EDGE_TO is 5 ms, but

can be modified to 2.5, 10, or 15 ms via SPI. The “edge timeout”

condition is shown as (1) in Figure 7.

If an incorrect pulse width is detected, the watchdog incre-

ments its fault counter by 10 (default). If a correct pulse width

is detected, the watchdog decrements its fault counter by 2

(default). If the watchdog fault counter exceeds 160 (default),

then both the WD_Fn and POE pins transition low. Operation of

the PWWD is shown in Figure 6 and Figure 7. The increment

value (PWWD_INC), decrement value (PWWD_DEC), and

maximum fault count (PWWD_MAX) all have alternate values

that can be accessed via SPI.

While in the NORMAL state, if clock activity at WD_INtermi-

nates for at least PWWD_ACT_TO, both WD_Fn and POE pins

transition low. By default, PWWD_ACT_TO is 16 ms, but can be

modified to 8, 24, or 32 ms via SPI. The “loss of clock activity”

condition is shown as (2) in Figure 7.

The pulse widths generated by a microcontroller or DSP depend

on many factors and will have some pulse-to-pulse variation. The

A81407 accommodates pulse width variations by allowing the

designer to select a “window” of allowable variations. By default,

the window tolerance (PWWD_WIN_TOL) is set to ±13%, but

can be modified to ±8, ±18, and ±23 percent via SPI.

The watchdog default values are loaded when:

1. The internal rail, VCC, transitions low (i.e. V_INis removed,

or ENB and ENBAT are both low) or

2. The band gap, BG1, transitions low

The watchdog performs its calculations based on an internally gen-

erated clock. The internal clock typically has an accuracy of ±2.5%

at 25°C, but may vary as much as ±5% due to IC process shifts and

temperature variations. Variations in the watchdog clock result in a

shift of the “OK Region” (i.e. the expected pulse width) at WD_IN.

This is shown as a green, shaded area in Figure 8.

The watchdog can be restarted by the microcontroller when:

1. The microcontroller sends either a RESTART or CONFIG

command via the 3-word WD_KEYs

By default, the PWWD watchdog is enabled after NPOR transi-

tions high and remains high for at least t_CONFIG(WD)(1000 ms).

23

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Pulses low if conﬁgured

via NPOR_KEY

t_{ꢂꢃꢋꢈAUꢊꢁꢌ}

ꢄorrect Pꢉlse ꢂidths

NPꢅR

ꢂꢃ_ꢈAUꢊꢁ

ꢋlatched stateꢌ

ꢍ t_{ꢄꢅNꢈꢆꢎꢋꢂꢃꢌ}

Sꢀꢊ_Pꢂꢂꢃ

+10

+10 +10

+10

–2 –2 –2 –2

–2

–2 –2 –2 –2 –2

+10

20

+10

92

+10

168

ꢂꢃ_ꢆN

+10

0

10

30

40

68 66 64 62 72

50 60 70

82

102 100 110 120 130 140 138 148

8

6

4

2

0

10

8

6

4

2

0

10

ꢂꢃ_{ꢄꢅUNꢁꢀR}

158

ꢄorrect Pꢉlse ꢂidths

ꢂꢃꢇꢈn

Pꢅꢀ

RꢀSꢁARꢁ ꢏia ꢂꢃ ꢇꢐꢀꢑs

RꢀSꢁARꢁ

Figure 6: Watchdog (WD) operation with both correct and incorrect pulse widths.

1. Incorrect pulse widths increment the WD counter by 10.

2. Correct pulse widths decrement the WD counter by 2.

3. A WD fault occurs if the total fault count exceeds 160.

4. PWWD_POE_DLY is set to 10. So, 5 valid pulse widths

(10 ÷ 2 counts per valid pulse) are required before POE

transitions high

Pulses low if conﬁgured

via NPOR_KEY

Pulses low if conﬁgured

t_{ꢀꢁꢅꢂAUꢃꢄꢆ}

via NPOR_KEY

NPꢋR

ꢈorrect Pꢐlse ꢀidths

ꢀꢁ_{Aꢈꢄꢅꢄꢋꢆ}

ꢏ t_{ꢈꢋNꢂꢇꢎꢅꢀꢁꢆ}

ꢀꢁ_{ꢍꢁꢎꢍꢅꢄꢋꢆ}

Sꢍꢃ_Pꢀꢀꢁ

ꢀꢁ_ꢇN

No ꢀꢁ

Aꢈꢄꢇꢉꢇꢄꢊ

ꢇN

ꢀꢁ_ꢇNAꢈꢄꢇꢉꢇꢄꢊ

SꢄꢋPS

–2 –2 –2 –2 –2

1

2

10

8

6

4

2

0

10

8

6

4

2

0

10

0

ꢀꢁ_{ꢈꢋUNꢄꢍR}

ꢀꢁꢌꢂn

ꢀꢁ_ꢂAUꢃꢄ

ꢅlatched stateꢆ

ꢀꢁ_ꢂAUꢃꢄ

ꢅlatched state ꢆ

Pꢋꢍ

RꢍSꢄARꢄ ꢑia ꢀꢁ ꢌꢒꢍꢊs

RꢍSꢄARꢄ

Figure 7: Watchdog operation with faults from:

1. No WD_INActivity for WD_EDGE(TO)

2. WD_INActivity Stops

3. PWWD_POE_DLY is set to 10.

24

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

PWWD TIMING DIAGRAM (not to scale):

ꢀatchdog ꢁetects Rising

ꢂdge and Starts

Monitoring

ꢊnternal ꢀꢁ ꢆlocꢕ Set ꢖy R_Aꢁꢗꢉ t_ꢒSꢆꢋ 1ꢘꢇ1 MHꢙꢈ ꢋ 1 μs

ꢊnternal ꢀꢁ ꢚimer Perio ꢉ t_ꢀꢁꢋ 1000 ꢍ 1 μs ꢋ 1000 μs

Assume MCU

Output Perfect

1 ms ꢃ 0%

ꢑꢅaranteed

ꢒꢓ, ꢃꢄ0 μs

Maꢎimꢅm ꢆoꢅntꢇ1080ꢈꢉ

N_MAꢏꢋ 10ꢄ0 ꢍ 1 ꢐs ꢋ 1080 μs

Minimꢅm ꢆoꢅntsꢇꢀꢁ0ꢈꢉ

_MꢊNꢋ 9ꢌ0 ꢍ 1 μs ꢋ ꢀꢁ0 μs

t

WD Window with

ꢃꢄ% Programmed

Window Tolerance

AND 0% WD

Oscillator Error

t_WD= 1000 μs

Guaranteed Fault Detec�on

OK

REGION

-8% of 1 ms = 920 μs

+8% of 1 ms = 1080 μs

t_OSC= 1000 μs

ꢑꢅaranteed

ꢒꢓ, ꢃꢄꢔ μs

WD Window with

ꢃꢄ% Programmed

Window Tolerance

AND ꢛ5% WD

Minimꢅm ꢆoꢅntsꢇꢀꢁ0ꢈꢉ

_MꢊNꢋ 9ꢌ0 ꢍ 1.05 μs ꢋ ꢀꢂꢂ μs

Maꢎimꢅm ꢆoꢅntꢇ1080ꢈꢉ

t

N_MAꢏꢋ 10ꢄ0 ꢍ 1.05 ꢐs ꢋ 11ꢃ4 μs

OK

REGION

Oscillator Error

Guaranteed Fault Detec�on

t

_WD= 1050 μs

t_OSC= 1050 μs

WD Output is alwaꢄs correct

ꢑꢅaranteed

ꢒꢓ, ꢃꢜꢝ μs

WD Window with

ꢃꢄ% Programmed

Window Tolerance

AND വ5% WD

Maꢎimꢅm ꢆoꢅntꢇ1080ꢈꢉ

Minimum Counts(920):

_MIN= 920 × 0.95 μs = 874 μs

N_MAꢏꢋ 10ꢄ0 ꢍ 0.95 ꢐs ꢋ 10ꢁꢂ μs

t

OK

REGION

Oscillator Error

t_WD= 950 μs

Guaranteed Fault Detec�on

t_OSC= 950 μs

WD Output is alwaꢄs correct

+26 µs

–34 µs

1000 µs

Required System Clock

Figure 8: Typical Watchdog Timer System Level Functionality (times are not to scale)

A81407 and System Operating Parameters:

1. 1 ms pulse widths coming from the micro-controller

2. ±8% WD Window Tolerance Selected (WD_ADJ= GND)

3. ±5% WD Oscillator Tolerance (worst case maximum)

25

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

The options available by WWD_TIMER are 0.5 to 12.5 ms for

t_WD(FAST), and 4 to 100 ms for t_WD(SLOW)

WINDOW WATCHDOG (WWD)

.

The window watchdog monitors the time between rising edges of

an external clock applied to the WD_INpin. This clock should be

generated by the microcontroller or DSP. The time between rising

edges (i.e. the frequency) of the clock must fall within an accept-

able “window”, or a watchdog fault is generated. In general, valid

watchdog clocks must be present at WD_INfor at least t_WD(SLOW)

before POE will transition high.

It is strongly recommended that the processor produce valid

clock pulses at WD_INprior to selecting the watchdog or issu-

ing a RESTART command. As shown in Figure 9 and Figure

10, after setting WD_SEL(1:0) or issuing a RESTART com-

mand, valid watchdog clocks should be present at WD_INfor at

least t_WD(SLOW)before POE is allowed to transition high. This

“prequalifies” correct operation of the microcontroller before

enabling the gate driver (via POE). At least 1 complete clock

cycle must occur during the pre-qualification time (t_WD(SLOW)).

For prequalification, the maximum WD_IN clock frequency

(f_{WD_IN(MAX)}, including system tolerances) and the selected value

of WWD_TIMER from register 0x0A must satisfy the following

equation:

After NPOR transitions high, the processor must:

1. Program the conﬁguration registers and initiate valid WD

pulses on the WD_INpin and,

2. Select the WWD by setting WD_SEL_(1:0) = [10].

Both these tasks must be completed before t_CONFIGexpires.

A window watchdog fault occurs if the time between rising clock

edges is either too short (a “fast” fault) or too long (a “slow”

t_{WD_SLOW}> 1.5 / f_{WD_IN(MAX)}

fault). The “fast” and “slow” limits, t_WD(FAST)and t_WD(SLOW)

are selected with WWD_TIMER(2:0). The default values for

t_WD(FAST)and t_WD(SLOW)are 4 ms and 32 ms, respectively.

,

Typical watchdog operation with both FAST and SLOW fault

events, along with recommended RESTART conditions, are

shown in Figure 9 and Figure 10.

t

_{ꢀꢁꢃꢄASꢆꢇ}set to ꢈ ms ꢃꢉ0.1ꢊ msꢇ

t_{ꢀꢁꢃꢄAUꢅꢆꢇ}

Pulses low if conﬁgured via NPOR_KEY

NPOR

t_{ꢀꢁꢃSꢅꢋꢀꢇ}set to 3ꢌ ms ꢃꢉ1.ꢌꢍ msꢇ

< t_{ꢎꢋNꢄꢏꢐꢃꢀꢁꢇ}

t < 3.84 ms

4.16 ms < t < 30.72 ms

SEL_ꢀꢀꢁꢂ

WD_IN

WD_Fn

POE

t

1 POE pre-qualiﬁca�on cycle

3 POE pre-qualiﬁca�on cycles

t_{ꢀꢁꢃSꢅꢋꢀꢇ}

RESTART

Figure 9: Window Watchdog (WWD) Operation

A watchdog fault occurs when the WD_IN period (T) is too short. * Signal is internal to A81407

t

_{ꢂꢃꢅꢆASꢁꢈ}set to ꢉ ms ꢅꢊ0.1ꢋ msꢈ

t _{ꢂꢃꢅꢆAUꢇꢁꢈ}

Pulses low if conﬁgured via NPOR_KEY

NPOR

t_{ꢂꢃꢅSꢇꢌꢂꢈ}set to 3ꢍ ms ꢅꢊ1.ꢍꢎ msꢈ

4.16 ms < t < 30.72 ms

< t_{ꢏꢌNꢆꢐꢑꢅꢂꢃꢈ}

t > 33.28 ms

SEL_ꢂꢂꢃꢄ

WD_IN

WD_Fn

POE

t

t_{ꢂꢃꢅSꢇꢌꢂꢈ}

RꢀSꢁARꢁ

Figure 10: Window Watchdog (WWD) Operation

A watchdog fault occurs when the WD_IN period (t) is too long. * Signal is internal to A81407

26

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

and wait for the minimum time limit to elapse (t_QA(MIN)). After

the minimum time limit expires, the microcontroller must write

Q&A WATCHDOG

The Q&A watchdog periodically generates a random word

and must receive an answer code from the microcontroller or

DSP within a specific time window. The Q&A watchdog must

be fully configured through SPI before being “activated” with

WD_SEL_(1:0). For example, the minimum and maximum time

limits (t_QA(MIN), t_QA(MAX)) must be selected from a list of 16

possibilities using QAWD_TIMER_(3:0). Any time POE is low,

the microcontroller must successfully complete a Q&A session

before POE will transition high.

the modified word back to QAWD_RAND_(5:0). The write

must be fully completed before the maximum time limit expires

(t_QA(MAX)), with margin. Immediately after the writeback occurs,

both the Q&A watchdog and the microcontroller must again

synchronize their internal timers (i.e. set them to zero and begin

counting) to start the next Q&A session.

The microcontroller is allowed to retry the Q&A sequence a num-

ber of times before a Watchdog fault is declared. The number of

retries can be selected by a 2-bit word, QAWD_RETRY_(1:0). A

Q&A Watchdog fault occurs only after the retry counter reaches

zero, as shown in Figure 11. The retry counter is decremented if:

After the Q&A watchdog is activated, via WD_SEL_(1:0), the

A81407 will generate a 6-bit random word, QAWD_RAND_(5:0)

and start an internal timer. Shortly thereafter, the microcontroller

must synchronize its own timer. Then the microcontroller must

read the random word and allow enough time, with margin, to

modify and write the word back to the watchdog. The writeback

must not occur before the minimum time limit expires (t_QA(MIN)),

nor after the maximum time limit expires (t_QA(MAX)).

1. An answer is received before the minimum time limit expires

(t_QA(MIN)).

2. An answer is not received before the maximum time limit

expires (t_QA(MAX)).

The microcontroller must invert each bit of the random word

3. An incorrect answer is received from the microcontroller.

t _{ꢊꢋAꢆMꢄNꢉ}

t _{ꢊꢋAꢆMAꢌꢉ}

t _{ꢊꢋAꢆMꢄNꢉ}

t _{ꢊꢋAꢆMAꢌꢉ}

t_{ꢇꢈꢆꢃAUꢍꢎꢉ}

NPOR

< t_{ꢁꢂNꢃꢄꢅꢆꢇꢈꢉ}

RETRY=2

NPOR pulses low if conﬁgured via

SEL_QAWDꢀ

RETRY*

NPOR_KEY

RETRY=1

RETRY=0

WD_Fn

POE

POE transi�ons high aꢀer1

successful Q&A session

Watchdog starts its �mers and

generates 6-bit random word

Host writes “correct” 6-bit word back ,

but aꢀer t _Q&A(MAX)

Host starts an internal �mer

RETRY should decrement , but RETRY=0, so a

Watchdog Fault occurs

Host reads 6-bit random word and

inverts each bit

Host writes “correct” 6-bit word back aꢀer

Host does not respond before t_Q&A(MAX)

t_Q&A(MIN)but before t _Q&A(MAX)

Host reads 6-bit random word and

inverts each bit

Watchdog re-starts its �mers and

generates a new 6-bit random word

Host re-starts internal �mer

Host reads 6-bit random word and

Watchdog re-starts its �mers and

generates a new 6-bit random word

inverts each bit

Host writes 6-bit word back too early, before

t_Q&A(MIN)expires, RETRY decrements

Host writes “incorrect” 6-bit word back

aꢀer t_Q&A(MIN)but before t _Q&A(MAX)

,

RETRY decrements

Watchdog re -starts its �mers and

generates a new 6-bit random word

Host reads 6-bit random word but

does not invert each bit

Host re-starts internal �mer

Figure 11: Q&A Selection, Operation, and Fault Examples.

27

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

IDLꢄ ꢂWDꢃ

Pꢀꢁ ꢂ 0

ꢃꢄꢅꢆn ꢂ 1

ꢇPOR ꢈ 0,

ꢃꢄꢅSꢁꢉꢂꢏ00ꢐ

Start

NPꢀR ꢄelay

ꢒꢁS

ꢓUꢍ Uꢓ or

ꢓUꢍ ꢀꢓꢎ

Nꢀ

NPꢀR

ꢄelay

ꢄoneꢎ

Nꢀ

ꢊncrement

NPꢀR ꢄelay

ꢒꢁS

ꢇPOR ꢈ 1

ꢆOꢇꢀIG ꢂWDꢃ

Start

ꢍonꢇigꢅꢈꢀ

Pꢀꢁ ꢂ 0

ꢃꢄꢅꢆn ꢂ 1

NPꢀR ꢂ 1

ꢍonꢇigꢌre ꢃꢄ

Registers

RꢄSꢅARꢅ

ꢒꢁS

ꢊncrement

ꢍonꢇigꢅꢈꢀ

ꢃꢄꢅSꢁꢉꢂꢏ00ꢐꢎ

Nꢀ

ꢀLASꢁ ꢂWDꢃ

Pꢀꢁ ꢂ 0

DISABLꢄ ꢂWDꢃ

Pꢀꢁ ꢂ 1

ꢃꢄꢅꢆn ꢂ 1

NPꢀR ꢂ 1

ꢃꢄꢅꢆn ꢂ 1

NPꢀR ꢂ 1

Nꢀ

ꢍonꢇigꢅꢈꢀ

ꢄoneꢎ

ꢒꢁS

Uꢑdate ꢃꢄ

ꢍircꢌits ꢇrom

Registers

Uꢑdate ꢃꢄ

ꢍircꢌits ꢇrom

Registers

ꢀLASꢁ

Start

Selected ꢃꢄ

Start

ꢄeꢇaꢌlt ꢃꢄ

DISABLꢄ

ꢆOꢇꢀIG

Pꢀꢁ ꢂ 1

ꢃꢄꢅꢆn ꢂ 1

NPꢀR ꢂ 1

ꢇORMAL ꢂWDꢃ

ꢀLASꢁ

WIN

WD

PW

WD

Q&A

WD

DISABLꢄ

ꢃatchdog ꢆaꢌlt

Pꢀꢁ ꢂ 0

ꢃꢄꢅꢆn ꢂ 0

NPꢀR ꢂ 1

RꢄSꢄꢅ ꢂWDꢃ

RꢄSꢅARꢅ

ꢀLASꢁ

DISABLꢄ

ꢃait ꢇor a RꢁSꢈARꢈ, ꢆꢉASH, or

ꢄꢊSAꢋꢉꢁ command

Figure 12: State Diagram of Watchdog Operation

28

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Window Watchdog

ꢂWWDꢃ

Pulse Width Watchdog

ꢂPWWDꢃ

ꢀꢁA Watchdog

ꢂꢀAWDꢃ

Pꢃꢃꢄ

ꢃꢄꢅSꢁꢆ ꢇ ꢈ01ꢉ

ꢊAꢃꢄ

ꢃꢄꢅSꢁꢆ ꢇ ꢈ11ꢉ

ꢃꢃꢄ

ꢃꢄꢅSꢁꢆ ꢇ ꢈ10ꢉ

Pre-ꢊꢋaliꢌicationꢍ

aꢌter one sꢋccessꢌꢋl

ꢊA session, Pꢂꢁ ꢇ 1

Pre-ꢊꢋaliꢌication when ꢎꢂUNꢏ

starts ꢌromꢀꢀꢁD_ꢀꢂE_DLꢃ

and decrements to0, Pꢂꢁ ꢇ 1

Pre-ꢊꢋaliꢌication

to allow Pꢂꢁꢇ 1

WD_Fn = 1

POE = 0

WD_Fn = 1

POE = 0

WD_Fn = 1

POE = 0

Set TRY =

QAWD_RETRY

Measure period

of pulses at

COUNT =

PPWD_POE_DLY

WD_IN (t_WD(IN)

)

Microcontroller

starts �mer

First-Edge

Timeout

expired?

QAWD

generates

6-bit word

ꢀꢁS

Pulses

valid for ≥

t_WD(SLOW)

Nꢂ

RꢄSꢄꢅ

State

?

QAWD starts

MIN and MAX

�mers

Nꢂ

WD_Fn = 0, POE = 0,

FFn = 0

ꢀꢁS

NPOR = 1,

or 1 → 0 _2ms→ 1

if unlocked via SPI

WD_Fn = 1

POE = 1

Microcontroller

reads word

Microcontroller

inverts each bit of

the word

Non-Ac�vity

Timeout

expired?

ꢀꢁS

Set TRY =

QAWD_RETRY

Wait for RESTART,

FLASH, or DISABLE

Command

Nꢂ

Measure period

of pulses at

RꢄSꢄꢅ

State

Nꢂ

MIN �me

expired?

Posi�ve or

nega�ve

pulse-width

correct?

COUNT =

COUNT +

PWWD_INC

WD_IN (t_WD(IN)

)

Nꢂ

WD_Fn = 0, POE = 0,

FFn = 0

WD_Fn = 1

POE = 1

ꢀꢁS

NPOR = 1,

or 1 → 0 _2ms→ 1

if unlocked via SPI

Microcontroller

writes word back to

QAWD

ꢀꢁS

Nꢂ

t_WD(FAST)< t_WD(IN)

t_WD(SLOW)

<

ꢀꢁS

?

Wait for RESTART,

FLASH, or DISABLE

Command

COUNT =

COUNT –

PWWD_DEC

COUNT

PWWD_MAX?

Nꢂ

MAX �me

expired?

Correct

answer?

COUNT = 0?

ꢀꢁS

WD_Fn = 0, POE = 0,

FFn = 0

ꢀꢁS

Nꢂ

ꢀꢁS

NPOR = 1,

or 1 → 0 _2ms→ 1

if unlocked via SPI

TRY = TRY о 1

WD_Fn = 1

POE = 1

Wait for RESTART,

FLASH, or DISABLE

Command

ꢀꢁS

Nꢂ

TRY = 0?

RꢄSꢄꢅ

State

Figure 13: Watchdog Flowcharts

29

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

SERIAL COMMUNICATION INTERFACE

The A81407 provides the user with a full-duplex, four-wire,

synchronous serial interface. It is compatible with the Serial

Peripheral Interface (SPI) standard using mode 3 (CPOL = 1,

CPHA = 1). The SPI interface uses an “out-of-frame” commu-

nications protocol, meaning the logical response of the slave is

within the next frame of the master, as shown in the following

figure. The serial interface timing requirements are specified in

the Electrical Characteristics table and illustrated in the Serial

Interface Timing diagram (Figure 1).

MISO: Master Input Slave Output (data output from the slave, or

A81407). A 32-bit word, sent/received MSB first. This pin is high

impedance when CS is high or when the Chip_ID (bit 30 from

the previous frame) was incorrect. When CS is low, data from

the slave is sent on this pin. The master reads/latches the data on

the rising edge of SCK. The slave advances to the next bit on the

falling edge of SCK.

SCK: Serial Clock (input) from the master. There must be 32 ris-

ing clock edges per frame. During each clock cycle, a full duplex

data transmission occurs. The master sends a bit on the MOSI

line and the slave reads it, while the slave sends a bit on the

MISO line and the master reads it. This sequence is maintained

even when only one-directional data transfer is intended. Data

changes state on the falling edge of SCK and is latched on the ris-

ing edge of SCK. SCK must be set high before CS transitions.

ꢃrame 1

ꢃrame ꢄ

ꢀS

MꢁSꢂ

MꢂSꢁ

CS: Chip Select (input) from the master. When CS is high MISO

is high impedance, and activity on MOSI and SCK is ignored.

This allows multiple SPI slaves to have common MISO, SCK, and

MOSI connections. However, each slave must have a dedicated

CS signal. CS is brought low to initiate a serial transfer. When 32

data bits have been clocked into the shift register, CS must be taken

high to latch the data into the selected register. When this occurs,

the internal control circuits act on the new data.

Figure 14: Out-of-Frame SPI Communication

Each 32-bit frame has a read/write bit, WR (bit 29). This bit must

be set to 1 to write the subsequent bits into the selected register.

If WR is set to 0 (a read), then the data bits (20 to 5) are ignored.

The state of the WR bit also determines the data output on MISO.

If WR is set to 1 then general diagnostic information is output.

If WR is set to 0 then the contents of the register selected by the

address bits is output.

If CS transitions high and there are fewer than 32 rising edges

on SCK, the write will be cancelled and no data will be written

to the registers. Similarly, if there are more than 32 rising edges

on SCK while CS is low, the write will be cancelled and no data

will be written. In both cases, the SE (serial error) and FF (Fault

Flag) bits will be set high, and FFn pin (microcontroller interrupt)

pulled low to indicate a data transfer error.

MOSI: Master Output Slave Input (data input from the master). A

32-bit word, sent/received MSB first. When CS is low, data from

the master is received on this pin. The slave reads/latches the data

on the rising edge of SCK. The master advances to the next bit on

the falling edge of SCK.

ꢂS

Sꢂꢃ

Always

0

Always

0

R ꢈ ꢉ

1 or 0

Hꢄ-ꢆ

1 or 0

Hꢄ-ꢆ

MꢅSꢄ

MꢄSꢅ

Always

0

Always

1

ꢇataꢅꢃ

ꢀit ꢁ9

ꢀit 31

ꢀit 30

ꢀit 0

Undeꢊined

Figure 15: Example SPI Communications

Data changes on the falling edge of SCK. Data is latched on the rising edge of SCK

30

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

SPI FRAME DEFINITIONS:

1. Chip_ID, bit 30 in both the MISO or MOSI frames, ensures that the A81407 only accepts commands meant for it when it shares

SPI with a second device. For the A81407, the Chip_ID shall be internally ﬁxed at 0. For the second device on SPI , Chip_ID

should be internally ﬁxed at 1. Seperate chip selects are still required for each device.

An incorrect Chip_ID bit can have varying results on the MISO line. These results depend on what MISO is doing during the cur-

rent frame (sending data or tri-state) and if there is an error on the MOSI data. Below table summarizes MISO response based on

Chip_ID and errors.

Current Frame

Next Frame

MOSI

MISO

Bit 31

Bit 30

Error

No

0

1

0

x

Tri-state

Normal response

Tri state

0

No

x

Tri state

Sending data

x

Yes

No

x

Sends error frame

Tristate

1

x = don’t care

2. MOSI and MISO frames: include a 5-bit CRC calculated from bits 30 to bit 5.

A. The MSB is static, so it does not need to be included in the CRC calculation. It can be checked at the Host or Device side

independently.

B. Polynomial of 0x12 (x⁵+ x²+1) is used, with a start value of 11111b and a target of 00000b.

C. Covers every single and dual bit errors.

D. Achieves a Hamming Distance of 3.

E. Every 4 consecutive bit error.

F. Line stuck low/high detected.

G. If a CRC Error occurs, the SE and FF bits are set to 1, and the FFn pin is pulled low

3. MISO frame includes a 5-bit Message ID, bits 28 to 24.

4. MISO frame includes a 3-bit Frame Counter, bits 23 to 21.

5. Writing and reading 2-bit patterns to the read-back register checks SPI integrity.

31

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

HOST COMMANDS:

Bits 31 is static and must be set to 0.

Bit 30, the Chip_ID, is fixed at 0 for the A81407.

Bit 29 indicates a write or a read: 1 = Write, 0 = Read.

For a read command, the data bits are considered “don’t care” (DC).

Write command from the Host to the MOSI pin:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

5-bit address

DC

16-bit data

5-bit CRC

Read command from the Host to the MOSI pin:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

5-bit address DC

2

0

16-bit data (ignored for a read command)

5-bit CRC

Device Responses:

Bit 31 is static, fixed at 1.

Bit 30, the Chip_ID, is fixed at 0 for the A81407

Bit 29 indicates if the 16-bit data is valid:

1 = valid data, no errors detected

0 = normal response after a MOSI Write, or an error was detected (i.e. SE or CRC) so general status bits are sent

Pattern at the MISO pin after a MOSI Read where the 16-bit data is valid (i.e. no errors detected)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

5-bit Message ID

(Prev_A4:0)

Frame

Counter

1

0

1

16-bit data

5-bit CRC

Pattern at the MISO pin after an MOSI Write, or

Pattern at the MISO pin after an MOSI Read where the 16-bits of data are not as requested (i.e. an error was detected)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

5-bit Message ID

(Prev_A4:0)

Frame

Counter

1

0

5-bit CRC

32

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

This should capture the cause of the FFn transition. The Write

operation and status update are shown as Frame 1 / WRITE_n

in Figure 16. After the first Write, the microcontroller should

perform a second write (in this case only, a read would also be

acceptable). This operation is shown as Frame 2 / WRITE_n+1in

Figure 16. During Frame 2, the 16 SPI diagnostic status bits (FF,

SE, DBE, ENBAT_S, ENB_S, etc.) are clocked out on the MISO

pin. If the root cause of FFn is not clear from these 16 bits, then

the microcontroller must read each of the four status registers

(0x00 to 0x03) to search for the root cause.

STATUS UPDATES AND SPI PROCEDURE IF FFN→0

The SPI diagnostic status bits of the A81407 are updated at the

end of each SPI frame (i.e. when CS transitions high). This is

shown by the “STATUS Latched” signal in Figure 16.

If the FFn signal transitions low, the microcontroller must imme-

diately perform a SPI Write. To avoid inadvertently changing

important configuration data, the Write should be done to the

readback register (0x0C). Any 16-bits of data will suffice. At the

end of this Write, the SPI diagnostic status bits will be latched.

t_ꢀSꢃHꢆ

ꢊrame ꢋ

ꢊrame n-1

ꢀS

ꢊrame 1

MꢂSꢁ

ꢃꢄata ꢁnꢆ

WRITE_n-1

or READ_n-1

WRITE_n+1

or READ_n+1

WRITE_n

SꢇAꢇUS ꢈ

ꢉatched

STATUS _n,

why FFn→0

MꢁSꢂ

ꢃꢄata ꢂꢅtꢆ

STATUS _n-1

or DATA _n-1

Don͛ t Care

ꢇhe caꢅse oꢌ ꢊꢊn actiꢍation is latched

at the end oꢌ the ꢌollowing SPꢁ ꢌrame.

ꢊꢊn

Figure 16: Recommended SPI Operations after FFn→0

* The “STATUS Latched” signal is internal to the IC

33

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

mally, this would cause an UV fault to occur. However the fault

flag (both FF and FFn) will not register a fault as this condition

Register Mapping

STATUS REGISTERS

is expected and internally “masked”. Both the UV and OV faults

are masked when any LDO is disabled. This allows the system to

disable one of the V5P LDOs and still maintain interrupt func-

tionality to the microcontroller via the fault flag (FFn) pin. Also,

if an LDO is disabled/off, the corresponding SPI diagnostic status

bits (V5P1_OK or V5P2_OK) will indicate “OK”, (i.e. be 1b).

The A81407 provides four status registers. These registers are

read only. They provide realtime status of various functions

within the A81407.

These registers report on the status of all four system rails: VUC,

V5A, V5P1, and V5P2. They also report on internal rail status,

such as VREG and the charge pumps. The general fault flag (FF),

watchdog fault flag (WD_F), and watchdog state (WD_STATE)

are found in these status registers.

Control Bits

Status Bits

FF

Bit

FFn

V5Px_EN_1

V5Px_EN_0

V5Px_UV

Don’t care

V5Px_OV

0

1

0

1

0

1

Don’t care

Mask UV & OV

If previous state was off

CONFIGURATION REGISTERS

1

0

1

0

Four registers in the A81407 are used for configuration. Two of

these registers are dedicated to setting the watchdog parameters.

The watchdog registers can only be configured while in the

CONFIG state. This occurs after the A81407 is first enabled or the

watchdog receives a secure SPI “RESTART” command.

WATCHDOG MODE KEY REGISTER

At times it may be necessary to reflash or restart the processor. To

do this, the user should put the watchdog into “FLASH” mode.

This is done by writing a sequence of keywords to the “wd_cmd_

key” register. If the correct word sequence is not received, then

the sequence must restart. While in FLASH mode, the A81407

sets NPOR high, WD_Fn high, and POE low.

The type of watchdog is selected via WD_SEL_(1:0). The default

watchdog is the Pulse Width Watchdog (PWWD). The pulse width

watchdog parameters are programmed in registers 0x0B.

The window watchdog (WWD) fast and slow timers are pro-

grammed in register 0x0A. The Q&A watchdog (QAWD) timers,

allowed number of retries, and 6-bit random word reside in regis-

ter 0x0A.

Once flash is complete the processor must send the restart sequence

of keywords for the watchdog to exit FLASH mode. If VCC has not

been removed the watchdog will restart with the new configuration.

Configuration register 0x08 and 0x09 allows the user to disable

the PWM dither feature, modify the response to a watchdog fault

(at pins Gz and FFn), mask faults, select the battery disconnect

deglitch/filter time, select the phase isolator delay time, change the

safe-state of the phase isolators, and control the analog multiplexor.

VERIFY RESULT REGISTERS

At power-up, the A81407 performs a self-test of the UV and OV

detect circuits. This test should cause their diagnostic registers to

toggle state. If any diagnostic register does NOT change state, the

corresponding verify result register will latch high and FFn will

be set low. Self-test requires much less than 1 ms at power-up,

typically 350 to 500 µs.

ENABLE/DISABLE REGISTER

The enable/disable registers provide the user independent control

of the V5Px outputs and the phase isolator gate drivers (GVBB,

GU, GV, GW).

Upon completion of power-up, the system’s microcontroller may

be interrupted by FFn. At that time, the microcontroller should

examine the verify result registers to determine which self-test

failed. If a register contains a “1”, the microcontroller should

make note of the failure and decide how to proceed.

Two, nonadjacent control bits must be set to enable or disable an

output. If the two bits do not match (01, or 10), then the output or

gate drivers maintains its previous state.

Lastly, the microcontroller should write a “1” to the failed regis-

ter bits (RW1C) to clear it and regain functionality of FFn.

By default, V5P1, and V5P2 are “on”, but can be disabled via

SPI. If either LDO is disabled its output will decay to 0 V. Nor-

34

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Table 3: Register Map

D20

D12

FF

D19

D11

D18

D10

D17

D9

D16

D8

D15

D7

D14

D6

D13

D5

DEC

HEX Address

Register

Name

Type

RO

Address

SE

WD_Fn_S

WD_Fn_OK

V5A_OK

LG_OK

POE_S

POE_OK

NPOR_S

NPOR_OK

TSD_F

DBE

UNUSED

ENBAT_S

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0

1

status_0

status_1

LX_OK

ENB_S

V5P2_OK

VCP_OK

VREG_OK

UNUSED

*SVBB_UV

UNUSED

VUC_OK

UNUSED

GSVBB_UV

GSVBB_OV

V5P1_OK

RO

D1_OK ^[1]

GSV_UV

GSV_OV

VCP2_OK

GSW_UV

GSW_OV

[1]

GSU_UV

GSU_OV

NPOR_IN_(1:0)

*RW1C,

RO

2

status_2

WD_STATE_(2:0)

PWWD_COUNT_(7:0)

3

status_3

RO

RW1C

RW

UNUSED

VCP_UV

UNUSED

VUC_OV

UNUSED

VUC_UV

VREG_OV

VREG_UV

4

diagnostic_0

diagnostic_1

enable/disable

V5A_OV

UNUSED

ENU_1

V5A_UV

UNUSED

ENVBB_1

VCP2_OV (1) VCP2_UV (1)

V5P1_OV

UNUSED

V5P1_UV

UNUSED

V5P2_OV

UNUSED

ENU_0

V5P2_UV

UNUSED

ENVBB_0

5

UNUSED

ENW_1

UNUSED

ENV_1

ENW_0

ENV_0

6

V5P2_EN_1

WD_KEY_7

V5P1_EN_1

WD_KEY_6

V5P2_EN_0

WD_KEY_3

V5P1_EN_0

WD_KEY_2

wd_cmd_keys

WD_KEY_5

WD_KEY_4

WD_KEY_1

WD_KEY_0

7

WO

npor_inputs_key

NPOR_KEY_7 NPOR_KEY_6 NPOR_KEY_5 NPOR_KEY_4 NPOR_KEY_3 NPOR_KEY_2 NPOR_KEY_1 NPOR_KEY_0

DITH_DIS

UNUSED

8

config_0

config_1

RW

WDF_2_Gz

WDF_2_FFn

GD_FLT_ON

MASK_(3:0)

WD_SEL_(1:0)

GD_UV_SEL

GD_EN_SEL

UNUSED

9

RW

SEL_MUX_(3:0)

WWD_TIMER_(2:0)

QAWD_RETRY_(1:0)

UNUSED

QAWD_TIMER_(3:0)

QAWD_RAND_(5:0)

10

11

12

13

14

config_2: WD ^[2]

config_3: WD ^[2]

readback

RW

PWWD_EDGE_TO_(1:0)

PWWD_DEC_(1:0)

PWWD_ACT_TO_(1:0)

PWWD_INC_(1:0)

PWWD_WIN_TOL_(1:0)

PWWD_MAX_(1:0)

PWWD_PW_(1:0)

PWWD_POE_DLY_(1:0)

RW

READBACK_(15:8)

READBACK_(7:0)

VUC_OV_FAIL VUC_UV_FAIL V5A_OV_FAIL V5A_UV_FAIL

BIST_FAIL TSD_BIST_FAIL VREG_OV_FAIL VREG_UV_FAIL V5P1_OV_FAIL V5P1_UV_FAIL V5P2_OV_FAIL V5P2_UV_FAIL

RW

verify_result_0

verify_result_1

RW1C

UNUSED

^[1]Applies only if the block diagram includes this pin or function. If the pin or function does not exist the status bit will always indicate a non-fault or OK condition.

^[2]With the exception of QAWD_RAND, the WatchDog (WD) registers only take effect after the state machine exits the CONFIG mode.

35

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x00. Status Register 0:

D20

D19

SE

D18

WD_Fn_S

D10

D17

POE_S

D9

D16

NPOR_S

D8

D15

TSD_F

D7

D14

DBE

D13

UNUSED

D5

Data Bit /

Name

FF

D12

D11

D6

Data Bit /

Name

UNUSED

LX_OK

WD_Fn_OK

POE_OK

NPOR_OK

UNUSED

ENB_S

ENBAT_S

ADDRESS: 00000b, TYPE: Read Only (RO)

FF [D20]

Fault Flag

0

No Fault (default)

1

Fault detected

SE [D19]

Serial Communications Error

No error (default)

0

1

Fault: less than or more than 32 rising SCK edges in a frame, or CRC Error

WD_Fn_S [D18]

Watchdog Fault, Pin Status

0

Fault

1

No fault or watchdog is disabled (default)

POE_S [D17]

Power On Enable internal logic status

0

POE is low (default)

1

POE is high

NPOR_S [D16]

Power On Reset internal logic status

0

NPOR is low (default)

1

NPOR is high

TSD_F [D15]

Thermal Shutdown status

0

Temperature is OK (default)

1

Overtemperature event

DBE [D14]

EEPROM configuration/calibration error of 2 or more bits at power-up

0

No fault (default)

1

Fault

UNUSED [D13:D12]

Unused at this time.

LX_OK [D11]

Shows the switching node of the pre-regulator is OK

0

Fault, LX is likely shorted to ground

1

No fault, LX is functioning/switching (default)

WD_Fn_OK [D10]

WD_Fn pin matches what the A81407 is demanding (the WD_F bit)

0

Fault

1

No fault (default)

POE_OK [D9]

Power On Enable output pin matches what the A81407 is demanding

0

Fault

1

No fault (default)

NPOR_OK [D8]

NPOR output pin matches what the A81407 is demanding

0

Fault

1

No fault (default)

UNUSED [D7]

Unused at this time

ENB_S [D6]

Status of the logic enable input pin (ENB)

ENB is low (default)

0

1

ENB is high

ENBAT_S [D5]

Status of the high voltage enable input pin (ENBAT)

ENBAT is low (default)

ENBAT is high

0

1

36

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x01. Status Register 1:

D20

VREG_OK

D12

D19

VUC_OK

D11

D18

V5A_OK

D10

D17

UNUSED

D9

D16

UNUSED

D8

D15

V5P1_OK

D7

D14

V5P2_OK

D6

D13

UNUSED

D5

Data Bit /

Name

Data Bit /

Name

UNUSED

LG_OK

D1_OK

VCP2_OK

UNUSED

VCP_OK

UNUSED

ADDRESS: 00001b, TYPE: Read Only (RO)

VREG_OK [D20]

Shows the voltage at the pre-regulator output pin is within regulation

0

Fault

1

No fault (default)

VUC_OK [D19]

Shows the voltage at the VUC pin is within regulation

0

Fault

1

No fault (default)

V5A_OK [D18]

Shows the voltage at the V5A output is within regulation

0

Fault

1

No fault (default)

UNUSED [D17:D16]

Unused at this time

V5P1_OK [D15]

Shows the voltage at the V5P1 output is within regulation

0

Fault

1

No fault (default), or V5P1 has been turned off

V5P2_OK [D14]

Shows the voltage at the V5P2 output is within regulation

0

Fault

1

No fault (default), or V5P2 has been turned off

UNUSED [D13:D11]

Unused at this time

LG_OK [D10]

Indicates if the Boost drive, LG pin, matches the commanded value

0

Fault

1

No fault, LG is either off (V_VIN> 8.5 V), or working correctly (default)

D1_OK [D9]

Indicates if the Pre-Regulator Asynchronous diode is OK, or missing

0

Fault, D1 is missing

1

No fault, D1 is OK (default)

VCP2_OK [D8]

Shows the voltage at the VCP2 pin is within regulation

0

Fault

1

No fault (default)

UNUSED [D7]

Unused at this time

VCP_OK [D6]

Shows the voltage at the VCP pin is within regulation

0

Fault

1

No fault (default)

Unused at this time

UNUSED [D5]

37

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x02. Status Register 2:

D20

* SVBB_UV

D12

D19

D18

GSU_UV

D10

D17

GSV_UV

D9

D16

GSW_UV

D8

D15

NPOR_IN_1

D7

D14

NPOR_IN_0

D6

D13

UNUSED

D5

Data Bit /

Name

GSVBB_UV

D11

Data Bit /

Name

UNUSED

GSVBB_OV

GSU_OV

GSV_OV

GSW_OV

WD_STATE_(2:0)

ADDRESS: 00010b, TYPE: Read Only (RO)

SVBB_UV [D20]

GND (‒) to SVBB (+) under voltage status

The voltage at the SVBB pin is OK (default)

The voltage at the SVBB pin is too low

0

1

GSVBB_UV [D19]

Indicates the voltage from SVBB (‒) to GVBB (+) is stuck low

Gate-to-source voltage is OK (default)

0

1

Gate-to-source voltage is supposed to be high/on, but remains low

Indicates the voltage from SU (‒) to GU (+) is stuck low

Gate-to-source voltage is OK (default)

GSU_UV [D18]

0

1

Gate-to-source voltage is supposed to be high/on, but remains low

Indicates the voltage from SV (‒) to GV (+) is stuck low

Gate-to-source voltage is OK (default)

GSV_UV [D17]

0

1

Gate-to-source voltage is supposed to be high/on, but remains low

Indicates the voltage from SW (‒) to GW (+) is stuck low

Gate-to-source voltage is OK (default)

GSW_UV [D16]

0

1

Gate-to-source voltage is supposed to be high/on, but remains low

NPOR_IN_1

NPOR_IN_0

[D14]

NPOR Input Control

[D15]

0

1

0

1

0

1

VUC_OK only (default)

VUC_OK and V5A_OK

VUC_OK and Watchdog Fault (WD_F)

VUC_OK and V5A_OK and Watchdog Fault (WD_F)

Unused at this time

UNUSED [D13:D12]

GSVBB_OV [D11]

Indicates the voltage from SVBB (‒) to GVBB (+) is stuck high

Gate-to-source voltage is OK (default)

0

1

Gate-to-source voltage is supposed to be low/off, but remains high

Indicates the voltage from SU (‒) to GU (+) is stuck high

Gate-to-source voltage is OK (default)

GSU_OV [D10]

0

1

Gate-to-source voltage is supposed to be low/off, but remains high

Indicates the voltage from SV (‒) to GV (+) is stuck high

Gate-to-source voltage is OK (default)

GSV_OV [D9]

0

1

Gate-to-source voltage is supposed to be low/off, but remains high

Indicates the voltage from SW (‒) to GW (+) is stuck high

Gate-to-source voltage is OK (default)

GSW_OV [D8]

0

1

Gate-to-source voltage is supposed to be low/off, but remains high

WD_STATE_2 WD_STATE_1

WD_STATE_0

WatchDog State

[D5]

[D7]

[D6]

0

1

0

1

0

1

0

1

IDLE

0

CONFIG

0

1

RESET

0

1

NORMAL

1

0

FLASH

1

0

DISABLED

Reserved / Future Use

1

38

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x03. Status Register 3:

D20

D19

D18

D17

D16

D15

D14

D13

Data Bit /

Name

PWWD_COUNT_(7:0)

D12

D11

D10

D9

D8

D7

D6

D5

Data Bit /

Name

UNUSED

ADDRESS: 00011b, TYPE: Read Only (RO)

PWWD_COUNT_ [D20:D13]

Indicates the value of the error counter of the Pulse Width Watchdog

00000000

0 (starting value)

.

10100000

160, default maximum value

.

11011100

220, alternate maximum value selectable via SPI

UNUSED [D12:D5]

Unused at this time

39

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x04. Diagnostic Register 0:

D20

UNUSED

D12

D19

UNUSED

D11

D18

UNUSED

D10

D17

UNUSED

D9

D16

VREG_OV

D8

D15

VREG_UV

D7

D14

VUC_OV

D6

D13

VUC_UV

D5

Data Bit /

Name

Data Bit /

Name

UNUSED

VCP_UV

V5A_OV

V5A_UV

UNUSED

ADDRESS: 00100b, TYPE: Read, or Write 1 to Clear (RW1C)

UNUSED [D20:D17]

Unused at this time

VREG_OV [D16]

Indicates an overvoltage occurred at the buck pre-regulator output

0

No fault (default)

1

Fault

VREG_UV [D15]

Indicates an undervoltage occurred at the buck pre-regulator output

0

No fault (default)

1

Fault

VUC_OV [D14]

Indicates an overvoltage occurred at the VUC LDO output

0

No fault (default)

1

Fault

VUC_UV [D13]

Indicates an undervoltage occurred at the VUC LDO output

0

No fault (default)

1

Fault

UNUSED [D12]

Unused at this time

VCP_UV [D11]

Indicates an undervoltage occurred at the VCP pin

0

No fault (default)

1

Fault

V5A_OV [D10]

Indicates an overvoltage occurred at the V5A LDO output

0

No fault (default)

1

Fault

V5A_UV [D9]

Indicates an undervoltage occurred at the V5A LDO output

0

No fault (default)

Fault

1

UNUSED [D8:D5]

Unused at this time

40

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x05. Diagnostic Register 1:

D20

VCP2_OV

D12

D19

VCP2_UV

D11

D18

UNUSED

D10

D17

UNUSED

D9

D16

V5P1_OV

D8

D15

V5P1_UV

D7

D14

V5P2_OV

D6

D13

V5P2_UV

D5

Data Bit /

Name

Data Bit /

Name

UNUSED

ADDRESS: 00101b, TYPE: Read, or Write 1 to Clear (RW1C)

VCP2_OV [D20]

Indicates an overvoltage occurred at the VCP2 pin

0

No fault (default)

1

Fault

VCP2_UV [D19]

Indicates an undervoltage occurred at the VCP2 pin

0

No fault (default)

1

Fault

UNUSED [D18:D17]

Unused at this time.

V5P1_OV [D16]

Indicates an overvoltage occurred at the V5P1 LDO output

0

No fault (default)

1

Fault

V5P1_UV [D15]

Indicates an undervoltage occurred at the V5P1 LDO output

0

No fault (default)

1

Fault

V5P2_OV [D14]

Indicates an overvoltage occurred at the V5P2 LDO output

0

No fault (default)

1

Fault

V5P2_UV [D13]

Indicates an undervoltage occurred at the V5P2 LDO output

0

No fault (default)

Fault

1

UNUSED [D12:D5]

Unused at this time.

41

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x06. Enable/Disable Register:

D20

ENW_1

D12

D19

D18

ENU_1

D10

D17

ENVBB_1

D9

D16

ENW_0

D8

D15

ENV_0

D7

D14

ENU_0

D6

D13

ENVBB_0

D5

Data Bit /

Name

ENV_1

D11

Data Bit /

Name

V5P2_EN_1

V5P1_EN_1

UNUSED

V5P2_EN_0

V5P1_EN_0

UNUSED

ADDRESS: 00110b, TYPE: Read or Write (RW)

ENW_1 [D20]

ENW_0 [D16]

Controls the on/off status of the GW gate driver

Disabled (default)

0

1

Maintain previous state

Enabled

1

0

1

ENV_1 [D19]

ENV_0 [D15]

Controls the on/off status of the GV gate driver

Disabled (default)

0

1

Maintain previous state

Enabled

1

0

1

ENU_1 [D18]

ENU_0 [D14]

Controls the on/off status of the GU gate driver

Disabled (default)

0

1

0

1

0

Maintain previous state

Enabled

1

ENVBB_1 [D17]

ENVBB_0 [D13] Controls the on/off status of the GVBB gate driver

0

1

0

1

Disabled (default)

Maintain previous state

Enabled

0

1

V5P2_EN_1 [D12]

V5P2_EN_1 [D8] Controls the on/off status of the V5P2 LDO output

0

1

0

1

Disabled

0

Maintain previous state

Enabled (default)

1

V5P1_EN_1 [D11]

V5P1_EN_1 [D7] Controls the on/off status of the V5P1 LDO output

0

1

0

1

0

1

Disabled

Maintain previous state

Enabled (default)

UNUSED [D10:D9]

UNUSED [D6:D5]

Unused at this time

42

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x07. Watchdog Command & NPOR Input Keys:

D20

D19

D18

D17

D16

D15

D14

D13

Data Bit /

Name

WD_

KEY_7

WD_

KEY_6

WD_

KEY_5

WD_

KEY_4

WD_

KEY_3

WD_

KEY_2

WD_

KEY_1

WD_

KEY_0

D12

D11

D10

D9

D8

D7

D6

D5

Data Bit /

Name

NPOR_

KEY_7

NPOR_

KEY_6

NPOR_

KEY_5

NPOR_

KEY_4

NPOR_

KEY_3

NPOR_

KEY_2

NPOR_

KEY_1

NPOR_

KEY_0

ADDRESS: 00111b, TYPE: Write Only (WO)

Watchdog Mode Key – Three 8-bit words (WORD1 – WORD3) must be

sent in the correct order to enable flash mode or restart the watchdog.

If an incorrect word is receive then the register resets and the first word

must be resent. The third 8-bit word (WORD3) is the command to force

the Watchdog to transition from state to state.

WD_KEY [D20:D13]

FLASH

Command

CONFIG

Command

RESTART

Command

DISABLE

Command

WORD1 (Key)

WORD2 (Key)

0xD3

0x33

0xCC

0xD3

0x33

0xCD

0xD3

0x33

0xCE

0xD3

0x33

0xCF

WORD3 (Command)

NPOR Key – Two 8-bit words (WORD1, WORD2) must be sent in the

correct order to unlock the NPOR configuration register. If an incorrect

word is received then the register resets and the first word must be

resent. A third 8-bit word (WORD3) adds V5A_OK to the NPOR logic. If

the A81407 experiences a master reset (MPOR) it will transition back to

the default state.

NPOR_KEY [D12:D5]

Inputs to the NPOR logic are

VUC_OK

WD_F

V5A_OK

WORD1 (Key)

WORD2 (Key)

0xD4

0x2B

0xA5

0xA6

0xA7

Yes (default)

No (default)

Yes

Yes (low for 2 ms)

No

Yes

WORD3 (Command)

Yes (low for 2 ms)

43

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x08. Configuration Register 0:

D20

DITH_DIS

D12

D19

UNUSED

D11

D18

UNUSED

D10

D17

UNUSED

D9

D16

UNUSED

D8

D15

UNUSED

D7

D14

UNUSED

D6

D13

UNUSED

D5

Data Bit /

Name

Data Bit /

Name

WDF_2_Gz

UNUSED

WDF_2_FFn

UNUSED

Pre-Reg Off

UNUSED

ADDRESS: 01000b, TYPE: Read or Write (RW)

DITH_DIS [D20]

Controls the status of PWM frequency dithering

Dithering is enabled (default)

0

1

Dithering is disabled

UNUSED [D19:D13]

WDF_2_Gz [D12]

0

Unused at this time.

Determines if a watchdog fault affects the four gate drivers

Gate drivers will not be affected if a WD_F occurs (default)

All four gate drivers (GVBB, GU, GV, GW) will be turned off if a WD_F

occurs.

1

UNUSED [D11]

Unused at this time.

WDF_2_FFn [D10]

Determines if a Watchdog Fault force FFn low

FFn will not transition low if a Watchdog Fault occurs (default)

FFn will transition low if a Watchdog Fault occurs

Unused at this time.

0

1

UNUSED [D9:D8]

Pre-Reg Off [D7]

Controls the masking of VREG_OV fault

FFn will transition low if an overvoltage occurs on VREG (default)

FFn will not transition low if an overvoltage occurs on VREG

Unused at this time.

0

1

UNUSED [D6:D5]

44

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x09. Configuration Register 1:

D20

D19

D18

GD_FLT_ON

D10

D17

GD_UV_SEL

D9

D16

GD_EN_SEL

D8

D15

UNUSED

D7

D14

UNUSED

D6

D13

UNUSED

D5

Data Bit /

Name

WD_SEL_(1:0)

D12

D11

Data Bit /

Name

SEL_MUX_(3:0)

UNUSED

ADDRESS: 01001b, TYPE: Read or Write (RW)

WD_SEL_1 [D20]

WD_SEL_0 [D19] TYPE OF ACTIVE WATCHDOG

0

1

0

1

0

1

None, power-up value for WD_SEL_(1:0)

Pulse Width Watchdog (PWWD) (default, after t_CONFIG(WD)

)

Window Watchdog (WWD)

Q&A Watchdog (QAWD)

Sets the fault-state of the three gate drivers, GU, GV, and GW,

for any fault other than a watchdog fault.

GD_FLT_ON [D18]

0

Fault-state of GU, GV, and GW is off. Inverse of the fault table.

1

GU, GV, and GW operate as shown in the fault table (default).

GD_UV_SEL [D17]

Selects the gate driver under voltage filter/deglitch delay times

0

Slow

1

Fast (default)

GD_EN_SEL [16]

Selects the gate driver enable/disable delay times

0

1

Slow

Fast (default)

SEL_MUX_3

[D12]

SEL_MUX_2

[D11]

SEL_MUX_1

[D10]

SEL_MUX_0

[D9]

MUX

OUTPUT

DIVIDER

RATIO

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VREG

VUC

÷2

÷8

÷1

**

V5A

V5P1

V5P2

ENBAT

BG1

BG2

TEMP

VIN

÷10

÷12

‒

VCP2

VCP

Unused

‒

** V_TEMP= 1440 mV – 3.92 mV/°C × T_J(°C)

UNUSED [D8:D5]

Unused at this time.

45

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x0A. Configuration Register 1 (WD):

D20

D19

WWD_TIMER_(2:0)

D11

D18

D10

D17

UNUSED

D9

D16

D15

D14

D13

Data Bit /

Name

QAWD_TIMER_(3:0)

D12

D8

D7

D6

D5

Data Bit /

Name

QAWD_RETRY_(1:0)

QAWD_RAND_(5:0)

ADDRESS: 01010b, TYPE: Read or Write (RW)

WWD_TIMER_2

[D20]

WWD_TIMER_1

[D19]

WWD_TIMER_0

[D18]

t_WD(FAST)(ms)

t_WD(SLOW)(ms)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.5

4

1

8

2

16

4 (default)

32 (default)

6

8

42

64

10

12.5

80

100

QAWD_

MIN_TIMEOUT MAX_TIMEOUT

TIMER_3 [D16] TIMER_2 [D15] TIMER_1 [D14] TIMER_0 [D13]

t_Q&A(MIN)(ms)

t_Q&A(MAX)(ms)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.5

1

2

4

2

3

8

16

12

24

16 (default)

32 (default)

48

24

32

64

40

80

64

128

144

160

192

256

288

72

80

96

128

144

QAWD_RETRY_1 QAWD_RETRY_0 ACCEPTABLE NUMBER OF RETRIES

[D12]

[D11]

0

1

0

1

0

1

0 times

1 time (default)

3 times

7 times

Randomly generated 6-bit word for the Q&A watchdog.

These bits must support read (Q) and write (A) from the micro-

controller during NORMAL mode of operation.

QAWD_RAND [D10:D5]

46

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x0B. Configuration Register 2 (WD):

D20

PWWD_EDGE_TO(1:0)

D12 D11

PWWD_DEC_(1:0)

D19

D18

PWWD_NONACT_TO_(1:0)

D10 D9

PWWD_INC_(1:0)

D17

D16

PWWD_WIN_TOL_(1:0)

D8 D7

PWWD_MAX_(1:0)

D15

D14

D13

Data Bit /

Name

PWWD_PW_(1:0)

D6

D5

Data Bit /

Name

PWWD_POE_DLY_(1:0)

ADDRESS: 01011b, TYPE: Read or Write (RW)

PWWD_EDGE_TO_1 [D20]

PWWD_EDGE_TO_0 [D19]

FIRST-EDGE TIMEOUT (ms)

0

2.5

0

1

5 (default)

1

0

10

1

15

PWWD_ACT_TO_1 [D18]

PWWD_ACT_TO_0 [D17]

NON-ACTIVITY TIMEOUT (ms)

0

8

0

1

16 (default)

1

0

24

1

32

PWWD_WIN_TOL_1 [D16]

PWWD_WIN_TOL_0 [D15]

WINDOW TOLERANCE (%)

0

±8

0

1

±13 (default)

1

0

±18

1

±23

PWWD_PW_1 [D14]

PWWD_PW_0 [D13]

PULSE WIDTH (ms)

0

0.5

0

1

1.0 (default)

1

0

1.5

1

2.0

PWWD_DEC [D12]

PWWD_DEC [D11]

DECREMENT AMOUNT (counts)

0

1

0

1

2 (default)

1

0

3

1

4

PWWD_INC [D10]

PWWD_INC [D9]

INCREMENT AMOUNT (counts)

0

5

0

1

10 (default)

1

0

20

1

30

PWWD_MAX [D8]

PWWD_MAX [D7]

MAXIMUM FAULT COUNTER VALUE

0

1

0

1

0

1

80

120

160 (default)

220

Value pre-loaded into the PWWD error

counter. This value is used to “pre-

qualify” the WDIN clock before POE is

allowed to transition high.

PWWD_POE_DLY [D6]

PWWD_POE_DLY [D5]

0

1

0

1

0

1

2 (default)

4

10

16

47

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x0C. Readback Register:

D20

D19

D11

D18

D10

D17

D16

D15

D14

D13

Data Bit /

Name

Readback_(15:8)

D12

D9

D8

D7

D6

D5

Data Bit /

Name

Readback_(7:0)

ADDRESS: 01100b, TYPE: Read Only (RO)

The host microcontroller can implement a loopback test with this

register. The host should write a specific pattern (value) to this

register, read it back, and compare the two results. The host should

use at least two different write patterns to be certain there are no

stuck bits.

Readback [15:0]

48

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x0D. Verify Result Register 0:

D20

VUC_OV_FAIL

D12

D19

VUC_UV_FAIL

D11

D18

V5A_OV_FAIL

D10

D17

V5A_UV_FAIL

D9

D16

UNUSED

D8

D15

UNUSED

D7

D14

UNUSED

D6

D13

UNUSED

D5

Data Bit /

Name

Data Bit /

Name

BIST_FAIL

TSD_BIST_FAIL VREG_OV_FAIL VREG_UV_FAIL V5P1_OV_FAIL

V5P1_UV_FAIL

V5P2_OV_FAIL

V5P2_UV_FAIL

ADDRESS: 01101b, TYPE: Read, or Write 1 to Clear (RW1C)

VUC_OV_FAIL [D20]

Indicates if the VUC overvoltage circuit failed its self-test

0

Self-test passed (default value at power-up)

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the VUC undervoltage circuit failed its self-test

Self-test passed (default value at power-up)

VUC_UV_FAIL [D19]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the V5A overvoltage circuit failed its self-test

Self-test passed (default value at power-up)

V5A_OV_FAIL [D18]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the V5A undervoltage circuit failed its self-test

Self-test passed (default value at power-up)

V5A_UV_FAIL [D17]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Unused at this time.

UNUSED [D16:D13]

BIST_FAIL [D12]

Indicates if the A81407 failed one or more of its self-tests

Self-test passed (default value at power-up)

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the TSD circuit failed its self-test

TSD_BIST_FAIL [D11]

0

Self-test passed (default value at power-up)

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the VREG overvoltage circuit failed its self-test

Self-test passed (default value at power-up)

VREG_OV_FAIL [D10]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the VREG undervoltage circuit failed its self-test

Self-test passed (default value at power-up)

VREG_UV_FAIL [D9]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the V5P1 overvoltage circuit failed its self-test

Self-test passed (default value at power-up)

V5P1_OV_FAIL [D8]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the V5P1 undervoltage circuit passed its self-test

Self-test passed (default value at power-up)

V5P1_UV_FAIL [D7]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the V5P2 overvoltage circuit failed its self-test

Self-test passed (default value at power-up)

V5P2_OV_FAIL [D6]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

Indicates if the V5P2 undervoltage circuit failed its self-test

Self-test passed (default value at power-up)

V5P2_UV_FAIL [D5]

0

1

Self-test failed. FFn set low. Write “1” to clear and regain FFn functionality.

49

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

0x0E. Verify Result Register 1:

D20

UNUSED

D12

D19

UNUSED

D11

D18

UNUSED

D10

D17

UNUSED

D9

D16

UNUSED

D8

D15

UNUSED

D7

D14

UNUSED

D6

D13

UNUSED

D5

Data Bit /

Name

Data Bit /

Name

UNUSED

ADDRESS: 01110b, TYPE: Read, or Write 1 to Clear (RW1C)

[D20:D5] Unused at this time.

50

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

DESIGN AND COMPONENT SELECTION

The following section briefly describes the component selection

procedure for the A81407. Refer to following pages for full sche-

matic and recommended bill of materials.

Pre-Regulator Output Inductor

A 10 µH inductor is recommended for the pre-regulator buck and

buck-boost topologies.

Setting Up the Pre-Regulator

A molded or distributed air gap type is recommended to aid

passing EMC tests. Due to topology and frequency switching of

the A81407 pre-regulator, the inductor ripple current varies with

input voltage per Figure 18 below.

This section discusses the component selection for the A81407

pre-regulator. It covers the charge pump circuit, inductor, diodes,

boost MOSFET, and input and output capacitors.

Charge Pump Capacitors

The charge pump circuits require four capacitors: VCP2, a 2.2 µF

capacitor connected from pin VCP to VIN and 1 µF capacitor

connected between pins CP2C1 and CP2C2; and VCP, a 1 µF

capacitor connected from pin VCP2 to VCP and 0.22 µF capaci-

tor connected between pins CP1 and CP2. These capacitors

should be high-quality ceramic capacitors, such as an X5R or

X7R, with a voltage rating of at least 16 V.

PWM Switching Frequency

The switching frequency of the A81407 is fixed at 2.2 MHz

nominal. The A81407 includes a frequency foldback scheme that

starts when V_INis greater than 18 V. Between 18 V and 36 V,

the switching frequency will foldback from 2.2 MHz typical to

1 MHz typical. The switching frequency for a given input voltage

above 18 V and below 36 V is:

Figure 18: Typical Peak Inductor Current versus Input

Voltage for 0.765 A Output Current and 10 µH Inductor

The inductor should not saturate given the peak operating current

during overload. Equation 2 below calculates this current. In Equa-

tion 2, V_VIN(MAX)is the maximum continuous input voltage, such

as 16 V, and V_Fis the asynchronous diode’s forward voltage.

Equation 1:

1.2

= 3.4 −

×

18

Equation 2:

(

)

×

+

=

−

(

)

,

0.9 ×

× (

+

)

(

After an inductor is chosen, it should be tested during output

overload and short-circuit conditions. The inductor current should

be monitored using a current probe. A good design should ensure

the inductor or the regulator are not damaged when the output

is shorted to ground at maximum input voltage and the highest

expected ambient temperature.

Inductor ripple current can be calculated using equations below

for buck mode, and buck-boost mode.

Equation 3:

(

)

×

−

=

Figure 17: Typical Switching Frequency

versus Input Voltage

×

51

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Equation 4:

Ceramic Input Capacitors

(

)

×

−

The ceramic input capacitor(s) must limit the voltage ripple at the

VIN pin to a relatively low voltage during maximum load. Equa-

tion 8 can be used to calculate the minimum input capacitance,

=

×

Pre-Regulator Output Capacitors

Equation 8:

The output capacitors filter the output voltage to provide an

acceptable level of ripple voltage. They also store energy to help

maintain voltage regulation during a load transient. The voltage

rating of the output capacitors must support the output voltage

with sufficient design margin.

₎× 0.25

(

≥

0.90 ×

× 50

where I_VREG(MAX)is the maximum current from the pre-regulator,

Equation 9:

The output voltage ripple (ΔV_VREG) is a function of the output

=

)

+

+ 20

(

capacitors parameters: C_O, ESR_CO, ESL_CO

.

where I_LINEARis the sum of all the internal linear regulators

output currents, I_AUXis any extra current drawn from the VREG

output to power other devices external to the A81407.

Equation 5:

∆

= ∆

×

+

−

A good design should consider the DC bias effect on a ceramic

capacitor—as the applied voltage approaches the rated value, the

capacitance value decreases. The X5R and X7R type capacitors

should be the primary choices due to their stability versus both

DC bias and temperature. For all ceramic capacitors, the DC bias

effect is even more pronounced on smaller case sizes, so a good

design will use the largest affordable case size.

×

+

∆

8 ×

×

The type of output capacitors will determine which terms of

Equation 6 are dominant. For ceramic output capacitors, the

ESR_COand ESL_COare virtually zero, so the output voltage ripple

will be dominated by the third term of Equation 5.

Also for improved noise performance, it is recommended to add

smaller sized capacitors close to the input pin and the D1 anode.

Use a 0.1 µF 0603 capacitor or less.

Equation 6:

∆

Buck-Boost Asynchronous Diode (D1)

∆

=

8 ×

×

The highest peak current in the asynchronous diode (D1) occurs

during overload and is limited by the A81407. Equation 3 can be

used to calculate this current.

To reduce the voltage ripple of a design using ceramic output

capacitors, simply increase the total capacitance, reduce the

inductor current ripple (i.e. increase the inductor value), or

increase the switching frequency.

The highest average current in the asynchronous diode occurs

when V_VINis at its maximum, D_BOOST= 0%, and D_BUCK= mini-

mum (10%),

The transient response of the regulator depends on the number and

type of output capacitors. In general, minimizing the ESR of the

output capacitance will result in a better transient response. The

ESR can be minimized by simply adding more capacitors in paral-

lel or by using higher quality capacitors. At the instant of a fast

load transient (di/dt), the output voltage will change by the amount:

Equation 10:

I

_ꢀVꢁ= ꢂ.ꢃ × I_{Vꢄꢅꢁ(Mꢀꢆ)}

where I_VREG(MAX)is calculated using Equation 10.

Boost MOSFET (Q1)

Equation 7:

The RMS current in the boost MOSFET (Q1) occurs when V_VINis

at its minimum and both the buck and boost operate at their maxi-

mum duty cycles (approximately 64% and 58%, respectively),

∆

= ∆

×

+

×

After the load transient occurs, the output voltage will deviate

from its nominal value for a short time. This time will depend

on the system bandwidth, the output inductor value, and output

capacitance. Eventually, the error amplifier will bring the output

voltage back to its nominal value.

Equation 11:

2

∆

( / )

∆

(

/

)

=

×

−

+

1,

(

)

[

]

2

12

52

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

where ΔI_L(B/B)and I_PEAKare derived using Equation 3 and Equa-

tion 5, respectively.

Boost Diode (D2)

In buck mode, this diode will simply conduct the output current.

However, in buck-boost mode, the peak currents in this diode

may increase a lot. The A81407 limits the peak current to the

value calculated using Equation 3. The average current is simply

the output current.

Linear Regulators

The four linear regulators only require a single ceramic capacitor

located near A81407 terminals to ensure stable operation. The

range of acceptable values is shown in the Electrical Characteris-

tics table. A 2.2 μF capacitor per regulator is recommended.

Also, since the V5P1 and V5P2 are used to power remote cir-

cuitry, their load may include external wiring. The inductance of

this wiring may cause LC-type ringing and negative spikes on

the V5P1 (V5P2) pin if a “fast” short-to-ground occurs. A small

Schottky diode is recommended to be placed close to the V5P1

(V5P2) pin to clamp this negative spike. The MSS1P5 (or equiva-

lent) is a good choice.

Internal Bias (VCC)

The internal bias voltage should be decoupled at the VCC pin

using a 1 μF ceramic capacitor. It is not recommended to use this

pin as a source.

Signal Pins (NPOR, FFn, POE)

The A81407 has many signal level pins. The NPOR, FFn, and

ENBAT are open-drain outputs and require external pull-up resis-

tors. Allegro recommends sizing the external pull-up resistors so

each pin will sink less than 2 mA when it is a logic low. The POE

signal is push-pull output and does not require an external pull-up

resistor.

53

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

ꢂ3

1 ꢄꢅ

ꢂꢋ

0.ꢈꢈ ꢄꢅ

ꢂ1

ꢈ.ꢈ ꢄꢅ

ꢂꢈ

1 ꢄꢅ

ꢓ1

10 ꢄH

3ꢃ

3ꢈ

ꢓꢔ

ꢓꢒ

ꢂ5

ꢊꢈ

SS3Pꢋ

ꢂꢃ

ꢈꢈ0ꢐꢅ

ꢂ13

0.1 ꢄꢅ

ꢂ1ꢈ

10 nꢅ

3

ꢊ1

SS3Pꢋ

ꢀin

ꢃꢑ0ꢐꢅ

ꢀꢁN

ꢂꢇ

ꢋꢇ ꢄꢅ

ꢂꢑ

ꢋ.ꢇ ꢄꢅ

ꢂ11

10 nꢅ

ꢂ9

ꢋ.ꢇ ꢄꢅ

ꢂ10

0.1 ꢄꢅ

R1

Rꢈ

5.ꢃꢈ Ω

ꢋ

ꢑ.ꢃꢃ Ω

ꢒNꢊ

ꢌ1

ꢈꢇ

ꢂꢆMP

ꢂ1ꢋ

39 ꢐꢅ

R3

ꢈꢈ.1 ꢉΩ

ꢈ ꢉΩ

5

ꢀꢂꢂ

ꢂ15

1.5 nꢅ

31

33

ꢂ1ꢃ

1 ꢄꢅ

ꢀUꢂ

ꢀRꢍꢒ

PꢒNꢊ

ꢂ1ꢇ

10 nꢅ

ꢂ1ꢑ

0.1 ꢄꢅ

ꢂ19

10 ꢄꢅ

ꢂꢈ0

10 ꢄꢅ

ꢂꢈ1

10 ꢄꢅ

ꢂꢈꢈ

10 ꢄꢅ

ꢂꢈ3

10 ꢄꢅ

R5

ꢈ0 ꢉΩ

ꢑ

NPꢆR

ꢍNꢎ

30

ꢈ9

ꢃ

ꢀUꢂ

ꢀ5A

Rꢃ

3.3 ꢉΩ

10

ꢂꢈꢃ

ꢈ.ꢈ ꢄꢅ

ꢂ30

0.1 ꢄꢅ

ꢂꢈ5

ꢈ.ꢈ ꢄꢅ

ꢂꢈ9

0.1 ꢄꢅ

ꢍNꢎAꢏ

ꢂꢈꢋ

0.ꢈꢈ ꢄꢅ

ꢀUꢂ

Rꢇ

ꢀUꢂ

Rꢑ

19

ꢈ0

ꢀ5P1

ꢀ5Pꢈ

ꢈ0 ꢉΩ

ꢈ5

ꢂꢈꢇ

ꢈ.ꢈ ꢄꢅ

ꢊ3

MSS1P5

ꢊ3

MSS1P5

ꢂꢈꢑ

ꢈ.ꢈ ꢄꢅ

ꢂ31

0.1 ꢄꢅ

ꢂ3ꢈ

0.1 ꢄꢅ

ꢕꢊꢖꢁN

ꢕꢊꢖꢅn

ꢈꢑ

9

11

1ꢈ

13

1ꢋ

15

1ꢃ

1ꢇ

1ꢑ

ꢅꢅn

ꢒꢀꢎꢎ

ꢇ

ꢈꢃ

ꢈ3

ꢈꢋ

ꢈ1

ꢈꢈ

Pꢆꢍ

Sꢀꢎꢎ

ꢒꢕ

AMUꢔꢆ

MꢁSꢆ

MꢆSꢁ

Sꢕ

ꢒꢀ

Sꢂꢗ

ꢂS

Sꢀ

ꢒU

SU

Figure 19: Typical Application Schematic

Table 4: Bill of Materials

Ref. Des.

Description

Qty.

Footprint

Manufacturer

Manufacturer P/N

U1

A81407 Buck-Boost w/ 4 LDOs, 4 Drivers,

SPI

1

TSSOP-38

Allegro MicroSystems

Q1

FET, N, 20 V / 30 V, 25 mΩ and 14 nC_MAX

@ 4.5 V_GS

1

PQFN

ST

STL10N3LLH5

NVTFS4823N

SQS420EN

3.3 mm × 3.3 mm Onsemi

Vishay

R3

Resistor, 22.1 kΩ, 1/10 W, 1%

Resistor, 20 kΩ, 1/10 W, 5%

Resistor, 3.3 kΩ, 1/10 W, 5%

Resistor, 2.00 kΩ, 1/16 W, 1%

Resistor, 8.66 Ω, 1/4W, 1%

Resistor, 5.62 Ω, 1/10W, 1%

1

3

1

0603

0402

1206

0603

Panasonic

ERJ-3EKF2212V

R5, R7, R8

Panasonic

Vishay

ERJ-3EKF2002V

R6

ERJ-3EKF3301V

R4

CRCW04022K00FKED

CRCW12068R66FKEA

ERJ-3RQF5R6V

R1

Vishay

R2

Panasonic

Continued on next page...

54

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Table 4: Bill of Materials (continued)

Ref. Des.

Description

Qty.

Footprint

0603

Manufacturer

TDK

Murata

Taiyo Yuden

Manufacturer P/N

C1

Capacitor, Ceramic, 2.2 µF, 16 V, 10%, X7R

1

C1608X7S1C225K080AC

GRM188Z71E225KE43D

EMK107BB7225KA-T

C2, C3, C16

C4, C24

Capacitor, Ceramic, 1 µF, 35 V, 10%, X7R

Capacitor, Ceramic, 0.22 µF, 50 V, 10%, X7R

Capacitor, Ceramic, 4.7 µF, 50 V, 10%, X7R

3

2

0603

1210

TDK

Taiyo Yuden

C1608X7R1V105K080AC

GMK107AB7105KAHT

Murata

TDK

GCM188R71H224KA64J

CGA3E3X7R1H224K080AB

C8, C9

Murata

TDK

Taiyo Yuden

GRM32ER71H475KA88L

C3225X7R1H475K250AB

UMK325B7475KM-T

C10, C13, C18,

C29, C30, C31, C32

Capacitor, Ceramic, 0.1 µF, 50 V, 10%, X7R

Capacitor, Ceramic, 10 µF, 16 V, 10%, X7R

7

5

0603

1206

Murata

TDK

GCM188L81H104KA57D

CGA3E2X7R1H104K080AA

C19, C20, C21,

C22, C23

Murata

TDK

GRM31CR71C106KAC7L

C3216X7R1C106K

Taiyo Yuden

EMK316B7106KL-TD

C25, C26

Capacitor, Ceramic, 2.2 µF, 16 V, 10%, X7R

Capacitor, Ceramic, 2.2 µF, 50 V, 10%, X7R

2

0805

TDK

Murata

CGA4J3X7R1C225K125AB

GCM21BR71C225KA64L

C27, C28

C7

2

1

0805

8mm

TDK

CGA4J3X7R1H225M125AE

Capacitor, Electrolytic, 47 µF, 35 V, 20%,

125°C

Nichicon

Panasonic

UCX1V470MCL1GS

EEE-TP1V470AP

United Chemi Con

EMHB350ADA470MHA0G

C14

C15

Capacitor, Ceramic, 39 pF, 50 V, 5%, COG

Capacitor, Ceramic, 1.5 nF, 50 V, 10%, X7R

1

0603

Murata

TDK

GCM1885C1H390JA16D

CGA2B2C0G1H390J050BA

Murata

TDK

GCM188R71H152KA37D

CGA3E2X7R1H152K080AA

C11, C12, C17

C5

Capacitor, Ceramic, 10 nF, 50 V, 10%, X7R

Capacitor, Ceramic, 680 pF, 50 V, 10%, COG

3

1

0603

TDK

CGA1A2X7R1H101K030BA

Murata

TDK

GCM1555C1H681JA16D

CGA3E2C0G1H681J080AA

C6

Capacitor, Ceramic, 220 pF, 50 V, 10%, COG

Diode, Schottky, 3 A, 40 V

1

2

0603

SMP

eSMP

Murata

TDK

GCM1555C1H221JA16D

CGA3E2C0G1H221J080AA

D1, D2

Vishay

SS3P4-M3/84A

D3, D4

L1

Diode, Schottky, 1 A, 50 V

2

1

Vishay

MSS1P5-M3/89A

Inductor, 10 µH, 5.4 A_dc, 6.4A_sat, 52 mΩ max

8.6 mm ×

8.2 mm ×

4 mm

IHLP3232DZER100M11

55

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

PCB LAYOUT RECOMMENDATIONS

The input ceramic capacitors must be located as close as possible sible to VCP, CP1/CP2 and VCP2, CP2C1/CP2C2.

to the VIN pins. In general, the smaller capacitors (0402, 0603)

The ceramic capacitors for the LDOs (VUC, V5A, V5P1, and

must be placed very close to the VIN pin. The larger capacitors

V5P2) must be placed near their output pins. The V5P1 and V5P2

should be placed within 0.5 inches of the VIN pin. There must

outputs must have a 1 A / 40 V Schottky diode located very close

not be any vias between the input capacitors and the VIN pins.

to their pins to limit negative voltages.

The pre-regulator asynchronous diode (D1), input ceramic

capacitors, and RC snubber must be routed on one layer and

pin.

“star” grounded at a single location with multiple vias.

The VCC bypass capacitor must be placed very close to the VCC

The COMP network of pre-regulator (C14, C15, and R3) must be

The pre-regulator output inductor (L1) should be located close to

the LX pins. The LX trace widths (to L1, D1, and D2) should be

relatively wide and preferably on the same layer as the IC.

located very close to the COMP pin.

The thermal pad under the A81407 must connect to the ground

plane(s) with multiple vias.

The pre-regulators output ceramic capacitors should be located

near the VREG pin. There must be 1 or 2 smaller ceramic capaci-

tors as close as possible to the VREG pin.

The boost MOSFET (Q1) and the boost diode (D2) must be

placed very close to each other. Q1 should have thermal vias to a

polygon on the bottom layer. Also, there should be “local” bypass

capacitors from D2 cathode to Q1 source.

The four charge pump capacitors must be placed as close as pos-

56

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

PACKAGE OUTLINE DRAWING

For Reference Only – Not for Tooling Use

(Reference JEDEC MO-153 BDT-1)

Dimensions in millimeters

NOT TO SCALE

Dimensions exclusive of mold ﬂash, gate burrs, and dambar protrusions

Exact case and lead conﬁguration at supplier discretion within limits shown

9.70 0.10

8º

0º

6.50 0.10

38

0.20

0.09

B

4.40 0.10 6.40 BSC

3.00 0.10

A

1.00 REF

0.60 0.15

1

2

0.25 BSC

Branded Face

SEATING PLANE

GAUGE PLANE

C

38X

0.90 0.05

1.10 MAX

0.10

C

SEATING

PLANE

0.27

0.17

0.15

0.00

0.50 BSC

0.50

0.30

1.70

38

3.00 6.00

1

2

Terminal #1 mark area

Exposed thermal pad (bottom surface)

A

B

C

6.5

Reference land pattern layout (reference IPC7351 SOP50P640X120-39M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances; when

mounting on a multilayer PCB, thermal vias at the exposed thermal pad land

can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

C

PCB Layout Reference View

Figure 20: Package LV, 38-Pin eTSSOP

57

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator,

4× LDO Outputs, Watchdog, 4× Gate Drivers, and SPI

A81407

Revision History

Number

Date

Description

–

December 10, 2019

Initial release

Updated Product Title, Features and Benefits, Description, and Applications (page 1) and Overview

section (page 20)

1

2

June 10, 2020

December 1, 2020

Updated “CS Input Pull-Up to 3.3 V” to “CS Input Pull-Up to 3.0 V” (page 14).

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit

improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor

for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

58

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com


型号：	A81407KLVATR-1
厂家：	ALLEGRO MICROSYSTEMS
描述：	Multi-Output Regulator with Buck or Buck-Boost Pre-Regulator
文件：	总58页 (文件大小：3082K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

A81407KLVATR-1 [ALLEGRO]

相关型号：

A8145300

A814AY-100M

A814AY-100M=P3

A814AY-101K

A814AY-101K=P3

A814AY-102K

A814AY-102K=P3

A814AY-120M

A814AY-120M=P3

A814AY-121K

A814AY-121K=P3

A814AY-122K