A8303-1 [ALLEGRO]
Single LNB Supply and Control Voltage Regulator;
| 型号： | A8303-1 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Single LNB Supply and Control Voltage Regulator |
| 文件： | 总30页 (文件大小：3067K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A8303 and A8303-1
Single LNB Supply and Control Voltage Regulator
Pre-End-of-Life
This device is in production, however, it has been deemed Pre-End
of Life. The product is approaching end of life. Within a minimum of
6 months, the device will enter its final, Last Time Buy, order phase.
Date of status change: December 5, 2018
Recommended Substitutions: Generation 4 and 5 devices
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, LLC reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8303 and A8303-1
Single LNB Supply and Control Voltage Regulator
FEATURES AND BENEFITS
DESCRIPTION
• Integrated boost MOSFET, current sensing, and
compensation
Intended for analog and digital satellite receivers, these single
low noise block converter regulator (LNBR) are monolithic
linear and switching voltage regulators, specifically designed
to provide the power and the interface signals to an LNB
down converter via coaxial cable. The A8303 and A8303-1
require few external components, with the boost switch and
compensation circuitry integrated inside of the devices.Ahigh
switchingfrequencyischosentominimizethesizeofthepassive
filtering components, further assisting in cost reduction. The
high levels of component integration ensure extremely low
noise and ripple figures.
• Stable with low-profile ceramic boost capacitors
• Configurable output settings to meet global requirements
• A8303-1 includes 11.667 V setting to meet Japanese
market requirements
• Adjustable LNB output current limit from 250 to 950 mA
□ Covers wide array of application requirements
□ Minimizes component sizing to fit each application
□ For startup, reconfiguration, and continuous output
(maximum value depends on PCB thermal design)
• Boost peak current limit scales with LNB current limit
setting
TheA8303andA8303-1havebeendesignedforhighefficiency,
using the Allegro™ advanced BCD process. The integrated
boost switch has been optimized to minimize both switching
and static losses. To further enhance efficiency, the voltage
drop across the tracking regulator has been minimized.
• 8 programmable LNB output voltage (DAC) levels
• LNB overcurrent limiter with shutdown timer
• Static LNB current limit reliably starts a wide
range of loads
• Tracking boost converter minimizes power dissipation
• LNB transition times configurable by external capacitor
For DiSEqC™ communications, a tone control pin is provided
to gate the internally generated 22 kHz tone on-and-off.
Continued on the next page…
A comprehensive set of fault registers are provided, which
complywithallthecommonstandards,including:overcurrent,
thermal shutdown, undervoltage, and power not good.
PACKAGE:
Furthermore, design methodology and structure ensure the
highest level of robustness against transients and component
failures.Thedevicesusea2-wirebidirectionalserialinterface,
compatiblewiththeI2C™standard,thatoperatesupto400 kHz.
20-contact MLP/QFN (suffix ES)
4 mm × 4 mm × 0.75 mm
TheA8303andA8303-1aresuppliedinalead(Pb)freepackage.
Functional Block Diagram
GNDLX
LX
BOOST
VCP
VIN
VFB
CLK
Charge
Pump
IC
Power
352 kHz
Osc
Boost
Regulator
VREG
GND
BOOSTREF
0.8 V
+
VIN
Linear
Regulator
ILIM OC
LNB
Slew
Rate
Limiter
LNBREF
Ref
DAC
+
22 kHz
Tone
Generator
TCAP
On / Off
ISET
TONECTRL
3
VSEL2 / 1 / 0
Unlatched
Status
SDA
SCL
ADD
PNG, CPOK
I2C
Interface
SET
RST
Latched
Faults
UVLO, OCP,
TSD
TSD
VIN
Timer
45 ms
Read
Fault
IRQ
ADJ
TDO
Tone
Detector
TDI
TDET
8303-DS, Rev. 9
MCO-0000367
February 8, 2019
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
FEATURES AND BENEFITS (continued)
• Push-pull LNB output stage maintains 13→18 V and 18→13 V • Diagnostic features: PNG, TDET
transition times, even with highly capacitive loads
• Built-in 22 kHz tone oscillator facilitates DiSEqC™ tone
encoding, even at no-load
• Tone generation does not require additional external
components
• Dynamic tone detect amplitude and frequency transmit/
receive thresholds
• Extensive protection features: UVLO, OCP, TSD, CPOK
• 2-wire I2C-compatible interface
SELECTION GUIDE
Part Number
A8303SESTR-T
A8303SESTR-T-1
Output Voltage Settings
Packing [1]
Description
Refer to Table 3a
7 in. reel, 1500 pieces/reel
12 mm carrier tape
ES package [2], MLP/QFN surface mount
4 mm × 4 mm × 0.75 mm nominal height
Refer to Table 3b
[1] Contact Allegro for additional packing options.
[2] Leadframe plating 100% matte tin.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Conditions
Rating
Unit
Load Supply Voltage, VIN pin
VIN
30
V
Internally
Limited
Output Current [3]
IOUT
A
Output Voltage: BOOST pin
Output Voltage: LNB pin
Output Voltage: LX pin
Output Voltage: VCP pin
Logic Input Voltage
–0.3 to 43
–1.0 to 43
–0.3 to 30
–0.3 to 48
–0.3 to 5.5
–0.3 to 5.5
–20 to 85
150
V
V
Surge [4]
V
V
V
Logic Output Voltage
V
Operating Ambient Temperature
Junction Temperature
Storage Temperature
TA
TJ(max)
Tstg
Range S
°C
°C
°C
–55 to 150
[3] Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the
specified current ratings, or a junction temperature, TJ, of 150°C.
[4] See application schematics 3 and 4 on pages 24 and 25.
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions [5]
Value
Unit
Package Thermal Resistance
RθJA
4-layer PCB based on JEDEC standard
37
°C/W
[5] Additional thermal information available on the Allegro website.
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
Table of Contents
Features and Benefits........................................................... 1
Description.......................................................................... 1
Package ............................................................................. 1
Functional Block Diagram ..................................................... 1
Selection Guide ................................................................... 2
Absolute Maximum Ratings................................................... 2
Thermal Characteristics ........................................................ 2
Pinout Diagram and Terminal List........................................... 4
Electrical Characteristics....................................................... 5
Functional Description .......................................................... 8
Protection ........................................................................ 8
Boost Converter/Linear Regulator ....................................... 8
Charge Pump ............................................................... 8
LNB and Boost Current Limit Setting................................ 8
Slew Rate Control ......................................................... 9
Pull-Down Rate Control.................................................. 9
Pull-Down Rate Control.................................................. 9
ODT (Overcurrent Disable Time)......................................... 9
Short Circuit Handling........................................................ 9
Auto-Restart..................................................................... 9
In-Rush Current.............................................................. 10
Tone Generation ............................................................. 10
Tone Detection ............................................................... 10
Component Selection .......................................................11
Boost Inductor..............................................................11
Boost Capacitors......................................................... 12
Boost Capacitors......................................................... 14
Surge Components...................................................... 14
BOOST Filtering and LNB Noise ................................... 14
Surge Components...................................................... 14
I2C™-Compatible Interface .............................................. 15
SDA and SCL Signals .................................................. 15
Acknowledge (AK) Bit .................................................. 15
Acknowledge Bit During a Write Sequence..................... 15
Acknowledge Bit During a Read Sequence..................... 15
I2C™ Communications ................................................... 16
I2C™ Start and Stop Conditions ................................... 16
I2C™ Write Cycle Description ....................................... 16
I2C™ Read Cycle Description ....................................... 16
Interrupt (IRQ) and Fault Clearing ..................................... 17
Control Registers (I2C™-Compatible Write Register)........... 21
Status Register (I2C™-Compatible Read Register).............. 22
Application Information ....................................................... 23
Package Outline Drawing.................................................... 28
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
Pinout Diagram
VCP
LNB
NC
VIN
1
2
3
4
5
15
14
13
12
11
GND
VREG
ISET
TCAP
PAD
TDI
TDO
Terminal List Table
Name
Number
Function
ADD
9
20
14
17
6
Address select
BOOST
GND
GNDLX
IRQ
Tracking supply voltage to linear regulator
Signal ground
Boost switch ground
Interrupt request
ISET
LNB
12
2
Output current limit set via external resistor
Output voltage to satellite dish
LX
16
3,18,19
Pad
7
Inductor drive point
NC
No connection
PAD
Exposed pad; connect to the ground plane, for thermal dissipation
I2C™-compatible clock input
SCL
SDA
8
I2C™-compatible data input/output
Capacitor for setting the rise and fall time of the LNB output
Connect to output for 22 kHz tone verification function
Open-drain logic output that transitions low when a 22 kHz tone is present at TDI
Gates the 22 kHz tone on-and-off
Gate supply voltage
TCAP
TDI
11
4
TDO
5
TONECTRL
VCP
10
1
VIN
15
13
Supply input voltage
VREG
Analog supply
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS [1]: Valid at TA = 25°C, VIN = 10 to 16 V,
as noted [2], unless noted otherwise
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
GENERAL
VIN = 12 V, IOUT = 50 mA, see tables 3a and
3b for DAC settings
Output Voltage Accuracy
Load Regulation
VOUT
–2
–
–
75
85
0
2
%
VIN = 12 V, VOUT = 13.667 V,
ΔIOUT = 50 to 700 mA
120
150
10
mV
mV
mV
ΔVOUT(Load)
VIN = 12 V, VOUT = 19.000 V,
ΔIOUT = 50 to 700 mA
–
VIN = 10 to 16 V, VOUT = 13.667 V,
IOUT = 50 mA
–10
Line Regulation
Supply Current
ΔVOUT(Line)
VIN = 10 to 16 V, VOUT = 19.000 V,
IOUT = 50 mA
–10
–
0
4
10
–
mV
mA
mA
IIN(OFF)
ENB = 0, VIN = 12 V
ENB = 1, VIN = 12 V, VOUT = 19 V,
ILOAD = 0 mA, TONECTRL = 0
–
11
–
IIN(ON)
ENB = 1, VIN = 12 V, VOUT = 19 V,
ILOAD = 0 mA, TONECTRL = 1
–
17
–
mA
RDS(on)
BOOST
fSW
Boost Switch On Resistance
Switching Frequency
ISW = 450 mA
–
300
352
800
–
mΩ
kHz
mV
320
600
384
1000
VBOOST – VLNB, no tone signal,
ILOAD = 700 mA
Linear Regulator Voltage Drop
∆VREG
TCAP capacitor (C12) charging
TCAP capacitor (C12) discharging
–13
7
–10
10
–7
13
µA
µA
TCAP Pin Current
ITCAP
For VLNB 13.667 to 19.667 V; C12 = 100 nF,
ILOAD = 700 mA
Output Voltage Rise Time [3]
tr(VLNB)
–
–
10
25
–
–
ms
ms
For VLNB 19.667 to 13.667 V; CLOAD = 100
µF,
Output Voltage Pull-Down Time [3]
tf(VLNB)
ILOAD = 0 mA
ENB = 0, VLNB = 21 V, Boost capacitor fully
charged
–
–
–
2
9
9
4
mA
mA
mA
ENB = 1, VSEL2,1,0 = 001 (13.667 V),
VLNB = 21 V, TONECTRL = 0 or 1
15
15
LNB Sink Current [3]
IRLNB
ENB = 1, VSEL2,1,0 = 101 (19.000 V),
VLNB = 21 V, TONECTRL = 0 or 1
ENB = 1, VSEL2,1,0 = 110 (19.667 V),
18.5 V < VLNB <21 V, TONECTRL = 0
–
–
30
–
40
10
mA
µA
LNB Off Current
ILNB(Off)
VIN = 16 V
Continued on the next page…
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TA = 25°C, VIN = 10 to 16 V,
as noted [2], unless noted otherwise
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
GENERAL (continued)
20 MHz BWL; reference circuit shown in
Application Information section; contact
Allegro for additional information on
application circuit board design
Ripple and Noise on LNB Output [4]
Vrip,n(pp)
–
15
–
mVPP
VREG Voltage
ISET Voltage
VVREG
VISET
VIN = 10 V
4.97
3.4
–
5.25
3.5
5.53
3.6
–
V
V
V
V
VIN = 10 V
VIN = 10 V, VOUT = 13.667 V
VIN = 10 V, VOUT = 19.000 V
2.28
3.17
TCAP Voltage
VTCAP
–
–
PROTECTION CIRCUITRY
250
720
300
800
350
880
mA
mA
RSET = 100 kΩ
RSET = 37.4 kΩ
Output Overcurrent Limit [5]
IOUT(MAX)
Overcurrent Disable Time
VIN Undervoltage Lockout Threshold
VIN Turn On Threshold
tDIS
VUVLO
–
8.05
8.40
–
45
8.35
8.70
350
1680
4030
165
20
–
8.65
9.00
–
ms
V
VIN falling
VIN rising
VIN(th)
V
Undervoltage Hysteresis
VUVLOHYS
mV
mA
mA
°C
°C
RSET = 100 kΩ
RSET = 37.4 kΩ
–
–
Boost MOSFET Current Limit
IBOOST(MAX)
–
–
Thermal Shutdown Threshold [3]
Thermal Shutdown Hysteresis [3]
TJ
–
–
∆TJ
–
–
With respect to VLNB setting; VLNB low,
PNG set to 1
PNGLOSET
88
91
94
%
Power Not Good (Low)
With respect to VLNB setting; VLNB low,
PNG reset to 0
PNGLORESET
92
–
95
4
98
–
%
%
%
Power Not Good (Low) Hysteresis
Power Not Good (High)
PNGLOHYS With respect to VLNB setting
With respect to VLNB setting; VLNB high,
PNG set to 1
PNGHISET
106
109
112
With respect to VLNB setting; VLNB high,
PNG reset to 0
PNGHIRESET
102
–
105
4
108
–
%
%
Power Not Good (High) Hysteresis
PNGHIHYS With respect to VLNB setting
TONE
Amplitude (A8303)
Amplitude (A8303-1)
Frequency
VTONE(PP) ILNB = 0 to 700 mA, CLNB = 750 nF
VTONE(PP) ILNB = 0 to 700 mA, CLNB = 330 nF
fTONE
400
400
20
650
650
22
900
800
24
mVPP
mVPP
kHz
ILNB = 0 to 700 mA,
CLNB = 750 nF or 330 nF
Duty Cycle
Rise Time
Fall Time
DCTONE
tR(TONE)
tF(TONE)
40
5
50
10
10
60
15
15
%
μs
μs
5
Continued on the next page…
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS [1] (continued): Valid at TA = 25°C, VIN = 10 to 16 V,
as noted [2], unless noted otherwise
Characteristics
TONE DETECTION
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VTDX(PP)
VTDR(PP)
TONECTRL = 1
TONECTRL = 0; 22 kHz sine wave
400
250
–
650
650
–
900
900
250
100
1100
1100
27
mVPP
mVPP
mVPP
mVPP
mVPP
mVPP
kHz
Amplitude
VTD(XMT)L TONECTRL = 1
Reject Amplitude, Low
Reject Amplitude, High
Frequency Capture
Frequency Reject, Low
Frequency Reject, High
VTD(RCV)L TONECTRL = 0; 22 kHz sine wave
VTD(XMT)H TONECTRL = 1
–
–
–
–
VTD(RCV)H TONECTRL = 0; 22 kHz sine wave
–
–
fTD(RCV)
fTD(XMT)
fTD(RCV)L
fTD(XMT)L
fTD(RCV)H
TONECTRL = 0; 650 mVPP sine wave
TONECTRL = 1; 650 mVPP sine wave
TONECTRL = 0; 650 mVPP sine wave
TONECTRL = 1; 650 mVPP sine wave
TONECTRL = 0; 650 mVPP sine wave
TONECTRL = 1; 650 mVPP sine wave
650 mVPP, 22 kHz sine wave
17
20
12
15
–
22
22
14
17
34
30
1.5
8.6
−
24
kHz
–
kHz
–
kHz
37
kHz
f
–
33
kHz
TD(XMT)H
Detection Delay
tDET
ZTDI
VTDO(L)
ITDO
–
3
cycle
kΩ
TDI Input Impedance
TDO Output Voltage
–
–
Tone present, ILOAD = 3 mA
−
0.4
10
V
TDO Output Leakage
TONE CONTROL (TONECTRL)
Tone absent, 0 V < VTDO < 5 V
−
−
µA
VH
VL
2.0
–
–
–
–
–
0.8
1
V
V
Logic Input
Input Leakage
–1
μA
I2C™-COMPATIBLE INTERFACE
Logic Input (SDA,SCL) Low Level
Logic Input (SDA,SCL) High Level
Logic Input Hysteresis
VSCL(L)
VSCL(H)
VI2CIHYS
II2CI
–
2.0
–
–
–
0.8
–
V
V
150
<±1.0
–
–
mV
µA
V
Logic Input Current
VI2CI = 0 to 5 V
ILOAD = 3 mA
–1
–
1
Logic Output Voltage SDA and IRQ
VOUT(L)
0.4
Logic Output Leakage SDA and IRQ
SCL Clock Frequency
VLKG
fCLK
VOUT = 0 to 5 V
–
–
–
–
10
µA
400
kHz
I2C™ ADDRESS SETTING
ADD Voltage for Address 0001,000
ADD Voltage for Address 0001,001
ADD Voltage for Address 0001,010
ADD Voltage for Address 0001,011
Address1
Address2
Address3
Address4
0
–
–
–
–
0.7
1.7
2.7
5.0
V
V
V
V
1.3
2.3
3.3
[1] Operation at 16 V may be limited by power loss in the linear regulator.
[2] Indicates specifications guaranteed from 0 ≤ TJ ≤ 125°CMIN
[3] Guaranteed by worst case process simulations and system characterization. Not production tested.
.
[4] LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the Application Schematic and PCB layout
recommendations. Not production tested.
[5] Current from the LNB output may be limited by the choice of Boost components.
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
FUNCTIONAL DESCRIPTION
higher than its programmed voltage (e.g., 19 V on the output of a
13 V programmed voltage). The output with the highest voltage
will effectively turn off the other outputs. As soon as this voltage
is reduced below the value of the other outputs, the A8303 and
A8303-1 output will auto-recover to their programmed levels.
Protection
The A8303 and A8303-1 have a wide range of protection features
and fault diagnostics which are detailed in the Status Register
section.
Boost Converter/Linear Regulator
Charge Pump. Generates a supply voltage above the internal
tracking regulator output to drive the linear regulator control.
The A8303 and A8303-1 solution contains a tracking current-
mode boost converter and linear regulator. The boost converter
tracks the requested LNB voltage to within 800 mV, to minimize
power dissipation. Under conditions where the input voltage,
VBOOST, is greater than the output voltage, VLNB, the linear regu-
lator must drop the differential voltage. When operating in these
conditions, care must be taken to ensure that the safe operating
temperature range of the A8303 and A8303-1 is not exceeded.
LNB and BOOST Current Limits. The LNB output current
limit, IOUT(MAX) can be set by connecting a resistor (RSET) from
the ISET pin to GND as shown in the applications schematic. The
LNB current limit can be set from 300 to 800 mA, correspond-
ing to an RSET value of 100 to 37.4 kΩ, respectively. If the LNB
current limit is exceeded for more than the Overcurrent Disable
Time (tDIS) then the A8303 and A8303-1 will be shut down and
the OCP bit set, as shown in figure 1. The LNB output current
limit can be set as high as 950 mA (RSET = 31.6 kΩ) but care
should be taken not to exceed the thermal limit of the package or
thermal shutdown (TSD) will occur. The typical LNB output cur-
rent limit can be set according to the following equation:
The boost converter operates at 352 kHz typical: 16 times the
internal 22 kHz tone frequency. All the loop compensation,
current sensing, and slope compensation functions are provided
internally.
The A8303 and A8303-1 have internal pulse-by-pulse current
limiting on the boost converter and DC current limiting on the
LNB output to protect the IC against short circuits. When the
LNB output is shorted, the LNB output current is limited, and
if the overcurrent condition lasts for more than 45 ms, the LNB
output will be disabled. If this occurs, the A8303 and A8303-1
output must be reenabled for normal operation. The system
should provide sufficient time between successive restarts to limit
internal power dissipation; 1 to 2 seconds is recommended
IOUT(MAX) = 29,925 / RSET
,
where IOUT(MAX) is in mA and RSET is in kΩ. If the voltage at
the ISET pin is 0 V (that is, shorted to GND), IOUT(MAX) will
be clamped to a moderately high value (approximately 1.5 A).
Care should be taken to ensure that ISET is not inadvertently
grounded. If no resistor is connected to the ISET pin (that is, if
ISET is open-circuit), IOUT(MAX) will be set to approximately 0 A
and the A8303 and A8303-1 will not support any load (OCP will
occur prematurely).
At extremely light load or no load, if the BOOST voltage tries
to exceed the BOOST target voltage, the boost converter oper-
ates with minimum on time. BOOST settling voltage depends on
supply voltage, boost inductance, minimum on time, switching
frequency, output power and power loss in boost inductor, capaci-
tor and A8303 and A8303-1. If the BOOST voltage settles below
pulse skipping threshold (23.7 V), the boost converter continues
to operate with minimum on time. If BOOST voltage tries to
exceed 23.7 V, pulse skipping occurs, and pulse skipping stops
when the BOOST voltage drops to 23.4 V.
The BOOST pulse-by-pulse current limit, IBOOST(MAX), is auto-
matically scaled along with the LNB output current limit. The
typical BOOST current limit is set according to the following
equation:
IBOOST(MAX) = 4.7 × IOUT(MAX) + 270 mA ,
where both IBOOST(MAX) and IOUT(MAX) are in mA.
Automatically scaling the BOOST current limit allows the
designer to choose the lowest possible saturation current of the
boost inductor, reducing its physical size and PCB area, thus
minimizing cost.
In the case that two or more set top box LNB outputs are con-
nected together by the customer (e.g., with a splitter), it is pos-
sible that one output could be programmed at a higher voltage
than the other. This would cause a voltage on one output that is
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
ensures that the LNB output voltage is ramped from 18 to 13 V in a
reasonable amount of time. When the tone is on (TONECTRL = 1),
the output linear stage must increase its pull-down capability to
approximately 100 mA. This ensures that the tone signal meets all
specifications, even with no load on the on the LNB output.
Slew Rate Control. During either start-up, or when the output
voltage at the LNB pin is transitioning, the output voltage rise
and fall times can be set by the value of the capacitor connected
from the TCAP pin to GND (C12 in the Applications Schematic).
Note that during start-up, the BOOST pin is pre-charged to the
input voltage minus a diode voltage drop. As a result, the slew
rate control for the BOOST pin occurs from this voltage.
ODT (Overcurrent Disable Time)
If the LNB output current exceeds the set output current, for more
than 45 ms, then the LNB output will be disabled and the OCP bit
will be set. See figure 1.
The value of C12 can be calculated using the following formula:
C12 = (ITCAP × 6) / SR ,
where SR is the required slew rate of the LNB output voltage, in
V/s, and ITCAP is the TCAP pin current specified in the Electrical
Characteristics table. The recommended value for C12, 100 nF,
should provide satisfactory operation for most applications.
Short Circuit Handling
If the LNB output is shorted to ground, the LNB output current
will be clamped to IOUT(MAX). If the short circuit condition lasts
for more than 45 ms, the A8303 and A8303-1 will be disabled
and the OCP bit will be set.
The minimum value of C12 is 10 nF. There is no theoretical maxi-
mum value of C12 however too large a value will probably cause
the voltage transition specification to be exceeded. Tone genera-
Auto-Restart
tion is unaffected by the value of C12
.
After a short circuit condition occurs, the host controller should
periodically reenable the A8303 and A8303-1 to check if the
short circuit has been removed. Consecutive startup attempts
should allow 1 to 2 seconds of delay between restarts.
Pull-Down Rate Control. In applications that have to oper-
ate at very light loads and that require large load capacitances (in
the order of tens to hundreds of microfarads), the output linear
stage provides approximately 45 mA of pull-down capability. This
Figure 1. Startup, Reconfiguration, and Short Circuit operation using RSET = 37.4 kΩ, and
a capacitive load
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A8303 and
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In-Rush Current
At start-up or during an LNB reconfiguration event, a transient
surge current above the normal DC operating level can be pro-
vided by the A8303 and A8303-1. This current increase can be
as high as the set output current, for as long as required, up to a
maximum of 45 ms.
Tone Generation
TONECTRL
A 22 kHz tone is generated internally, and can be controlled on
and off via the TONECTRL pin as shown in figure 2. Note this
tone can be generated under no-load conditions, and does not
require the use of an external DiSEqC filter.
Tone
LNB (V)
(LNB Ref)
Figure 2. Internal tone, gated by TONECTRL pin
Tone Detection
A 22 kHz tone detector is provided in the A8303 and A8303-1.
The detector extracts the 22 kHz signal from the AC-coupled TDI
pin and provides it as an open-drain logic output at the TDO pin.
Also, when a tone is present, the TDET bit in the Status register
is set high and can be seen via the I2C interface. The tone detec-
tion delay is typically shorter than 1.5 cycles.
900
TONECTRL = 1
(Transmit)
TONECTRL = 0
(Receive)
400
250
The tone detector dynamically adjusts its amplitude and fre-
quency thresholds depending on whether the A8303 and A8303-1
are transmitting or receiving a tone signal. If TONECTRL is a
logic high, the A8303 and A8303-1 are transmitting and the tone
detect amplitude threshold is relatively high and the acceptable
frequency range is tight. This guarantees a high quality tone
signal is always generated by the A8303 and A8303-1. On the
other hand, if TONECTRL is a logic low, the A8303 and A8303-1
are receiving and the tone detect amplitude threshold is reduced
and the acceptable frequency range is increased slightly. This
guarantees the A8303 and A8303-1 have maximum sensitivity
to remotely generated tone signals that may be degraded by long
lengths of coaxial cable. The Electrical Characteristics table of
this datasheet documents the guaranteed specifications of the
tone detector and how they are adjusted by TONECTRL. To help
in the understanding, typical tone detector operation is shown
graphically in figures 3a and 3b. The shaded areas in figure 3a
indicate the accept range of the detector when TONECTRL is
a logic high (transmit) and a logic low (receive). The shaded
areas in figure 3b indicate the reject range of the detector when
TONECTRL is a logic high (transmit) and a logic low (receive).
17
20
24
27
Tone Frequency (kHz)
Figure 3a. Accept Ranges of Tone Detection feature
1100
TONECTRL = 0
(Receive)
TONECTRL = 1
(Transmit)
250
100
12 15
33 37
Tone Frequency (kHz)
Figure 3b. Reject Ranges of Tone Detection feature
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Single LNB Supply and Control Voltage Regulator
3250
3000
2750
2500
Component Selection
BOOST INDUCTOR
2250
Maximum
The A8303 and A8303-1 are designed to operate with a boost
inductor value of 15 µH +30%/–40% with a DCR less than
75 mΩ. The error amplifier loop compensation, current sense
gain, and PWM slope compensation were chosen for this value
of inductor. The boost inductor must be able to support the peak
currents required to maintain the maximum LNB output current
without saturating. Figure 4 can be used to determine the peak
current in the inductor given the LNB load current. The “typical”
curve uses VIN = 12 V, VOUT = 19 V, L = 15 µH, and f = 352 kHz,
while the “maximum” curve assumes VIN = 9 V, VOUT = 20 V,
L = 12 µH, and f = 282 kHz.
2000
1750
1500
1250
1000
750
Typical
500
100
200
300
400
500
(mA)
600
700
800
900
I
LNB
Figure 4. Boost inductor peak current versus ILNB
VIN , 20 VOUT, +2% DAC tolerance, 1V of ΔVREG, 1.1 A load,
and 320 kHz), these conditions could certainly occur in an appli-
cation. This plot shows that, as the boost inductance increases,
the 0 dB crossover frequency remains relatively constant but the
phase and gain margins are reduced. With 22 µH, the phase mar-
gin is 32° and with 33 µH the phase margin is only 10°.
The system will have reduced gain and phase margins, if the
boost inductor is higher than 22 µH. Figure 6 shows a Bode plot
of the boost loop with 3 × 10 µF of boost capacitance and 33,
22, 18, 15, and 10 µH of boost inductance. Although this plot
assumes many of the system variables are “worst case” (10.8
Figure 6. Gain and Phase Margin of the boost loop at various inductance levels
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capacitance becomes less than 7.5 µF, then the converter will
very likely be unstable.
BOOST CAPACITORS
The A8303 and A8303-1 are designed to operate with two or
three, high-quality ceramic capacitors on the boost node. Allegro
recommends capacitors that are rated at least 35 V, ±10%, X7R,
1210 size. Physically smaller capacitors, like 0603 and 0805,
with lower temperature ratings, like X5R and Z5U, should be
avoided. Figure 5 can be used to determine the necessary rms
current rating of the boost capacitor given the LNB load current.
The “typical” curve uses VIN = 12 V, VOUT = 19 V, L = 15 µH,
and f = 352 kHz while the “maximum” curve assumes VIN = 9 V,
VOUT = 20 V, L = 12 µH, and f = 282 kHz.
Figure 7 shows a Bode plot of the boost loop with 15 µH of boost
inductance and 20, 15, 10, 7.5, and 5 µF of boost capacitance.
Although this plot assumes many of the system variables are
“worst case” (10.8 VIN , 20 VOUT, +2% DAC tolerance, 1 V of
ΔVREG , 1.1 A load, and 320 kHz), these conditions could cer-
tainly occur in an application. This plot shows that, as the boost
capacitance decreases, the 0 dB crossover frequency increases
and the phase and gain margins are reduced. At 7.5 µF the phase
margin is only 6° and at 5 µF this system is unstable.
The nominal boost capacitance should total 18.8 to 30 µF.
Allegro recommends either four 4.7 µF or three 10 µF capacitors,
with the characteristics shown in table 1. If tolerance, tempera-
ture, and DC bias effects are considered, the capacitance must
total at least 13 µF. The DC bias effect is very significant on
ceramic capacitors with lower voltage ratings, smaller packages,
or wider temperature characteristics. For example, a 10 µF, 25 V,
1206, X5R capacitor can lose 85% of its value at 20 VDC bias. If
the total boost capacitance becomes less than 12 µF, the converter
will have reduced gain and phase margins. If the total boost
Two possible ceramic based capacitor solutions have been pre-
sented. Other capacitor combinations are certainly possible, such
as a very low ESR electrolytic capacitor in parallel with several
microfarads of ceramic capacitance. However, there are two
critical requirements that must be satisfied: 1) the zero formed by
the electrolytic capacitor and its ESR should be at least 1 decade
higher than the 0 dB crossover of the boost loop (typically around
25 kHz), and 2) the ceramic capacitors must eliminate the high
frequency switching spikes/edges in the boost voltage, or the
LNB output noise will be too high.
1100
1000
900
800
700
Maximum
600
500
400
300
200
Typical
100
200
300
400
500
(mA)
600
700
800
900
I
LNB
Figure 5. Boost capacitor rms current versus ILNB
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A8303 and
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Table 1. Recommended Boost Capacitor Characteristics
Temperature
Coefficient of
Capacitance
Total Capacitance at –10%
and 20 VDC Bias
(µF)
Quantity of
Capacitors
Value
(µF)
Tolerance
(%)
Rating
(V)
Size
1210
1210
4
3
4.7
10
±10
±10
50
35
X7R
X7R
14.0
18.6
Figure 7. Gain and Phase Margin of the boost loop at various capacitance values
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A8303 and
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To protect at these higher voltage/current levels three modifica-
tions must be made:
BOOST FILTERING AND LNB NOISE
The LNB output noise depends on the amount of high-frequency
noise at the BOOST pin. To minimize the high-frequency noise
at the BOOST pin, the ceramic capacitors should be placed as
close as possible to the BOOST pin.
• For increased positive surge, the shunting diode from the LNB
pin to the BOOST pin (D3, 3A/40 V) will no longer be able
to protect the body diode of the output stage. This diode must
be increased to a 3 A/50 V device and be located so that it is
in series with the BOOST pin as shown in schematics 3 and 4.
In this position D3 will block surge current to the majority of
the boost capacitance, but the 1 µF ceramic capacitor will still
filter the high frequency switching noise.
SURGE COMPONENTS
The circuit shown in schematic 1 includes external diodes for
surge protection. The Applications Information section includes
D2, D3, and D4 component recommendations in table 6. This
configuration and these components have successfully passed
surge tests up to ±1000 V/500 A, with a 1.2/50 µs − 8/20 µs
combination wave.
• For increased negative surge, the relatively small clamping
diode (D2) from LNB to ground will no longer be sufficient.
This diode must be increased from a 1 A/40 V, SOD123 to a
3 A/50 V, SMA device.
• For a DiSEqC 1.0 application, a 0.47 Ω/1%/0.25 W series
resistor also must be added as shown in the application
drawings. The 0.47 Ω resistor could be reduced if there is
enough equivalent resistance in any series output components
such as jumpers, inductors, or PCB traces.
Recently, set-top box suppliers have increased their surge speci-
fications to require “surge to failure of the TVS” or ±4000 V,
whichever occurs first. These increased surge voltages produce
significantly more current in the both the external circuitry and
the A8303 and A8303-1. Allegro surge testing has shown that
the SMDJ20A and LNBTVS6-221 usually fail at approximately
43 V, so all the LNBR output components (ceramic capacitors,
diodes, etc.) should support at least 50 V.
Every application will have its own surge requirements and
the surge solution can be changed. However, Allegro strongly
recommends incorporating a form of surge protection to prevent
any pin of the A8303 and A8303-1 from exceeding its Absolute
Maximum voltage ratings shown in this datasheet.
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A8303 and
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I2C™-Compatible Interface
ninth SCL pulse to signal “good transmission” to the slave. The
receiver (either the master or the slave) should set the AK bit high
(AK=1 or NAK) for the ninth SCL pulse if eight bits of data are
not received successfully.
The I2C™ interface is used to access the internal Control and
Status registers of the A8303 and A8303-1. This is a serial inter-
face that uses two lines, serial clock (SCL) and serial data (SDA),
connected to a positive supply voltage via a current source or a
pull-up resistor. Data is exchanged between a microcontroller
(master) and the A8303 and A8303-1 (slave). The master always
generates the SCL signal. Either the master or the slave can
generate the SDA signal. The SDA and SCL lines from the A8303
and A8303-1 are open-drain signals so multiple devices may be
connected to the I2C™ bus. When the bus is free, both the SDA
and the SCL lines are high.
AK Bit During a Write Sequence. When the master sends
control data (writes) to the A8303 and A8303-1 there are three
instances where AK bits are toggled by the A8303 and A8303-1.
First, the A8303 and A8303-1 use the AK bit to indicate reception
of a valid seven-bit chip address plus a read/write bit (R/W=0 for
write). Second, the A8303 and A8303-1 use the AK bit to indicate
reception of a valid eight-bit Control register address. Third, the
A8303 and A8303-1 use the AK bit to indicate reception of eight
bits of control data. This protocol is shown in figure 8(A).
SDA and SCL Signals. SDA can only be changed while
SCL is low. SDA must be stable while SCL is high. However,
an exception is made when the I2C™ Start or Stop condition is
encountered. See the I2C™ Communication section for further
details.
AK Bit During a Read Sequence. When the master reads
status data from the A8303 and A8303-1 there are four instances
where AK bits are sent–three sent by the A8303 and A8303-1
and one sent by the master. First, the A8303 and A8303-1 use
the AK bit to indicate reception of a valid seven-bit chip address
plus a read/write bit (R/W=0 for write). Second, the A8303 and
A8303-1 use the AK bit to indicate reception of a valid eight-bit
status register address. Third, the A8303 and A8303-1 use the AK
bit to indicate reception of a valid seven-bit chip address plus a
Acknowledge (AK) Bit. The Acknowledge (AK) bit indicates
a “good transmission” and can be used two ways. First, if the
slave has successfully received eight bits of either an address or
control data, it will pull the SDA line low (AK=0) for the ninth
SCL pulse to signal “good transmission” to the master. Second, if read/write bit (R/W=1 for read). Finally, the master uses the AK
the master has successfully received eight bits of status data from bit to indicate receiving eight bits of status data from the A8303
the A8303 and A8303-1, it will pull the SDA line low for the
and A8303-1. This protocol is shown in figure 8(B).
acknowledge
acknowledge
acknowledge
from LNBR (slave)
from LNBR (slave)
from LNBR (slave)
Start
Chip Address
W
0
Control Register Address
Control Data
Stop
SDA
SCL
A6 A5 A4 A3 A2 A1 A0
AK RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 AK
AK
9
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
(A) Write to Control Register
acknowledge
from LNBR (slave)
Status Data
acknowledge
from master
acknowledge
from LNBR (slave)
Status Register Address
acknowledge
from LNBR (slave)
Chip Address
A6 A5 A4 A3 A2 A1 A0
R
1
Start
Chip Address
A6 A5 A4 A3 A2 A1 A0
W
0
Stop
Start
Stop
AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
SDA
SCL
AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
(B) Read from Status Register
Figure 8. I2C™ Interface Read and Write Sequences. (A) for the I2C™ Write cycle and (B) for the I2C™ Read cycle
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A8303 and
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I2C™ Communications
an Acknowledge bit from the slave. The control data must
be transmitted MSB first (D7). The Control register bits are
identified in the Control Registers section of this datasheet.
I2C™ Start and Stop Conditions. The I2C™ Start condi-
tion is defined by a negative edge on the SDA line while SCL is
highConversely, the Stop condition is defined by a positive edge
on the SDA line while SCL is high. The Start and Stop conditions
are shown in figure 8. It is possible for the Start or Stop condition
to occur at any time during a data transfer. If either a Start or Stop
condition is encountered during a data transfer, the A8303 and
A8303-1 will respond by resetting the data transfer sequence.
I2C™ Read Cycle Description. Reading from the A8303
and A8303-1 Status register requires transmission of a total of 36
bits–four 8-bit bytes of data plus an Acknowledge bit after each
byte. Reading the A8303 and A8303-1 Status register requires
a chip address with R/W=0, a Status register address, an I2C™
Stop condition, an I2C™ Start condition, a “repeated” chip
address with R/W=1, and finally the status data from the A8303
and A8303-1. Reading from the A8303 and A8303-1 Status regis-
ter is shown in figure 8(B).
I2C™ Write Cycle Description. Writing to the A8303 and
A8303-1 Control register requires transmission of a total of
27 bits–three 8-bit bytes of data plus an Acknowledge bit after
each byte. Writing to the A8303 and A8303-1 Control register is
shown in figure 8(A). Writing to the A8303 and A8303-1 Control
register requires a chip address with R/W=0, a Control register
address, and the control data, as follows:
• This 9-bit Chip Address cycle is identical to the Chip Address
cycle previously described for the Write Control register
sequence. It consists of A6 to A0, plus one read/write bit
(R/W=0) from the master, followed by an Acknowledge bit
from the slave and finally an I2C™ Stop condition.
• The Chip Address cycle consists of a total of nine bits—
seven bits of chip address (A6 to A0) plus one read/write bit
(R/W=0) to indicate a write from the master followed by an
Acknowledge bit (AK=0 for reception of a valid chip address)
from the slave. The chip address must be transmitted MSB
(A6) first. The first five bits of the A8303 and A8303-1 chip
address (A6 to A2) are fixed as 00010. The remaining two
bits (A1 and A0) are used to select one of four possible A8303
and A8303-1 chip addresses. The DC voltage on the ADD pin
programs the chip address. See the Electrical Characteristics
table for the ADD pin voltages and the corresponding chip
addresses.
• The Status Register Address cycle consists of a total of nine
bits–eight bits of Status register address (RS7 to RS0) from
the master, followed by an Acknowledge bit from the slave.
The Status register address must be transmitted MSB (RS7)
first. The A8303 and A8303-1 only have one Status register, so
the Status register address is fixed at 00000000.
• The “Repeated” Chip Address cycle begins with an I2C™
Start condition followed by a 9-bit cycle identical to the Chip
Address cycle previously described for the Write Control
Register sequence. It consists of A6 to A0, plus one read/write
bit (R/W=1) from the master, followed by an Acknowledge
bit from the slave.
• The Control Register Address cycle consists of a total of nine
bits—eight bits of control register address (RC7 to RC0) from
the master followed by an Acknowledge bit from the slave.
The Control register address must be transmitted MSB (RC7)
first. The A8303 and A8303-1 only have one Control register
each, so the Control register address is fixed as 00000000.
• The Status Data cycle consists of a total of nine bits–eight
bits of status data (RD7 to RD0) from the slave, followed
by an Acknowledge bit from the master. The status data is
transmitted MSB (RD7) first. The Status register bits are
identified in the Status Register section of this data sheet.
• The Control Data cycle consists of a total of nine bits—eight
bits of control data (D7 to D0) from the master followed by
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A8303 and A8303-1 are disabled). After VIN rises above 8.70
Interrupt (IRQ) and Fault Clearing
V (typ) the I2C port reactivates and the IRQ pin is pulled low
to report that a brown-out had occurred. An I2C Read cycle is
required to report and clear the UVLO fault before the A8303
and A8303-1 can be re-enabled. A detailed timing diagram is
shown in figure 10(A).
The A8303 and A8303-1 provide an interrupt request pin (IRQ),
which is an open-drain, active low output. This output may be
connected to a common IRQ line with a suitable external pull-up
resistor and can be used with other I2C™ compatible devices to
request attention from the master controller.
• The second method uses I2C address setting (Address 1). In
this method the I2C port is active when VIN is above the I2C
UVLO (6 V when VIN is rising). IRQ transitions low when
VIN goes above I2C UVLO (6 V, VIN rising), and the I2C Read
cycle resets IRQ to logic high even if VIN is below UVLO.
Even though IRQ is cleared below UVLO, one more Read
cycle is required after VIN goes above UVLO, to re-enable the
A8303 and A8303-1. While VIN is falling, IRQ transitions low
when VIN goes below UVLO, and the I2C Read cycle resets
IRQ to logic high. A detailed timing diagram is shown in
figure 10(B).
The IRQ output becomes active (logic low) when the A8303 and
A8303-1 recognize a fault condition. The fault conditions that
will force IRQ active include undervoltage lockout (UVLO),
overcurrent protection (OCP), and thermal shutdown (TSD). The
UVLO, OCP, and TSD faults are latched in the Status register and
will not be unlatched until the A8303 and A8303-1 Status register
is successfully transmitted to the master controller (an AK bit
must be received from the master). See the description in the
Status Register section and figure 9 for further details.
The A8303 and A8303-1 IRQ response to VIN(UVLO) is controlled
by the I2C address setting. The A8303 and A8303-1 have two
methods to control the IRQ for UVLO fault:
When the master device receives an interrupt, it should address
all slaves connected to the interrupt line in sequence and read the
status register of each to determine which device is requesting
attention. As shown in figure 9, the A8303 and A8303-1 latch
all conditions in the Status register and set the IRQ to logic low
when a UVLO, OCP, or TSD event occurs. The IRQ bit is reset
to logic high and the Status register is unlatched when the master
acknowledges the status data from the A8303 and A8303-1 (an
AK bit must be received from the master).
• The first method uses the I2C address setting (Address 2,
Address 3, or Address 4). In this method while VIN is below
8.70 V (typ), the A8303 and A8303-1 are disabled and the
I2C port is inactive. After VIN rises above 8.70 V (typ), the
I2C port becomes active and the IRQ pin is pulled low. An
I2C Read cycle is required to report and clear the UVLO fault
and set the IRQ pin to a logic high before the A8303 and
A8303-1 can be enabled. If a brown-out occurs, such that
VIN drops below 8.35 V (typ), the A8303 and A8303-1 will
be disabled and the I2C port will become inactive (note that
the IRQ pin will remain high during this time because the
The disable (DIS) and Power Not Good (PNG) conditions do not
cause an interrupt and are not latched in the Status register.
acknowledge
from LNBR (slave)
acknowledge
from master
acknowledge
from LNBR (slave)
acknowledge
from LNBR (slave)
Chip Address
R
1
Status Data
Start
Chip Address
W
0
Status Register Address
Start
Stop
Stop
A6 A5 A4 A3 A2 A1 A0
AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
SDA
A6 A5 A4 A3 A2 A1 A0
AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SCL
IRQ
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
STATUS
register
FAULT event, IRQ set low, Status register latched
unlatched
IRQ reset
Figure 9. Fault, IRQ, and Status Register Timing. When a UVLO, OCP, or TSD event occurs, the IRQ bit is set low
and the Status register is latched. The IRQ bit is reset to high when the A8303 and A8303-1 acknowledges it is
being read. The Status register is unlatched when the master acknowledges the status data from the A8303 and
A8303-1.
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A8303 and
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UVLO
Thresholds
8.70 V
8.35 V
V
IN
Brown Out
LNB Output
2
I C Read Cycle
IRQ (active low)
ENABLE Bit
2
2
I C
I C
Inactive
Inactive
2
(via I C)
t
10(A). IRQ and Fault Clearing in Response to Undervoltage at VIN (UVLO), with I2C address set to (Address 2, Address 3, or Address 4).
In this method, while VIN is below 8.70 V (typ), the A8303 and A8303-1 are disabled and the I2C port is inactive. After VIN rises above 8.70
V (typ), the I2C port becomes active and the IRQ pin is pulled low. An I2C Read cycle is required, to report and clear the UVLO fault and set
the IRQ pin to a logic high, before the A8303 and A8303-1 can be enabled. If a brown-out occurs, such that VIN drops below 8.35 V (typ), the
A8303 and A8303-1 will be disabled and the I2C port will become inactive (note that the IRQ pin will remain high during this time because
the A8303 and A8303-1 are disabled). After VIN rises above 8.70 V (typ) the I2C port reactivates and the IRQ pin is pulled low to report that a
brown-out had occurred. An I2C Read cycle is required to report and clear the UVLO fault before the A8303 and A8303-1 can be re-enabled.
I2C UVLO (typ),
UVLO
rising: 6 V, falling: 4.2 V
Thresholds
V
IN
LNB Output
2
I C Read Cycle
2
2
I C
I C
Inactive
Inactive
IRQ (active low)
ENABLE Bit
2
(via I C)
t
10(B). IRQ and Fault Clearing in Response to Undervoltage at VIN (UVLO), with I2C address set to (Address 1). In this method, the I2C port
is active when VIN is above I2C UVLO (6 V when VIN is rising). IRQ transitions low when VIN goes above I2C UVLO (6 V, VIN rising), and the
I2C Read cycle resets IRQ to logic high even if VIN is below UVLO. Even though IRQ is cleared below UVLO, one more Read cycle is required
after VIN goes above UVLO, to re-enable the A8303 and A8303-1. While VIN is falling, IRQ transitions low when VIN goes below UVLO, and the
I2C Read cycle resets IRQ to logic high.
Figure 10. IRQ and Fault Clearing in Response to Undervoltage at VIN (UVLO), showing the alternate methods, set by selection of I2C address
18
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
45 ms
45 ms
I
SET
LNB I
OUT
LNB shorted to GND
LNB V
OUT
2
I C Read Cycle
IRQ (acꢀve low)
Enable
2
(ENB bit, via I C)
Figure 11. IRQ and Fault Clearing in Response to Overcurrent (OCP). If the LNB output is grounded for more than 45 ms, the LNB
output will be shut off, an overcurrent fault (OCP) will be latched in the Status Register, and the IRQ pin will transition low. After an
OCP fault, the LNB output does not respond to the Enable (ENB) bit until an I2C Read cycle is executed to report and clear the OCP
fault. After a successful I2C Read, the IRQ pin transitions high and the A8303 and A8303-1 can be re-enabled, provided the LNB
output is no longer grounded.
TSD
Threshold
165°C
145°C
TJ
Loss of cooling
or STB overload
LNB O/P
I2C Read Cycle
IRQ
(active low)
TSD Bit
(via I2C)
ENABLE Bit
(via I2C)
t
Figure 12. IRQ and Fault Clearing in Response to Thermal Shutdown (TSD). If the LNB junction temperature rises above 165°C
(typ), the LNB output will be shut off, a thermal shutdown fault (TSD) will be latched in the Status Register, and the IRQ pin will
transition low. After a TSD fault, the LNB output does not respond to the Enable (ENB) bit until an I2C Read cycle is executed to
report and clear the TSD fault. After a successful I2C Read, the IRQ pin transitions high and the A8303 and A8303-1 can be re-
enabled, provided the junction temperature is below 145°C (typ).
19
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
I2C™-Compatible Interface Timing Diagram
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
SDA
SCL
tLOW
tHIGH
I2C™-Compatible Timing Requirements
Characteristics
Symbol
Min.
1.3
0.6
0.6
1.3
0.6
100
0
Typ.
Max.
–
Unit
µs
µs
µs
µs
µs
ns
ns
µs
ns
Bus Free Time Between Stop/Start
Hold Time Start Condition
Setup Time for Start Condition
SCL Low Time
tBUF
–
–
–
–
–
–
–
–
–
tHD:STA
tSU:STA
tLOW
–
–
–
SCL High Time
tHIGH
–
Data Setup Time
tSU:DAT
tHD:DAT
tSU:STO
tfI2COut
–
Data Hold Time*
900
–
Setup Time for Stop Condition
0.6
–
Output Fall Time (VfI2COut(H) to VfI2COut(L)
)
250
*For tHD:DAT(min), the master device must provide a hold time of at least 300 ns for the SDA
signal in order to bridge the undefined region of the SCL signal falling edge.
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A8303 and
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Single LNB Supply and Control Voltage Regulator
Control Registers (I2C™-Compatible Write Register)
All main functions of the A8303 and A8303-1 are controlled
through the I2C™ compatible interface via the 8-bit Control
register. Table 2 shows the functionality and bit definitions of the
Control register. At power-up, the Control register is initialized
to all 0s.
Table 2. Control Register Definition
Bit
0
Name
VSEL0
VSEL1
Function
LNB output voltage control
Description
The available voltages provide levels for all the common
standards plus the ability to add line compensation.
VSEL0 is the LSB and VSEL2 is the MSB to the internal
DAC.
1
See Table 3a for A8303 output voltage selections
2
VSEL2
See Table 3b for A8303-1 output voltage selections
0: Disable LNB Output
3
ENB
Turns the LNB output on or off.
1: Enable LNB Output
4
5
6
7
–
–
–
–
Set to 0
Unused
Table 3a. A8303 Output Voltage Selection
Table 3b. A8303-1 Output Voltage Selection
VSEL2
VSEL1
VSEL0
LNB (V)
13.333
13.667
14.333
15.667
18.667
19.000
19.667
20.000
VSEL2
VSEL1
VSEL0
LNB (V)
11.667
13.333
13.667
14.333
15.667
18.667
19.000
19.667
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
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A8303 and
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Single LNB Supply and Control Voltage Regulator
Status Registers (I2C™-Compatible Read Register)
reset when there are no faults and the A8303 and A8303-1 output is
turned back on using the Enable (ENB) bit via the I2C™ interface.
The main fault conditions: overcurrent (OCP), and thermal
shutdown (TSD) are all indicated by setting the relevant bits in
the Status register. For these two fault cases, after the bit is set, it
remains latched until the I2C™ master has successfully read the
A8303 and A8303-1, assuming the fault has been resolved.
The Power Not Good (PNG), Charge Pump OK (CPOK), and
Tone Detect (TDET) bits are set based on the conditions sensed at
the LNB output, VCP, and Tone Detect Input (TDI) pins, respec-
tively. These bits are not latched and, unlike the other fault bits,
may become reset without an I2C™ read sequence. The PNG,
CPOK, and TDET bits are continuously updated.
The undervoltage lockout (UVLO) bit indicates either VIN is below
VUVLO , or VREG is out of regulation. UVLO disables the LNB
output and forces IRQ low. UVLO is a latched fault, and can only
be cleared by performing an I2C™ READ cycle.
There are three methods to detect when the Status register
changes: responding to the interrupt request (IRQ) pin going low,
continuously polling the Status register via the I2C™ interface,
or detecting a fault condition external to the A8303 and A8303-1
and performing a diagnostic poll of the A8303 and A8303-1. In
any case, the master should read and re-read the Status register
until the status changes.
The Disable bit (DIS) indicates the status of the LNB output.
The DIS is set when either a fault occurs (UVLO, OCP, TSD, or
CPOK) or when the LNB output is turned off using the Enable bit
(ENB) via the I2C™ interface. The DIS bit is latched and is only
Table 4. Status Register Description and IRQ Operation
Bit
0
Name
DIS
Function
LNB output disabled
Charge pump OK
Overcurrent
Latched?
Yes
Reset Condition
LNB enabled and no faults
VCP > VBOOST + 5V
Effect on IRQ Pin
None
1
CPOK
OCP
No
None
2
Yes
I2C™ READ and ILOAD < ISET
None
IRQ set low
None
3
TRIMS
PNG
Trim bits locked
Yes
4
Power Not Good
Tone detect
No
LNB voltage within range
Tone removed from LNB pin
I2C™ READ and TJ < 145°C
I2C™ READ and VIN > 9.0 V
None
5
TDET
TSD
No
None
6
Thermal shutdown
VIN or VREG undervoltage
Yes
IRQ set low
IRQ set low
7
UVLO
Yes
Table 5. Status Register Bit Descriptions
Bit
0
Name
DIS
Description
The DIS bit is set to 1 when the A8303 and A8303-1 are disabled, (ENB = 0) or there is a fault: UVLO, OCP, CPOK, or TSD.
1
CPOK
If this bit is set low, the internal charge pump is not operating correctly (VCP). If the charge pump voltage is too low, the LNB
output is disabled and the DIS bit is set.
2
OCP
This bit will be set to a 1 if the LNB output current exceeds the overcurrent threshold (IOUT(MAX)) for more than the overcurrent
disable time (tDIS). If the OCP bit is set to 1, then the DIS bit is also set to 1.
3
4
TRIMS
PNG
Factory use only.
Set to 1 when the A8303 and A8303-1 are enabled and the LNB output voltage is either too low or too high (nominally ±9%
from the LNB DAC setting). Set to 0 when the A8303 and A8303-1 are enabled and the LNB voltage is within the acceptable
range (nominally ±5% from the LNB DAC setting).
5
TDET
The TDET bit is set to 1 if a tone is detected at the TDI pin that is within the specified voltage and frequency ranges. If
TONECTRL = 1, the tone is being transmitted by the A8303 and A8303-1 and the tone detect low threshold is determined
by VTD(XMT)L. If TONECTRL I = 0, it is assumed the tone is being received from an external source and the tone detect low
threshold is determined by VTD(RCV)L
.
6
7
TSD
The TSD bit is set to 1 if the A8303 and A8303-1 have detected an overtemperature condition. If the TSD bit is set to 1, then
the DIS bit is also set to 1.
UVLO
The UVLO bit is set to 1 if either the voltage at the VIN pin or the voltage at the VREG pin is too low. If the UVLO bit is set to
1, then the DIS bit is also set to 1.
22
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
APPLICATION INFORMATION
D1
3A/40V
D3
1A/40V
L1
15uH
VIN
C2
C5 to C7
2X4.7uF
or
1X10uF
4X4.7uF
or
3X10uF
C1
100nF
C4
100nF
15
14
VIN
GND
1
VCP
C3
220nF
13
C11
10nF
R5
100
VREG
4
2
U1
TDI
L2
220uH
GND C12
A8303
A8303-1
100nF
11
3.3V 3.3V
LNB
LNBout
TCAP
D2
1A/40V
C8
100nF
C10
220nF
C9
10nF
D4
32V/500A
3000W
R1
2K
R2
2K
GND
10
8
TONECTRL
SDA
TONECTRL
SDA
GND
R3
15
RSET
37.4K
7
R4
2.0
SCL
SCL
12
ISET
6
IRQ
IRQ
3
18
19
NC
NC
NC
GND
R8
10K
Q1
> 40V
< 0.5ohm
5
TDO
TDO
9
0
ADD
PAD
R9
10K
R6
10K
GND
Q2
> 40V
100mA
TONE XMIT
R7
10K
GND
GND
See next page for bill of materials
,
Schematic 1. DiSEqC 2.0 Applications, 12 VIN ±10%, 700 mA IOUT
surge of ±1000 V, 2 Ω, 1.2/50 μs – 8/20 μs combination wave
23
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
Table 6. Component Selection Table
Component
Characteristics
Recommended Devices
C1, C4, C8, C12 100 nF, 50 V, X5R or X7R, 0603
C2
C3
2X: 4.7 µF or 1X 10 µF, 25 V, X5R or X7R, 1206
220 nF, 10 V (min.) , X5R or X7R, 0603
4.7 µF: Murata: GRM32ER71H475KA88
Taiyo Yuden: UMK325B7475KM
AVX: 12105C475KAT2A
4X: 4.7 µF, ±10%, 50 V, X7R, 1210
or
3X: 10 µF, ±10%, 35 V, X7R, 1210
C5, C6, C7
10 µF: Murata: GRM32ER7YA106K
C9, C11
C10
10 nF, 50 V, X5R or X7R, 0603
220 nF, 50 V, X5R or X7R, 0603
Sanken: SFPB-74
Vishay: B340A-E3/5AT
Diodes, Inc.: B340A-13-F
Central Semiconductor: CMSH3-40MA
D1
Schottky diode, 3 A, 40 V, SMA
Diodes, Inc.: B140HW-7
Central Semiconductor: CMMSH1-40
D2, D3
D4
Schottky diode, 1 A, 40 V, SOD-123
Littelfuse: SMDJ20A
ST: LNBTVS6-221S
TVS, 20 VRM, 32 VCL at 500 A, 3000 W
Cooper Bussmann: DR1040-150-R
TDK: VLF10045T-150M3R5
L1
15 µH, ±20%, ISAT ≥ 3.1 A, DCR < 75 mΩ
Sumida: CDRH10D43FBNP-150M
Cooper Bussmann: DR1040-221-R
TDK: VLF10045T-221MR90
L2
220 µH, ±20%, ISAT ≥ 800 mA, DCR < 0.8 Ω
Vishay: SI2309DS-T1-E3
Diodes, Inc.: ZXMP6A13FTA
Q1
MOSFET, P-channel, 50 V, < 0.5 Ω, SOT-23
Diodes, Inc.: BC846AW-7-F
NXP: BC846W
Q2
Transistor, NPN, 50 V, 100 mA, SOT-323
ON Semiconductor: BC846AWT1G
R1, R2
R3
Resistor, 2 kΩ, 1%, 0402 or 0603
Resistor, 15 Ω, 1%, 0402 or 0603
Resistor, 2.0 Ω, 1%, 0402 or 0603
Resistor, 100 Ω, 1%, 0402 or 0603
R4
R5
R6, R7, R8, R9 Resistor, 10 kΩ, 1%, 0402 or 0603
RSET Resistor, 37.4 kΩ, 1%, 0402 or 0603
24
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
D1
3A/40V
D3
3A/40V
L1
15uH
VIN
C2
C5 to C7
2X4.7uF
or
1X10uF
4X4.7uF
or
3X10uF
C1
100nF
C4
100nF
15
14
VIN
GND
1
VCP
C3
220nF
13
C11
10nF
R5
100
U1
VREG
4
2
TDI
A8303
A8303-1
GND C12
100nF
11
3.3V 3.3V
LNB
LNBout
TCAP
D2
1A/40V
C8 C10
100nF 220nF
C9
10nF
D4
32V/500A
3000W
R1
2K
R2
2K
GND
10
8
TONECTRL
SDA
TONECTRL
SDA
GND
RSET
37.4K
7
SCL
SCL
12
ISET
6
IRQ
IRQ
3
18
19
NC
NC
NC
GND
5
TDO
TDO
9
0
ADD
PAD
GND
Schematic 2. DiSEqC 1.0 Applications, 12 VIN ±10%, 700 mA IOUT
,
surge of ±1000 V, 2 Ω, 1.2/50 μs – 8/20 μs combination wave
25
Allegro MicroSystems, LLC
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
D1
3A/50V
D3
3A/50V
C13
1uF
L1
15uH
VIN
C2
C5 to C7
2X4.7uF
or
1X10uF
4X4.7uF
or
3X10uF
C1
100nF
C4
100nF
15
14
VIN
GND
1
VCP
C3
220nF
13
C11
10nF
R5
100
VREG
4
2
TDI
U1
L2
220uH
GND C12
A8303
A8303-1
100nF
11
3.3V 3.3V
LNB
LNBout
TCAP
D2
3A/50V
C8
100nF
C10
220nF
C9
10nF
D4
32V/500A
3000W
R1
2K
R2
2K
GND
10
8
TONECTRL
SDA
TONECTRL
SDA
GND
RSET
37.4K
R3
15
7
R4
2.0
SCL
SCL
12
ISET
6
IRQ
IRQ
3
18
19
NC
NC
NC
GND
R8
10K
Q1
50V
< 0.5ohm
5
TDO
TDO
9
0
ADD
PAD
R9
10K
R6
10K
GND
Q2
50V
100mA
TONE XMIT
R7
10K
GND
GND
Schematic 3. DiSEqC 2.0 Applications for increased surge requirements ±1000 V, 2 Ω,
1.2/50 µs – 8/20 µs combination wave, and “stress to TVS failure” (or ±4000 V) test
26
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
D1
3A/50V
D3
3A/50V
C13
1uF
L1
10uH
VIN
C2
2X4.7uF
or
1X10uF
C5 to C7
3X4.7uF
or
2X10uF
C1
100nF
C4
100nF
15
14
VIN
GND
1
VCP
C3
220nF
13
C11
10nF
R5
100
4
VREG
TDI
U1
R10
0.47, 1/4W
GND C12
A8303
A8303-1
100nF
11
2
3.3V 3.3V
LNB
LNBout
TCAP
D2
3A/50V
C8
C10
C9
D4
32V/500A
3000W
R1
2K
R2
2K
100nF
220nF 10nF
GND
10
8
TONECNTL
SDA
TONECTRL
SDA
GND
Rset
37.4K
7
SCL
SCL
12
3
ISET
NC
6
IRQ
IRQ
GND
5
NC 18
NC
TDO
TDO
19
9
ADD
0
PAD
GND
Schematic 4. DiSEqC 1.0 Applications for increased surge requirements ±1000 V, 2 Ω,
1.2/50 µs – 8/20 µs combination wave, and “stress to TVS failure” (or ±4000 V) test
27
Allegro MicroSystems, LLC
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
PACKAGE OUTLINE DRAWING
0.30
4.00 ±0.10
0.50
20
20
0.95
1
2
A
1
2
4.00 ±0.10
2.45
4.10
2.45
4.10
D
C
21X
C
PCB Layout Reference View
SEATING
PLANE
0.08
C
+0.05
–0.07
0.25
0.75 ±0.05
For Reference Only
(reference JEDEC MO-220WGGD)
Dimensions in millimeters
0.50
Exact case and lead configuration at supplier discretion within limits shown
A
B
Terminal #1 mark area
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C
Reference land pattern layout (reference IPC7351
0.40 ±0.10
QFN50P400X400X80-21BM)
B
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
2.45
2
1
D
Coplanarity includes exposed thermal pad and terminals
20
2.45
Package ES 20-Pin MLP/QFN
28
Allegro MicroSystems, LLC
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A8303 and
A8303-1
Single LNB Supply and Control Voltage Regulator
Revision History
Number
Date
Description
Corrected Terminal List Table (page 3)
Updated Component Selection Table (page 22)
Minor editorial updates
5
6
7
8
9
January 11, 2016
July 22, 2016
January 11, 2018
January 22, 2019
February 8, 2019
Minor editorial updates
Product status changed to Pre-End-of-Life
I2C™ is a trademark of Philips Semiconductors.
DiSEqC™ is a trademark of Eutelsat S.A.
Copyright ©2011-2019, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
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www.allegromicro.com
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