AMT49702 [ALLEGRO]
Dual DMOS Full-Bridge Motor Driver;
| 型号： | AMT49702 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Dual DMOS Full-Bridge Motor Driver |
| 文件： | 总10页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMT49702
Dual DMOS Full-Bridge Motor Driver
FEATURES AND BENEFITS
DESCRIPTION
Designed for pulse-width-modulated (PWM) control of low-
voltage stepper motors and single and dual DC motors, the
AMT49702 is capable of output currents up to 1Aper channel
and operating voltages from 3.5 to 15 V.
• AEC-Q100 Grade 1 qualified
• Wide, 3.5 to 15 V input voltage operating range
• Dual DMOS full-bridges: drive two DC motors or
one stepper motor
• Low RDS(ON) outputs
• Synchronous rectification for reduced power dissipation
• Low-current sleep mode
The AMT49702 is an automotive-grade device and is tested
across extended temperature and voltage ranges to ensure
compliance in automotive or industrial applications.
• Overcurrent protection
TheAMT49702 has an internal fixed off-time PWM timer that
sets a peak current based on the selection of a current sense
resistor. An output fault flag is provided that notifies the user
of a TSD or overcurrent protection event.
• Internal UVLO and thermal shutdown circuitry
• Integrated charge pump
PACKAGE:
The AMT49702 is supplied in a low-profile 16-lead TSSOP
(suffix “LP”) with exposed power tab for enhanced thermal
dissipation.
16-lead TSSOP
(suffix LP)
Not to scale
VCP
VCP
0.1 µF
0.1 µF
3.5 to 15 V
3.5 to 15 V
VBB
VBB
SLEEPn
SLEEPn
AMT49702
AMT49702
IN1
IN1
IN2
IN2
OUT1A
OUT1A
IN3
IN3
OUT1B
OUT1B
IN4
IN4
DC
Motor
Step
Motor
SENSE1
FAULTn
FAULTn
SENSE1
OUT2A
OUT2B
OUT2A
OUT2B
DC
Motor
GND
SENSE2
SENSE2
GND
Figure 1: Typical Applications
AMT49702-DS, Rev. 2
MCO-0000239
September 12, 2018
AMT49702
Dual DMOS Full-Bridge Motor Driver
SPECIFICATIONS
SELECTION GUIDE
Part Number
Packaging
Packing
AMT49702KLPATR
16-lead TSSOP package
4000 pieces per 13-inch reel
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
VBB
Notes
Rating
15
Unit
V
Supply Voltage
Output Current
IOUT
Continuous
1.0
A
Output Current (parallel mode)
IOUT(PAR)
Continuous
1.8
A
Continuous
0.5
V
Sense Voltage
VSENSEx
Pulsed, tw < 1 µs
2.5
V
Logic Input Voltage Range
Junction Temperature
VIO
TJ(MAX)
Tstg
–0.3 to 5.5
150
V
°C
°C
°C
Storage Temperature Range
Operating Temperature Range
–55 to 150
–40 to 125
TA
Range K
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions*
Value
Unit
°C/W
LP package, 16-lead TSSOP
RθJA
4-layer PCB based on JEDEC standard
34
*Additional thermal information available on the Allegro website.
2
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
PINOUT DIAGRAM AND TERMINAL LIST TABLE
16
15
14
13
12
11
10
9
OUT2A
SENSE2
OUT2B
VBB
FAULTn
IN4
1
2
3
4
5
6
7
8
IN3
IN2
PAD
OUT1B
NC
IN1
SLEEPn
GND
VCP
SENSE1
OUT1A
16-Lead TSSOP (LP) Package
Terminal List Table
Number
Name
Function
LP
10
11
12
13
14
15
16
1
GND
SLEEPn
IN1
Ground
Active-Low Sleep Input
Control Input
IN2
Control Input
IN3
Control Input
IN4
Control Input
FAULTn
OUT2A
SENSE2
OUT2B
VBB
Open-Drain Logic Output
DMOS H-Bridge 2, Output A
Sense Resistor Terminal, Bridge 2
DMOS H-Bridge 2, Output B
Motor Supply Voltage
2
3
4
5
OUT1B
SENSE1
OUT1A
VCP
DMOS H-Bridge 1, Output B
Sense Resistor Terminal, Bridge 1
DMOS H-Bridge 1, Output A
Charge Pump Capacitor
No Internal Connection
Exposed Pad for Enhanced Thermal Performance
7
8
9
6
NC
–
PAD
3
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
FUNCTIONAL BLOCK DIAGRAM
TSD
VCP
VBB
CHARGE PUMP
VREG
VBB
0.1 µF
3.5 to 15 V
VBB
UVLO
DMOS H BRIDGE
SLEEPn
Control
Logic
IN1
IN2
IN3
IN4
OUT1A
OUT1B
DC
Motor
SENSE1
VBB
DMOS H BRIDGE
FAULTn
OUT2A
OUT2B
DC
Motor
GND
SENSE2
4
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
ELECTRICAL CHARACTERISTICS[1][2]: Valid at TJ = –40°C to 125°C, VBB = 3.5 to 15 V, unless noted otherwise
Characteristics
GENERAL
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Load Supply Voltage Range
Output On Resistance
Diode Forward Voltage
VBB Supply Current
VBB
Operating
3.5
–
–
335
550
375
575
0.85
2.2
3.1
–
15
450
690
525
750
1.0
4.5
4.5
0.5
10
V
TJ = 25°C, 500 mA
mΩ
mΩ
mΩ
mΩ
V
RDS(ON,HS)
TJ = 125°C, 500 mA
TJ = 25°C, 500 mA
–
–
RDS(ON,LS)
TJ = 125°C, 500 mA
I = 500 mA
–
VF
–
IBB(2p7V)
IBB(15V)
Outputs disabled, VBB = 3.5 V
Outputs disabled, VBB = 15 V
Sleep Mode; TJ = 25°C
Sleep Mode; TJ = 125°C
–
mA
mA
µA
µA
–
–
IBB(SLEEP)
–
–
CONTROL LOGIC
VIN(1)
VIN(0)
VHYS
VIN(1)
VIN(0)
VHYS
IIN
2.0
–
–
–
–
V
V
Logic Input Voltage, INx
Logic Input Hysteresis, INx
Logic Input Voltage, SLEEPn
0.8
500
–
100
2.0
–
–
mV
V
–
–
0.4
–
V
Logic Input Hysteresis, SLEEPn
Logic Input Current
100
–
–
mV
µA
mV
µA
µs
µs
mV
µs
VIN = 3.3 V, pulldown = 100 kΩ
Flag asserted, IFAULTn = 1 mA
VFAULTn = 5 V
33
–
50
Fault Output Voltage
VFAULTn
IFAULTn
–
200
1.0
4.1
4.5
240
40
Fault Output Leakage Current
–
–
TJ = 25°C to 125°C
TJ = –40°C
2.1
1.5
170
20
3.1
3.1
205
30
VSENSE Blank Time
tBLANK
V
SENSE Trip Voltage
VTRIP
tOFF
Fixed Off-Time
PROTECTION CIRCUITS
Crossover Delay
tOCD
VBB(UVLO)
VBB(UVLO,HYS)
TJ1
200
–
550
2.55
125
165
20
1000
2.65
–
ns
V
VBB Undervoltage Lockout
VBB Hysteresis
VBB rising
–
V
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
150
–
180
–
°C
°C
ΔTJ1
[1] Typical data is for design information only.
[2] Specified limits are tested at a single temperature and assured over operating temperature range by design and characterization.
5
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
CONTROL LOGIC
Table 1: DC Motor Operation
IN1
0
IN2
0
OUT1A
Off
OUT1B
Off
Function
Disabled
Forward
Reverse
Brake
1
0
High
Low
Low
0
1
High
Low
1
1
Low
IN3
0
IN4
0
OUT2A
Off
OUT2B
Off
Function
Disabled
Forward
Reverse
Brake
1
0
High
Low
Low
0
1
High
Low
1
1
Low
Table 2: Stepper Motor Operation
IN1
0
IN2
0
IN3
0
IN4
0
OUT1A
Off
OUT1B
Off
OUT2A
Off
OUT2B
Off
Function
Disabled
Disabled
½ Step 1
½ Step 2
½ Step 3
½ Step 4
½ Step 5
½ Step 6
½ Step 7
½ Step 8
1
0
1
0
High
Off
Low
Off
High
High
High
Off
Low
Low
Low
Off
Full Step 1
0
0
1
0
–
0
1
1
0
Low
Low
Low
Off
High
High
High
Off
Full Step 2
0
1
0
0
–
0
1
0
1
Low
Low
Low
Off
High
High
High
Off
Full Step 3
0
0
0
1
–
Full Step 4
–
1
0
0
1
High
High
Low
Low
1
0
0
0
6
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
FUNCTIONAL DESCRIPTION
Device Operation
Enable
The AMT49702 is a dual full-bridge motor driver capable of
operating one stepper motor, two DC motors, or one high-current
DC motor. MOSFET output stages substantially reduce the volt-
age drop and the power dissipation of the AMT49702 outputs,
compared to typical drivers with bipolar transistors.
When all logic inputs are pulled to logic low, the outputs of the
bridges are disabled. The charge pump and internal circuitry
continue to run when the outputs are disabled.
Thermal Shutdown
The AMT49702 will disable the outputs if the junction tempera-
ture reaches 165°C. When the junction temperature drops 20°C,
the outputs will be enabled.
Output current can be regulated by pulse-width modulating
(PWM) the inputs. In addition to supporting external PWM of
the driver, the AMT49702 limits the peak current by internally
PWMing the source driver when the current in the winding
exceeds the peak current, as determined by a sense resistor. If
internal current limiting is not needed, the sense pin should be
shorted to ground.
Brake Mode
When driving DC motors, the AMT49702 goes into brake mode
(turns on both sink drivers) when both of its inputs are high (IN1
and IN2, or IN3 and IN4). There is no current limiting during
braking, so care must be taken to ensure that the peak current dur-
ing braking does not exceed the absolute maximum current.
Internal circuit protection includes thermal shutdown with hys-
teresis, undervoltage lockout, internal clamp diodes, crossover
current protection, and overcurrent protection.
Internal PWM Current Control
External PWM
Each full-bridge is controlled by a fixed off-time PWM current
Output current regulation can be achieved by pulse-width modu-
lating the inputs. Slow decay mode is selected by holding one
input high while PWMing the other input. Holding one input low
and PWMing the other input results in fast decay.
control circuit that limits the load current to a desired value, ITRIP
.
Initially, a diagonal pair of source and sink DMOS outputs are
enabled and current flows through the motor winding and the
current sense resistor, RSENSEx. When the voltage across RSENSEx
equals the internal reference voltage, the current sense compara-
tor resets the PWM latch, which turns off the source driver.
Blanking
This function blanks the output of the current sense comparator
when the outputs are switched. The comparator output is blanked
to prevent false overcurrent detections due to reverse recovery
currents of the clamp diodes or to switching transients related to
the capacitance of the load. The blank time, tBLANK, is approxi-
mately 3 μs.
The maximum value of current limiting, ITRIP(max), is set by the
selection of the sense resistor, RSENSEx, and is approximated by a
transconductance function:
ITRIP(max) = 0.2 ÷ RSENSEx
It is critical to ensure the maximum rating on SENSEx pins
(0.5 V) is not exceeded.
Sleep Mode
Synchronous Rectification
An active-low control input used to minimize power consump-
tion when the AMT49702 is not in use. This disables much of the
internal circuitry including the output drivers, internal regulator,
and charge pump. A logic high allows normal operation. When
When a PWM off-cycle is triggered by an internal fixed off-time
cycle, load current recirculates in slow decay SR mode. During
slow decay, current recirculates through the sink-side FET and
coming out of sleep mode, wait 1.5 ms before issuing a command the sink-side body diode. The SR feature enables the sink-side
to allow the internal regulator and charge pump to stabilize.
FET, effectively shorting out the body diode. The sink driver is
7
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
not enabled until the source driver is turned off and the cross-
over delay has expired. This feature helps lower the voltage drop
during current recirculation, lowering power dissipation in the
bridge.
OCP
If an overcurrent event occurs, both motor bridges are disabled
until either SLEEPn is brought low or the VBB supply is cycled.
FAULTn
This is an open-drain output that is pulled low during a TSD
or overcurrent event. The output is released when the die tem-
perature falls below the TSD level minus the hysteresis. For an
over-current event, the output is held low until either SLEEPn is
brought low or the VBB supply is cycled.
Parallel Operation
The AMT49702 can be paralleled for applications that require
higher output currents. In paralleled mode, the driver can source
1.8 A continuous. The AMT49702 has two completely indepen-
dent bridges with separate overcurrent latches. This allows the
device to supply two separate loads, and as a result, when paral-
leled, it is imperative that the internal current control is disabled
by shorting the sense pins to ground.
Because the overcurrent trip threshold is internally fixed at 0.2 V,
the trace resistance must be kept small so the internal current
latch is not triggered prematurely. With acceptable margin, the
voltage drop across the trace resistance should be under 0.1 V. At
a peak current of 2.5 A, the trace resistance should be kept below
40 mΩ to prevent false tripping of the overcurrent latch.
Each bridge has some variation in propagation delay. During this
time, it is possible that one bridge will have to support the full
load current for a very short period of time. Propagation delays
are characterized and guard banded to protect the driver from
damage during these events.
8
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
PACKAGE OUTLINE DRAWING
For Reference Only – Not for Tooling Use
(Reference MO-153 ABT)
Dimensions in millimeters. NOT TO SCALE
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
0.45
0.65
8º
0º
16
5.00 0.10
16
1.70
0.20
0.09
B
3.00
4.40 0.10
6.10
3 NOM
6.40 0.20
A
0.60 0.15
1.00 REF
1
2
3 NOM
1
2
0.25 BSC
Branded Face
SEATING PLANE
GAUGE PLANE
3.00
C
16X
SEATING
PLANE
0.10
C
C
PCB Layout Reference View
0.30
0.19
1.20 MAX
0.65 BSC
NNNNNNN
YYWW
LLLL
0.15
0.00
A
B
C
Terminal #1 mark area
Exposed thermal pad (bottom surface); dimensions may vary with device
1
D
Standard Branding Reference View
Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
N = Device part number
= Supplier emblem
Y = Last two digits of year of manufacture
W = Week of manufacture
L
= Characters 5-8 of lot number
D
Branding scale and appearance at supplier discretion
Figure 2: 16-lead TSSOP package (Suffix LP)
9
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
AMT49702
Dual DMOS Full-Bridge Motor Driver
Revision History
Number
Date
Description
–
1
2
July 17, 2017
August 30, 2017
Initial release
Corrected selection guide (p. 2)
September 12, 2018 Minor editorial updates
Copyright ©2018, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
10
Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
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