APS12450LUAA-1SLA [ALLEGRO]
Three-Wire Hall-Effect Latch with Advanced Diagnostics;型号: | APS12450LUAA-1SLA |
厂家: | ALLEGRO MICROSYSTEMS |
描述: | Three-Wire Hall-Effect Latch with Advanced Diagnostics |
文件: | 总23页 (文件大小:1158K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
APS12450
2
-
Three-Wire Hall-Effect Latch with Advanced Diagnostics
FEATURES AND BENEFITS
• Functional safety
DESCRIPTION
The APS12450 three-wire planar Hall-effect sensor integrated
circuits(ICs)weredevelopedinaccordancewithISO26262:2011
as a hardware safety element out of context with ASIL B
capability (pending assessment) for use in automotive safety-
related systems when integrated and used in the manner
prescribed in the applicable safety manual and datasheet. The
enhanced three-wire interface provides interconnect open/
short diagnostics and a fault state to communicate diagnostic
information while maintaining compatibility with legacy
three-wire systems. The continuous background diagnostics
are transparent to the host system and results in a reduced
fault tolerant time.
□ Developed in accordance with ISO 26262:2011 to meet
ASIL B requirements (pending assessment)
□ Integrated background diagnostics for:
○ Signal path
○ Regulator
○ Hall plate and bias
○ Overtemperature detection
○ Nonvolatile memory
□ Defined fault state
• Multiple product options
□ Magnetic polarity, switchpoints, and hysteresis
□ Temperature coefficient
□ Output polarity
TheAPS12450productoptionsincludemagneticswitchpoints,
temperature coefficient, and output polarity. The response can
be matched to SmCo, NdFeB, or low-cost ferrite magnets. For
situations where a functionally equivalent three-wire switch
device is preferred, refer to the APS11450.
• Reduces module bill-of-materials (BOM) and assembly cost
□ ASIL B sensor can replace redundant sensors
□ Integrated overvoltage clamp and reverse-battery diode
Continued on the next page…
Continued on the next page…
PACKAGES
TYPICAL APPLICATIONS
• Automotive and industrial safety systems
• Seat/window motors
3-pin SOT23-W (LH)
3-pin ultramini SIP (UA)
• Sun roof/convertible top/tailgate/liftgate actuation
• Brake and clutch by wire actuators
• Engine management actuators
• Electric power steering (EPS)
• Transmission shift actuator
Not to scale
VCC
REGULATOR
To All Subcircuits
Schmitt Output
Low-Pass
Filter
VOUT
(Internal)
O
UTPUT
CONTROL
S
AMPLE, HOLD
&
H
AMALPL
.
SYSTEM DIAGNOSTICS
A
VERAGING
CLOCK LOGIC
GND
Functional Block Diagram
APS12450-DS, Rev. 1
MCO-0000562
April 23, 2019
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
FEATURES AND BENEFITS (continued)
• Automotive-grade ruggedness and fault tolerance
□ Extended AEC-Q100 Grade 0 qualification
○ Operation to 175°C junction temperature
□ 3 to 30 V operating voltage range
DESCRIPTION (continued)
APS12450 sensors are engineered to operate in the harshest
environmentswithminimalexternalcomponents.Theyarequalified
beyond the requirements of AEC-Q100 Grade 0 and will survive
extended operation at 175°C junction temperature.
□ ±8 kV HBM ESD
□ Overtemperature indication
These monolithic ICs include on-chip reverse-battery protection,
overvoltage protection (e.g., 40 V load dump), ESD protection,
overtemperature detection, and an internal voltage regulator for
operation directly from an automotive battery bus. These integrated
features reduce the end-product bill-of-materials (BOM) and
assembly cost.
Packageoptionsincludeindustry-standardsurface-mountSOT(LH)
and through-hole SIP (UA) packages. Both packages are RoHS-
compliantandlead(Pb)freewith100%matte-tin-platedleadframes.
SELECTION GUIDE [1]
Magnetic
Operate Point,
BOP (typ)
Output Polarity
Temperature
Coefficient
Part Number
Package
Packing
(B > BOP
)
APS12450LLHALX-0SLA
APS12450LLHALT-0SLA
APS12450LUAA-0SLA
APS12450LLHALX-1SLA
APS12450LLHALT-1SLA
APS12450LUAA-1SLA
APS12450LLHALX-3SLA
APS12450LLHALT-3SLA
APS12450LUAA-3SLA
3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel
3-pin SOT23W surface mount
3-pin SIP through-hole
7-in. reel, 3000 pieces/reel
bulk, 500 pieces/bag
Low
0%/°C
0%/°C
0%/°C
22 G
50 G
3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel
3-pin SOT23W surface mount
3-pin SIP through-hole
7-in. reel, 3000 pieces/reel
bulk, 500 pieces/bag
Low
Low
3-pin SOT23W surface mount 13-in. reel, 10,000 pieces/reel
3-pin SOT23W surface mount
3-pin SIP through-hole
7-in. reel, 3000 pieces/reel
bulk, 500 pieces/bag
150 G
[1] Contact Allegro MicroSystems for options not listed in the selection guide.
RoHS
COMPLIANT
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
ꢀoꢁꢂlete Part
ꢃꢄꢁꢅer ꢆorꢁat
Allegro Iden�fier (Device Family)
APS – Digital Posi�on Sensor
Allegro Device Number
12450 – ASIL B Hall-effect Latch
Configura�on Op�ons
-
A P S 1 2 4 5 0
L L H A L T 0 S L C
Temperature Coefficient
A – Flat
B – -0.035 %/°C
C – -0.12 %/°C
D – -0.2 %/°C
Output Polarity for B > BOP
H – High (Output Off)
L – Low (Output On)
Opera�ng Mode
S – Unipolar South Sensing
N – Unipolar North Sensing
Device Switch Threshold Magnitude
0 – 22 G BOP, -22 G BRP (typ.)
1 – 50 G BOP, -50 G BRP (typ.)
3 – 150 G BOP, -150 G BRP (typ.)
Instruc�ons (Packing)
LT – 7-in. reel, 3,000 pieces/reel (LH Only)
LX – 13-in. reel, 10,000 pieces/reel (LH Only)
TN – 13-in. reel, 4,000 pieces/reel (UA Only)
(no op�on code) – bulk, 500 pieces/bag (UA only)
Package Designa�on
LHA – 3-pin SOT23W Surface Mount
UAA – 3-pin SIP Through-Hole
Ambient Opera�ng Temperature Range
L – -40°C to +150°C
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Notes
Rating
35
Unit
V
Supply Voltage [2]
VCC
VRCC
Reverse Supply Voltage
Forward Output Voltage
Reverse Output Voltage
Output Current Sink
–30
V
VOUT
30
V
VROUT
IOUT(SINK)
–0.3
12
V
VCC to VOUT
For 500 hours
mA
°C
°C
°C
165
Maximum Junction Temperature
Storage Temperature
TJ(MAX)
Tstg
175
–65 to 170
[2] This rating does not apply to extremely short voltage transients such as load dump and/or ESD. Those events have individual ratings
specific to the respective transient voltage event. Contact your local field applications engineer for information on EMC test results.
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
PINOUT DIAGRAMS AND TERMINAL LIST
3
ꢀ
1
ꢀ
3
1
LH Package, 3-Pin SOT23W Pinout
UA Package, 3-Pin SIP Pinout
Terminal List Table
Pin Number
Name
Function
LH
1
UA
1
VCC
VOUT
GND
Supply voltage
Output
2
3
3
2
Ground
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
OPERATING CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max),
unless otherwise specified
Characteristics
SUPPLY AND STARTUP
Supply Voltage [2]
Symbol
Test Conditions
Min.
Typ. [1]
Max.
Unit
VCC
Operating, TJ < 165°C
3.0
–
–
–
30
V
Supply Current
ICC
4.5
mA
VCC > VCC(min), B < BRP(min) – 10 G,
B > BOP(max) + 10 G
Power-On Time [3]
ton
–
–
150
µs
Power-On State
Output Rise Time
Output Fall Time
Output On Voltage
Output Off Voltage
POS
tRISE
t < ton(max)
VOUT(FAULT)
–
2
2
4
4
15
15
30
90
µs
µs
%
%
See Applications Circuit, Figure 9;
VPU = VCC, RPU = 3 kΩ, COUT = 1 nF, IOUT < 12 mA
tFALL
VOUT(LOW)
VOUT(HIGH)
10
70
20
80
Output ratiometric to VPU
VPU = VCC, τ < 3 µs [5], IOUT < 12 mA
;
Overshoot percentage relative to VPU (see Figure 8);
VOUT(HIGH)OVER
tVOUT(H)OVER
–
–
2
–
–
5
%
VPU = VCC, τ < 3 µs [5], IOUT < 12 mA
Output Off Voltage Overshoot [4]
Duration of output voltage overshoot (VOUT(HIGH)OVER
)
µs
ON-BOARD PROTECTION
Fault Reaction Time
tDIAG
–
–
25
2
60
–
µs
Diagnostics Fault Retry Time [6]
tDIAGF
ms
Fault Mode Output Voltage
(Fault State)
> VOUT(HIGH)
VOUT(FAULT)
VPU = VCC, τ < 3 µs, IOUT < 12 mA
VPU
–
V
MAX
Overtemperature Shutdown
Overtemperature Hysteresis
TSD
Temperature increasing
–
205
25
–
–
°C
°C
TJHYS
–
[1] Typical data is at TA = 25°C and VCC = 12 V and is for design information only.
[2]
V
represents the voltage between the VCC pin and the GND pin.
CC
[3] Power-On Time (tON) is measured from VCC = VCC(min) to 50% of the output transition from VPU to final value. Adding a bypass capacitor will
increase Power-On Time.
[4] The overshoot specification pertains only to conditions where the overshoot is greater than the VOUT(HIGH)MAX specification.
[5]
τ is the time constant of the RC circuit; τ = RPU × COUT
The diagnostics fault retry repeats continuously until a fault condition is no longer observed. See Diagnostics Mode Operation section for details.
.
[6]
TRANSIENT PROTECTION CHARACTERISTICS: Valid for TA = 25°C and CBYP = 0.1 µF, unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
PROTECTION
Forward Supply Zener
Clamp Voltage
VZ
ICC(max) + 3 mA
35
–
–
V
Reverse Supply Zener
Clamp Voltage
VRCC
ICC = –1 mA
–
–
–
–
–30
–5
V
Reverse Supply Current
IRCC
VRCC = –30 V
mA
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
MAGNETIC CHARACTERISTICS: Valid over full operating voltage and ambient temperature ranges for TJ < TJ(max),
unless otherwise specified
Characteristics
Symbol
Test Conditions
Min.
–
Typ. [1]
0
Max.
–
Unit [2]
%/°C
%/°C
%/°C
%/°C
kHz
G
(A) Flat
(B) SmCo
(C) NdFeB
(D) Ferrite
–
–0.035
–0.12
–0.2
10
–
Sensitivity Temperature
Coefficient
Relative to sensitivity
at 25°C
TCSENS
–
–
–
–
Analog Signal Bandwidth
Operate Point
f(-3dB)
–
–
APS12450–0SxA
APS12450–1SxA
APS12450–3SxA
APS12450–0SxA
APS12450–1SxA
APS12450–3SxA
APS12450–0SxA
APS12450–1SxA
APS12450–3SxA
BOP + BRP
5
22
40
90
180
–5
–15
–100
80
180
360
30
–
BOP
15
100
–40
–90
–180
10
30
200
-30
–
50
G
150
–22
–50
–150
45
G
G
Release Point
Hysteresis
BRP
G
G
G
BHYS
100
300
–
G
G
Symmetry
Jitter [3]
BSYM
–
G
BOP = 22 G, B = 100 GPK-PK, 1000 Hz
0.25
%
[1] Typical data is at TA = 25°C and VCC = 12 V, unless otherwise noted; for design information only.
[2] 1 G (gauss) = 0.1 mT (millitesla).
[3] Output edge repeatability as a percentage of the period.
THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic
Symbol
Test Conditions*
Value
Unit
Package LH, on 1-layer PCB based on JEDEC standard
228
110
165
°C/W
Package Thermal Resistance
RθJA
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side
Package UA, on 1-layer PCB with copper limited to solder pads
°C/W
°C/W
*Additional thermal information available on the Allegro website.
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
CHARACTERISTIC PERFORMANCE DATA
VOUT(HIGH) vs. TA
VOUT(HIGH) vs. VCC
90
90
88
86
84
82
80
78
76
74
72
70
88
86
84
82
80
78
76
74
72
70
TA (°C)
-40
VCC (V)
3
25
150
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
V
OUT(LOW) vs. TA
VOUT(LOW) vs. VCC
30
28
26
24
22
20
18
16
14
12
10
30
28
26
24
22
20
18
16
14
12
10
TA (°C)
-40
VCC (V)
3
25
150
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
VOUT(FAULT) vs. TA
V
OUT(FAULT) vs. VCC
102
100
98
102
100
98
96
96
TA (°C)
-40
94
94
VCC (V)
92
92
25
3
150
30
90
90
0
5
10
15
20
25
30
35
-50
-20
10
40
70
100
130
160
Supply Voltage, VCC (V)
Ambient Temperature, TA (°C)
tDIAGF vs. TA
tDIAGF vs. VCC
4
3.5
3
4
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
TA (°C)
-40
VCC (V)
3
25
0.5
0
0.5
0
30
150
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
CHARACTERISTIC PERFORMANCE DATA (continued)
ICC vs. TA
ICC vs. VCC
4.5
4.5
4
4
3.5
3
3.5
3
2.5
2
2.5
2
VCC (V)
3
TA (°C)
-40
1.5
1
1.5
1
12
24
30
25
0.5
0
0.5
0
150
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
ton vs. TA
tRISE & tFALL vs. TA
150
135
120
105
90
15
12.5
10
7.5
5
75
60
45
30
2.5
0
Fall
15
Rise
0
-50
-20
10
40
70
100
130
160
-50
-20
10
40
70
100
130
160
Ambient Temperature, TA (°C)
Ambient Temperature, TA (°C)
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
CHARACTERISTIC PERFORMANCE DATA
APS12450–0SxA
BOP(0S_A) vs. TA
BOP(0S_A) vs. VCC
40
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
TA (°C)
-40
VCC (V)
3
25
30
150
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BRP(0S_A) vs. TA
BRP(0S_A) vs. VCC
-5
-5
TA (°C)
-40
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
25
150
VCC (V)
3
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BHYS(0S_A) vs. TA
BHYS(0S_A) vs. VCC
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
TA (°C)
-40
VCC (V)
3
25
150
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BSYM(0S_A) vs. TA
BSYM(0S_A) vs. VCC
25
20
15
10
5
25
20
15
10
5
0
0
-5
-5
TA (°C)
-40
-10
-15
-20
-25
-10
-15
-20
-25
VCC (V)
3
25
150
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
CHARACTERISTIC PERFORMANCE DATA
APS12450–1SxA
BOP(1S_A) vs. TA
BOP(1S_A) vs. VCC
90
90
82.5
75
82.5
75
67.5
60
67.5
60
52.5
45
52.5
45
TA (°C)
-40
37.5
30
37.5
30
VCC (V)
3
25
22.5
15
22.5
15
30
150
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BRP(1S_A) vs. TA
BRP(1S_A) vs. VCC
-15
-22.5
-30
-15
-22.5
-30
TA (°C)
-40
25
-37.5
-45
-37.5
-45
150
-52.5
-60
-52.5
-60
-67.5
-75
-67.5
-75
VCC (V)
3
-82.5
-90
-82.5
-90
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BHYS(1S_A) vs. TA
BHYS(1S_A) vs. VCC
180
155
130
105
80
180
155
130
105
80
TA (°C)
-40
VCC (V)
3
55
55
25
150
30
30
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BSYM(1S_A) vs. TA
BSYM(1S_A) vs. VCC
25
20
15
10
5
25
20
15
10
5
0
0
-5
-5
TA (°C)
-40
-10
-15
-20
-25
-10
-15
-20
-25
VCC (V)
3
25
150
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
CHARACTERISTIC PERFORMANCE DATA
APS12450–3SxA
BOP(3S_A) vs. TA
BOP(3S_A) vs. VCC
180
180
170
160
150
140
130
120
110
100
170
160
150
140
130
120
110
100
TA (°C)
-40
VCC (V)
3
25
30
150
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BRP(3S_A) vs. TA
BRP(3S_A) vs. VCC
-100
-110
-120
-130
-140
-150
-160
-170
-180
-100
-110
-120
-130
-140
-150
-160
-170
-180
TA (°C)
-40
25
150
VCC (V)
3
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BHYS(3S_A) vs. TA
BHYS(3S_A) vs. VCC
360
340
320
300
280
260
240
220
200
360
340
320
300
280
260
240
220
200
TA (°C)
-40
VCC (V)
3
25
150
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
BSYM(3S_A) vs. TA
BSYM(3S_A) vs. VCC
25
20
15
10
5
25
20
15
10
5
0
0
-5
-5
TA (°C)
-40
-10
-15
-20
-25
-10
-15
-20
-25
VCC (V)
3
25
150
30
-50
-20
10
40
70
100
130
160
0
5
10
15
20
25
30
35
Ambient Temperature, TA (°C)
Supply Voltage, VCC (V)
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
FUNCTIONAL DESCRIPTION
Figure 1 shows the output switching behavior relative to increas-
ing and decreasing magnetic field. On the horizontal axis, the
B+ direction indicates increasing south polarity magnetic field
strength. Figure 2 shows the sensing orientation of the magnetic
field, relative to the device package.
Operation
The output of these devices switches when a magnetic field perpen-
dicular to the Hall-effect sensor exceeds the operate point threshold
(BOP). When the magnetic field is reduced below the release point
(BRP), the device output switches to the alternate state. The output
state (polarity) and magnetic field polarity depends on the selected
device options. The device is a latch, therefore BOP and BRP will be
in opposite magnetic field polarities.
Note that this device latches; that is, a south pole of sufficient
strength towards the branded face of the device turns the device
on, and the device remains on with removal of the south pole.
The difference between operate (BOP) and release (BRP) points is
the hysteresis (BHYS). Hysteresis allows clean switching of the
output even in the presence of external mechanical vibration and
electrical noise. The hysteresis is set to double the programmed
operating point.
Figure 1 shows the potential unipolar and omnipolar options and
output polarity options of the APS12450 that can be configured.
The direction of the applied magnetic field is perpendicular to the
branded face of the APS12450 (see Figure 2).
Standard Polaritꢁ
ꢀnverted Polaritꢁ
ꢅꢄ
ꢅꢄ
ꢅꢃUꢆꢇHꢊꢋHꢉ
ꢅꢃUꢆꢇHꢊꢋHꢉ
ꢅꢃUꢆꢇꢀꢃꢈꢉ
ꢅꢃUꢆꢇꢀꢃꢈꢉ
ꢁ-
ꢇnorthꢉ
0
ꢁꢄ
ꢇsoꢌthꢉ
ꢁꢍ
ꢇnorthꢉ
0
ꢁꢄ
ꢇsoꢌthꢉ
ꢁHꢂS
ꢁHꢂS
Figure 1: Hall latch magnetic and output polarity options
B- indicates increasing north polarity magnetic field strength, and
B+ indicates increasing south polarity magnetic field strength.
Y
Y
X
X
A
B
Z
Z
Figure 2: Magnetic Sensing Orientations
APS12450 LH (Panel A), APS12450 UA (Panel B)
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
FUNCTIONAL SAFETY
The APS12450 was developed in accordance with ISO 26262:2011 The signal path monitoring system verifies two internal state
transitions (BOP and BRP within limits) under normal operation.
In cases when these output transitions do not occur, or if another
internal fault is detected, the output will go to the fault state (see
“Three-Wire Diagnostic Output” section).
as a hardware safety element out of context with ASIL B capability
(pending assessment) for use in automotive safety-related systems
when integrated and used in the manner prescribed in the appli-
cable safety manual and datasheet.
In the event of an internal fault, the device will continuously run
the diagnostics routine every 2 ms (tDIAGF). The periodic recov-
ery attempt sequence allows the device to continually check for
the presence of a fault and return to normal operation if the fault
condition clears.
Diagnostics Mode Operation
The APS12450 features a proprietary diagnostics routine that
meets ASIL B safety requirements (pending assessment). This
internal diagnostics routine continuously runs in the background,
monitoring all key subsystems of the IC. These subsystems are
shown in Table 1 and Figure 3. The diagnostic scheme runs at
high speed and provides minimal impact on device performance.
Signal path diagnostics are injected and measured in less than
2 μs, while all other diagnostics are running in real time in the
background. The Hall element biasing circuit and voltage regula-
tor are checked for valid operation, and the digital and non‐vola-
tile memory blocks are checked for valid device configuration.
In the case where the fault is no longer present, the output will
resume normal operation. However, if the fault is persistent, the
device will not exit fault mode and the output voltage will con-
tinue to be VOUT(FAULT)
.
When a system rating higher than ASIL B is required, additional
external safety measures may be employed (e.g., sensor redun-
dancy and rationality checks, etc.). Refer to the device safety
manual for additional details about the diagnostics.
Table 1: Diagnostics Coverage
Feature
Coverage
1
2
3
4
5
6
Hall plate
Connectivity and biasing of Hall plate
Signal path
Signal path and Schmitt trigger
Voltage regulator
Digital subsystem
Entire system
Output
Regulator voltage for normal operation
Digital subsystem and non-volatile memory
Overtemperature and redundancies for single point failures
Output verified through valid regulations states (external monitor)
VCC
3
5
REGULATOR
To All Subcircuits
Schmitt Output
(Internal)
Low-Pass
Filter
VOUT
4
1
2
S
6
O
UTPUT
AMPLE, HOLD
&
H
AMALPL
.
CONTROL
SYSTEM
D
IAGNOSTICS
A
VERAGING
CLOCK LOGIC
GND
Figure 3: Diagnostics Coverage Block Diagram
13
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
Power-On Behavior
Temperature Coefficient and Magnet Selection
During Power-on, the output voltage is in the fault state
(VOUT(FAULT)), which is the pull-up voltage (VPU), until the
device is ready to respond appropriately to the input magnetic
field (t > tON). If the device powers-on with the field within the
hysteresis band, the output will switch from VOUT(FAULT) to the
off state (VOUT(HIGH)) with standard output polarity as shown in
Figure 4. For inverted output polarity operation, the output will
switch from VOUT(FAULT) to VOUT(LOW) (not shown).
The APS12450 allows the user to select the magnetic temperature
coefficient to compensate for drifts of SmCo, NdFeB, and ferrite
magnets over temperature, as indicated in the Magnetic Char-
acteristics specifications table. This compensation improves the
magnetic system performance over the entire temperature range.
For example, the magnetic field strength from NdFeB decreases
as the temperature increases from 25°C to 150°C. This lower
magnetic field strength means that a lower switching threshold
is required to maintain switching at the same distance from the
magnet to the sensor. Correspondingly, higher switching thresh-
olds are required at cold temperatures, as low as –40°C, due to
the higher magnetic field strength from the NdFeB magnet. The
APS12450 compensates the switching thresholds over tempera-
ture as described above. It is recommended that system design-
ers evaluate their magnetic circuit over the expected operating
temperature range to ensure the magnetic switching requirements
are met.
ꢀ
POS
VOUT(FAULT )
B ꢁ BRP
BRP ꢁ B ꢁ BOP
VOUT(HIGH)
Output Undefined for VCC ꢁ VCC(MIꢀ)
VOUT(LOW)
B ꢂ BOP
t
t
ꢀ
VCC(MIꢀ)
A sample calculation is provided in the “Applications Informa-
tion” section.
0
tOꢀ
Figure 4: Power-On Sequence
14
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
VPULL-UP of 5 V, the output state levels will be 1.0 V and 4.0 V
Three-Wire Diagnostic Output
±0.5 V. The output RC time constant (τ) must be less than 3 µs
(e.g., RPU = 3 kΩ and COUT = 1 nF), and VPU must be equal to
VCC (recommend pulling up VOUT directly to VCC).
Three-wire diagnostic output enables the user to identify various
fault conditions external to the IC, in addition to the internal fault
detection. The output low (VOUT(LOW)) and high (VOUT(HIGH)
)
Under normal operation (Figure 5), the output switches between
the VOUT(LOW) (20%) and VOUT(HIGH) (80%) states.
states are ratiometric to the pull-up voltage, with low and high
states being 20% and 80% respectively. For example, a VCC and
ꢀꢂUꢃꢊꢑAUꢆꢃ ꢌ ꢊꢀPU
ꢌ
ꢀꢂUꢃꢊHꢋꢄHꢌ ꢊꢍ0ꢎꢌ
RPUꢆꢆ-UP
ꢀꢁꢁ
ꢄNꢅ
ꢁꢇꢈPASS
ꢀꢂUꢃ
ꢀꢂUꢃꢊꢆꢂꢏꢌ ꢊꢐ0ꢎꢌ
ꢄNꢅ
Normal
ꢂꢉeration
ꢁꢂUꢃ
Figure 5: The APS12450 diagnostic output under normal operation (no fault detected)
With various opens and shorts on any of the IC pins, the output
Any output voltage levels outside of the valid VOUT(HIGH) and
VOUT(LOW) ranges indicates a fault as shown in Figure 6. The
observed voltage on VOUT relative to potential fault conditions
are summarized in Table 2.
will no longer be controlled by the IC. The output itself may
continue to switch, depending on the external connectivity fault;
however, the output level(s) observed will deviate from the 20%
and 80% (of VPU) output levels.
The output relative to the fault condition is summarized in Table 2
below.
If an internal fault is detected via diagnostics monitoring, the
output will be set to the fault state, VOUT(FAULT), which is equal
Table 2: Fault Conditions and Resulting Output
Level
to the pull-up voltage, VPU
.
Fault
Output Level
ꢀ V
20% or 80% of VPU
,
VOUT(FAULT )
No Fault
VPU ꢃ VCC
respectively
Fault State
Range ꢁor valiꢂ VOUT(HIGH)
External Fault
Short, VCC-VOUT
Short, VOUT-GND
Short, VCC-GND
Open, VCC
VCC
GND
VPU
VPU
VPU
VPU
VPU
VOUT(HIGH) (max)
VOUT(HIGH) (min)
90% VPU
70% VPU
VOUT(LOW) (max)
VOUT(LOW) (min)
0
30% VPU
10% VPU
Open, VOUT
Range ꢁor valiꢂ VOUT(LOW)
External Fault
Open, GND
Internal Fault
Note: VOUT(FAULT) ≤ VPULL-UP and VPULL-UP = VCC
.
Figure 6: APS12450 valid (normal) and
fault condition output levels
15
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
Fault Detection and Retry
The fault detection diagnostics runs continuously in the background
during normal operation after the device has powered-on. In the
event a fault is detected, the output will immediately change to the
VOUT(FAULT) state. The diagnostics will continue to retry the diag-
nostics approximately every 2 ms. If the fault recovers, the output
will return to normal operation. See Figure 7.
VOUT(FAULT )
VOUT(HIGH)
Output switcꢀes accorꢁing
to external magne�c field
Output switcꢀes accorꢁing
to external magne�c field
VOUT(LOW )
t
Bacꢂgrounꢁ
Diagnos�csꢃ
Bacꢂgrounꢁ
Diagnos�csꢃ
2 ms
2 ms
t
Failure Detecteꢁ
Device Recovers
Diag Retryꢃꢃ
ꢃ
4x Diagnos�c Cycles completed every 0.025 ms (nom.)
ꢃꢃ Diagnos�c Fault Retry Time interval is 2 ms (nom.)
Figure 7: Fault Detection and Retry
this condition is not out of specification. The Output Off Voltage
Overshoot specification pertains only to conditions where the over-
shoot is greater than the VOUT(HIGH)MAX specification.
Output Overshoot
When the output switches from VOUT(LOW) to VOUT(HIGH)
,
depending upon the RC circuit, a small overshoot can occur
(VOUT(H)OVER). VOUT(H)OVER is specified as a percentage of
VPULL-UP (and/or VCC, which need to be the same). Therefore
with an RC Time Constant (τ) of 3 µs (see the “Applications
Information” section), a nominal overshoot of 2% is possible.
With VPULL-UP at 5.0 V, the output may overshoot by 0.1 V, for
less than 5 µs (tVOUT(H)OVER). Figure 7 demonstrates output edge
profile.
For example, with a 5 V pull-up, if VOUT(HIGH) is at the upper limit
(90%), VOUT(HIGH) will be 4.5 V. With a τ of 3 µs at room tem-
perature, the output can briefly reach 4.6 V until it settles to 4.5 V.
Since VOUT(HIGH) is valid between 70% and 90%, or 3.5 and 4.5 V,
Figure 8: Output Overshoot
16
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
APPLICATIONS INFORMATION
Temperature Compensation
Typical Applications
For the LH and UA packages, an external bypass capacitor,
CBYP, should be connected (in close proximity to the Hall sen-
sor) between the supply and ground of the device to reduce both
external noise and noise generated by the chopper stabilization
technique. As is shown in Figure 9, a 0.1 µF bypass capacitor is
typical, with an optional output capacitor, COUT (recommended
1 nF).
To calculate the typical effect of the TCSENS on BOP (or BRP),
simply multiply the BOP at the starting temperature by TCSENS
and the change in temperature.
Sample BOP calculation for TCSENS compensation from 25°C to
150°C, for TCSENS = –0.12%/°C, and BOP(25C) = 180 G:
ΔTA = 150°C – 25°C = 125°C
BOP(150C) = BOP(25C) + (BOP(25C) × TC × ΔTA )
= 180 G + (180 G × –0.12%/°C × 125°C)
= 180 G + (–27 G)
The time constant of the RC circuit (τ) on output must be less
than 3 µs, where:
τ
= RPULLUP × COUT
= 3 kΩ × 1 nF
= 3 µs
= 153 G
The resistor, RPULLUP, must be between 2 and 30 kΩ.
ꢈPUꢋꢋ-UP
ꢈꢁꢁ
Diagnostic Output*
RSꢓRꢀꢓS
ꢊoꢄtionalꢍ
VCC
VPU
3 to 30 V
VCC
RPUꢋꢋ-UP
ꢈꢁꢁ
CBYP
COUT
RPU
0.1 µF
ꢓꢁU
τRC < 3 µs
ꢈꢂUꢉ
ꢁꢏꢐPASS
0.1 ꢑꢒ
Aꢆꢁ
IOUT < 12 mA
τRC < 3 µs
2 kΩ < R < 30 kΩ
ꢎPꢀꢂ
ꢁꢂUꢉ
ꢊoꢄtionalꢍ
ꢎNꢆ
RS
100 Ω*
ꢀꢁ ꢂꢃtꢄꢃtꢅ ꢆiagnostic ꢂꢃtꢄꢃt
switching ꢇetween ꢈꢂUꢉꢊꢋꢂꢌꢍ and ꢈꢂUꢉꢊHꢀꢎHꢍ
* The following application circuit conditions are required
• The τ of the RC on output must be < 3 µs.
• 2 kΩ < RPU < 30 kΩ.
• VPU = VCC (recommend pulling VOUT up
to VCC).
Figure 9: Typical Applications Circuits
Diagnostic Output
17
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
Extensive applications information on magnets and Hall-effect
sensors is available in:
• Hall-Effect IC Applications Guide, AN27701
• Guidelines For Designing Subassemblies Using Hall-Effect
Devices, AN27703.1
• Soldering Methods for Allegro’s Products – SMT and Through-
Hole, AN26009
• Functional Safety Challenges to the Automotive Supply Chain
(https://www.allegromicro.com/en/Design-Center/Technical-
Documents/General-Semiconductor-Information/Functional-
Safety-Challenges-Automotive-Supply-Chain.aspx)
All are provided on the Allegro website:
www.allegromicro.com
18
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
Chopper Stabilization Technique
A limiting factor for switchpoint accuracy when using Hall-
effect technology is the small-signal voltage developed across
the Hall plate. This voltage is proportionally small relative to the
offset that can be produced at the output of the Hall sensor. This
makes it difficult to process the signal and maintain an accurate,
reliable output over the specified temperature and voltage range.
Chopper stabilization is a proven approach used to minimize
Hall offset.
subsequent demodulation acts as a modulation process for the
offset causing the magnetically induced signal to recover its origi-
nal spectrum at baseband while the DC offset becomes a high-
frequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innovative
chopper-stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate that
produces higher accuracy, reduced jitter, and faster signal pro-
cessing. Additionally, filtering is more effective and results in a
lower noise analog signal at the sensor output. Devices such as the
APS12450 that use this approach have an extremely stable quies-
cent Hall output voltage, are immune to thermal stress, and have
precise recoverability after temperature cycling. This technique is
made possible through the use of a BiCMOS process which allows
the use of low offset and low noise amplifiers in combination with
high-density logic and sample-and-hold circuits.
The technique, dynamic quadrature offset cancellation, removes
key sources of the output drift induced by temperature and
package stress. This offset reduction technique is based on a
signal modulation-demodulation process. “Figure 10: Model of
Chopper Stabilization Circuit (Dynamic Offset Cancellation)”
illustrates how it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
Regulator
Clock/Logic
Low-Pass
Filter
Hall Element
Amp
Figure 10: Model of Chopper Stabilization Circuit
(Dynamic Offset Cancellation)
19
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
POWER DERATING
The device must be operated below the maximum junction
temperature, TJ (max). Reliable operation may require derating
supplied power and/or improving the heat dissipation properties
of the application.
Finally, using equation 1, solve for maximum allowable VCC for
the given conditions:
V
CC (est) = PDꢀ(max)ꢀ÷ꢀICCꢀ(max)ꢀ=ꢀ91ꢀmWꢀ÷ꢀ4ꢀmAꢀ=ꢀ22.8ꢀV
The result indicates that, at TA, the application and device can
Thermal Resistance (junction to ambient), RθJA, is a figure of
merit summarizing the ability of the application and the device to
dissipate heat from the junction (die), through all paths to ambi-
ent air. RθJA is dominated by the Effective Thermal Conductivity,
K, of the printed circuit board which includes adjacent devices
and board layout. Thermal resistance from the die junction to
case, RθJC, is a relatively small component of RθJA. Ambient air
temperature, TA, and air motion are significant external factors in
determining a reliable thermal operating point.
dissipate adequate amounts of heat at voltages ≤ VCC (est).
If the application requires VCC > VCC(est) then RθJA must by
improved. This can be accomplished by adjusting the layout,
PCB materials, or by controlling the ambient temperature.
Determining Maximum TA
In cases where the VCC (max) level is known, and the system
designer would like to determine the maximum allowable ambi-
ent temperature TA (max), for example, in a worst-case scenario
with conditions VCC (max) = 40 V, ICC (max) = 4 mA, and RθJA
= 228°C/W for the LH package using equation 1, the largest pos-
sible amount of dissipated power is:
The following three equations can be used to determine operation
points for given power and thermal conditions.
PD = VIN × IIN
∆Tꢀ=ꢀPD × RθJA
TJ = TAꢀ+ꢀ∆Tꢀꢀ
(1)
(2)
(3)
ꢀ
ꢀ
PD = VIN × IIN
PD = 40 V × 4 mA = 160 mW
Then, by rearranging equation 3 and substituting with equation 2:
For example, given common conditions: TA = 25°C, VCC = 12 V,
I
CC = 4 mA, and RθJA = 110°C/W for the LH package, then:
TA (max) = TJꢀ(max)ꢀ–ꢀΔT
PD = VCC × ICC = 12 V × 4 mA = 48 mW
TA (max) = 165°C – (160 mW × 228°C/W)
ꢀ
∆Tꢀ=ꢀPD × RθJA = 48 mW × 110°C/W = 5.28°C
TJ = TAꢀ+ꢀ∆Tꢀ=ꢀ25°Cꢀ+ꢀ5.28°Cꢀ=ꢀ31.28°C
TAꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ36.5°Cꢀ=ꢀ128.5°C
In another example, the maximum supply voltage is equal to
V
CC (min). Therefore, VCC (max) = 3 V and ICC (max) = 4 mA.
Determining Maximum VCC
By using equation 1 the largest possible amount of dissipated
power is:
For a given ambient temperature, TA, the maximum allow-
able power dissipation as a function of VCC can be calculated.
PD (max) represents the maximum allowable power level without
exceeding TJ (max) at a selected RθJA and TA.
PD = VIN × IIN
PDꢀ=ꢀ3ꢀVꢀ×ꢀ4ꢀmAꢀ=ꢀ12ꢀmW
Example: VCC at TA = 150°C, package UA, using low-K PCB.
Then, by rearranging equation 3 and substituting with equation 2:
Using the worst-case ratings for the device, specifically: RθJA
=
TA (max) = TJꢀ(max)ꢀ–ꢀΔT
165°C/W, TJ (max) = 165°C, VCC (max) = 24 V, and ICC (max) =
4 mA, calculate the maximum allowable power level, PD (max).
First, using equation 3:
TA (max) = 165°C – (12 mW × 228°C/W)
TAꢀ(max)ꢀ=ꢀ165°Cꢀ–ꢀ11.6°Cꢀ=ꢀ162.3°C
∆Tꢀ(max)ꢀ=ꢀTJ (max) – TA = 165°C – 150°C = 15°C
The example above indicates that at VCC = 3 V and ICC = 4 mA,
the TA (max) can be as high as 162.3°C without exceeding
TJ (max). However the TA (max) rating of the device is 150°C;
the device performance is not guaranteed above TA = 150°C.
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, from equation 2:
PDꢀ(max)ꢀ=ꢀ∆Tꢀ(max)ꢀ÷ꢀRθJAꢀ=ꢀ15°Cꢀ÷ꢀ165°C/Wꢀ=ꢀ91ꢀmW
20
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
Package LH, 3-Pin SOT23W
ꢭꢀꢁꢔꢐꢂ
ꢮꢀꢁꢕꢂ
ꢐꢁꢓꢕꢂ
ꢚ
ꢔꢁꢖꢓ
ꢖꢯꢟꢖꢯ
ꢱ
A
ꢭꢀꢁꢀꢐꢀ
ꢮꢀꢁꢀꢂꢱ
ꢀꢁꢔꢞꢀ
ꢚ
ꢀꢁꢓꢳ
ꢚ
ꢭꢀꢁꢔꢀ
ꢐꢁꢓꢀ
ꢭꢀꢁꢔꢓ
ꢮꢀꢁꢀꢳ
ꢐꢁꢖꢀ
ꢔꢁꢓꢔ
ꢮꢀꢁꢐꢀ
ꢀꢁꢕꢀ
ꢀꢁꢐꢂ MIꢲ
ꢔꢁꢀꢀ
ꢐ
ꢔ
ꢀꢁꢂꢂ ꢃꢄꢅ
ꢀꢁꢐꢂ ꢑꢍꢒ
ꢀꢁꢓꢂ
ꢊꢒꢑ ꢩꢆꢣꢤꢇꢎ ꢃꢉꢡꢉꢙꢉꢌꢗꢉ Vꢏꢉꢪ
ꢍꢉꢆꢎꢏꢌꢈ ꢊꢋꢆꢌꢉ
Gꢆꢇꢈꢉ ꢊꢋꢆꢌꢉ
ꢑ
ꢑꢙꢆꢌꢢꢉꢢ ꢅꢆꢗꢉ
ꢞꢰ ꢔꢀꢯ ꢟꢂꢯ
ꢔꢁꢀꢀ ꢟꢀꢁꢔꢱ
ꢭꢀꢁꢔꢀ
XXX
ꢔ
ꢀꢁꢀꢂ
ꢮꢀꢁꢀꢂ
ꢒ
ꢍꢎꢆꢌꢢꢆꢙꢢ ꢑꢙꢆꢌꢢꢏꢌꢈ ꢃꢉꢡꢉꢙꢉꢌꢗꢉ Vꢏꢉꢪ
ꢀꢁꢓꢂ ꢑꢍꢒ
ꢀꢁꢖꢀ ꢟꢀꢁꢔꢀ
ꢩꢏꢌꢉ ꢔ ꢫ Tꢜꢙꢉꢉ ꢢꢏꢈꢏꢎ ꢆꢥꢥꢏꢈꢌꢉꢢ ꢬꢙꢆꢌꢢ ꢌꢇꢠꢬꢉꢙ
ꢅꢤꢙ ꢙꢉꢡꢉꢙꢉꢌꢗꢉ ꢤꢌꢋꢣꢧ ꢌꢤꢎ ꢡꢤꢙ ꢎꢤꢤꢋꢏꢌꢈ ꢇꢥꢉ (ꢙꢉꢡꢉꢙꢉꢌꢗꢉ ꢚꢴGꢵꢀꢀꢀꢀꢳꢐꢞꢝ ꢃꢉꢘꢁ ꢔ)ꢁ
ꢚꢏꢠꢉꢌꢥꢏꢤꢌꢥ ꢏꢌ ꢠꢏꢋꢋꢏꢠꢉꢎꢉꢙꢥꢁ
ꢚꢏꢠꢉꢌꢥꢏꢤꢌꢥ ꢉꢶꢗꢋꢇꢥꢏꢘꢉ ꢤꢡ ꢠꢤꢋꢢ ꢡꢋꢆꢥꢜꢝ ꢈꢆꢎꢉ ꢬꢇꢙꢙꢥꢝ ꢆꢌꢢ ꢢꢆꢠꢬꢆꢙ ꢛꢙꢤꢎꢙꢇꢥꢏꢤꢌꢥꢁ
ꢄꢶꢆꢗꢎ ꢗꢆꢥꢉ ꢆꢌꢢ ꢋꢉꢆꢢ ꢗꢤꢌꢡꢏꢈꢇꢙꢆꢎꢏꢤꢌ ꢆꢎ ꢥꢇꢛꢛꢋꢏꢉꢙ ꢢꢏꢥꢗꢙꢉꢎꢏꢤꢌ ꢪꢏꢎꢜꢏꢌ ꢋꢏꢠꢏꢎꢥ ꢥꢜꢤꢪꢌꢁ
Aꢗꢎꢏꢘꢉ Aꢙꢉꢆ ꢚꢉꢛꢎꢜꢝ ꢀꢁꢐꢞ ꢟꢀꢁꢀꢖ ꢠꢠ
A
ꢑ
ꢃꢉꢡꢉꢙꢉꢌꢗꢉ ꢋꢆꢌꢢ ꢛꢆꢎꢎꢉꢙꢌ ꢋꢆꢣꢤꢇꢎ
Aꢋꢋ ꢛꢆꢢꢥ ꢆ ꢠꢏꢌꢏꢠꢇꢠ ꢤꢡ ꢀꢁꢐꢀ ꢠꢠ ꢡꢙꢤꢠ ꢆꢋꢋ ꢆꢢꢦꢆꢗꢉꢌꢎ ꢛꢆꢢꢥꢧ ꢆꢢꢦꢇꢥꢎ ꢆꢥ ꢌꢉꢗꢉꢥꢥꢆꢙꢣ
ꢎꢤ ꢠꢉꢉꢎ ꢆꢛꢛꢋꢏꢗꢆꢎꢏꢤꢌ ꢛꢙꢤꢗꢉꢥꢥ ꢙꢉꢨꢇꢏꢙꢉꢠꢉꢌꢎꢥ ꢆꢌꢢ ꢊꢒꢑ ꢋꢆꢣꢤꢇꢎ ꢎꢤꢋꢉꢙꢆꢌꢗꢉꢥ
ꢒ
ꢚ
ꢑꢙꢆꢌꢢꢏꢌꢈ ꢥꢗꢆꢋꢉ ꢆꢌꢢ ꢆꢛꢛꢉꢆꢙꢆꢌꢗꢉ ꢆꢎ ꢥꢇꢛꢛꢋꢏꢉꢙ ꢢꢏꢥꢗꢙꢉꢎꢏꢤꢌ
Hꢆꢋꢋ ꢉꢋꢉꢠꢉꢌꢎꢝ ꢌꢤꢎ ꢎꢤ ꢥꢗꢆꢋꢉ
21
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
Package UA, 3-Pin SIP, Matrix HD Style
ꢳꢆꢃꢆꢣ
ꢇꢃꢆꢵ
ꢴꢆꢃꢆꢈ
ꢇꢈꢉ
ꢌ
ꢊ
ꢟ
ꢀꢃꢆꢇ ꢅOM
ꢂꢃꢈꢀ ꢋꢆꢃꢆꢈ
ꢂꢆꢉ
ꢂꢃꢇꢇ ꢅOM
ꢟ
ꢟ
Mꢘꢚꢑ ꢟꢯꢏꢠꢎꢘꢔ
ꢰꢒꢐ Iꢐꢑꢏꢐꢎ
ꢳꢆꢃꢆꢣ
ꢴꢆꢃꢆꢈ
ꢁꢃꢆꢀ
ꢇꢈꢉ
ꢌꢔꢍꢐꢑꢏꢑ
ꢥꢍꢠꢏ
XXX
ꢆꢃꢄꢵ ꢫꢟꢥ
A
ꢂꢃꢆꢀ
MAX
ꢂ
ꢮꢎꢍꢐꢑꢍꢔꢑ ꢌꢔꢍꢐꢑꢒꢐꢤ ꢫꢏꢦꢏꢔꢏꢐꢠꢏ Vꢒꢏꢭ
ꢖ
ꢱꢒꢐꢏ ꢂꢲ ꢱꢘꢤꢘ A
ꢱꢒꢐꢏ ꢀꢲ Tꢡꢔꢏꢏ ꢑꢒꢤꢒꢎ ꢍꢜꢜꢒꢤꢐꢏꢑ ꢓꢔꢍꢐꢑ ꢐꢕꢗꢓꢏꢔ
ꢂ
ꢀ
ꢁ
ꢂꢇꢃꢵꢵ ꢋꢆꢃꢀꢈ
ꢳꢆꢃꢆꢁ
ꢴꢆꢃꢆꢝ
ꢆꢃꢇꢂ
ꢥꢘꢔ ꢔꢏꢦꢏꢔꢏꢐꢠꢏ ꢘꢐꢚꢧꢨ ꢐꢘꢎ ꢦꢘꢔ ꢎꢘꢘꢚꢒꢐꢤ ꢕꢜꢏ (ꢔꢏꢦꢏꢔꢏꢐꢠꢏ ꢖꢩGꢪꢆꢆꢆꢆꢇꢆꢇꢢ ꢫꢏꢙꢃ ꢂ)ꢃ
ꢖꢒꢗꢏꢐꢜꢒꢘꢐꢜ ꢒꢐ ꢗꢒꢚꢚꢒꢗꢏꢎꢏꢔꢜꢃ
ꢖꢒꢗꢏꢐꢜꢒꢘꢐꢜ ꢏꢬꢠꢚꢕꢜꢒꢙꢏ ꢘꢦ ꢗꢘꢚꢑ ꢦꢚꢍꢜꢡꢢ ꢤꢍꢎꢏ ꢓꢕꢔꢔꢜꢢ ꢍꢐꢑ ꢑꢍꢗꢓꢍꢔ ꢛꢔꢘꢎꢔꢕꢜꢒꢘꢐꢜꢃ
ꢟꢬꢍꢠꢎ ꢠꢍꢜꢏ ꢍꢐꢑ ꢚꢏꢍꢑ ꢠꢘꢐꢦꢒꢤꢕꢔꢍꢎꢒꢘꢐ ꢍꢎ ꢜꢕꢛꢛꢚꢒꢏꢔ ꢑꢒꢜꢠꢔꢏꢎꢒꢘꢐ ꢭꢒꢎꢡꢒꢐ ꢚꢒꢗꢒꢎꢜ ꢜꢡꢘꢭꢐꢃ
ꢳꢆꢃꢆꢈ
ꢴꢆꢃꢆꢄ
ꢆꢃꢇꢁ
ꢖꢍꢗꢓꢍꢔ ꢔꢏꢗꢘꢙꢍꢚ ꢛꢔꢘꢎꢔꢕꢜꢒꢘꢐ (ꢝꢞ)
Gꢍꢎꢏ ꢍꢐꢑ ꢎꢒꢏ ꢓꢍꢔ ꢓꢕꢔꢔ ꢍꢔꢏꢍ
A
ꢀ
ꢁ
ꢖ
Aꢠꢎꢒꢙꢏ Aꢔꢏꢍ ꢖꢏꢛꢎꢡꢢ ꢆꢃꢈꢆ ꢋꢆꢃꢆꢣ ꢗꢗ
ꢌꢔꢍꢐꢑꢒꢐꢤ ꢜꢠꢍꢚꢏ ꢍꢐꢑ ꢍꢛꢛꢏꢍꢔꢍꢐꢠꢏ ꢍꢎ ꢜꢕꢛꢛꢚꢒꢏꢔ ꢑꢒꢜꢠꢔꢏꢎꢒꢘꢐ
Hꢍꢚꢚ ꢏꢚꢏꢗꢏꢐꢎ (ꢐꢘꢎ ꢎꢘ ꢜꢠꢍꢚꢏ)
ꢟ
ꢂꢃꢀꢄ ꢅOM
22
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Three-Wire Hall-Effect Latch with Advanced Diagnostics
APS12450
REVISION HISTORY
Number
Date
Description
–
1
January 31, 2019
April 23, 2019
Initial release
Updated ASIL status
Copyright 2019, Allegro MicroSystems.
Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
www.allegromicro.com
23
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
相关型号:
APS124F100BD
CAPACITOR, FILM/FOIL, POLYPROPYLENE, 100V, 0.12uF, THROUGH HOLE MOUNT, RADIAL LEADED
KEMET
APS124J100BD
CAPACITOR, FILM/FOIL, POLYPROPYLENE, 100V, 0.12uF, THROUGH HOLE MOUNT, RADIAL LEADED
KEMET
©2020 ICPDF网 联系我们和版权申明