ARG81800_技术文档

ARG81800

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

FEATURES AND BENEFITS

DESCRIPTION

TheARG81800includesallthecontrolandprotectioncircuitry

to produce a PWM regulator with ±1.5% output voltage

accuracy,withultralowquiescentcurrenttoenable “keepalive”

supply operation with minimal current draw from the supply

during very light load regulation. There are two versions of

theARG81800 available, 500 mAand 1A, so the physical size

of the power components can be optimized for lower current

systems, thus reducing PCB area and saving cost. PWM

switching frequency can be programmed over a wide range to

balance efficiency, component sizing, and EMC performance.

If V_INdecays and the duty cycle reaches its maximum, the

ARG81800 will automatically fold back its PWM frequency

• Automotive AEC-Q100 qualified

• Input operating voltage range: 3.5 to 36 V

□ Withstands surge voltages to 40 V for load dump

• Low-Power (LP) mode—draws just 8 µA from V_INwhile

maintaining 3.3 or 5.0 V_OUT

• AUTO mode allows automatic transition between PWM

and LP mode based on load current

• Programmable PWM frequency (f_SW): 250 kHz to 2.4 MHz

• PWM frequency dithering and controlled switch node

slew rate reduce EMI/EMC signature

• CLK_OUTallows interleaving and dithering of “downstream”

regulators using their synchronization inputs

to extend the duty cycle and maintain V_OUT

.

• Interleaving minimizes input filter capacitor requirement

and improves EMI/EMC performance

• Synchronization of PWM frequency to external clock on

SYNC_INpin

• Adjustable output voltage: ±1.5% accuracy over

operating temperature range (‒40°C to 150°C)

• Maximized duty cycle at low V_INimproves dropout

• Soft recovery from dropout condition

The ARG81800 employs Low-Power (LP) mode to maintain

the output voltage at no load or very light load conditions while

drawing only micro-amps from V_IN. TheARG81800 includes a

PWM/AUTO control pin so the system can dynamically force

either PWM or AUTO mode by setting this pin high or low,

respectively.

IftheSYNC_INpinisdrivenbyanexternalclock,theARG81800

willbeforcedintoPWMmodeandsynchronizetotheincoming

clock.TheARG81800addsfrequencyditheringtotheSYNC_IN

clocktoreduceEMI/EMC.TheARG81800providesaCLK_OUT

pin so “downstream” regulators can be easily interleaved and

dithered via their synchronization inputs.

• Adjustable soft-start time controls inrush current to

accommodate a wide range of output capacitances

• External compensation provides flexibility to tune the

system for maximum stability or fast transient response

Continued on next page...

APPLICATIONS

• Infotainment

• Battery Powered Systems

• Industrial Systems

• Network and Telecom

• Home Audio

PACKAGE:

• Navigation Systems

• Instrument Clusters

• Audio Systems

20-pin, 4 mm × 4 mm,

QFN (ES) with wettable flank

Not to scale

• ADAS Applications

• HVAC Systems

3.5 to 36 V

1 µF

VIN

GND

BIAS

BOOT

0.1 µF

3.3 µH

PGND

3.3 V, 1 A

SW

FB

301 kΩ

20 µF

PWM/AUTO

EN

95.3 kΩ

SYNC_IN

4.7 pF

10 kΩ

PGOOD

CLK_OUT

COMP

VREG

FSET

SS

14.3 kΩ

f_SW= 2.15 MHz

2.2 nF

68 pF

22 nF

4.7 µF

40.2 kΩ

Typical Application Diagram

ARG81800-DS

MCO-0000676

June 11, 2019

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

FEATURES AND BENEFITS

DESCRIPTION

• Enable input can command ultralow 1 µA shutdown current

• Open-drain PGOOD output with rising delay

• Pre-bias startup allows quick restart and avoids reset

• Overvoltage, pulse-by-pulse current limit, hiccup mode short

circuit, and thermal protections

The ARG81800 has external compensation, so it can be tuned to

satisfy a wide range of system goals with many different external

componentsoverawiderangeofPWMfrequencies.TheARG81800

includes adjustable soft start to minimize inrush current. The

ARG81800 monitors the feedback voltage to provide an open-drain

power good signal. The Enable input can command an ultra-low

current shutdown mode with V_OUT= 0 V.

• Robust FMEA: pin open/short and component faults

Extensive protection features of the ARG81800 include pulse-by-

pulse current limit, hiccup mode short circuit protection, BOOT

open/short voltage protection, V_INundervoltage lockout, V_OUT

overvoltage protection, and thermal shutdown. The ARG81800 is

supplied in a low profile 20-pin wettable flank QFN package (suffix

“ES”) with exposed power pad.

SELECTION GUIDE

Part Number

DC Current

1 A

Package

Packing

Lead Frame

ARG81800KESJSR

ARG81800KESJSR-1

20-pin wettable flank QFN

package with thermal pad

6000 pieces per 13-inch reel

100% matte tin

0.5 A

*Contact Allegro for additional packing options

Table of Contents

Low-Power (LP) Mode..................................................... 20

Protection Features......................................................... 21

Undervoltage Lockout (UVLO) ...................................... 21

Pulse-by-Pulse Peak Current Protection (PCP)............... 21

Overcurrent Protection (OCP) and Hiccup Mode ............. 21

BOOT Capacitor Protection .......................................... 22

Asynchronous Diode Protection .................................... 22

Overvoltage Protection (OVP)....................................... 22

SW Pin Protection ....................................................... 22

Pin-to-Ground and Pin-to-Short Protections.................... 22

Thermal Shutdown (TSD)............................................. 23

Application Information ....................................................... 25

Design and Component Selection ..................................... 25

PWM Switching Frequency (R_FSET) ............................... 25

Output Voltage Setting ................................................. 25

Output Inductor (L_O) .................................................... 26

Output Capacitors (C_O) ................................................ 27

Output Voltage Ripple – Ultralow-I_QLP Mode ................. 28

Input Capacitors.......................................................... 29

Bootstrap Capacitor..................................................... 29

Soft Start and Hiccup Mode Timing (C_SS) ....................... 29

Compensation Components (R_Z, C_Z, and C_P) ................. 30

Power Stage............................................................... 30

Error Amplifier............................................................. 31

A Generalized Tuning Procedure................................... 32

Power Dissipation and Thermal Calculations ......................... 34

EMI/EMC Aware PCB Design .............................................. 36

Typical Reference Designs.................................................. 39

Package Outline Drawing.................................................... 41

Features and Benefits........................................................... 1

Description.......................................................................... 1

Package ............................................................................. 1

Typical Application Diagram................................................... 1

Selection Guide ................................................................... 2

Absolute Maximum Ratings................................................... 3

Thermal Characteristics ........................................................ 3

Functional Block Diagram ..................................................... 4

Pinout Diagram and Terminal List........................................... 5

Electrical Characteristics....................................................... 6

Typical Performance Characteristics......................................11

Functional Description ........................................................ 16

Overview ....................................................................... 16

Reference Voltage .......................................................... 16

Internal VREG Regulator ................................................. 16

Oscillator/Switching Frequency......................................... 16

Synchronization (SYNC_IN) and Clock Output (CLK_OUT)........ 16

Frequency Dither ............................................................ 16

Transconductance Error Amplifier ..................................... 17

Compensation Components ............................................. 18

Power MOSFETs ............................................................ 18

BOOT Regulator............................................................. 18

Soft Start (Startup) and Inrush Current Control ................... 18

Slope Compensation....................................................... 18

Pre-Biased Startup.......................................................... 19

Dropout ......................................................................... 19

PGOOD Output .............................................................. 19

Current Sense Amplifier................................................... 19

Pulse-Width Modulation (PWM) ........................................ 19

2

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS ^[1]

Characteristic

Symbol

Notes

Rating

–0.3 to 40

Unit

V

VIN, EN, SS, BIAS Pin Voltage

Continuous

_IN≤ 36 V, t < 50 ns

–0.3 ^[2]to V_IN+ 0.3

–1.0 to V_IN+ 2

V_SW– 0.3 to V_SW+ 5.5

V_SW– 0.3 to V_SW+ 7.0

–0.3 to 5.5

V

SW Pin Voltage

V_SW

V

Continuous

V

BOOT Pin Voltage

V_BOOT

t < 1 ms

V

All Other Pin Voltages

V

Operating Junction Temperature

Storage Temperature

T_J(max)

T_stg

–40 to 150

°C

–55 to 150

^[1]Stresses beyond the ratings listed in this table may cause permanent damage to the device. The Absolute Maximum ratings are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to Absolute Maximum-rated

conditions for extended periods may aﬀect device reliability.

^[2]This voltage is a function of temperature.

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information

Characteristic

Symbol

Test Conditions ^[3]

Value

Unit

Package Thermal Resistance

R_qJA

On 4-layer PCB based on JEDEC standard

37

°C/W

^[3]Additional thermal information available on the Allegro website.

3

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

VIN

Bias

VREG

LD

EN

UVLO

3.55 V

3.3 V

Bias

>3.15V

REGOK

BOOT

BOOT REG

LDO

BG

0.8 V

Bias

BIAS

OOV

EN_d

21.6 V

5.4 V

VREG

Current

Sense Amp

G_cs

REGOK

2.5V

EN

t_DIS

FB

t_off

Div 2 or 4

Start up or Hiccup

or Drop out

LXGND_SC

Protection & Fault

VINLX_SC

PLL+

Dither

FSET

OSC

500mΩ

TSD

SYNC_IN

HD

CLK

SW

CLK_OUT

PWM

COMP

PWM/LP

Control

Logic

T/2

Slope

Compensation

VREG

210 mΩ

LD

Ramp

Offset

MODE

PWM/

AUTO

PGND

0.74 V

GND

FBUV

PGOOD

FBOV

0.88 V

Overcurrent

Clamp

Delay

Hiccup, Dropout,

Stop-Start Recovery,

Fault, Startup

Error Amp

FB

0.8 V

SS

Offset

MODE

LP Comparator

FB

LP

Clamp

SLEEP

0.804 V

MODE

COMP

Functional Block Diagram

4

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

PINOUT DIAGRAM AND TERMINAL LIST

Terminal List Table

Number

Name

Function

This pin supplies the drive for the high-side N-channel MOSFET. Connect a 100 nF

ceramic capacitor from BOOT to SW. Do not add any external resistor in series with the

boot capacitor.

1

BOOT

SW

SS

1

2

3

4

5

15 VREG

14 FB

Regulator switch node output pins. Connect these pins to power inductor with a short

and wide PCB trace.

2, 3

4

SW

SS

PAD

13 BIAS

12 PGOOD

11 COMP

Soft start pin. Connect a capacitor, C_SS, from this pin to GND to set the start-up time.

This capacitor also determines the hiccup period during overcurrent.

EN

This pin must be set high to enable the ARG81800. If this pin is low, the ARG81800 will

enter a very low current shutdown or “SLEEP” state where V_OUT= 0 V. If the application

5

6

7

EN

does not require a logic level controlled enable, then this pin can be tied directly to V_IN.

Also, if this pin is floated, it will be pulled low by an internal pull-down resistor, disabling

the ARG81800.

Dual function pin: Clock output pin for “Master” operation. Frequency dithering is added

to this pin when the ARG81800 is operating as a Master. For “Follower” operation, this

CLK_OUTpin must be connected to VREG so dithering will not be internally added to SYNC_IN; see

Figure 1. The exact functionality of this pin is dependent on the status of the SYNC_IN

pin; see Table 1 and the description for SYNC_INfor additional details.

Package ES, 20-Pin QFN

Pinout Diagram

Triple function pin: High/Low/ExtClock. Setting this pin high sets CLK_OUTto the internal

oscillator frequency (f_SW) but with 180 degree phase shift. Setting this pin low disables

SYNC_INthe CLK_OUTpin. Applying an external clock (at f_SYNC) forces PWM mode, synchronizes

the PWM switching frequency to the external clock plus dithering, and sets CLK_OUTto

the same dithered frequency but with 180 degree phase shift. See Table 1 for details.

8

9

GND

Analog ground pin.

Frequency setting pin. A resistor, R_FSET, from this pin to GND sets the oscillator

FSET

frequency, f_SW

.

PWM/

AUTO

Mode selection pin. High/Low. Setting this pin high forces PWM mode. Setting this pin

low allows AUTO changeover between PWM and LP mode based on the load current.

10

11

Output of the error amplifier and compensation node for the current mode control loop.

Connect a series RC network from this pin to GND for loop compensation.

COMP

Power good output signal. PGOOD is an open-drain output that remains low until

the output has achieved regulation for t_dPG(SU). The PGOOD pull-up resistor can be

connected to VREG, VOUT, or any external supply voltage less than 5.5 V. PGOOD will

pull low if the output voltage (V_OUT) is out of range.

12

PGOOD

Connect this pin to the output of the regulator. This pin supplies the internal circuitry

when the voltage level is high enough.

13

14

15

BIAS

FB

Feedback (negative) input to the error amplifier. Connect a resistor divider from the

regulators output, V_OUT, to this pin to program the output voltage.

Internal voltage regulator bypass capacitor pin. Connect a 4.7 µF capacitor from this pin

to PGND and place it very close to the ARG81800.

VREG

16, 17

18

PGND

NC

Power ground pins for the lower MOSFET, gate driver, and BOOT charge circuit.

No connection.

Power input for the control circuits and the drain of the internal high-side N-channel

MOSFET. Bypass VIN to PGND with an X7R or X8R ceramic capacitor. Place the

capacitor as close to the VIN and PGND pins as possible. Additional capacitors

may be required depending on the application to comply with EMC requirements.

19, 20

VIN

Exposed pad of the package providing enhanced thermal dissipation. This pad must be

connected to the ground plane of the PCB with at least 6 vias directly in the pad.

‒

PAD

5

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

ELECTRICAL CHARACTERISTICS: Valid at 3.5 V ≤ V_IN≤ 36 V, –40°C ≤ T_J≤ 150°C, unless otherwise speciﬁed

Characteristics

INPUT VOLTAGE

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Input Voltage Range

V_IN

V_INmust first rise above V_INUV(ON)(max)

3.5

3.35

3.1

−

–

36

3.8

3.5

−

V

VIN UVLO Start

V_INUV(ON)

V_INUV(OFF)

V_INUV(HYS)

V_INrising

V_INfalling

3.55

3.3

VIN UVLO Stop

V

VIN UVLO Hysteresis

INPUT SUPPLY CURRENT

Input Shutdown Current ^[2]

Input Current, PWM Mode ^[2]

250

mV

I_IN(SD)

V_IN= 12 V, V_EN= 0, V_SW= V_IN, T_J= 25°C

V_IN= 12 V, V_EN= 2 V, no load, no switching

V_IN= 12 V, I_OUT= 0 µA, T_J= 25°C

−

1

5

2

6.5

−

µA

mA

µA

I_IN(PWM)

8

3.3 V_OUTLP Input Current ^[3][4]

5.0 V_OUTLP Input Current ^[3][4]

I_LP(3.3V)

V

_IN= 12 V, I_OUT= 50 µA, T_J= 25°C

V_IN= 12 V, I_OUT= 0 µA, T_J= 25°C

_IN= 12 V, I_OUT= 50 µA, T_J= 25°C

33

8

−

I_LP(5.0V)

V

44

−

REGULATION ACCURACY (FB PIN)

Feedback Voltage Accuracy

V_FB

–40°C < T_J< 150°C, V_IN≥ 3.5 V, V_FB= V_COMP

788

800

812

mV

SWITCHING FREQUENCY AND DITHERING (FSET PIN)

R_FSET= 14.3 kΩ

1.93

0.90

450

360

−

2.15

1.00

500

410

f_SW/4

±5

2.37

1.10

550

460

−

MHz

R_FSET= 34 kΩ

R_FSET= 71.5 kΩ

R_FSET= 86.6 kΩ

PWM Switching Frequency

f_SW

kHz

Dropout Switching Frequency

PWM Frequency Dither Range

PWM Dither Modulation Frequency

f_DROP

−

CLK_OUTleft open

−

±6.5

−

% of f_SW

f_DITH(RNG)

CLK_OUTconnected to VREG

−

0

f_DITH(MAG)

−

±0.5

−

PULSE WIDTH MODULATION (PWM) TIMING AND CONTROL

Minimum Controllable SW On-Time

Minimum SW Off-Time

t_ON(MIN)

t_OFF(MIN)

gm_POWER1

gm_POWER2

S_E1

V_IN= 12 V, I_OUT= 0.7 A, V_BOOT– V_SW= 4.5 V

V_IN=12 V, I_OUT= 0.7 A

−

60

85

110

−

ns

ARG81800

−

2.0

1.0

900

450

100

50

A/V

COMP to SW Current Gain

ARG81800-1

−

A/V

f_SW= 2.15 MHz, ARG81800

f_SW= 2.15 MHz, ARG81800-1

f_SW= 252 kHz, ARG81800

f_SW= 252 kHz, ARG81800-1

650

325

75

35

−

1100

550

125

65

mA/µs

mV

S_E2

Slope Compensation

S_E3

S_E4

PWM Ramp Offset

V_PWM(OFFS)

650

−

Continued on next page...

6

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ V_IN≤ 36 V, –40°C ≤ T_J≤ 150°C, unless otherwise speciﬁed

Characteristics

LOW-POWER (LP) MODE

LP Output Voltage Ripple ^[3][4]

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

ΔV_OUT(LP)

I_PEAK(LP1)

I_PEAK(LP2)

LP Mode, 8 V < V_IN< 12 V

−

65

−

mV

mA

ARG81800, No Load, V_IN= 12 V

ARG81800-1, No Load, V_IN= 12 V

320

160

400

212

500

270

Low I_QPeak Current Threshold

INTERNAL POWER SWITCHES

High-Side MOSFET On-Resistance

T_J=25°C ^[3], V_BOOT– V_SW= 4.5 V, I_DS= 800 mA

T_J= 150°C, V_BOOT– V_SW= 4.5 V, I_DS= 800 mA

T_J=25°C ^[3], V_IN≥ 4.5 V, I_DS= 1 A

−

500

−

600

1075

250

450

1.5

25

mΩ

µA

R_DS(on)HS

−

210

−

Low-Side MOSFET On-Resistance

R_DS(on)LS

T_J=150°C, V_IN≥ 4.5 V, I_DS= 1 A

−

High-Side Leakage Current ^[5]

Low-Side Leakage Current

I_LKG(HS)

t_NO

T_J= 25°C, V_IN= 12 V, V_EN= 0 V, V_SW= 0 V

T_J= 25°C, V_IN= 12 V, V_EN= 0 V, V_SW= 12 V

−1.5

−

µA

Gate Drive Non-Overlap Time ^[3]

Switch Node Rising Slew Rate

10

5

ns

SR_HS

12 V < V_IN< 16 V ^[3]

−

V/ns

MOSFET CURRENT PROTECTION THRESHOLDS

I_LIMHS1

t_ON= t_ON(MIN), ARG81800

t_ON= t_ON(MIN), ARG81800-1

1.7

2.0

1.0

2.3

A

High-Side Current Limit

I_LIMHS2

0.85

1.15

% of

I_LIMHSx

Low-Side Current Limit

I_LIMLSx

−

50

−

SYNCHRONIZATION INPUT (SYNC_INPIN)

Synchronization Frequency Range

SYNC_INDuty Cycle

f_SW(SYNC)

0.25

20

80

−

50

2.5

70

−

MHz

%

DC_SYNC

t_PWSYNC

V_SYNC(HI)

V_SYNC(LO)

V_SYNC(HYS)

I_SYNC

SYNC_INPulse Width

−

ns

V

V_SYNC(IN)rising

V_SYNC(IN)falling

1.35

1.2

150

±1

1.5

−

SYNC_INVoltage Thresholds

0.8

−

V

SYNC_INHysteresis

V_SYNC(HI)‒ V_SYNC(LO

)

−

mV

µA

SYNC_INPin Current

V_SYNC(IN)= 5 V

−

CLOCK OUTPUT (CLK_OUTPIN)

R_FSET= 14.3 kΩ, V_SYNC(HI)= 3.3 V,

Dither disabled

1/(2×f_SW

± 70

)

SYNC_INto CLK_OUTDelay

Ф_SYNC(CLK)

Ф_SWM(SWF)

−

ns

1/(2×f_SW

± 30

SW_MASTERto SW_FOLLOWERDelay ^[3]

R_FSET= 14.3 kΩ, V_SYNC(HI)= 3.3 V

V_CLK(OUT)H

V_CLK(OUT)L

V_VREG= 4.8 V

2.2

−

V

CLK_OUTOutput Voltages

−

0.6

Continued on next page...

7

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ V_IN≤ 36 V, –40°C ≤ T_J≤ 150°C, unless otherwise speciﬁed

Characteristics

ERROR AMPLIFIER

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

Feedback Input Bias Current ^[2]

Open-Loop Voltage Gain

I_FB

V_FB= 800 mV

–40

−

–

–15

−

nA

dB

A_VOL

65

V

_FB> 400 mV

550

275

−

750

375

±75

1

950

550

−

μA/V

μA

Transconductance

gm

0 V < V_FB< 400 mV

Output Current

I_EA

COMP Pull-Down Resistance

SOFT START

R_COMP

FAULT = 1 or HICCUP = 1

−

kΩ

Startup (Source) Current

Hiccup/Dropout (Sink) Current

Soft Start Delay Time ^[3]

Soft Start Ramp Time ^[3]

FAULT/HICCUP Reset Voltage

I_SS

I_HIC

HICCUP = FAULT = 0

HICCUP = 1 or Dropout Mode

C_SS= 22 nF

−30

1

−20

2.2

−10

5

µA

µs

t_dSS

−

440

880

200

−

t_SS

C_SS= 22 nF

−

µs

V_SSRST

V_SSfalling due to HICCUP or FAULT

−

275

mV

Hiccup OCP (and LP) Counter Enable

Threshold

V_HIC/LP(EN)

V_SSrising

−

2.3

−

V

0 V < V_FB< 200 mV

–

−

f_SW/ 4

f_SW/ 2

f_SW

–

−

–

Soft Start Frequency Foldback

f_SW(SS)

200 mV < V_FB< 400 mV

400 mV < V_FB

–

Maximum Voltage

V_SS(MAX)

R_SS(FLT)

V_EN= 0 V or FAULT without HICCUP

V_VREG

2

−

Pull-Down Resistance

HICCUP MODE COUNTS

kΩ

f_SW

counts

High-Side Overcurrent Count

SW Short-to-Ground Count

BOOT Short Circuit Count

BOOT Open Circuit Count ^[3]

HIC_OC

After V_SS> V_HIC/LP(EN)

−

120

2

−

f_SW

counts

HIC_SW(GND)

HIC_BOOT(SC)

HIC_BOOT(OC)

f_SW

counts

120

7

f_SW

counts

Continued on next page...

8

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ V_IN≤ 36 V, –40°C ≤ T_J≤ 150°C, unless otherwise speciﬁed

Characteristics

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

OUTPUT VOLTAGE PROTECTION THRESHOLDS (VFB, OV, UV)

VFB OV PWM Threshold

V_FB(OV)

V_FB(OV,HYS)V_FBfalling, relative to V_FB(OV)

V_FB(UV)V_FBfalling

V_FB(UV,HYS)V_FBrising, relative to V_FB(UV)

V_FBrising

850

–

880

−15

740

+15

700

900

–

mV

VFB OV PWM Hysteresis

VFB UV PWM Threshold

716

–

764

–

VFB UV PWM Hysteresis

VFB UV LP Mode Threshold ^[3]

POWER GOOD OUTPUT (PGOOD PIN)

PGOOD Startup (SU) Delay

PGOOD Undervoltage (UV) Delay

V_FB(UV,LP)

V_FBfalling

665

735

t_dPG(SU)

t_dPG(UV)

Increasing V_FBdue to startup

Decreasing VFB

−

30

−

µs

f_SW

cycles

PGOOD Overvoltage (OV) Delay

t_dPG(OV)

After an overvoltage event

−

240

−

PGOOD Low Voltage

V_PG(L)

I_PGOOD= 5 mA

−

200

400

2

mV

µA

PGOOD Leakage ^[1]

I_PG(LKG)

V_PGOOD= 5.5 V

−

PWM/AUTO INPUT

PWM/AUTO High Threshold

PWM/AUTO Float Voltage

PWM/AUTO Low Threshold

V_HI(PWM)

V_PWM/AUTOrising

1.8

1.1

0.6

2.0

1.4

0.8

2.5

1.7

1.0

V

V_FLOAT(PWM)V_PWM/AUTOfloating

V_LO(PWM)

t_dPWM(LP)

V_PWM/AUTOfalling

V_PWM/AUTO= 0 V, V_SS> V_HIC/LP(EN)

PGOOD high

,

PWM to LP Transition Delay ^[3]

−

7.5

−

ms

ENABLE INPUT (EN PIN)

Enable High Threshold

Enable Low Threshold

Enable Input Hysteresis

V_ENHI

V_ENLO

V_ENHYS

V_ENrising

−

0.8

−

1.6

1.4

200

2.0

−

V

V_ENfalling

V_ENHI‒ V_ENLO

−

mV

V_ENtransitions low to when SW stops

switching

f_SW

cycles

Disable Delay

t_DISDLY

−

120

12

−

Enable Pin Input Current

I_EN

V_EN= V_PWM/AUTO= 5 V

µA

Continued on next page...

9

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ V_IN≤ 36 V, –40°C ≤ T_J≤ 150°C, unless otherwise speciﬁed

Characteristics

BOOT REGULATOR (BOOT PIN)

BOOT Charging Frequency

BOOT Voltage

Symbol

Test Conditions

Min.

Typ.

Max.

Unit

f_BOOT

−

f_SW

4.8

−

V_BOOT

V_IN= 12 V, V_BOOT– V_SW

5.3

V

INTERNAL REGULATOR (VREG PIN)

BIAS Disconnected

V_VREG1

V_VREG2

V_BIAS

6 V < V_VIN< 36 V, V_BIAS= 0 V

VBIAS = 3.3V

4.5

2.85

4.5

4.8

3.2

4.8

−

5.1

3.29

5.1

36

V

BIAS Connected

6 V < V_BIAS< 20 V

BIAS Input Voltage Range

3.3

THERMAL SHUTDOWN PROTECTION (TSD)

T_Jrising, PWM stops immediately and COMP

and SS are pulled low

TSD Rising Threshold ^[3]

TSD Hysteresis ^[3]

T_TSD

155

170

20

−

°C

T_SDHYS

T_Jfalling, relative to T_TSD

−

^[1]Negative current is deﬁned as coming out of the node or pin, positive current is deﬁned as going into the node or pin.

^[2]Thermally limited depending on input voltage, duty cycle, regulator load currents, PCB layout, and airﬂow.

^[3]Ensured by design and characterization, not production tested.

[4]

Using recommended external components speciﬁed in Table 3.

At V_IN= 36 V, I_OUT= 0 A, and T_J= 150°C, V_OUTrises to overvoltage threshold due to leakage.

[5]

10

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_EN= 12 V, C_BOOT= 0.1 µF, C_SS= 22 nF, unless otherwise noted −40°C ≤ T_J≤ 150°C. Typical Values are at T_A= 25°C.

ARG81800, V_OUT= 3.3 V, f_SW= 2.15 MHz. See Table 3 for External Component Values.

ARG81800-1, V_OUT= 5.0V, f_SW= 0.4 MHz. See Table 3 for External Component Values.

4

5

4.8

4.6

4.4

4.2

4

5

4.8

4.6

4.4

4.2

4

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3

3.8

3.6

3.4

3.2

3

3.8

3.6

3.4

3.2

3

-40

-20

0

20

40

60

80

100

120

140

160

3.5

8.5

13.5

18.5

23.5

28.5

33.5

38.5

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

Input Voltage (V)

Temperature (°C)

UVLO Stop

UVLO Start

No Load Input Current, PWM Mode

UVLO Start and Stop Thresholds

vs. Temperature

No-Load Input Current (PWM Mode)

vs. Input Voltage

No-Load Input Current (PWM Mode)

vs. Temperature

2

10

5

1.9

9

8

7

6

5

4

3

2

1

0

4.5

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

4

3.5

3

2.5

2

1.5

1

0.5

0

-40

-20

0

20

40

60

80

100

120

140

160

3.5

8.5

13.5

18.5

23.5

28.5

33.5

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

Input Voltage (V)

Temperature (°C)

EN High Threshold

EN Low Threshold

Input Shutdown Current

No Load Input Current, HLP Mode

Input Current

vs. Input Voltage

Input Shutdown Current

vs. Temperature

EN High and Low Thresholds

vs. Temperature

800

805

5.1

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.5

3.3

3.1

700

600

500

400

300

200

100

804

803

802

801

800

799

798

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

3.5

6.5

9.5

12.5

15.5

18.5

21.5

Temperature (°C)

Bias Voltage (V)

High-Side On Resistance

Low-Side On Resistance

Bias Pin Current, PWM Mode

Feedback Voltage

On Resistance (High-Side and Low-Side)

vs. Temperature

Bias Pin Current vs. Output Voltage

Feedback Voltage vs. Temperature

11

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_EN= 12 V, C_BOOT= 0.1 µF, C_SS= 22 nF, unless otherwise noted −40°C ≤ T_J≤ 150°C. Typical Values are at T_A= 25°C.

ARG81800, V_OUT= 3.3 V, f_SW= 2.15 MHz. See Table 3 for External Component Values.

ARG81800-1, V_OUT= 5.0V, f_SW= 0.4 MHz. See Table 3 for External Component Values.

70

65

60

55

50

45

40

35

1.1

1.05

1

2.1

2.05

2

0.95

0.9

1.95

1.9

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

High-Side Current Limit - ARG81800-1

Minimum On Time

Minimum Off Time

High-Side Current Limit - ARG81800

High-Side Current Limit vs. Temperature –

Minimum On and Oﬀ Time

High-Side Current Limit vs. Temperature

ARG81800-1

vs. Temperature

– ARG81800

0.1

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

-20

-21

-22

-23

-24

-25

-26

-27

-28

-29

-30

40

35

30

25

20

15

10

5

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

PGOOD Leakage Current

Feedback Input Bias Current

PGOOD UV/SU Delay

PGOOD Leakage Current

vs. Temperature

Feedback Input Bias Current

vs. Temperature

PGOOD Delay (UV and SU)

vs. Temperature

2.18

2.17

2.16

2.15

2.14

2.13

2.12

2.11

2.1

200

180

160

140

120

100

80

900

880

860

840

820

800

780

760

740

720

700

60

2.09

2.08

40

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

PGOOD Low Voltage

FB OV Threshold, PWM Mode

FB UV Threshold, PWM Mode

RFSET = 14.3 kΩ

PGOOD Low Voltage

vs. Temperature

Feedback OV and UV Threshold

vs. Temperature

Switching Frequency

vs. Temperature

12

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_EN= 12 V, C_BOOT= 0.1 µF, C_SS= 22 nF, unless otherwise noted −40°C ≤ T_J≤ 150°C. Typical Values are at T_A= 25°C.

ARG81800, V_OUT= 3.3 V, f_SW= 2.15 MHz. See Table 3 for External Component Values.

ARG81800-1, V_OUT= 5.0V, f_SW= 0.4 MHz. See Table 3 for External Component Values.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

0.001

0.01

0.1

1

0.001

0.01

0.1

0.5

Load Current (A)

VIN = 8 V, HLP Mode

VIN = 8 V, PWM Mode

VIN = 12 V, HLP Mode

VIN = 12 V, PWM Mode

VIN = 16 V, HLP Mode

VIN = 16 V, PWM Mode

VIN = 8 V, HLP Mode

VIN = 8 V, PWM Mode

VIN = 12 V, HLP Mode

VIN = 12 V, PWM Mode

VIN = 16 V, HLP Mode

VIN = 16 V, PWM Mode

Eﬃcency vs. Load Current

V_OUT= 3.3 V, f_SW= 2.15 MHz

V_OUT= 5.0 V, f_SW= 400 kHz

1

0.8

0.6

0.4

0.2

0

0.1

0.08

0.06

0.04

0.02

0

-0.2

-0.4

-0.6

-0.8

-1

-0.02

-0.04

-0.06

-0.08

-0.1

0.05

0.1

0.15

0.2

0.25

0.3

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Load Current (A)

VIN = 8 V

VIN = 12 V

VIN = 16 V

VIN = 8 V

VIN = 12 V

VIN = 16 V

Load Regulation

V_OUT= 3.3 V, f_SW= 2.15 MHz, LP Mode

Load Regulation

V_OUT= 5.0 V, f_SW= 400 kHz, PWM Mode

1

0.8

0.6

0.4

0.2

0

0.06

0.04

0.02

0

-0.2

-0.4

-0.6

-0.8

-1

-0.02

-0.04

-0.06

5.5

10.5

15.5

20.5

25.5

30.5

35.5

7

12

17

22

27

32

36

Input Voltage (V)

IOUT = 0 A

IOUT = 0.15 A

IOUT = 0 A

IOUT = 0.25 A

IOUT = 0.5 A

Line Regulation

V_OUT= 3.3 V, f_SW= 2.15 MHz, LP Mode

Line Regulation

V_OUT= 5.0 V, f_SW= 400 kHz, PWM Mode

13

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_EN= 12 V, C_BOOT= 0.1 µF, C_SS= 22 nF, unless otherwise noted −40°C ≤ T_J≤ 150°C. Typical Values are at T_A= 25°C.

ARG81800, V_OUT= 3.3 V, f_SW= 2.15 MHz. See Table 3 for External Component Values.

ARG81800-1, V_OUT= 5.0V, f_SW= 0.4 MHz. See Table 3 for External Component Values.

ꢀ

_ꢎNꢃ 5 ꢀꢄꢅꢆꢀ

_ꢁUꢂꢃ 1 ꢀꢄꢅꢆꢀ

ꢀ

_ꢎNꢃ 5 ꢀꢄꢅꢆꢀ

ꢀ

_ꢎNꢃ 5 ꢀꢄꢅꢆꢀ

_ꢁUꢂꢃ ꢇ ꢀꢄꢅꢆꢀ

ꢀ

ꢀ_SSꢃ ꢇ ꢀꢄꢅꢆꢀ

ꢀ

ꢀ_SSꢃ ꢇ ꢀꢄꢅꢆꢀ

_ꢉꢁꢃ 1 Aꢄꢅꢆꢀ

ꢀ_ꢁUꢂꢃ 1 ꢀꢄꢅꢆꢀ

_{Pꢈꢁꢁꢅ}ꢃ 5 ꢀꢄꢅꢆꢀ

ꢀ

ꢆ

ꢀ_{Pꢈꢁꢁꢅ}ꢃ 5 ꢀꢄꢅꢆꢀ

1 msꢄꢅꢆꢀ

100 ꢍsꢄꢅꢆꢀ

1 msꢄꢅꢆꢀ

Startꢀuꢁ with ꢂN rising

Shutꢀdown with ꢂN ꢇalling

Preꢀꢈias Startꢀuꢁ with ꢂN rising

V_OUTꢃ ꢄ.ꢄ V, I_OUTꢃ 1.0 A, Pꢅꢆ ꢆode

ꢀ

_Sꢏꢃ 10 ꢀꢄꢅꢆꢀ

ꢀ_ꢎNꢃ 5 ꢀꢄꢅꢆꢀ

ꢀ_SSꢃ ꢇ ꢀꢄꢅꢆꢀ

ꢀ

_Sꢏꢃ 10 ꢀꢄꢅꢆꢀ

ꢀ_ꢁUꢂꢊAꢋꢌꢃ ꢇ0 mꢀꢄꢅꢆꢀ

ꢀ

_ꢁUꢂꢃ ꢇ ꢀꢄꢅꢆꢀ

ꢀ_ꢁUꢂꢊAꢋꢌꢃ 100 mꢀꢄꢅꢆꢀ

ꢆ_ꢉꢃ 500 mAꢄꢅꢆꢀ

_{Pꢈꢁꢁꢅ}ꢃ 5 ꢀꢄꢅꢆꢀ

ꢀ_{Pꢈꢁꢁꢅ}ꢃ ꢇ ꢀꢄꢅꢆꢀ

500 nsꢄꢅꢆꢀ

10 ꢍsꢄꢅꢆꢀ

ꢇ00 ꢍsꢄꢅꢆꢀ

Preꢀꢈias Shutꢀdown with ꢂN ꢇalling

V_OUTꢃ ꢄ.ꢄ V, I_OUTꢃ 1.0 A, Pꢅꢆ ꢆode

SteadyꢀState Perꢇormance

V_OUTꢃ ꢄ.ꢄ V, I_OUTꢃ 1.0 A, Pꢅꢆ ꢆode

SteadyꢀState Perꢇormance

V_OUTꢃ ꢄ.ꢄ V, I_OUTꢃ 10 mA, LP ꢆode

ꢀ_Sꢏꢃ 10 ꢀꢄꢅꢆꢀ

ꢀ_ꢁUꢂꢊAꢋꢌꢃ ꢇ00 mꢀꢄꢅꢆꢀ

ꢀ_ꢁUꢂꢊAꢋꢌꢃ 100 mꢀꢄꢅꢆꢀ

ꢀ_ꢁUꢂꢊAꢋꢌꢃ 50 mꢀꢄꢅꢆꢀ

ꢆ_ꢉꢃ 500 mAꢄꢅꢆꢀ

ꢆ

_ꢁUꢂꢃ 500 mAꢄꢅꢆꢀ

ꢆ_ꢁUꢂꢃ 500 mAꢄꢅꢆꢀ

ꢐ0 mAꢄꢍs

ꢀ_{Pꢈꢁꢁꢅ}ꢃ ꢇ ꢀꢄꢅꢆꢀ

5 ꢍsꢄꢅꢆꢀ

ꢇ00 ꢍsꢄꢅꢆꢀ

SteadyꢀState Perꢇormance

V_OUTꢃ ꢄ.ꢄ V, I_OUTꢃ 100 mA, LP ꢆode

Load Transient Perꢇormance

V_OUTꢃ ꢄ.ꢄ V, Pꢅꢆ ꢆode

Load Transient Perꢇormance

V_OUTꢃ ꢄ.ꢄ V, LP ꢆode

14

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN= V_EN= 12 V, C_BOOT= 0.1 µF, C_SS= 22 nF, unless otherwise noted −40°C ≤ T_J≤ 150°C. Typical Values are at T_A= 25°C.

ARG81800, V_OUT= 3.3 V, f_SW= 2.15 MHz. See Table 3 for External Component Values.

ARG81800-1, V_OUT= 5.0V, f_SW= 0.4 MHz. See Table 3 for External Component Values.

ꢀ_Sꢎꢄ 10 ꢀꢅꢃꢆꢀ

ꢀ

_ꢂUꢇꢈAꢉꢊꢄ 100 mꢀꢅꢃꢆꢀ

ꢀ_ꢂUꢇꢈAꢉꢊꢄ 100 mꢀꢅꢃꢆꢀ

ꢀ

_ꢂUꢇꢈAꢉꢊꢄ 100 mꢀꢅꢃꢆꢀ

ꢋ0 mAꢅꢌs

_ꢂUꢇꢄ 500 mAꢅꢃꢆꢀ

ꢀ_{Pꢁꢂꢂꢃ}ꢄ 5 ꢀꢅꢃꢆꢀ

ꢆ_ꢂUꢇꢄ 500 mAꢅꢃꢆꢀ

ꢀ_{Pꢁꢂꢂꢃ}ꢄ 5 ꢀꢅꢃꢆꢀ

ꢆ

ꢋ00 ꢌsꢅꢃꢆꢀ

ꢀ

_SꢍNꢉꢆNꢄ 5 ꢀꢅꢃꢆꢀ

5 ꢌsꢅꢃꢆꢀ

Load Transient Perꢆormance

V_OUTꢇ 5.0 V, Pꢉꢊ ꢊode

Load Transient Perꢆormance

V_OUTꢇ 5.0 V, LP ꢊode

ꢋꢌternal Clock Synchroniꢍation

V_OUTꢇ ꢈ.ꢈ V, ꢆ_Sꢉꢇ ꢃ.15 ꢊꢎꢍ, ꢆ_ꢋꢏTꢇ 1 ꢊꢎꢍ

ꢀ_SꢎꢈMASꢇꢐRꢊꢄ 5 ꢀꢅꢃꢆꢀ

ꢀ_Sꢎꢄ 10 ꢀꢅꢃꢆꢀ

ꢀ_ꢆNꢄ 10 ꢀꢅꢃꢆꢀ

ꢀ_ꢂUꢇꢄ ꢋ ꢀꢅꢃꢆꢀ

ꢀ_SSꢄ ꢋ ꢀꢅꢃꢆꢀ

ꢀ

_Sꢎꢈꢏollowerꢊꢄ 5 ꢀꢅꢃꢆꢀ

ꢀ_{Pꢁꢂꢂꢃ}ꢄ ꢋ ꢀꢅꢃꢆꢀ

ꢆ_ꢂUꢇꢄ 1 Aꢅꢃꢆꢀ

ꢀ_ꢂUꢇꢄ ꢋ ꢀꢅꢃꢆꢀ

_{Pꢁꢂꢂꢃ}ꢄ 5 ꢀꢅꢃꢆꢀ

ꢀ

100 msꢅꢃꢆꢀ

5 msꢅꢃꢆꢀ

500 nsꢅꢃꢆꢀ

Interleaꢅed Clock Generation

V_OUTꢇ 5.0 V, ꢆ_Sꢉꢇ 500 kꢎꢍ, Pꢉꢊ ꢊode

Outꢐut Short Protection

V_OUTꢇ ꢈ.ꢈ V, Pꢉꢊ ꢊode

ISO 1ꢀꢁ50ꢂꢃꢄ Load Dumꢐ Pulse

V_OUTꢇ ꢈ.ꢈ V, I_OUTꢇ 1.0A, Pꢉꢊ ꢊode

10 sꢅꢃꢆꢀ

50 sꢅꢃꢆꢀ

ꢀ_ꢆNꢄ 5 ꢀꢅꢃꢆꢀ

ꢀ_ꢂUꢇꢄ ꢋ ꢀꢅꢃꢆꢀ

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_{Pꢁꢂꢂꢃ}ꢄ ꢋ ꢀꢅꢃꢆꢀ

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_ꢂUꢇꢄ 1 Aꢅꢃꢆꢀ

ꢆ_ꢂUꢇꢄ 1 Aꢅꢃꢆꢀ

ꢋ00 msꢅꢃꢆꢀ

V_INSlow Ramꢐ Uꢐ and Ramꢐ Down

V_OUTꢇ ꢈ.ꢈ V, I_OUTꢇ 1.0 A, Pꢉꢊ ꢊode

ISO 1ꢀꢁ50ꢂꢃꢄ Leꢅel 1 Starting Proꢆile

_OUTꢇ ꢈ.ꢈ V, I_OUTꢇ 1.0 A, Pꢉꢊ ꢊode

ISO 1ꢀꢁ50ꢂꢃꢄ Reset Voltage Proꢆile

V

_OUTꢇ ꢈ.ꢈ V, I_OUTꢇ 1.0 A, Pꢉꢊ ꢊode

15

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

FUNCTIONAL DESCRIPTION

quency of the oscillator by connecting an FSET resistor from the

FSET pin to GND. The internal clock has an accuracy of about

Overview

The ARG81800 is a wide input voltage (3.5 to 36 V) synchronous

PWM buck regulator that integrates low R_DS(on)high-side and

low-side N-channel MOSFETs. The ARG81800 employs peak

current mode control to provide superior line and load regulation,

cycle-by-cycle current limit, fast transient response, and simple

compensation. The features of the ARG81800 include ultralow

I_QLP mode, extremely low minimum on-time, maximized duty

cycle for low dropout operation, soft recovery from dropout con-

dition, and pre-bias startup capability.

±10% over the operating temperature range. Usually, an FSET

resistor with ±1% tolerance is recommended. A graph of switch-

ing frequency versus FSET resistor value is shown in the Design

and Component Selection section. The ARG81800 will suspend

operation if the FSET pin is shorted to GND or left open.

Synchronization (SYNC_IN) and Clock Output

(CLK_OUT

)

The Phase-Locked Loop (PLL) in the ARG81800 allows its inter-

nal oscillator to be synchronized to an external clock applied on the

SYNC_INpin. If the SYNC_INpin is driven by an external clock, the

ARG81800 will be forced to operate in PWM mode, with synchro-

nized switching frequency, overriding the mode selection on the

PWM/AUTO pin. The external clock must also satisfy the pulse

width, duty cycle, and rise/fall time requirements shown in the

Electrical Characteristics table. If the SYNC_INpin is continuously

pulled high, the ARG81800 outputs a 180-degree phase-shifted

internal oscillator clock on the CLK_OUTpin, so “downstream”

ARG81800 devices can be easily interleaved via their synchro-

nization inputs. Figure 1 shows the usage of multiple ARG81800

devices in master-follower configuration. If the SYNC_INpin is

continuously pulled low, the device disables the CLK_OUTpin.

Protection features of the ARG81800 include VIN undervoltage

lockout, cycle-by-cycle overcurrent protection, BOOT over-

voltage and undervoltage protection, hiccup mode short circuit

protection, overvoltage protection, and thermal shutdown. In

addition, the ARG81800 provides open circuit, adjacent pin short

circuit, and pin-to-ground short circuit protection.

Reference Voltage

The ARG81800 incorporates an internal precision reference

that allows output voltages as low as 0.8 V. The accuracy of the

internal reference is ±1.5% across –40°C to 150°C. The output

voltage of the regulator is programmed with a resistor divider

between VOUT and the FB pin of the ARG81800.

Internal VREG Regulator

Frequency Dither

VREG is used as the power supply for internal control circuitry

and a low-side MOSFET driver. The ARG81800 consists of two

internal low dropout regulators, VIN LDO and Bias LDO, to

generate VREG voltage. VIN LDO is powered from input voltage

to generate 4.8 V for VREG supply. Bias LDO uses the BIAS pin

as a supply to generate VREG voltage. When voltage at the BIAS

pin exceeds 3.0 V, VIN LDO is deactivated and Bias LDO gener-

ates the VREG voltage. Bias LDO can be made more efficient

than VIN LDO by providing an external voltage at the BIAS pin

that is less than the input voltage. If the output voltage of the

ARG81800 is programmed to be greater than 3.1 V, it is recom-

mended to supply the output voltage to the BIAS pin to improve

the efficiency of the regulator.

In addition to EMI-aware PCB layout, extensive filtering,

controlled switch node transitions, and shielding, switching

frequency dithering is an effective way to mitigate EMI concerns

in switching power supplies. Frequency dither helps to minimize

peak emissions by spreading the emissions across a wide range of

frequencies. The ARG81800 provides frequency dither by spread-

ing the switching frequency ±5% using a triangular modulated

wave of 0.5% switching frequency.

The ARG81800 is capable of adding dither to the external clock

applied on the SYNC_INpin. This unique feature allows the

minimizing of electromagnetic emissions even when the device

is using external clock. Frequency dither scheme can be disabled

by connecting the CLK_OUTpin to VREG pin. In master-follower

configuration, the CLK_OUTpin of the follower device should be

Oscillator/Switching Frequency

The PWM switching frequency of the ARG81800 is adjustable

from 250 kHz to 2.4 MHz by programming the internal clock fre- connected to VREG to avoid double-dithering.

16

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

ꢀ_SYNCꢁ ꢀ_DITꢂꢃRꢄ 180ꢅ

ꢎ_ꢈꢏ

Sꢂꢏ

ꢎRꢍꢀ

ꢊ_SꢃNꢄꢋ ꢊ_{ꢌꢅꢉHꢍR}

ARꢀꢁ1ꢁ00

Follower

ꢎ_ꢈ1

Sꢂ1

SꢃNꢄ_ꢅN

ꢄꢆꢇ_ꢈUꢉ

ARꢀꢁ1ꢁ00

Master

ꢀ_SYNCꢁ ꢀ_DITꢂꢃRꢄ 180ꢅ

ꢎ_ꢈ3

Sꢂ3

ꢊ_SꢃNꢄ

SꢃNꢄ_ꢅN

ꢄꢆꢇ_ꢈUꢉ

ꢎRꢍꢀ

ARꢀꢁ1ꢁ00

Follower

SꢃNꢄ_ꢅN

ꢄꢆꢇ_ꢈUꢉ

Figure 1: Master-Follower Conﬁguration

Table 1: PWM Frequency, CLKOUT, and Dithering Settings

PWM Frequency and Dithering

CLK_OUTFrequency and Dithering

Device

SYNC_IN

SW

Frequency

Magnitude of

Dithering

Dither Modulation

Magnitude of

Dithering

Dither Modulation

Frequency

0.005 × f_SW

Frequency

Low

High

f_SYNC

f_SW

Disabled/Off

f_SW+ 180°

None

±0.05 × f_SW

ARG81800/

ARG81800-1

±0.05 × f_SW

±0.05 × f_SYNC

0.005 × f_SW

0.005 × f_SYNC

f_SYNC

f_SYNC+ 180°

Transconductance Error Amplifier

400 mV

The transconductance error amplifier’s primary function is to

control the regulator’s output voltage. The error amplifier is a

three-terminal input device with two positive inputs and one

negative input, as shown in Figure 2. The negative input is simply

connected to the FB pin and is used to sense the feedback volt-

age for regulation. The error amplifier performs an “analog OR”

selection between its positive inputs and operates according to

the positive input with the lowest potential. The two positive

inputs are used for soft-start and steady-state regulation. The error

amplifier regulates to the soft-start pin voltage minus 400 mV

during startup and to the internal reference (VREF) during normal

operation.

Error Ampliﬁer

SS Pin

COMP

V_REF

800 mv

FB Pin

Figure 2: ARG81800 Error Ampliﬁer

17

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

start, the voltage at the SS pin will rise from 400 mV to 1.2 V (a

difference of 800 mV), the voltage at the FB pin will rise from

0 V to 800 mV, and the regulator output voltage will rise from

0 V to the set voltage determined by the feedback resistor divider.

Compensation Components

To stabilize the regulator, a series RC compensation network (R_Z

and C_Z) must be connected from the output of the error amplifier

(COMP pin) to GND as shown in the applications schematic. In

most instances, an additional low-value capacitor (C_P) should

be connected in parallel with the R_Z-C_Zcompensation network

to reduce the loop gain at very high frequencies. However, if

the C_Pcapacitor is too large, the phase margin of the converter

may be reduced. Calculation of R_Z, C_Z, and C_Pis covered in the

Component Selection section of this datasheet. If a fault occurs

or the regulator is disabled, the COMP pin is pulled to GND via

the approximately 1 kΩ internal resistor and PWM switching is

inhibited.

During startup, PWM switching frequency is reduced to 25% of

f

_SWwhile FB is below 200 mV. If FB voltage is above 200 mV

but below 400 mV, the switching frequency is 50% of f_SW. At

the same time, the transconductance of the error amplifier, gm,

is reduced to half of nominal value when FB is below 400 mV.

When FB is above 400 mV, the switching frequency will be

f

_SWand the error amplifier gain will be the nominal value. The

reduced switching frequency and error amplifier gain are neces-

sary to help improve output regulation and stability when V_OUTis

very low. During low V_OUT, the PWM control loop requires on-

time near the minimum controllable on-time and very low duty

cycles that are not possible at the nominal switching frequency.

Power MOSFETs

The ARG81800 includes a 500 mΩ, high-side N-channel MOS-

FET and a 210 mΩ, low-side N-channel MOSFET to provide

synchronous rectification. When the ARG81800 is disabled via

the EN input being low or a fault condition, its output stage is tri-

stated by turning off both the upper and lower MOSFETs.

When the voltage at the soft start pin reaches approximately

1.2 V, the error amplifier will switch over and begin regulating

the voltage at the FB pin to the fixed internal bandgap reference

voltage of 800 mV. The voltage at the soft start pin will con-

tinue to rise to the internal LDO regulator output voltage. If the

ARG81800 is disabled or a fault occurs, the internal fault latch is

set and the capacitor at the SS pin is discharged to ground very

quickly through a 2 kΩ pull-down resistor. The device will clear

the internal fault latch when the voltage at the SS pin decays to

approximately 200 mV. However, if the device enters hiccup

mode, the capacitor at the SS pin is slowly discharged through

a current sink, I_HIC. Therefore, the soft start capacitor C_SSnot

only controls the startup time but also the time between soft start

attempts in hiccup mode.

BOOT Regulator

The ARG81800 includes a BOOT regulator to supply the power

for a high-side MOSFET gate driver. The voltage across the

BOOT capacitor is typically 4.8 V. If the BOOT capacitor is

missing, the device will detect a BOOT overvoltage. Similarly,

if the BOOT capacitor is shorted, the ARG81800 will detect a

BOOT undervoltage. Also, the BOOT regulator has a current

limit to protect itself during a short-circuit condition.

Soft Start (Startup) and Inrush Current Control

Slope Compensation

The soft start function controls the inrush current at startup. The

soft start pin (SS) is connected to GND via a capacitor. When the

ARG81800 is enabled and all faults are cleared, the SS pin sources

the charging current I_SSand the voltage on the soft start capacitor

The ARG81800 incorporates internal slope compensation that

ensures stable operation at PWM duty cycles above 50% for a wide

range of input/output voltages, switching frequencies, and induc-

tor values. As shown in the functional block diagram, the slope

compensation signal is added to the sum of the current sense and

PWM Ramp Offset. The relationship between slope compensation

and adjustable switching frequency is given by

C_SSstarts ramping upward from 0 V. When the voltage at the soft

start pin exceeds the soft start offset voltage (SS Offset), typically

400 mV, the error amplifier will ramp up its output voltage above

the PWM Ramp Offset. At this instant, the top and bottom MOS-

FETs will begin switching. There is a small delay (t_dSS) from the

moment EN pin transitioning high to the moment soft start voltage

reaching 400 mV to initiate PWM switching.

Equation 1:

S_E= 12.84 / (37.037 / f_SW– 3)

where f_SWis switching frequency in MHz and S_Eis slope compen-

sation in A/µs. Internal slope compensation in ARG81800-1 is half

of that (Equation 1) in ARG81800.

Immediately after the start of PWM switching, the error amplifier

will regulate the voltage at the FB pin to the soft start pin voltage

minus approximately 400 mV. During the active portion of soft

18

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

The PGOOD output is pulled low if either an undervoltage or over-

voltage condition occurs or the ARG81800 junction temperature

Pre-Biased Startup

If the output of the buck regulator is pre-biased at a certain output

voltage level, the ARG81800 will modify the normal startup

routine to prevent discharging the output capacitors. As described

in the Soft Start (Startup) and Inrush Current Control section,

the error amplifier usually becomes active when the voltage at

the soft start pin exceeds 400 mV. If the output is pre-biased,

the voltage at the FB pin will be non-zero. The device will not

start switching until the voltage at SS pin rises to approximately

V_FB+ 400 mV. From then on, the error amplifier becomes active,

the voltage at the COMP pin rises, PWM switching starts, and

V_OUTwill ramp upward from the pre-bias level.

exceeds thermal shutdown threshold (T_SD). The PGOOD overvolt-

age and undervoltage comparators incorporate a small amount of

hysteresis (V_FB(OV,HYS), V_FB(UV,HYS)) to prevent chattering and

deglitch filtering (t_dPG(UV), t_dPG(OV)) to eliminate false triggering.

For other faults, PGOOD depends on the output voltage.

It is important that the correct status of PGOOD is reported

during either the input supply ramp up or ramp down. During a

supply ramp up, the PGOOD is designed to operate in the correct

state from a very low input voltage. Also, during supply ramp

down, the PGOOD is designed to operate in the correct state

down to a very low input voltage.

Dropout

Current Sense Amplifier

The ARG81800 is designed to operate at extremely wide duty

cycles to minimize any reduction in output voltage during drop-

out conditions (difference between input and output voltage drops

to a minimum value) such as cold crank. During dropout, if the

minimum off-time (85 ns typical) is reached for more than 5 con-

secutive switching cycles, the programmed switching frequency

f_SWis reduced by a factor of 4 and the off-time is extended to

115 ns (typical). While operating with reduced frequency, if the

device further reaches minimum off-time (115 ns typical) for

more than 35 consecutive switching cycles, it continues to oper-

ate with reduced frequency. Otherwise, the device toggles back

to the programmed switching frequency f_SW. In addition, during

dropout operation, the soft start capacitor C_SSwill discharge so

that if the input voltage increases, the output voltage recovers

with a slew rate set by the soft start ramp.

The ARG81800 incorporates a high-bandwidth current sense

amplifier to monitor the current through the top MOSFET. This

current signal is used to regulate the peak current when the top

MOSFET is turned on. The current signal is also used by the pro-

tection circuitry for the cycle-by-cycle current limit and hiccup

mode short circuit protection

Pulse-Width Modulation (PWM)

The ARG81800 employs fixed-frequency, peak current mode

control to provide excellent load and line regulation, fast transient

response, and simple compensation. A high-speed comparator and

control logic is included in the ARG81800. The inverting input

of the PWM comparator is connected to the output of the error

amplifier. The non-inverting input is connected to the sum of the

current sense signal, the slope compensation signal, and a DC

PWM Ramp offset voltage (Ramp Offset).

PGOOD Output

The ARG81800 provides a Power Good (PGOOD) status signal

to indicate if the output voltage is within the regulation limits.

Since the PGOOD output is an open-drain output, an external

pull-up resistor must be used as shown in the applications sche-

matic. PGOOD transitions high when the output voltage, sensed

at the FB pin, is within regulation.

At the beginning of each PWM cycle, the CLK signal sets the PWM

flip flop, the bottom MOSFET is turned off, the top MOSFET is

turned on, and the inductor current increases. When the voltage at

the non-inverting of PWM comparator rises above the error ampli-

fier output COMP, the PWM flip flop is reset, the top MOSFET is

turned off, the bottom MOSFET is turned on, and the inductor cur-

rent decreases. Since the PWM flip flop is reset, the dominant error

amplifier may override the CLK signal in certain situations.

During start-up, PGOOD signal exhibits an additional delay of

t_dPG(SU)after FB pin voltage reaches the regulation voltage. This

delay helps to filter out any glitches on the FB pin voltage.

19

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

When voltage on the COMP pin falls to the voltage correspond-

ing to the ultralow I_Qpeak current threshold value, an internal

Low-Power (LP) Mode

The ARG81800 operates in ultralow I_QLP mode when PWM/

AUTO pin is pulled to logic low. If the PWM/AUTO pin transi-

tions from logic high to logic low while output is in regulation,

the device waits for 7 clock cycles before entering the LP mode.

This delay provides adequate filtering to ensure no noise tran-

sients forces the device to erroneously enter LP mode.

clamp prevents the COMP voltage from falling further. This

results in a momentary rise in the FB voltage beyond LP com-

parator upper threshold which causes the LP comparator to trip.

Once the LP comparator trips, the device enters coast period

during which MOSFET switching is terminated and the associ-

ated control circuitry is also shut down. This ensures a very low

quiescent current is drawn from the input.

When LP mode is selected, the ARG81800 operates in continu-

ous conduction PWM Mode until peak inductor current decreases

to I_PEAK(LP). When peak inductor current falls below I_PEAK(LP)

the LP comparator monitors FB node and regulates the output

voltage in hysteretic manner. The reference for the LP compara-

tor is calibrated approximately 0.5% above the PWM regulation

point. The transition point from PWM to LP mode is defined by

the input voltage, output voltage, and inductor value. The exact

operation of the ARG81800 in LP mode is described below.

The coast period terminates once the FB voltage falls below the

LP comparator lower threshold. The device will fully power-up

approximately after a 2.5 μs delay and the high-side MOSFET is

repeatedly turned on, operating at the PWM switching frequency

until the voltage at the FB pin rises again above the LP compara-

tor threshold. The rate of rise of output voltage is determined by

the input voltage, output voltage, inductor value, output capaci-

tance, and load.

,

20

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

2.5

2.3

Protection Features

The ARG81800 was designed to satisfy the most demanding

automotive and non-automotive applications. In this section, a

description of each protection feature is described and Table 2

summarizes the protections and their operation.

2.1

1.9

1.7

1.5

1.3

1.1

0.9

0.7

0.5

ARꢀꢁ1ꢁ00 Maꢂ

ARꢀꢁ1ꢁ00 Min

ARꢀꢁ1ꢁ00-1 Maꢂ

ARꢀꢁ1ꢁ00-1 Min

UNDERVOLTAGE LOCKOUT (UVLO)

An undervoltage lockout (UVLO) comparator in the ARG81800

monitors the voltage at the VIN pin and keeps the regulator dis-

abled if the voltage is below the start threshold (V_INUV(ON), V_IN

rising) or the stop threshold (V_INUV(OFF), V_INfalling). The UVLO

comparator incorporates some hysteresis (V_INUV(HYS)) to help

prevent on-off cycling of the regulator due to resistive or inductive

drops in the V_INpath during heavy loading or during startup.

0

10 20 30 40 50 60 70 80 90

Duty Cycle (%)

PULSE-BY-PULSE PEAK CURRENT PROTECTION (PCP)

Figure 3: Peak Current Limit vs. Duty Cycle

The ARG81800 monitors the current in the high-side MOSFET,

and if the peak MOSFET current exceeds the pulse-by-pulse

overcurrent limit I_LIMHSx, the upper MOSFET is turned off and

the bottom MOSFET is turned on until the start of the next clock

pulse from the oscillator. The device includes leading edge blank-

ing to prevent false triggering of pulse-by-pulse current protec-

tion when the upper MOSFET is turned on.

OVERCURRENT PROTECTION (OCP)AND HICCUP MODE

An OCP counter and hiccup mode circuit protect the buck regula-

tor when the output of the regulator is shorted to ground or when

the load is too high. When the soft-start ramp is active (t < t_ss),

the OCP hiccup counter is disabled. The following two condi-

tions must be met for the OCP counter to be enabled and begin

counting:

Because of the addition of the slope compensation ramp to the

sensed inductor current, the ARG81800 can deliver more current

at minimum duty cycle and less current at maximum duty cycle.

Figure 3 illustrates the relationship between the high-side MOS-

FET peak current limit and duty cycle. As shown, the peak cur-

rent limit at minimum and maximum duty cycle remains fixed,

but the relationship versus duty cycle is skewed with frequency

due to the fixed minimum off-time. Given the relationship, it is

best to use the I_HSPKMINDand I_HSPKMAXDcurrent limits to calcu-

late the current limit at any given duty cycle.

• SS pin voltage, V_SS> V_HIC/LP(EN)(2.3 V), and

• Comp pin voltage, V_COMPclamped at its maximum

voltage (OCP = 1)

As long as these two conditions are met, the OCP counter

remains enabled and will count pulses from the overcurrent

comparator. If the COMP voltage decreases (OCP = 0), the OCP

counter is cleared. Otherwise, if the OCP counter reaches HIC_OCP

clock counts (120), PWM switching ceases, a hiccup latch is set,

and the COMP pin is quickly pulled down by a relatively low

resistance (1 kΩ). The hiccup latch also enables a small current

sink connected to the SS pin (I_HIC). This causes the voltage at

the soft start pin to slowly ramp downward. When the voltage at

the soft start pin decays to a low enough level (V_SSRST, 200 mV),

the hiccup latch is cleared, and the current sink is turned off. At

During synchronization, slope compensation scales in a similar

fashion as with R_FSETalthough with slightly less accuracy. The

exact current the buck regulators can support is heavily depen-

dent on duty cycle (V_IN, V_OUT), ambient temperature, thermal

resistance of the PCB, airflow, component selection, and nearby

heat sources.

21

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

this instant, the SS pin will begin to source current (I_SS) and the

voltage at the SS pin will ramp upward. This marks the begin-

ning of a new, normal soft start cycle as described earlier. When

the voltage at the soft start pin exceeds the error amp voltage by

approximately 400 mV, the error amplifier will force the voltage

at the COMP pin to quickly slew upward and PWM switching

will resume.

low. If the overvoltage fault is not cleared even beyond t_dPG(OV)

PGOOD is pulled low and the device continuously attempts to

reduce the output overvoltage. The output overvoltage protec-

tion threshold, at any given time, varies with the voltage on the

feedback node as shown in Figure 4. If the BIAS pin is connected

to VOUT, the maximum settable output voltage is limited to 20 V.

,

25

20

15

10

5

If the short circuit/overload at the regulator output persists,

another hiccup cycle will occur. Hiccups will repeat until the

short circuit/overload is removed or the converter is disabled. If

the short circuit/overload is removed, the device will soft start

normally and the output voltage will automatically recover to the

desired level. Thus, hiccup mode is a very effective protection for

the short-circuit/overload condition. It avoids false trigger during

short duration short-circuit/overload. On the other hand, for the

extended short-circuit/overload duration, the reduced average

power dissipation with hiccup mode of operation helps in lower-

ing the temperature rise of the device and enhancing the system

reliability.

0

100 200 300 400 500 600 700 800 900

FB Voltage (mV)

Note that OCP is the only fault that results in hiccup mode being

ignored while V_SS< 2.3 V.

Figure 4: Output Overvoltage Threshold Variation with

Increasing Feedback Voltage

BOOT CAPACITOR PROTECTION

The ARG81800 monitors the voltage across the BOOT capaci-

tor to detect if the BOOT capacitor is missing or short-circuited.

If the BOOT capacitor is missing, the regulator enters hiccup

mode after 7 clock counts. If the BOOT capacitor is shorted, the

device enters hiccup mode after 120 clock counts. Also, the boot

regulator has a current limit to protect itself during a short-circuit

condition.

SW PIN PROTECTION

Unlike most regulators, the ARG81800 protects itself when the

SW pin is shorted to ground. If the SW pin is shorted to ground,

there will be a very high current in the high-side MOSFET when

it is turned on. The ARG81800 incorporates an internal secondary

current protection to detect this unusually high current and turns

off the high-side MOSFET if the high current persists for more

than two consecutive switching cycles. After turning off the high-

side MOSFET, the device enables the hiccup latch and attempts

to restart after hiccup latch is cleared. If the short to ground is

removed, the regulator will automatically recover; otherwise, the

device continues hiccupping. Unlike other hiccup mode protec-

tions, the SW pin protection is not delayed until soft start is

completed, i.e., V_SS> 2.3 V.

For a boot fault, hiccup mode operates virtually the same as

described previously for overcurrent protection (OCP), with soft

start ramping up and down for repeated hiccups. Boot faults are

non-latched faults, so the device will automatically recover when

the fault is removed.

OVERVOLTAGE PROTECTION (OVP)

The ARG8100 consists of an always-on overvoltage protection

circuit that monitors output overvoltage on the BIAS pin, perhaps PIN-TO-GROUND AND PIN-TO-PIN SHORT PROTECTIONS

caused by the FB pin pulled to ground, high-side MOSFET leak-

The ARG81800 is designed to satisfy the most demanding

age current, or line/load transients. During an overvoltage fault

automotive applications. For example, the device has been care-

caused by any of the above events, the controller tries to reduce

fully designed to withstand a short circuit to ground at each pin

the output overvoltage by terminating the high-side MOSFET

without causing any damage to the IC.

switching and pulsing the low side MOSFET with minimum

In addition, care was taken when defining the device pinouts to

optimize protection against pin-to-pin adjacent short circuits. For

off-time (t_OFFmin) until FB returns to regulation. The ARG81800

waits for t_dPG(OV)(120) clock counts before pulling the PGOOD

22

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ARG81800

example, logic pins and high-voltage pins are separated as much as

possible. Inevitably, some low-voltage pins are located adjacent to

high voltage pins, but in these instances, the low voltage pins are

designed to withstand increased voltages, with clamps and/or series

input resistance, to prevent damage to the device.

THERMAL SHUTDOWN (TSD)

The ARG81800 monitors internal junction temperature and shuts

down the IC by disabling the switching pulses of high- and low-

side MOSFETs if the junction temperature exceeds the Thermal

Shutdown Threshold T_TSD. Also, to prepare for a restart, the

internal soft-start voltage (V_SS) and the voltage at the COMP pin

are pulled low until V_SS< V_SSRST. TSD is a non-latched fault,

so the device automatically recovers if the junction temperature

decreases by approximately 20°C.

23

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators

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ARG81800

Table 2: Summary of ARG81800 Fault Modes and Operation

During Fault Counting, before Hiccup Mode

Internal

BOOT

PGOOD

State

Latched

Fault

Reset

Fault Mode

High-Side

MOFSET

Low-Side

MOFSET

Soft Start

Charging

Condition

V_COMP

Pulled low via

2 kΩ resistor,

No Hiccup

Pulled low via

1 kΩ resistor,

No Hiccup

Automatic,

V_INabove UVLO

start threshold

V_IN

Forced

Turn-off

Forced

Turn-off

Depends on

V_REG

Disabled

NO

undervoltage

Clamped to

I_LIMHS, then

pulled low for

Hiccup

f_SW/ 4 due to

V_OUT< 25%,

responds to

V_COMP

Output

shorted to

ground

Hiccup, after

120 OCP

clock counts

Turned on if

BOOT voltage

is too low

Depends on

V_OUT

Automatic,

Short removed

Not affected

Clamped to

I_LIMHS, then

pulled low for

Hiccup

Output

overcurrent,

V_OUT> 50%

Hiccup, after

120 OCP

clock counts

Turned on if

BOOT voltage

is too low

Automatic,

Load current

decreased

f_SWresponds to

V_COMP

Depends on

V_OUT

Not affected

NO

High-side

MOSFET

overcurrent

(SW short to

GND)

Pulled low via

1 kΩ resistor

for hiccup

Hiccup, after

2 clock count

Forced

Turn-off

Forced

Turn-off

Depends on

V_OUT

Automatic,

Short removed

Pulled low via

1 kΩ resistor

for hiccup

Automatic,

Boot capacitor

replaced

Boot capacitor

open/missing

Hiccup, after

7 clock counts

Forced

Turn-off

Turned off when

fault occurs

Disabled when

fault occurs

Depends on

V_OUT

NO

Boot capacitor

shorted

(BOOTUV)

Hiccup, after

120 clock

counts

Pulled low via

1 kΩ resistor

for hiccup

Turned off

only during

hiccup

Forced

Turn-off

Disabled only

during hiccup

Depends on

V_OUT

Automatic,

Short removed

Transitions

low via loop

response

Pulsed with

Minimum

off-time

Disabled when

V_FB

is too high

Pulled low

when V_FBis

too high

Automatic,

After V_FBreturns

to normal range

Output

overvoltage

Turned-off by

low V_COMP

Not affected

Pulled Low

Not affected

Transitions

high via loop

response

Active,

Responds to

V_COMP

Turned on if

BOOT voltage

is too low

Pulled low

when V_FBis

too low

Automatic,

After V_FBreturns

to normal range

Output

undervoltage

Not affected

Disabled

FSET shorted

to GND or

above 1.0 V

Forced

Turn-off

Forced

Turn-off

Depends on

V_OUT

Pulled Low

Automatic

Transitions

low via loop

response

Pulsed with

Minimum

off-time

Disabled when

V_FB

is too high

Pulled low

when V_FBis

too high

Automatic,

After V_FBreturns

to normal range

Turned-off by

low V_COMP

FB open

Pulled low

until

V_SS< V_SSRST

and TSD = 0

Pulled low

until

V_SS< V_SSRST

and TSD = 0

Thermal

shutdown

(TSD)

Forced

Turn-off

Forced

Turn-off

Automatic,

Part cools down

Disabled

Pulled low

NO

24

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators

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ARG81800

APPLICATION INFORMATION

not occur at the maximum synchronized switching frequency (i.e.,

1.5 × f_SYNCshould be less than the frequency f_SWin Equation 3).

Design and Component Selection

PWM SWITCHING FREQUENCY (R_FSET

)

OUTPUT VOLTAGE SETTING

The PWM switching frequency is set by connecting a resistor

from the FSET pin to signal ground. Figure 5 shows the relation-

ship between the typical switching frequency (y-axis) and the

FSET resistor (x-axis). For a required switching frequency (f_SW),

the FSET resistor value can be calculated as follows:

The output voltage of the ARG81800 is determined by connect-

ing a resistive feedback divider (R_FB1, R_FB2) from the output

node (V_OUT) to the FB pin as shown in Figure 6. The feedback

resistors must satisfy the ratio shown in Equation 4 below to

produce the desired output voltage (V_OUT).

Equation 2:

Equation 4:

37037

=

− 2.ꢀꢁ

1

=

− 1.0

0.8

2

where f_SWis in kHz and R_FSETis in kΩ.

1% resistors are recommended to maintain the output voltage

accuracy. There are tradeoffs while choosing the value of the

feedback resistors. If the series combination (R_FB1+ R_FB2) is too

low, the light load efficiency of the regulator will be reduced. So to

maximize the efficiency, it is best to choose large values for feed-

back resistors. On the other hand, large values of feedback resistors

increases the parallel combination (R_FB1//R_FB2) and makes the

regulator more susceptible to noise coupling onto the FB pin.

3000

ꢀ500

ꢀ000

1500

1000

500

ꢄꢅUꢆ

R_ꢀꢁ1

ꢃ_ꢀꢀ

ꢀꢁ

ꢇ_ꢀꢁ

R_ꢀꢁꢂ

0

10 ꢀ0 30 ꢁ0 50 ꢂ0 ꢃ0 ꢄ0 90 100 110 1ꢀ0 130 1ꢁ0

ꢅSꢎꢏ Resistor, R_ꢅSꢎꢏꢊꢋΩꢍ

Figure 5: PWM Switching Frequency vs. R_FSET

Figure 6: Feedback Divider

While choosing the PWM switching frequency, the designer should

be aware of the minimum controllable on-time, t_ON(MIN), of the

ARG81800. If the required on-time of the system is less than the

minimum controllable on-time, pulse skipping will occur and the

output voltage will have increased ripple. The PWM switching

frequency should be calculated using Equation 3, where V_OUTis

the output voltage, t_ON(MIN)is the minimum controllable on-time of

the device (see EC table), and V_IN(MAX)is the maximum required

operational input voltage (not the peak surge voltage).

with Feedforward Capacitor

Large values of R_FB1also impact the output voltage accuracy of

the regulator. A small amount of leakage current I_FBflowing into

the FB pin increases the output voltage beyond the set regulation

voltage. The output voltage of the regulator considering the FB

pin leakage current is given by:

Equation 5:

ꢀ

= 0.8 ꢀ (1 ꢁ

¹) ꢁ

1

Equation 3:

2

ꢂ_ꢉꢊꢋ

ꢀ

FB pin leakage current increases the output voltage beyond the

set regulation voltage by an amount of I_FBRFB1. The larger the

value of R_FB1, the larger is the inaccuracy in the output voltage.

A feedforward capacitor (C_FF) can be connected in parallel with

f_SW

ꢈ

ꢂ

ꢃꢄ(ꢅꢆꢇ)

_{ꢉꢄ(ꢅꢃꢄ)}ꢁ

If an external clock f_SYNCis used for synchronization, the base

switching frequency should be chosen such that pulse skipping will

25

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators

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ARG81800

R_FB1to increase phase margin and loop crossover frequency

for improving transient response of the regulator. Addition of

C_FFresults in an additional zero and pole in the compensation

network and boosts the loop phase at the crossover frequency. In

general, C_FFshould be less than 25 pF. While large value of C_FF

increases the loop crossover frequency and reduces the phase

margin, very small value of C_FFwill not have any effect. Optimal

value of C_FFcan be calculated from the below equation.

Equation 8:

≥

ꢀ ( 1 − 0.18 ꢀ

)

(

)

where L_Ois output inductance in µH and S_Eis external slope

compensation provided in the Electrical Characteristics table.

To avoid dropout, V_IN(MIN)must be approximately 1 to 1.5 V

above V_OUT. Choose output inductor such that its inductance

is greater than the maximum of inductance values calculated in

Equation 7 and Equation 8. However, absolute maximum induc-

Equation 6:

1

=

tance should not exceed 1.1 × V_OUT/ S_E(min)

.

2 ꢀ

ꢀ

₁ꢀ

The saturation current of the inductor should be higher than the

peak current capability of the ARG81800. Ideally, for output

short-circuit conditions, inductor should not saturate, given the

highest peak current limit (I_LIMHSx) at minimum duty cycle. At

the very least, the output inductor should not saturate with the

peak operating current according to the following equation:

OUTPUT INDUCTOR (L_O)

The ARG81800 incorporates a peak current mode control

technique for closed-loop regulation of the output voltage. It is

common knowledge that, without adequate slope compensation,

a peak current mode controlled regulator will become unstable

when duty cycle is near or above 50%. Hence, to stabilize the

regulator over the complete range of its operating duty cycle,

the ARG81800 employs a fixed internal slope compensation

(S_E). Many factors determine the selection of output inductor,

such as switching frequency, output/input voltage ratio, transient

response, and ripple current. A larger value inductor will result in

less ripple current, which also results in lower output ripple volt-

age. However, the larger value inductor will have a larger physi-

cal size, higher series resistance, and/or lower saturation current.

Equation 9:

ꢇ

ꢀ_{Sꢅꢊꢋꢁꢌ}

ꢉ ꢀ_{ꢁꢀꢂꢃSꢄ(ꢂꢅꢆ)}− (

)

1.1ꢈ ꢇ

ꢇ

(

)

where t_ON(MIN)is the minimum on-time provided in the Electri-

cal Characteristics table.

The typical DC output current capability of the regulator at any

given duty cycle (D) is:

Equation 10:

A good rule of thumb for determining the output inductor is to

allow the peak-to-peak ripple current in the inductor to be approxi-

mately 30% of the maximum output current (I_OUT(MAX)). The

inductance value can be calculated from the following equation:

(

)

ꢀ

ꢀ 1 −

ꢁ_{ꢂꢃꢄ(ꢄꢅꢆ)}= ꢁ_{ꢇꢁꢈꢉSꢊ(ꢄꢅꢆ)}

−

2 ꢀ

ꢀ

After an inductor is chosen, it should be tested during output

short-circuit conditions. The inductor current should be moni-

tored using a current probe. A good design should ensure neither

the inductor nor the regulator are damaged when the output is

shorted to ground at maximum input voltage and the highest

expected ambient temperature.

Equation 7:

=

ꢀ ( 1 −

)

ꢀ ∆

where ∆I_LOis the peak-to-peak inductor ripple current, which

is 0.3 × I_OUT(MAX)

.

A second constraint on inductor value arises from the loop stabil-

ity at duty cycles greater than 50%. Although slope compensa-

tion is primarily required to avoid subharmonic oscillations, the

inductor value calculated from the formula derived by Dr. Ridley,

given below in Equation 8, can critically damp the pole pair at

half the switching frequency.

26

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators

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ARG81800

The transient response of the regulator depends on the quantity

and type of output capacitors. In general, minimizing the ESR of

OUTPUT CAPACITORS (C_O)

The output capacitor of switching regulators filter the output volt-

age to provide an acceptable level of ripple on the output voltage,

and they also store energy to help maintain voltage regulation

during a load transient. The voltage rating of the output capacitors

must support the output voltage with sufficient design margin.

the output capacitance will result in a better transient response.

The ESR can be minimized by simply adding more capacitors in

parallel or by using higher quality capacitors. At the instant of a

fast load transient (high di_O/dt), the change in the output voltage,

using electrolytic output capacitors, is:

The output voltage ripple (ΔV_OUT) is a function of the output

Equation 14:

capacitor parameters: C_O, ESR_CO, and ESL_CO

:

∆

= ∆

ꢀ

ꢁ

ꢀ

Equation 11:

−

∆

= ∆

ꢀ

ꢁ

ꢀ

When ceramic capacitors are used in the output, the output

voltage deviation during load transients depends on the bulk

output capacitance along with various other factors. To calculate

the bulk ceramic capacitance required, the entire load transient

duration can be divided into two stages: large signal and small

signal. During large signal load transients, immediately after the

transient event, the output voltage deviates from the nominal

value due to large mismatch in the load current requirement and

the inductor current. The output voltage deviation during this

interval is maximum and depends on output inductor, bulk output

capacitance, and closed-loop crossover frequency. For designs

with higher crossover frequency, the controller typically saturates

the duty cycle, i.e., either minimum or maximum. For a chosen

output inductor and crossover frequency values, the output volt-

age deviation can be minimized by increasing the output bulk

capacitance. In the case of a buck converter, operating with a low

duty cycle, the step-down load transient is more severe and hence

the output capacitance should be determined for this scenario.

The bulk ceramic output capacitance required is given by:

∆

ꢁ

8 ꢀ

ꢀ

The type of output capacitors determine which terms of Equa-

tion 11 are dominant. For ceramic output capacitors, ESR_COand

ESL_COare virtually zero, so the output voltage ripple will be

dominated by the third term of Equation 11. The value of C_Ocan

be calculated as:

Equation 12:

∆

≥

8 ꢀ

ꢀ ∆

Voltage ripple of a regulator using ceramic output capacitors

can be reduced by increasing the total capacitance, reducing the

inductor current ripple, or increasing the switching frequency.

For electrolytic output capacitors, the value of capacitance will

be relatively high, so the third term in Equation 11 will be very

small and the output voltage ripple will be determined primarily

by the first two terms:

Equation 15:

∆

²ꢁ

Equation 13:

=

ꢀ

2 ꢁ

ꢁ ∆

ꢀ

−

∆

= ∆

ꢀ

ꢁ

ꢀ

where ∆I_Ois the magnitude of the change in the load current,

∆V_OUT,specis the maximum allowed output voltage deviation

during load transient event. Gradually, as the mismatch between

the load current and the inductor current becomes small, the

output voltage deviation also reduces, resembling a small signal

transient event. Eventually, during small signal transient interval,

the error amplifier brings the output voltage back to its nominal

value. The speed with which the error amplifier brings the output

voltage back into regulation depends mainly on the loop cross-

over frequency. A higher crossover frequency usually results in a

shorter time to return to the nominal set voltage.

Voltage ripple of a regulator using electrolytic output capacitors

can be reduced by: decreasing the equivalent ESR_COand ESL_CO

by using a high quality capacitor, adding more capacitors in par-

allel, or reducing the inductor current ripple.

As the ESR of some electrolytic capacitors can be quite high,

Allegro recommends choosing a quality capacitor for which

the ESR or the total impedance is clearly documented in the

capacitor datasheet. Also, ESR of electrolytic capacitors usually

increases significantly at cold ambient temperatures, as much as

10 times, which increases the output voltage ripple and in most

cases reduces the stability of the system.

27

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators

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ARG81800

Equation 18:

OUTPUT VOLTAGE RIPPLE – ULTRALOW-I_Q

ꢁ

LP MODE

ꢀ

=

After choosing output inductor and output capacitor(s), it is

important to calculate the output voltage ripple (V_PP(LP)) during

ultralow-I_QLP mode. With ceramic output capacitors, the output

voltage ripple in PWM mode is usually negligible, but this is not

the case during LP mode.

ꢀ_ꢁUꢂ

ꢀ_PPꢅꢄPꢆ

In LP mode, the peak inductor current during on-time of the high-

side switch is limited to I_PEAK(LP). Also, in LP mode, the low-side

switch is constantly turned off thereby forcing the regulator to

operate in Discontinuous Conduction Mode (DCM) in order to

reduce switching losses. A LP comparator monitors the output

voltage on the FB pin and allows the regulator to switch until the

FB pin voltage is greater than 0.5% of its nominal value (0.8 V).

When FB voltage is greater than 0.804 V, the ARG81800 coasts

by terminating the switching pulses.

ꢃ_ꢄo

ꢃ_{PꢇAꢈꢉꢄo}

ꢃ_ꢁUꢂ

t₁

t_ꢋ

During coasting, the device shuts down most of its internal con-

trol circuitry to ensure very low quiescent current is drawn from

the input. The number of switching pulses, in LP mode, required

to coast the device depend on various factors including: input

voltage, output voltage, load current, output inductor, and output

capacitor. If ARG81800 starts coasting after a single switching

pulse, then the output voltage ripple would be dictated by this

single pulse. The peak inductor current without slope compensa-

tion (I_{PEAK_LO}) is given by:

t_ꢁꢊꢊ

t_ꢁN

Figure 7: Output Voltage Ripple in LP Mode

During on-time interval, the length of time for the inductor cur-

rent to rise from 0 A to I_OUTis:

Equation 19:

ꢀ

=

1

−

ꢀ (

ꢂ

)

ꢁ

(

)

(

Equation 16:

During off-time interval, the length of time for the inductor cur-

rent to fall from I_OUTto 0 A is:

ꢂ_{ꢃEꢄꢅ(ꢆꢃ)}

ꢂ_{ꢃEꢄꢅꢇꢆꢈ}

=

ꢁ

−

1 ꢀ

Equation 20:

ꢀ

where I_PEAK(LP)is the peak inductor current, specified in the

Electrical Characteristics table, at which device enters into LP

mode. Referring to Figure 7, on-time and off-time calculations

are given as:

=

2

Given the peak inductor current (I_{PEAK_L}) and the rise and fall

times (t_ONand t_OFF) for the inductor current, the output voltage

ripple for a single switching pulse can be calculated as follows:

Equation 17:

ꢁ

Equation 21:

ꢀ

=

−

ꢁ (

ꢂ

)

−

(

)

(

ꢀ

=

ꢁ (

ꢂ

−

)

2

(

)

1

2 ꢁ

28

Allegro MicroSystems

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

INPUT CAPACITORS

Three factors should be considered when choosing the input

capacitors. First, the capacitors must be chosen to support the

maximum expected input surge voltage with adequate design

margin. Second, the capacitor RMS current rating must be higher

than the expected RMS input current to the regulator. Third, the

capacitors must have enough capacitance and a low enough ESR

to limit the input voltage dV/dt to much less than the hysteresis

of the UVLO circuitry (250 mV nominal) at maximum loading

and minimum input voltage. The input capacitors must deliver an

RMS current (I_RMS) given by:

0.55

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.15

0.1

0.05

0

10 20 30 40 50 60 70 80 90 100

Duty Cycle, D(%)

Equation 22:

=

ꢀ

√

ꢀ (1 − )

where the duty cycle (D) is defined as:

Equation 23:

Figure 8: Normalized Input Capacitor Ripple

versus Duty Cycle

A good design should consider the DC bias effect on a ceramic

capacitor: as the applied voltage approaches the rated value, the

capacitance value decreases. This effect is very pronounced with

the Y5V and Z5U temperature characteristic devices (as much

as 90% reduction), so these types should be avoided. The X5R,

X7R, and X8R type capacitors should be the primary choices due

to their stability versus both DC bias and temperature.

≈

Figure 8 shows the normalized input capacitor RMS current

versus duty cycle. To use this graph, simply find the operational

duty cycle (D) on the x-axis and determine the input/output cur-

rent multiplier on the y-axis. For example, at a 20% duty cycle,

the input/output current multiplier is 0.40. Therefore, if the

regulator is delivering 1.0 A of steady-state load current, the input

capacitor(s) must support 0.40 × 1.0 A or 0.4 A RMS.

For all ceramic capacitors, the DC bias effect is even more pro-

nounced on smaller sizes of device case, so a good design uses

the largest affordable case size (such as 1206 or 1210). Also, it is

advisable to select input capacitors with plenty of design margin

in the voltage rating to accommodate the worst case transient

input voltage (such as a load dump as high as 40 V for automo-

tive applications).

The input capacitor(s) must limit the voltage deviations at the

VIN pin to significantly less than the device UVLO hysteresis

during maximum load and minimum input voltage condition.

The following equation allows to calculate the minimum input

capacitance required:

BOOTSTRAP CAPACITOR

Equation 24:

ꢀ

ꢀ (1 −

ꢀ ∆

)

A bootstrap capacitor must be connected between the BOOT and

SW pins to provide floating gate drive to the high-side MOSFET.

Usually, 47 nF is an adequate value. This capacitor should be a

high-quality ceramic capacitor, such as an X5R or X7R, with a

voltage rating of at least 16 V.

≥

0.8ꢁ ꢀ

(

)

where ΔV_IN(MIN)is chosen to be much less than the hysteresis

of the VIN UVLO comparator (ΔV_IN(MIN)≤ 150 mV is recom-

mended), and f_SWis the nominal PWM frequency. The D × (1–D)

term in Equation 22 has an absolute maximum value of 0.25 at

50% duty cycle. So, for example, a very conservative design

based on I_OUT= 1.0 A, f_SW= 0.5 MHz, D × (1–D) = 0.25, and

ΔV_IN=150 mV yields:

SOFT START AND HICCUP MODE TIMING (C_SS

)

The soft start time of the ARG81800 is determined by the

value of the capacitance (C_SS) at the soft start pin. When the

ARG81800 is enabled, the SS pin sources the charging current

I_SSand the voltage across the soft start capacitor C_SSstarts ramp-

ing upward from 0 V. However, PWM switching will begin only

after the voltage across the C_SSrises above 400 mV.

1.0 ꢀ 0.2ꢁ

0.8ꢁ ꢀ 0.ꢁ ꢀ 10^ꢂꢀ 1ꢁ0 ꢀ 10⁻³

≥

= 1.95 µ

29

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators

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ARG81800

The soft start delay (t_dSS) can be calculated using the equation

below:

COMPENSATION COMPONENTS (R_Z, C_Z, AND C_P)

The objective of the selection of the compensation components is

to ensure adequate stability margins to avoid instability issues, to

maintain a high loop gain at DC to achieve excellent output volt-

age regulation and to obtain a high loop bandwidth for superior

transient response. To a first order, the closed-loop model of a

peak current mode controlled regulator can be broken into two

blocks as shown below in Figure 9.

Equation 25:

0.4

=

ꢀ

ꢁ

(

)

If the device is starting with a very heavy load, a very fast soft

start time may cause the regulator to exceed the pulse-by-pulse

overcurrent threshold. This occurs because the sum of the full

load current, the inductor ripple current, and the additional cur-

rent required to charge the output capacitors

Power Stage

Equation 26:

ꢅ_ꢃ

ꢀ_ꢁUꢂ

ꢃ_ꢁ

ꢅ_ꢁUꢂ

R_ꢄ

g_mPꢁꢆꢇR

Aꢈꢅ

=

ꢀ

is higher than the pulse-by-pulse current threshold. This phenom-

enon is more pronounced when using high value electrolytic type

output capacitors. To avoid prematurely triggering hiccup mode,

the soft start capacitor (C_SS) should be calculated according to

equation below:

R_ꢉꢊ1

ꢉꢊ Pin

ꢅ_ꢉꢊ

ꢃꢁMP

R_ꢉꢊꢋ

g_mꢌ

Equation 27:

ꢍ50 ꢎAꢈꢅ

ꢀ

≥

R_ꢑ

ꢃ_ꢑ

0.8 ꢀ

R_ꢁ

ꢃ_P

0.ꢏ ꢅ

Reꢐerence

where V_OUTis the output voltage, C_Ois the output capacitance,

_COis the amount of current allowed to charge the output capaci-

I

ꢇrror Amꢒliꢐier

tance during soft start (0.1 A < I_CO< 0.3 A is recommended). The

soft start time (t_SS) can be calculated as below:

Figure 9: Closed-Loop Model of Peak Current Mode

Controlled Regulator

Equation 28:

= 0.8 ꢀ

POWER STAGE

(

)

The power stage includes the output filter capacitor, C_O, the

equivalent load, R_L, and the inner current loop which consists of

the PWM modulator and the output inductor, L_O. The inner current

loop, with a first-order approximation, can be effectively modeled

as a transconductance amplifier that converts the control voltage

(V_C) from the error amplifier to a peak output inductor current with

an equivalent gain g_mPower. Although, the peak current through the

inductor is being controlled—neglecting the inductor ripple cur-

Higher values of I_COresult in faster soft start times. However,

lower values of I_COensure that hiccup mode is not falsely trig-

gered. Allegro recommends starting the design with an I_COof

0.1 A and increasing it only if the soft start time is too slow. If a

non-standard capacitor value for C_SSis calculated, the next larger

value should be used.

When the device is in hiccup mode, the soft start capacitor is used

as a timing capacitor and sets the hiccup period. The soft start pin

charges the soft start capacitor with I_SSduring a startup attempt

and discharges the same capacitor with I_HICbetween startup

attempts. Because the ratio of I_SS:I_HICis approximately 4:1, the

time between hiccups will be about four times as long as the

startup time. Therefore, the effective duty cycle will be very low

and the junction temperature will be kept low.

rent—it is acceptable to replace it with output current I_OUT

.

From a small-signal point of view, the current mode control loop

behaves like a current source and therefore the power inductor

can be ignored. The output capacitor integrates the ripple current

through the inductor, effectively forming a single pole with the

output load. A control-to-output transfer function between the

control voltage (V_C), output of the error amplifier in the feed-

30

Allegro MicroSystems

955 Perimeter Road

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www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

back loop, and the regulator output voltage (V_OUT) describes the

dynamics of the power stage. The DC gain of the power stage,

i.e., control-to-output transfer function, is given by:

where A_VOLis the open-loop DC gain of the error amplifier (spec-

ified in the Electrical Characteristics table).

The DC gain of the error amplifier is 65 dB (equivalent to 1778)

and with a g_mvalue of 750 μA/V, the effective output impedance,

R_O, of the amplifier is:

Equation 29:

=

)

ꢀ

(

Equation 33:

where g_mPOWERis the equivalent gain of the inner current loop

(specified in the Electrical Characteristics table) and R_Lis the

load resistance.

1778

7ꢀ0 ꢁ 10^−ꢂ

=

= 2.37

Ω

Typically, R_O≫ R_Zand C_Z≫ C_P, which simplifies the derivation

of the transfer function of the Type-II compensated error ampli-

fier. The transfer function has a (very) low frequency pole f_P1(EA)

dominated by the error amplifier output impedance R_Oand the

compensation capacitor C_Z:

The control-to-output transfer function has a pole f_P(CO), formed by

the output capacitance (C_O) and load resistance (R_L), located at:

Equation 30:

1

=

(

)

2 ꢀ

ꢀ

Equation 34:

The control-to-output transfer function has a zero f_Z(CO), formed

by the output capacitance (C_O) and its associated ESR, located at:

1

=

1(

)

2 ꢀ

ꢀ

Equation 31:

The transfer function of the Type-II compensated error amplifier

also has a zero at frequency f_Z(EA)caused by the resistor R_Zand

the capacitor C_Z:

1

=

(

)

2 ꢀ

ꢀ

For a design with very low-ESR type output capacitors (such as

ceramic or OSCON output capacitors), the ESR zero, f_Z(CO), is

usually at a very high frequency so it can be ignored. On the other

hand, with high-ESR electrolytic output capacitors, the ESR zero

falls below or near the 0 dB crossover frequency of the closed-loop;

hence, it should be cancelled by the pole formed by the C_Pcapacitor

Equation 35:

1

=

(

)

2 ꢀ

ꢀ

Lastly, the transfer function of the Type-II compensated error

amplifier has a (very) high frequency pole f_P2(EA)dominated by

the resistor R_Zresistor and the capacitor C_P:

and the R_Zresistor discussed and identified later as f_P2(EA)

.

ERROR AMPLIFIER

Equation 36:

1

The error amplifier, as a part of the output voltage feedback loop,

comprises a transconductance amplifier with an external Type-II

compensation formed by R_Z-C_Z-C_Pnetwork. A Type-II compen-

sated error amplifier introduces two poles and a zero. The place-

ment of these poles and zero should be such that the closed-loop

system has sufficient stability margins and high bandwidth (loop

crossover frequency) and provides optimal transient response.

=

2(

)

2 ꢀ

ꢀ

Although there are many different approaches for designing the

feedback loop, a good design approach attempts to maximize the

closed-loop system stability, while providing a high bandwidth

and optimized transient response. A generalized tuning procedure

is presented below to systematically determine the values of com-

pensation components (R_Z, C_Z, and C_P) in the feedback loop.

The DC gain of the feedback loop, including the error amplifier

and the feedback resistor divider is given by:

Equation 32:

2

=

ꢀ

(

)

₁ꢁ

2

31

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

To maximize system stability, i.e., high gain and phase mar-

gins, use a higher value of C_Z. To optimize transient recovery

time, although at the expense of low stability margins, use a

lower value of C_Z.

A GENERALIZED TUNING PROCEDURE

1. Choose the system bandwidth (f_C). This is the frequency at

which the magnitude of the gain crosses 0 dB. Recommended

values for f_C, based on the PWM switching frequency, are

in the range f_SW/ 20 < f_C< f_SW/ 10. A higher value of f_C

generally provides a better transient response, while a lower

value of f_Cgenerally makes it easier to obtain higher gain and

phase margins.

4. Calculate the frequency of the ESR zero f_Z(CO)formed by the

output capacitor(s) by using Equation 31 (repeated here):

1

=

(

)

2. Calculate the R_Zresistor value. This sets the system band-

width (f_C):

2 ꢀ

ꢀ

If f_Z(CO)is at least one decade higher than the target crossover

frequency f_C, then f_Z(CO)can be ignored. This is usually the case

for a design using ceramic output capacitors. Use Equation 36

to calculate the value of C_Pby setting f_P2(EA)to either 5 × f_Cor

f_SW/ 2, whichever is higher.

Equation 37:

2 ꢀ

=

ꢀ

3. Calculate the range of values for the C_Zcapacitor. Use the

following:

Alternatively, if f_Z(CO)is near or below the target crossover

frequency f_C, then use Equation 36 to calculate the value of C_Pby

setting f_P2(EA)equal to f_Z(CO). This is usually the case for a design

using high ESR electrolytic output capacitors.

Equation 38:

4

1

ꢁ

2 ꢀ

ꢀ

2 ꢀ

ꢀ 1.ꢂ ꢀ

(

)

32

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

VIN

BIAS

ꢀ_ꢉN

GND

PGND

BOOT

ꢅ_ꢁ

0.1 μꢂ

ꢇ_ꢁUꢈ

ꢀ_ꢁ

Sꢂ

ꢁB

R_ꢂꢃ1

ꢁSꢃT

VRꢃG

R_ꢂSꢌꢈ

R_ꢂꢃꢄ

10 kΩ

ꢀ_ꢂꢂ

PGOOD

COꢀP

ꢊ.ꢋ μꢂ

R_ꢆ

ꢀ_ꢆ

ꢀ_P

Figure 10: Applications Schematic Showing Component Locations

Table 3: Recommended External Components (for load transient slew rate < 50 mA/µs)

ARG81800

COMP Components

(BW ~75 kHz / 30 kHz, PM > 60 deg)

FB Components

V_OUT

f_SW

R_FSET

L_O

C_O

C_IN(MIN)

R_Z

C_Z

C_P

R_FB1

R_FB2

C_FF

5.0 V

3.3 V

5.0 V

3.3 V

2.15 MHz

400 kHz

14.3 kΩ

90.9 kΩ

4.7 µH

3.3 µH

22 µH

15 µH

20 µF

33 µF

47 µF

51.1 kΩ

40.2 kΩ

24.9 kΩ

29.4 kΩ

1.2 nF

2.2 nF

82 pF

68 pF

100 pF

47 pF

732 kΩ

301 kΩ

732 kΩ

301 kΩ

137 kΩ

95.3 kΩ

137 kΩ

95.3 kΩ

4.7 pF

1.0 µF

4.7 µF

ARG81800-1

COMP Components

(BW ~75 kHz / 30 kHz, PM > 60 deg)

FB Components

V_OUT

f_SW

R_FSET

L_O

C_O

C_IN(MIN)

R_Z

C_Z

C_P

R_FB1

R_FB2

C_FF

5.0 V

3.3 V

5.0 V

3.3 V

2.15 MHz

400 kHz

14.3 kΩ

90.9 kΩ

9.1 µH

7.5 µH

43 µH

33 µH

20 µF

33 µF

47 µF

150 kΩ

60.4 kΩ

51.1 kΩ

49.9 kΩ

1.0 nF

2.2 nF

47 pF

33 pF

47 pF

732 kΩ

301 kΩ

732 kΩ

301 kΩ

137 kΩ

95.3 kΩ

137 kΩ

95.3 kΩ

4.7 pF

1.0 µF

4.7 µF

Note 1: Components were chosen to maintain LP ripple voltage and minimize voltage droop during LP to PWM changeover.

Note 2: C_FFis chosen to offset 15 to 25 pF of stray capacitance at the FB pin.

Table 4: Recommended External Components (for load transient slew rate > 50 mA/µs)

ARG81800

COMP Components

(BW ~75 kHz / 30 kHz, PM > 60 deg)

FB Components

V_OUT

f_SW

R_FSET

L_O

C_O

C_IN(MIN)

R_Z

C_Z

C_P

R_FB1

R_FB2

C_FF

5.0 V

3.3 V

5.0 V

3.3 V

2.15 MHz

400 kHz

14.3 kΩ

90.9 kΩ

90.0 kΩ

4.7 µH

3.3 µH

22 µH

15 µH

42 µF

55 µF

69 µF

10.0 kΩ

8.06 kΩ

5.11 kΩ

5.23 kΩ

5.6 nF

9.1 nF

10 pF

732 kΩ

301 kΩ

732 kΩ

301 kΩ

137 kΩ

95.3 kΩ

137 kΩ

95.3 kΩ

4.7 pF

1.0 µF

4.7 µF

ARG81800-1

COMP Components

(BW ~75 kHz / 30 kHz, PM > 60 deg)

FB Components

V_OUT

f_SW

R_FSET

L_O

C_O

C_IN(MIN)

R_Z

C_Z

C_P

R_FB1

R_FB2

C_FF

5.0 V

3.3 V

5.0 V

3.3 V

2.15 MHz

400 kHz

14.3 kΩ

90.9 kΩ

9.1 µH

7.5 µH

43 µH

33 µH

42 µF

55 µF

69 µF

30.1 kΩ

12.1 kΩ

10.0 kΩ

5.6 nF

9.1 nF

10 pF

732 kΩ

301 kΩ

732 kΩ

301 kΩ

137 kΩ

95.3 kΩ

137 kΩ

95.3 kΩ

4.7 pF

1.0 µF

4.7 µF

Note 1: Components were chosen to maintain LP ripple voltage and minimize voltage droop during LP to PWM changeover.

Note 2: C_FFis chosen to offset 15 to 25 pF of stray capacitance at the FB pin.

33

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

POWER DISSIPATION AND THERMAL CALCULATIONS

The total power dissipated in the ARG81800 is the sum of the

power dissipated from the V_INsupply current (P_IN), the power

dissipated due to the switching of the high-side power MOS-

FET (P_SWH), the power dissipated due to the conduction of rms

current in the high-side MOSFET (P_CH) and low-side MOSFET

(P_CL), power dissipated due to the low-side MOSFET body diode

conduction during the non-overlap time (P_NO) and the power dis-

sipated by both high-side and low-side gate drivers (P_DRIVER).

Equation 42:

2

=

ꢁ

(

)

ꢀ

2

∆

2

= 1 −

ꢁ

ꢂ

ꢁ

(

)

(

)

(

)

12

where I_OUTis the regulator output current, ΔI_LOis the peak-

to-peak inductor ripple current, R_DS(ON)His the on-resistance

of the high-side MOSFET, R_DS(ON)Lis the on-resistance of the

low-side MOSFET.

The power dissipated from the V_INsupply current (with BIAS pin

open) can be calculated using Equation 39:

The R_DS(ON)of both MOSFETs have some initial tolerance plus an

increase from self-heating and elevated ambient temperatures. A

conservative design should accommodate an R_DS(ON)with at least

15% initial tolerance plus 0.39%/°C increase due to temperature.

Equation 39:

=

ꢀ

ꢁ

(

)

(

)

ꢀ

ꢄ

ꢂ

−

ꢀ

_ꢃꢂ

The power dissipated in the low-side MOSFET body diode dur-

ing the non-overlap time can be calculated as follows:

where V_INis the input voltage, I_IN,PWMis the input quiescent

current drawn by the ARG81800 in PWM mode (see EC table),

V_GSis the MOSFET gate drive voltage (typically 4.8 V), Q_GH

and Q_GLare the internal high-side and low-side MOSFET gate

charges (approximately 0.3 nC and 0.6 nC, respectively), and

f_SWis the PWM switching frequency.

Equation 43:

=

ꢀ

ꢀ 2 ꢀ

ꢀ

where V_SDis the source-to-drain voltage of the low-side MOS-

FET (typically 0.60 V), and t_NOis the non-overlap time (15 ns

typical).

The power dissipated by the high-side MOSFET during PWM

switching can be calculated using Equation 40:

The power dissipated in the internal gate drivers can be calcu-

lated using Equation 44:

Equation 40:

ꢀ

ꢀ (

ꢁ

) ꢀ

Equation 44:

=

2

(

)

ꢁ

=

ꢀ

ꢁ

where V_INis the input voltage, I_OUTis the regulator output cur-

rent, f_SWis the PWM switching frequency, t_rand t_fare the rise

and fall times measured at the switch node.

where V_GSis the gate drive voltage (typically 4.8 V).

Finally, the total power dissipated in the ARG81800 is given by:

Equation 45:

The exact rise and fall times at the SW node will depend on the

external components and PCB layout, so each design should be

measured at full load. Approximate values for both t_rand t_frange

from 10 to 20 ns.

=

ꢀ

The average junction temperature (T_J) can be calculated as follows:

Equation 46:

The power dissipated in the high-side MOSFET while it is con-

ducting can be calculated using Equation 41:

=

ꢀ

ꢁ

where P_TOTALis the total power dissipated from Equation 45,

R_θJAis the junction-to-ambient thermal resistance (37°C/W on

a 4-layer PCB), and T_Ais the ambient temperature.

Equation 41:

2

=

ꢁ

(

)

ꢀ

2

∆

2

=

ꢁ

ꢂ

ꢁ

R

_θJAincludes the thermal impedance from junction to case, R_θJC

(

)

(

)

(

)

12

and the thermal impedance from case to ambient, R_θCA. R_θCAis

generally determined by the amount of copper that is used under-

neath and around the device on the printed circuit board.

Similarly, the conduction losses dissipated in the low-side MOSFET

while it is conducting can be calculated by the following equation:

34

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

The maximum allowed power dissipation depends on how effi-

ciently heat can be transferred from the junction to the ambient

air, i.e., minimizing the R_θJA. As with any regulator, there are

limits to the amount of heat that can be dissipated before risking

thermal shutdown. There are tradeoffs between ambient operat-

ing temperature, input voltage, output voltage, output current,

switching frequency, PCB thermal resistance, airflow, and other

nearby heat sources. Even a small amount of airflow will reduce

the junction temperature considerably.

35

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

EMI/EMC AWARE PCB DESIGN

The ARG81800 is designed to minimize electromagnetic (EM)

emissions when proper PCB layout techniques are adopted. A good

PCB layout is also critical for the ARG81800 to provide clean and

stable output voltages. Design guidelines for EMI/EMC-aware

PCB layout are presented below. Figure 10 shows a typical appli-

cation schematic of a synchronous buck regulator IC with critical

power paths/loops.

copper area can be placed underneath the SW node to provide

additional shielding. Also, noise sensitive analog signals (like

FB, COMP) should not be routed near the SW polygon.

6. Place the feedback resistor divider (R_FB1and R_FB2) very

close to the FB pin. Route the ground side of R_FB2as close as

possible to the ARG81800.

7. Place the compensation components (R_Z, C_Z, and C_P) as

close as possible to the COMP pin. Also route the ground side

of C_Zand C_Pas close as possible to the ARG81800.

1. Place the ceramic input capacitors as close as possible to the

VIN pin and PGND pins to make the loop area minimal, and

the traces of the input capacitors to VIN pin should be short

and wide to minimize the inductance. This critical loop is

shown as trace 1 in Figure 11. The bulk/electrolytic input ca-

pacitor can be located further away from VIN pin. The input

capacitors and ARG81800 IC should be on the same side of

the board with traces on the same layer.

8. Place the FSET resistor as close as possible to the FSET pin;

Place the soft start capacitor C_SSas close as possible to the

SS pin.

9. The output voltage sense trace (from VOUT to R_FB1) should

be routed as close as possible to the load to obtain the best

load regulation.

2. The loop from the input supply and capacitors, through the high-

side MOSFET, into the load via the output inductor, and back to

ground should be minimized with relatively wide traces.

10. Place the bootstrap capacitor (C_BOOT) near the BOOT pin

and keep the routing from this capacitor to the SW polygon

as short as possible. This critical trace is shown as trace 5 in

Figure 11.

3. When the high-side MOSFET is oﬀ, free-wheeling cur-

rent ﬂows from ground, through the synchronous low-side

MOSFET, into the load via the output inductor, and back to

ground. This loop should be minimized and have relatively

wide traces. This loop is shown as trace 2 in Figure 11.

11. A two-layer (TOP and BOT) PCB is suﬃcient for better

thermal performance.

12. When connecting the input and output ceramic capacitors,

use multiple vias to GND planes and place the vias as close

as possible to the pads of the components. Do not use thermal

reliefs around the pads for the input and output ceramic

capacitors.

4. Place the output capacitors relatively close to the output induc-

tor (L_O) and the ARG81800. Ideally, the output capacitors, out-

put inductor and the ARG81800 should be on the same layer.

Connect the output inductor and the output capacitors with

a fairly wide trace. The output capacitors must use a ground

plane to make a very low-inductance connection to the GND.

These critical connections are shown as trace 3 in Figure 11.

13. Place all the components on the TOP layer and limit the rout-

ing only to the top layer. Use BOT layer as GND plane.

14. To minimize thermal resistance, extend ground planes on

TOP layer as much as possible and use thermal vias to con-

nect them to GND plane in BOT layer.

5. Place the output inductor (L_O) as close as possible to the SW

pin with short and wide traces. This critical trace is shown as

trace 4 in Figure 11. The voltage at SW node transitions from

0 V to V_INwith a high dv/dt rate. This node is the root cause of

many noise issues. It is suggested to minimize the SW copper

area to minimize the coupling capacitance between SW node

and other noise-sensitive nodes; however, the SW node area

cannot be too small in order to conduct high current. A ground

15. To minimize PCB losses and improve system eﬃciency, the

power traces should be as wide as possible.

16. EMI/EMC issues are always a concern. Allegro recommends

having placeholder for an RC snubber from SW to ground.

The resistor should be 0805 or 1206 size.

36

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

ꢊ_Rꢃꢅ

1

R_Pꢐllꢐꢑ

ꢃN

ꢀꢄN

ꢀRꢃꢅ

ꢊꢎꢒ_ꢁUꢂ

ꢊ_ꢈoot

ꢈꢁꢁꢂ

ꢄnternal

Regꢐlator

ꢈoot

R_ꢇꢈ1

Regꢐlator

ꢊ_ꢄN

Pꢅꢁꢁꢆ

ꢈꢄAS

Sꢋ

ꢇꢈ

5

ꢎ_ꢁ

ꢀꢁUꢂ

ꢏ

ꢊꢁMP

ꢇSꢃꢂ

ꢀRꢃꢅ

R_ꢇꢈꢍ

R_ꢎ

SꢉNꢊ_ꢄN

SS

ꢊ_ꢁ

ꢍ

ꢊ_P

ꢊ_ꢌ

R_ꢇSꢃꢂ

ꢊ_SS

ꢅNꢆ PꢅNꢆ

R_ꢌ

1

Figure 11: PCB Layout for Minimizing EM Emissions

3

ꢇ.ꢒ μH, ꢂ.5 A

ꢃꢄAꢅꢆ 3.5 ꢃ to 3ꢇ ꢃ

VIN

BIAS

0.1 μꢊ

ꢀ.ꢌ μꢊ

10 μꢊ

ꢀ.ꢌ μꢊ

0.1 μꢊ

BOOT

GND

PGND

50 ꢃ, ꢋꢌR

0.1 μꢊ

1ꢇ ꢃ, ꢋꢌR

3.3 μH, ꢂ.5 A

3.3 ꢃ ꢈ 1 A

Sꢀ

0.1 μꢊ

10 Ω

ꢂ ꢍ 10 μꢊ

Pꢀꢁ/AUTO

ꢂN

1ꢇ ꢃ, ꢋꢌR

0.ꢂ5 ꢉ

1ꢇ ꢃ, ꢋꢌR

ꢇꢒ0 ꢎꢊ

50 ꢃ, ꢏꢐꢑ

SYNC_IN

10 kΩ

301 ꢁΩ

ꢃB

ꢃSꢂT

SS

95.3 kΩ

1ꢀ.3 ꢁΩ

ꢓ_Sꢉꢔ ꢂ.15 MHꢕ

ꢀ.ꢌ ꢎꢊ

50 ꢃ, ꢏꢐꢑ

ꢂꢂ nꢊ

PGOOD

CLK_OUT

COꢁP

1ꢇ ꢃ, ꢋꢌR

VRꢂG

ꢀ.ꢌ μꢊ

ꢂ.ꢂ nꢊ

10 ꢎꢊ

1ꢇ ꢃ, ꢋꢌR

50 ꢃ, ꢏꢐꢑ

30.1 ꢁΩ

Figure 12: 3.3 V, 1 A Buck Regulator with Input EMI Filter

37

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

45

Horizontal Polarization

Vertical Polarization

40

35

30

25

20

15

10

5

40

35

EN 55025 (2008) Automotive Components PK

EN 55025 (2008) Automotive Components AV

EN 55025 (2008) Automotive Components PK

EN 55025 (2008) Automotive Components AV

30

25

20

15

10

5

0

30M

50

60

70 80 90 100M

Frequency in Hz

200

330M

30M

50

60

70 80 90 100M

Frequency in Hz

200

330M

Figure 13: Radiated EMI – Biconical Antenna

Figure 14: Radiated EMI – Biconical Antenna

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 1 A, f_SW= 2.15 MHz

50

45

80

70

60

50

EN 55025 (2008) Automotive Radiated Class 5 PK

40

35

30

25

EN 55025 (2008) Automotive Voltage PK

EN 55025 (2008) Automotive Voltage AV

40

30

20

10

0

EN 55025 (2008) Automotive Radiated Class 5 AV

20

15

10

5

0

-10

-5

150k

300 400500 8001M

2M 3M 4M5M 6 8 10M

Frequency in Hz

20M 30M 40 50 60 80 108M

150k

300 400 500

800 1M

2M

3M 4M 5M

6

8

10M

20M

30M

Frequency in Hz

Figure 15: Radiated EMI – Monopole Antenna

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 1 A, f_SW= 2.15 MHz

Figure 16: Conducted EMI

V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 1 A, f_SW= 2.15 MHz

EMI test results are obtained using standard evaluation board with Input EMI filter and Snubber (see Figure 12 above).

38

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

TYPICAL REFERENCE DESIGNS

U1

ꢋꢀAꢂꢔ 3.5 ꢋ to 3ꢏ ꢋ

ꢋꢇN

ꢀꢇAS

ꢃꢒ

R1

ꢉNꢊ

PꢉNꢊ

ꢃ3

ꢀꢁꢁꢂ

ꢃ1

ꢍ1

ꢋꢁUꢂ

ꢃ5

Sꢄ

ꢌꢀ

Rꢒ

PꢄMꢅAUꢂꢁ

ꢃꢑ

ꢃꢏ

R3

ꢈN

ARG81800

Rꢏ

ꢃꢓ

SꢆNꢃ

ꢇN

ꢋRꢈꢉ

ꢌSꢈꢂ

SS

Pꢉꢁꢁꢊ

ꢃꢍꢎ_ꢁUꢂ

ꢃꢁMP

ꢃꢐ

Rꢑ

ꢃ10

R5

ꢃ11

ꢃ9

Figure 17: Reference Design 1 – AUTO Mode with CLK_OUTenabled

V_IN= 3.5 to 36 V, V_OUT= 3.3 V, I_OUT= 0 to 1.0 A, f_SW= 2.15 MHz

Table 5: Reference Design 1 – Recommended Bill of Materials

Designator

C1

Description

Capacitor, X7R

Value

Footprint

0603

Manufacturer

Murata

Manufacturer P/N

0.1 µF, 50 V

4.7 µF, 50 V

0.1 µF, 50 V

10 µF, 16 V

4.7 pF, 50 V

4.7 µF, 16 V

22 nF, 50 V

2.2 nF, 50 V

10 pF, 50 V

3.3 µH, 2 A

10 kΩ

GCM188R71H104KA57D

GRJ31CR71H475KE11L

GCM188R71H104KA57D

GCM319R71H104KA37J

GRM32DR71C106KA01L

GCM1885C1H4R7BA16D

GCJ21BR71C475KA01L

GRM188R71H223KA01D

GCM188R71H222KA37D

C0603C100J5GACTU

74437334033

C2

Capacitor, X7R

1206

Murata

C3

Capacitor, X7R

0603

Murata

C4

Capacitor, X7R

1206

Murata

C5

Capacitor, X7R

1210

Murata

C6

Capacitor, X7R

1210

Murata

C7

Capacitor, C0G (NP0)

Capacitor, X7R

0603

Murata

C8

0805

Murata

C9

Capacitor, X7R

0603

Murata

C10

C11

L1

Capacitor, X7R

0603

Murata

Capacitor, C0G (NP0)

Inductor

0603

Kemet

5.2 mm × 5.2 mm

0603

Wurth Electronics

Panasonic

Allegro

R1

Resistor, 1%, 1/10 W

Allegro IC

ERJ-3EKF1002V

R2

301 kΩ

0603

ERJ-3EKF3013V

R3

95.3 kΩ

0603

ERJ-3EKF9532V

R4

14.3 kΩ

0603

ERJ-3EKF1432V

R5

30.1 kΩ

0603

ERJ-3EKF3012V

R6

10 kΩ

0603

ERJ-3EKF1002V

U1

ARG81800

QFN20_4x4

ARG81800KESJSR

39

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

U1

ꢋꢀAꢂꢔ 3.5 ꢋ to 3ꢏ ꢋ

ꢋꢇN

ꢀꢇAS

ꢃꢒ

R1

ꢉNꢊ

PꢉNꢊ

ꢃ3

ꢀꢁꢁꢂ

ꢃ1

ꢍ1

ꢋꢁUꢂ

ꢃ5

Sꢄ

ꢌꢀ

Rꢒ

SꢆNꢃ

ꢇN

ꢃꢑ

ꢃꢏ

ꢈN

ARG81800ꢀ1

R3

Rꢏ

ꢃꢓ

PꢄMꢅAUꢂꢁ

ꢋRꢈꢉ

Pꢉꢁꢁꢊ

ꢃꢍꢎ_ꢁUꢂ

ꢃꢁMP

ꢃꢐ

ꢌSꢈꢂ

SS

Rꢑ

ꢃ10

R5

ꢃ11

ꢃ9

Figure 18: Reference Design 2 – Forced PWM Mode with CLK_OUTdisabled

V_IN= 3.5 to 36 V, V_OUT= 5.0 V, I_OUT= 0 to 0.5 A, f_SW= 400 kHz

Table 6: Reference Design 2 – Recommended Bill of Materials

Designator

C1

Description

Capacitor, X7R

Value

0.1 µF, 50 V

4.7 µF, 50 V

0.1 µF, 50 V

22 µF, 16 V

10 µF, 16 V

4.7 pF, 50 V

4.7 µF, 16 V

22 nF, 50 V

2.2 nF, 50 V

10 pF, 50 V

47 µH, 2.2A

10 kΩ

Footprint

0603

Manufacturer

Murata

Manufacturer P/N

GCM188R71H104KA57D

GRJ31CR71H475KE11L

GCM188R71H104KA57D

GCM319R71H104KA37J

GRM32ER71C226MEA8L

GRM32DR71C106KA01L

GCM1885C1H4R7BA16D

GCJ21BR71C475KA01L

GRM188R71H223KA01D

GCM188R71H222KA37D

C0603C100J5GACTU

7447714470

C2

Capacitor, X7R

1206

Murata

C3

Capacitor, X7R

0603

Murata

C4

Capacitor, X7R

1206

Murata

C5

Capacitor, X7R

1210

Murata

C6

Capacitor, X7R

1210

Murata

C7

Capacitor, C0G (NP0)

Capacitor, X7R

0603

Murata

C8

0805

Murata

C9

Capacitor, X7R

0603

Murata

C10

C11

L1

Capacitor, X7R

0603

Murata

Capacitor, C0G (NP0)

Inductor

0603

Kemet

10 mm × 10 mm

0603

Wurth Electronics

Panasonic

Allegro

R1

Resistor, 1%, 1/10 W

Allegro IC

ERJ-3EKF1002V

R2

732 kΩ

0603

ERJ-3EKF7323V

R3

140 kΩ

0603

ERJ-3EKF1403V

R4

90.9 kΩ

0603

ERJ-3EKF7152V

R5

34 kΩ

0603

ERJ-3EKF3402V

R6

10 kΩ

0603

ERJ-3EKF1002V

U1

ARG81800-1

QFN20_4x4

ARG81800KESJSR-1

40

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

PACKAGE OUTLINE DRAWING

For Reference Only – Not for Tooling Use

(Reference JEDEC MO-220WGGD)

Dimensions in millimeters

NOT TO SCALE

Exact case and lead conﬁguration at supplier discretion within limits shown

0.30

0.50

4.00 0.10

0.08 REF

20

0.95

1

2

A

1

2

4.00 0.10

4.10

2.60

DETAIL A

2.60

4.10

D

C

21X

0.75 0.05

0.08

C

SEATING

PLANE

C

PCB Layout Reference View

0.22 0.05

0.50 BSC

0.40 0.10

0.203 REF

0.08 REF

0.20

0.40 0.10

0.05 REF

B

Detail A

2.45 0.10

2

1

A

B

Terminal #1 mark area

Exposed thermal pad (reference only, terminal #1 identiﬁer appearance at supplier

discretion)

20

0.25

2.45 0.10

0.10

C

Reference land pattern layout (reference IPC7351 QFN50P400X400X80-21BM);

all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to

meet application process requirements and PCB layout tolerances; when mounting

on a multilayer PCB, thermal vias at the exposed thermal pad land can improve

thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

Coplanarity includes exposed thermal pad and terminals

D

Figure 19: Package ES, 20-pin wettable ﬂank QFN with exposed thermal pad

41

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

40 V, 500 mA / 1.0 A Synchronous Buck Regulators

with Ultralow Quiescent Current, SYNC_IN, CLK_OUT, and PGOOD

ARG81800

Revision History

Number

Date

June 11, 2019

Description

–

Initial release

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit

improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor

for any infringement of patents or other rights of third parties which may result from its use.

Copies of this document are considered uncontrolled documents.

42

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com


型号：	ARG81800
厂家：	ALLEGRO MICROSYSTEMS
描述：	40 V, 500 mA / 1.0 A Synchronous Buck Regulators
文件：	总42页 (文件大小：3880K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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