ATS636LSE_12 [ALLEGRO]
The ATS636LSE programmable, true power-on state (TPOS), device is optimized Hall-effect IC and rare-earth pellet combinations that switch in response to magnetic signals...; 该ATS636LSE可编程的，真正的通电状态（ TPOS ） ，器件经过优化，霍尔效应IC和切换响应磁信号稀土颗粒组合...
| 型号： | ATS636LSE_12 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | The ATS636LSE programmable, true power-on state (TPOS), device is optimized Hall-effect IC and rare-earth pellet combinations that switch in response to magnetic signals... |
| 文件： | 总15页 (文件大小：348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATS636LSE
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
Features and Benefits
Description
▪ Chopper Stabilization
TheATS636LSE programmable, true power-on state (TPOS),
▫ Extremely low switchpoint drift over temperature
▪ On-chip Protection
▫ Supply transient protection
▫ Output short-circuit protection
▫ Reverse-battery protection
device is optimized Hall-effect IC and rare-earth pellet
combinations that switch in response to magnetic signals
created by ferromagnetic targets in gear-tooth sensing and
proximity applications.
▪ True Zero-Speed Operation
▪ True Power-On State
▪ Single-chip Sensing IC for High Reliability
▪ Optimized Magnetic Circuit
▪ Wide Operating Voltage Range
▪ Internal Regulator
The device is externally programmable. A wide range of
programmability is available on the magnetic operate point
(BOP) while the hysteresis remains fixed. This advanced
feature allows for optimization of the circuit switchpoint and
can drastically reduce the effects of mechanical placement
tolerances found in production environments .
A proprietary dynamic offset cancellation technique, with
an internal high-frequency clock, reduces the residual offset
voltage, which is normally caused by device overmolding,
temperaturedependencies, andthermalstress. HavingtheHall
elementandamplifierinasinglechipminimizesmanyproblems
normally associated with low-level analog signals.
Package: 4-pin SIP (suffix SE)
This device is ideal for use in gathering speed or position
information using gear-tooth-based configurations, or for
proximity sensing with ferromagnetic targets.
Continued on the next page…
Not to scale
Functional Block Diagram
VCC
Program / Lock
To all
subcircuits
Reg
Programmming
Logic
Offset Adjust
OUT
Current
Limit
AMP
S/H
LPF
Clock/Logic
GND
635LSE-DS, Rev. 5
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Description (continued)
The ATS636LSE has the opposite polarity and switches low in the
presence of a ferromagnetic target or tooth and switches high in
the presence of a target valley, window, or when the ferromagnetic
target is removed.
These devices are lead (Pb) free, with 100% matte tin leadframe
plating.
Selection Guide
Output
(Tooth)
Part Number
Packing*
ATS636LSETN-T
Low
13-in. reel, 450 pieces/reel
®
*Contact Allegro for additional packing options.
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Unit
Fault conditions that produce supply voltage
transients will be clamped by an internal Zener
diode. These conditions can be tolerated but
should be avoided.
Supply Voltage
VCC
28
V
Reverse Supply Voltage
Overvoltage Supply Current
Output Off Voltage
VRCC
ICC
–18
100
26.5
V
mA
V
VOUT
Internal current limiting is intended to protect
the device from output short circuits, but is not
intended for continuous operation.
Output Sink Current
IOUT
20
mA
Magnetic Flux Density
B
PD
TA
Unlimited
See Graph
–40 to 150
165
–
Package Power Dissipation
Operating Ambient Temperature
Junction Temperature
–
Range L
ºC
ºC
ºC
TJ
Storage Temperature Range
Tstg
–65 to 170
Pin-out Diagram
Terminal List
Number
Name
Function
1
VCC
Device supply
Device output
2
VOUT
3
4
NC
No connect
GND
Device ground
1
2
3
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
ELECTRICAL CHARACTERISTICS over operating voltage and junction temperature range; unless otherwise noted
Characteristics
Supply Voltage2
Symbol
Test Conditions
Min.
Typ.1
Max.
Unit
VCC
Operating
4.2
–
24
V
After programming VCC = 0 × VCC(min), t > tON
: B < BOP
Power-Up State
POS
High
High
High
–
Low Output Voltage
VOUT(SAT) Output on, IOUT = 20 mA
–
30
–
175
50
–
400
90
10
5.5
5.5
–5
50
5
mV
mA
μA
mA
mA
mA
μs
Output Current Limit3
Output Leakage Current
IOUTM
IOFF
Pulse test method, output on
Output off, VOUT = 24 V
Output off (high)
–
2.5
2.5
–
Supply Current
ICC
Output on (low)
–
Reverse Supply Current
Power-On Delay4
IRCC
tON
VRCC = –18 V
–
Output off, VCC > VCC(min)
RL = 820 Ω, CL = 10 pF
RL = 820 Ω, CL = 10 pF
–
35
1.2
1.2
250
–
Output Rise Time
tr
–
μs
Output Fall Time
tf
–
5
μs
Sampling Frequency
fsample
VZsupply
VZoutput
IZsupply
IZoutput
–
–
kHz
V
Supply Zener Voltage
Output Zener Voltage
Supply Zener Current5
Output Zener Current
1Typical data is at VCC = 12 V and TA = 25°C.
ICC = ICC(max) + 3 mA, TA = 25°C
IOUT = 3 mA, TA = 25°C
VS = 28 V
28
30
–
–
–
–
V
–
8.5
3
mA
mA
VO = 30 V
–
–
2Do not exceed the maximum thermal junction temperature: see power derating curve.
3Short circuit protection is not intended for continuous operation and is tested using pulses.
4The Power-On Delay is the time that is necessary before the output signal is valid.
5The maximum spec limit for this parameter is equivalent to ICC(max) + 3 mA.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
MAGNETIC CHARACTERISTICS over operating voltage and junction temperature range using reference target; unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
bit
Switchpoint
–
–
–
7
1
1
–
–
–
Number of Programming Bits
Switchpoint Polarity
Programming Lock
bit
bit
Gear Tooth / Proximity Characteristics (Low switchpoint only)
Temperature = 25°C, Code = –127
2.5
–
–
–
–
1.5
–
mm
mm
mm
Programming Air Gap Range1
AGRange
Temperature = 25°C, Code = +127
Programming Resolution
AGRes
AGDrift
Temperature = 25°C Program Air Gap = 2.5 mm
–
0.05
Air Gap Drift Over Full Temperature
Range2
Device programmed to 2.5 mm
–
0.2
–
mm
Over tooth (ATS636LSE)
Over valley (ATS636LSE)
–
–
Low
–
–
–
–
Polarity
P
High
1The switchpoint will vary over temperature. A sufficient margin obtained through customer testing is required to guarantee functionality over
temperature. Programming at larger air gaps leaves no safety margin for switchpoint drift. See the applications note Proximity Sensing
Programming Technique on the Allegro website at http://www.allegromicro.com for additional information.
2The switchpoint will vary over temperature, proportionally to the programmed air gap. This parameter is based on characterization data and is not
a tested parameter in production. Switchpoint air gap generally drifts downward as temperature increases.
Reference Target Flux Density vs. Position
Tooth and Valley Field vs. Air Gap
Reference Target
1400
1200
1000
800
600
400
200
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
5.25
5.50
5.75
6.00
1400
1200
1000
Reference Target Tooth
Reference Target Valley
800
600
400
200
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
30 60
90 120 150 180 210 240 270 300 330 360
Position (º)
Air Gap [mm]
Reference Target Tooth and Valley Field vs. Air Gap
Reference Target Flux Density vs. Position: Typical
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Characteristic Performance
Data taken from 3 lots, 30 pieces/lot
Reference Target 8x
ICC ON
ICC OFF
6
5
4
3
2
1
0
6
5
4
3
4V
15V
24V
4V
15V
24V
2
1
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
TEMPERATURE (°C)
VSAT
500
400
300
200
100
20mA
0
-50
-25
0
25
50
75
100
125
150
175
TEMPERATURE (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Data taken from 3 lots, 30 pieces/lot
Reference Target 8x
BOP/BRP vs. Program Code
7
6
5
4
3
2
1
0
Code -8 BOP
Code -8 BRP
Code
Code
0
0
BOP
BRP
Code +32 BOP
Code +32 BRP
Code +127 BOP
Code +127 BRP
-50
0
50
100
150
200
TEMPERATURE (°C)
Notes:
• Air gaps for Code 127 at 150°C are interpolated due to test limitations at minimum air gap.
• These graphs are intended to provide an understanding of how the program codes affect the switchpoints. In a production
environment, individual devices would be programmed to individual codes to ensure all devices switch at the same air gap.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
REFERENCE TARGET DIMENSIONS
Target
Outside Diameter
(Do)
Face Width
(F)
Circular Tooth Length Circular Valley Length Tooth Whole Depth
(T)
(PC – T)
(ht)
Reference Target
120 mm
6 mm
23.5 mm
23.5 mm
5 mm
Reference Target
Reference Target
Gear Parameters for Correct Operation
Characteristic
Description
Min. Typ. Max. Unit
Tooth Whole Depth (ht)
Circular Valley Length (Pc – T)
Circular Tooth Length (T)
Face Width (F)
Depth of Target Valley
Length of Target Valley
5
13
5
–
–
–
–
–
–
–
–
mm
mm
mm
mm
Length of Target Tooth
Thickness or Width of Target Tooth
5
Material: CRS 1018
Electromagnetic Capability (EMC) Performance
Please Contact Allegro MicroSystems for EMC Performance
Test Name
ESD – Human Body Model
ESD – Machine Model
Conducted Transients
Direct RF Injection
Bulk Current Injection
TEM Cell
Reference Specification
AEC-Q100-002
AEC-Q100-003
ISO 7637-1
ISO 11452-7
ISO 11452-4
ISO 11452-3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Functional Description
separated from the magnetically induced signal in the frequency
Chopper-Stabilized Technique
The basic Hall element is a small sheet of semiconductor material
in which a constant bias current will flow when a constant volt-
age source is applied. The output will take the form of a voltage
measured across the width of the sheet and will have negligible
value in the absence of a magnetic field. When a magnetic field
with flux lines at right angles to the Hall current is applied, a
small signal voltage directly proportional to the strength of the
magnetic field will occur at the output terminals.
domain. The offset (and any low frequency noise) component of
the signal can be seen as signal corruption added after the signal
modulation process has taken place. Therefore, the DC offset is
not modulated and remains a low frequency component. Con-
sequently, the signal demodulation process acts as a modulation
process for the offset causing the magnetically induced signal
to recover its original spectrum at baseband while the DC offset
becomes a high frequency signal. Then, using a low pass filter,
the signal passes while the modulated DC offset is suppressed.
This signal voltage is proportionally small relative to the offset
produced at the input of the chip. This makes it very difficult
to process the signal and maintain an accurate, reliable output
over the specified temperature and voltage range. Therefore, it is
important to reduce any offset on the signal that could be ampli-
fied when the signal is processed.
The advantage of this approach is significant offset reduction,
which desensitizes the chip against the effects of temperature and
stress. The disadvantage is that this technique features a demodu-
lator that uses a sample and hold block to store and recover the
signal. This sampling process can slightly degrade the signal-to-
noise Ratio (SNR) by producing replicas of the noise spectrum at
the baseband. The degradation is a function of the ratio between
the white noise spectrum and the sampling frequency. The effect
of the degradation of the SNR is higher jitter, a.k.a. signal repeat-
ability. In comparison to a continuous time device, the jitter spec
can be increased by a factor of five.
Chopper stabilization is a unique approach used to minimize
input offset on the chip. This technique removes a key source of
output drift with temperature and stress, and produces a 3× reduc-
tion in offset over other conventional methods.
This offset reduction chopping technique is based on a signal
modulation-demodulation process. The undesired offset signal is
Regulator
Sample/
Amplifier
Hold
Clock
Hall Element
Figure 1. Concept of Chopper-Stabilization Algorithm
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Addressing / Programming Protocol
The ATS636LSE magnetic operate point, BOP, is programmed by a high voltage pulse, VPP, while the remaining pulses should
serially addressing the devices through the supply terminal (1).
After the correct operate point is determined, the device program-
ming bits are selected and blown, then a lock bit is selected and
blown to prevent any further (accidental) programming.
be VPH pulses. Note that the difference between BOP and the
magnetic release point, BRP, the hysteresis, BHYS , is fixed for all
addresses.
Addressing with negative polarity The magnetic operate
point, BOP, is adjustable with negative polarity using 7 bits or
128 addresses. To invert the polarity it is necessary to first apply
a keying sequence (figure 3). The polarity key contains a VPP
pulse and at least 1 VPH pulse, but no more than 6 VPH pulses;
the key in figure 3 shows 2 VPH pulses. The addresses are then
sequentially selected until the required operate point is reached.
Addressing BOP is programmable in both the positive and
negative direction from its initial value. Addressing is used to
determine the desired code, while programming is used to lock
the code. A unique key is needed to blow fuses, while addressing
as described below does not allow for the device to be pro-
grammed accidentally.
Addressing with positive polarity The magnetic oper-
ate point, BOP, is adjustable using 7 bits or 128 addresses. The
addresses are sequentially selected (figure 2) until the required
operate point is reached. The first address must be selected with
The first address must be selected with a high voltage pulse, VPP
while the remaining pulses should be VPH pulses.
,
VPP
VPP
VPH
VPL
VPH
VPL
td(1)
td(0)
td(1)
td(0)
0
0
Figure 3. Addressing Pulses: Negative Polarity
Figure 2. Addressing Pulses: Positive Polarity
PROGRAMMING PROTOCOL Valid over operating temperature range, unless otherwise noted
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Programming Protocol (TA = 25°C)
VPL
VPH
VPP
IPP
td(0)
td(1)
tdP
tr
Minimum voltage range during programming
4.5
8.5
25
–
5
–
5.5
15
27
–
V
V
Programming Voltage1,2
Programming Current
Pulse Width
–
V
Maximum supply current during programming
Off-time between bits
500
–
mA
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
20
20
100
–
–
Enable, address, program, or lock bit on-time
Program pulse on-time
–
–
300
–
–
Pulse Rise Time
Pulse Fall Time
VPL to VPH or VPP
11
5
tf
VPH or VPP to VPL
–
–
1Programming voltages are measured at pin 1 (VCC) of the SIP. A minimum capacitance of 0.1 ꢀF must be connected from VCC to GND of the SIP to
provide the current necessary to blow the fuse.
2Testing is the only method that guarantees successful programming.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
3 need to be programmed. A bit is programmed by addressing
the code and then applying a VPP pulse, the programming is not
reversible. An appropriate sequence for blowing code 5 is shown
in figure 5.
Program Enable To program the device, a keying sequence
is used to activate /enable the programming mode as shown in
figure 4. This program key sequence consisting of a VPP pulse, at
least seven VPH pulses, and a VPP pulse with no supply interrup-
tions. The sequence is designed to prevent the device from being
programmed accidentally (e.g., as a result of noise on the supply
line).
Polarity Bit Programming If the desired switchpoint has
negative polarity, the polarity bit must be programmed. To do this
it is necessary to first apply the polarity key sequence before the
program key sequence (figure 6). Finally a VPP pulse of duration
tdP must be applied to program this bit, the programming is not
reversible. The polarity bit is for adjusting programming range
Code Programming After the desired switchpoint code is
selected (0 through 127), each bit of the corresponding binary
address should be programmed individually, not at the same
time. For example, to program code 5 (binary 000101), bits 1 and only and will not affect the output polarity.
PROGRAM ENABLE
7 or More Pulses
VPP
(8 Pulses Shown)
VPH
VPL
td(1)
td(1)
td(0)
0
Figure 4. Program Enable Pulse Sequence
VPP
Bit 3 Address
Program Enable
000100
Code 4
Program Enable
VPH
VPL
td(1)
td(1)
td(0)
tdP
000001
Code 1
0
Figure 5. Code Programming Example
VPP
Program Enable
VPH
VPL
td(1)
td(0)
td(1)
tdP
0
Figure 6. Polarity Bit Programming
Allegro MicroSystems, Inc.
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Lock-BitProgrammingAfterthedesiredcodeisprogrammed,the information on device programming as well as programming
lock bit (code 128), can be programmed (figure 7) to prevent further products. Programming hardware is available for purchase and
programming of the device. Again, programming is not reversible. programming software is available for free.
See Allegro website at http://www.allegromicro.com for extensive
Lock Bit
Address
128 Pulses
VPP
Program Enable
VPH
VPL
td(1)
td(1)
td(0)
tdP
0
Figure 7. Lock -Bit Programming Pulse Sequence
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Typical Application Circuit
For applications it is strongly recommended that an external
ceramic bypass capacitor in the range of 0.01 μF to 0.1 μF be
connected between the supply and ground of the device to reduce
both external noise and noise generated by the chopper-stabi-
lization technique. (The diagram below shows a 0.1 μF bypass
capacitor.)
of the device. The pull-up resistor should be chosen to limit the
current through the output transistor; do not exceed the maximum
continuous output current of the device.
Note: This circuit cannot be used to program the device, as the
series resistance is too large, and a minimum capacitance of
0.1 μF must be connected from VCC to GND of the SIP to pro-
vide the current necessary to blow the fuse.
The series resistor RS in combination with the bypass capacitor
creates a filter for EMC pulses. The series resistor will have a
drop of approximately 800 mV, this must be considered for the
minimum VCC requirement of the ATS636LSE. The small capaci-
tor on the output of the device improves the EMC performance
Extensive applications information on magnets and Hall-
effect ICs including chopper stabilization is available in
the Allegro Electronic Data Book CD, or at the website:
http://www.allegromicro.com.
RS
5V
100 Ohm
VCC
1.2k Ohm
RL
1
ATS636
2
0.1 μF
VSupply
VOUT
120 pF
4
GND
Typical Application:
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Power Derating – SE Package
Due to internal power consumption, the junction temperature
of the IC (junction temperature, TJ) is higher than the ambient
environment temperature, TA. To ensure that the device does not
operate above the maximum rated junction temperature use the
following calculations:
ΔT = PD × RθJA
Where:
PD = VCC × ICC
∴ΔT = VCC × ICC × RθJA
Power Dissipation versus Ambient Temperature
Where ΔT denotes the temperature rise resulting from the IC’s
4500
4000
3500
3000
2500
2000
1500
1000
500
power dissipation.
TJ = TA + ΔT
RθJA = 77°C/W
TJ(max) = 165°C
2-layer PCB
(RQJA = 77 ºC/W)
Typical TJ calculation:
TA = 25°C
VCC = 5 V
ICC(on) = 5.5 mA
PD = VCC × ICC = 5 V × 5.5 mA = 27.5 mW
ΔT = PD × RθJA = 27.5 mW × 77°C/W = 2.0°C
TJ = TA + ΔT = 25°C + 2.0°C = 27.0°C
0
Maximum Allowable Power Dissipation Calculation:
20
40
60
80
100
120
140
160
180
Temperature (°C)
TJ = TA + ΔT
TJ(max) = 165°C, if TA = 150°C
then:
165 = 150 + ΔT
ΔT = 15°C
ΔT = PD × RθJA (RθJA = 77°C/W)
\ PD(max) = 15°C / 77°C/W = 195 mW at TA = 150°C
Maximum VCC for PD(max) = 111 mW at TA = 150°C
PD = VCC × ICC , ICC = 10 mA (max) at 150°C
VCC = PD / ICC = 195 mW / 5.5 mA = 35.4 V
Allegro MicroSystems, Inc.
115 Northeast Cutoff
13
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Package SE 4-Pin SIP
7.00±0.05
B
E
10.00±0.05
LLLLLLL
NNN
YYWW
3.3±0.1
Branded
Face
F
Standard Branding Reference View
D
= Supplier emblem
L = Lot identifier
1.3±0.1
N = Last three numbers of device part number
Y = Last two digits of year of manufacture
W = Week of manufacture
A
4.9±0.1
1
2
3
4
6.23±0.10
0.9±0.1
+0.06
–0.04
0.38
24.65±0.10
0.60±0.10
For Reference Only, not for tooling use (reference DWG-9001)
Dimensions in millimeters
Dambar removal protrusion (16X)
A
11.60±0.10
B
C
D
E
F
Metallic protrusion, electrically connected to pin 4 and substrate (both sides)
Thermoplastic Molded Lead Bar for alignment during shipment
Branding scale and appearance at supplier discretion
1.0 REF
2.00±0.10
Active Area Depth, 0.43 mm
Hall element (not to scale)
1.0 REF
A
1.60±0.10
C
0.71±0.10
0.71±0.10
1.27±0.10
5.50±0.10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
14
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable Back Biased Hall-Effect
Switch with TPOS Functionality
ATS636LSE
Revision History
Revision
Revision Date
January 30, 2012
Description of Revision
Update product availability
Rev. 5
Copyright ©2005-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
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