SMA6861MLF2175 [ALLEGRO]
AC Motor Controller, ROHS COMPLIANT, SIP-24;
| 型号： | SMA6861MLF2175 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | AC Motor Controller, ROHS COMPLIANT, SIP-24 局域网 电动机控制 |
| 文件： | 总27页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Information
High Voltage SLA6860M and SMA6860M Series
Driver ICs for 3-Phase DC Motor Applications
Leadform 2451
Introduction
The SLA6860M and SMA6860M Series consists of inverter
power module (IPM) devices that integrate within a single,
compact package: power MOSFETs, pre-driver ICs, and fast
recovery diodes. These products are especially suitable for
driving the inverters of low-capacity motors, such as those
used in 100 to 200 V fans or pumps for air conditioners.
Leadform 2175
Leadform 2452
Features and benefits include the following:
▪ Three built-in bootstrap fast recovery diodes (FRD),
each with current-limiting resistor, and capable of
withstanding high voltages: 600 V at 1 A
▪ Overcurrent limiting (OCL) function, with fault signal
output and shutdown input terminal; when the user-
determined maximum current level is exceeded, PWM
on-off cycling is initiated to effectively limit current
▪ Built-in overcurrent protection (OCP) function; when an
overcurrent condition, such as an output short circuit, is
detected, the internal high-side and low-side logic ICs
shut down the output driver gates and issue a fault signal
▪ Optional automatic shutdown of high-side and low-side
gates if an abnormal condition occurs (overtemperature,
overcurrent, undervoltage on control power supply, and
so forth); enabled by connecting together the SD1 and
SD2 terminals
▪ Built-in overtemperature protection for both high-side
and low-side circuits; thermal shutdown (TSD) occurs
when the temperature of the logic chips exceed a user-
determined value, the internal high-side and low-side
logic ICs shut down the output driver gates and issue a
fault signal
Leadform 2171
Figure 1. SMA6860M Series packages are SIPs, offering compact
configurations both with heatsink pad (leadforms 2171 and 2175)
and without (leadforms 2451 and 2452). Both horizontal mount and
vertical mount are available.
▪ Built-in undervoltage lockout (UVLO) protection for
each control power supply, VCC1, VCC2, and VBx;
when voltage falls below a set value, the gates are shut
down and VCC1 and VCC2 output an alarm signal
▪ Alarm signal (shutdown) output when protection circuits
enable; high-side faults (UVLO and TSD) are signaled
on the SD1 terminal, low-side faults (TSD, OCP, and
UVLO) are signaled on the SD2 terminal
Product Lineup*
Input
Voltage
(VAC)
MOSFET
Rating
Heat-
sink
Type
Application
Contents
Introduction
1
2
3
SMA6861M 250 V / 2 A
FAN Motor, Pump
230
230
230
230
230
230
–
–
Functional Description
Terminal Descriptions
SMA6862M 500 V / 1.5 A FAN Motor, Pump
SMA6863M 500 V / 2.5 A FAN Motor, Pump
–
Protection Functions
8
SLA6866M 250 V / 2 A
FAN Motor, Pump
Yes
Yes
Yes
Typical Applications
12
18
19
19
Protection Function Timing
Application Circuit Recommendations
Electrical Characteristics Data
SLA6867M 500 V / 1.5 A FAN Motor, Pump
SLA6868M 500 V / 2.5 A FAN Motor, Pump
*SMA6861M:SLA6866M, SMA6862M:SLA6867M, and also
SMA6863M:SLA6868M are electrically identical respectively.
28610.14, Rev. 2
MOSFET turns on at VxINx = high). The boot capacitors are con-
nected between VB1 and U, VB2 and V, and VB3 and W1, as the
high voltage power source.
▪ Power MOSFETs incorporating fast recovery diodes (FRD)
provide low losses in comparison with IGBT technology
▪ Use of SIP 24-pin power package, proven in other high-
volume Sanken product lines, with L-bend and zigzag
leadforms available; L-bends formed with precautions to
ensure device integrity; zigzags for stable mounting; heatsink
tab option
The protection functions, including overcurrent protection
(enable at detected short circuit, and so forth), overtemperature
protection (at abnormal ambient temperature, overload, and so
forth), and undervoltage of low control power supply voltage
(at instantaneous fall, and so forth) are built-in and when any of
these functions is operated, it can be monitored at the correspond-
ing output terminal.
Functional Description
The functional block diagram for one of the three device phases
is shown in figure 2. High voltage power and 15 VDC are input
between VBB and LS1/LS2, between VCC1 and COM1, and
between VCC2 and COM2. The on/off signals of the power
MOSFETs are operated by six signals: HIN1, HIN2, HIN3,
The current limiter (OCL) signal is provided as a control signal,
and when the current flowing across the shunt resistor exceeds
the typical limit value, the OCL terminal turns on. Current limit-
ing can be enabled by connecting this signal to the SD1 terminal
(for high-side limiting) or to the SD2 terminal (for low-side
LIN1, LIN2, and LIN3. These input signals are positive logic (the limiting).
VB1
VB2
VB3
VCC1
VBB
UVLO
UVLO
UVLO
UVLO
HIN1
HIN2
HIN3
Input
Logic
High-Side
Level Shift Driver
COM1
W1
W2
V
SD1
VCC2
U
UVLO
LIN1
LIN2
LIN3
Input Logic
(OCP Reset
Low-Side
Driver
)
COM2
OCP
Thermal
LS2
LS1
Shutdown
SD2
OCL
RC
OCP and OCL
Figure 2. SLA6860M/SMA6860M Series Phase Block Diagram. These devices
support high-side and low-side three-phase MOSFET output drivers.
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LS1 and LS2 These are the source terminals for the low-side
power MOSFETs. LS1 and LS2 should be connected together
externally. When a shunt resistor is connected to this terminal, the
lengths of the traces should be as short as practicable. If the trace
lengths are long, malfunctions due to noise are likely to occur.
Terminal Descriptions
A summary description of the function of the various terminals is
given in the Terminal List table. Pin 1 for each package appears
in figure 3. This section provides detailed functional descriptions
of the individual pins.
VCC1 and VCC2 These are the power supply terminals of the
built-in pre-driver ICs. VCC1 and VCC2 should be should be
connected together externally. In order to prevent malfunctions
due to noise on the power supply lines, a ceramic bypass capaci-
tor (0.01 to 0.1 μF) should be mounted near the terminals.
VBB This is the terminal for the main power supply. For supply-
ing the SMA6861M, VBB should be 200 VDC or lower and in
other products, 400 VDC or lower. To suppress surge voltage, a
snubber capacitor (0. 01 to 0.1 μF) and an electrolytic capacitor
should be connected to the device by traces having the shortest
length practicable. If the trace lengths are long, surge voltages
will be increased. It should be verified that surge voltage does not
exceed the breakdown voltage of the MOSFETs internal to the
device itself.
Note: If VCCx exceeds 20 V, permanent damage may occur. It is
recommended to add a Zener diode (VZ = 18 to 20 V) to protect
against such surge voltages.
The control power supply undervoltage protection circuit is inte-
grated with VCC1 and VCC2. The supplied voltage should not be
allowed to drop below the rated threshold voltage of VCC1 and
VCC2.
U, V, W1, and W2 These are the output terminals connected to
the motor. W1 and W2 should be connected together externally,
and are used in short circuit events.
Terminal List Table
Number
Name
Function
1
VB1
High side bootstrap terminal (U phase)
2
VB2
VB3
VCC1
SD1
COM1
HIN3
HIN2
HIN1
VBB
W1
High side bootstrap terminal (V phase)
High side bootstrap terminal (W phase)
High side logic supply voltage
3
4
5
High side shutdown input and UVLO fault signal output
High side logic GND terminal
6
7
High side input terminal (W phase)
8
High side input terminal (V phase)
9
High side input terminal (U phase)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Main supply voltage
Output of W phase (connect to W2 externally)
Output of V phase
V
W2
Output of W phase (connect to W1 externally)
Low side emitter terminal (connect to LS1 externally)
Overcurrent protection hold time adjustment input terminal
Low side emitter terminal (connect to LS2 externally)
Output for overcurrent limiting
LS2
RC
LS1
OCL
LIN3
LIN2
LIN1
COM2
SD2
VCC2
U
Low side input terminal (W phase)
Low side input terminal (V phase)
Low side input terminal (U phase)
Low side GND terminal
Low side shutdown input and overtemperature, overcurrent, and UVLO fault signals output
Low side logic supply voltage
Output of U phase
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31.3 ±0.2
31 ±0.2
24.4 ±0.2
16.4 ±0.2
4.8 ±0.2
0.6
Gate protrusion
Exposed
heatsink pad
1.7 ±0.1
Ø3.2 ±0.15
Ø3.2 ±0.15
2X Gate protrusion
2.45 ±0.2
BSC
16 ±0.2
B
12.9 ±0.2
(A)
9.9 ±0.2
Branding Area
2X Exposed
tie bar
R1
REF
5 ±0.5
+0.7
– 0.5
9.5
+0.15
– 0.05
0.5
4.5
REF
1.27 ±0.7
4.5 ±0.7
4.8 ±0.2
0.5 ±0.1
A
+0.15
– 0.05
0.6
31.3 ±0.1
31 ±0.2
24.4 ±0.2
16.4 ±0.2
0.6
Gate protrusion
Exposed
heatsink pad
1.7 ±0.1
Ø3.2 ±0.15
Ø3.2 ±0.15
2X Gate protrusion
2.45 ±0.1
BSC
16 ±0.2
B
12.9 ±0.2
(B)
3 ±0.3
BSC
9.9 ±0.1
Branding Area
2X Exposed
tie bar
2.2 ±0.6
BSC
R1
REF
4.4
REF
+0.2
– 0.1
0.6
2.2 ±0.6
BSC
1.27 ±0.2
A
Figure 3(A) and (B). Package Outline Drawings. (A) LF2171 vertical
mount, (B) LF2175 horizontal mount, with heatsink pads.
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Gate protrusion
31.3 ±0.2
31 ±0.2
4 ±0.2
2X Gate protrusion
1.2 ±0.1
BSC
(C)
10.2 ±0.2
3 ±0.5
BSC
2X Exposed
tie bar
2.2 ±0.7
BSC
R1
REF
4.4
REF
+0.15
– 0.05
A
1
2.2 ±0.7
BSC
1.27 ±0.1
1.27 ±0.6
+0.2
– 0.1
0.7
C
0.55
+0.15
– 0.05
B
0.6
Gate protrusion
31.3 ±0.2
31 ±0.2
4 ±0.2
2X Gate protrusion
1.2 ±0.1
BSC
(D)
10.2 ±0.2
2X Exposed
tie bar
R1
REF
5 ±0.5
+0.7
– 0.5
9.5
+0.15
– 0.05
0.5
4.5
REF
A
1.27 ±0.5
1
4.5 ±0.5
+0.15
– 0.05
0.6
Figure 3 (C) and (D). Package Outline Drawings. (C) LF2451, L-bend
horizontal mount and (D) LF2452, vertical mount; no heatsink pads.
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COM1 and COM2 These are the ground terminals of the built-
in logic control ICs. COM1 and COM2 should be connected
together externally.
▪ Consider the time interval, tOFF, when the low-side MOSFETs
are not on (except when the FRD conducts); the longer tOFF
becomes, the further the capacitor voltage falls; therefore, the
larger the capacity required.
▪ In the case of 2-phase modulation or a 120° conduction
system, the time interval when the MOSFETs are on becomes
longer.
▪ The relationship between tOFF and the recommended
capacitance of a CBOOT capacitor is shown by the following
formula (given ∆V ≤ 0.5 V):
Because malfunctions are likely to be caused by variations in the
potential at these terminals, attention should be paid to the exter-
nal connections for these terminals. Connections should be made
such that there are no appreciable variations in potential, such as
due to fluctuations in power current levels, short wiring length, or
other causes.
VB1, VB2, and VB3 These are the power supply terminals for
driving the high-side MOSFETs. As shown in figure 4, three
bootstrap capacitors, CBOOTx, should be connected, with one
each between VB1 and U, VB2 and V, and VB3 and Wx. Because
these bootstrap circuits perform independent operations, a capaci-
tor is required for each phase. At start-up, the CBOOTx capaci-
tors should be charged. CBOOTx should be sufficiently charged
by turning on the low-side MOSFET at the beginning.
CBOOTx (μF) ≥ tOFF (ms) .
The validity of the result yielded by this formula should be
verified using the actual product.
▪ The control power supply undervoltage protection circuit is
integrated with VB1, VB2, and VB3. The supplied voltage
should not be allowed to drop below the rated threshold
voltage of these terminals.
One 210 Ω series resistor and one 600 V/1 A bootstrap diode are
built in inside the device. To determine the constants for the boot-
strap circuit, the following factors should be taken into account:
HINx and LINx These are the command signal inputs for
directing power to the MOSFETs. A pull-down resistor (20 kΩ)
is built-in for these active high inputs, and the command signals
are received at the Schmidt trigger circuit for the input logic (see
figure 5).
▪ What constitutes the optimal capacitance value of the
bootstrap capacitor is dependent on: the driving method
(modulation method and output frequency), the switching
frequency (carrier frequency), the modulation rate (duty
cycle), and the gate input capacitance of the MOSFETs.
The input voltage is 7 V maximum; if a higher voltage is input,
the circuit may be permanently damaged. Adding a series resistor
VBB
VBx
VBB
CBOOT
charge current
5V
High-Side
CBOOTx
To Motor
Drive Circuit
VCC1
VCC2
HIN
LIN
2 kΩ
U,V,W
LSx
VCC
20kΩ
Low-Side
Drive Circuit
COM
Figure 4. Connection of Bootstrap Capacitor. There is a separate CBOOT
capacitor for each of the three phases.
Figure 5. HINx and LINx Terminals Internal Equivalent Circuit
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(100 Ω to 1 kΩ) between the external system microprocessor
and this device should be considered. Also, a ceramic capacitor
(100 to 1000 pF) and a Zener diode (VZ = 5. 6 to 6. 2 V) between
the xINx terminals and the corresponding COMx terminal should
be considered.
When RR is short-circuited, the OPC function does not operate.
In case of disconnection of the capacitor CC, the duration of OCP
becomes short, to release protection operation immediately.
SD2 This is the terminal for fault signal output at abnormal
operation, and also a shutdown command input terminal. During
OCP, low-side drive circuit IC overtemperature protection, or
control power supply undervoltage protection between VCC2 and
COM2, the transistor of the open collector circuit is turned on
(see figure 7).
RC When the current that is flowing across the shunt resistor is
excessive and the voltage of the LS terminal exceeds 1 V typical,
for 2 μs or longer, the device evaluates this as an overcurrent
condition and initiates the overcurrent protection (OCP) function.
OCP operates as follows:
Because the SD2 terminal also plays the role of shutdown com-
mand input terminal, when it is externally short-circuited between
SD2 and COM2, the low-side MOSFETs are turned off com-
pletely.
1. Short-circuit the SD2 terminal (open collector).
2. Turn off the low-side power MOSFETs completely.
3. Short-circuit the RC terminal.
A filter (3.3 μs typical) is integrated into the device, for the pre-
vention of malfunction due to noise. A pull-up resistor, R2, with a
value of 3.3 to 10 kΩ, should be externally connected, even if the
SD2 terminal is not used. In addition, a capacitor, C2, of 0.01 μF
or less should be connected for eliminating noise.
When the power MOSFETs are turned off, although the voltage
falls below 1 V, the gate-off operation and the short-circuiting of
the SD2 terminal continue for a fixed period. This period is set by
an external pull-up resistor RR and capacitor CC, connected to
this terminal as shown in figure 6. The relationship between the
constants of RR, CC and the duration of OCP operation, tOCP, is
given in the following formula (given a pull-up voltage of 5 V):
SD1 This is the terminal for fault signal output for high-side
drive circuit IC overtemperature protection, and also a shutdown
command input terminal. The transistor of the open collector
circuit is turned on at the operation of overtemperature protection
(see figure 8).
tOCP (μs) = 1.2 × RR (kΩ) × CC (nF) .
The application should be designed for values of RR between
33 and 390 kΩ, and CC between 1 and 4.7 nF. In case where RR =
360 kΩ and CC = 4.7 nF, tOCP would be approximately 2 ms.
Because the SD1 terminal also plays the role of shutdown
command input terminal, when it is externally short-circuited
between SD1 and COM1, the high-side MOSFETs are turned off
completely. Furthermore, after a short-circuit between SD1 and
If the pull-up resistor RR becomes disconnected (open) from the
RC terminal, the OCP function will not be released.
50 Ω
50 Ω
+5V
+5V
On during OCP
On during OCP
+3.5 V
RR
R2
OCP
release
To Shutdown
–
+
RC
SD2
Filter
3.3 μs
CC
C2
Comparator
COM2
COM2
Figure 6. RC Terminal Internal Equivalent Circuit
Figure 7. SD2 Terminal Internal Equivalent Circuit
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COM1 is removed, the MOSFETs begin again to turn on at the
rising edge of the HIN terminal signal.
should have RL and Cf connected as shown in figure 10. RL and
Cf should be placed near the SDx terminal, which is an input
terminal.
A filter (3.3 μs typical) is integrated into the device, for the pre-
vention of malfunction due to noise. A pull-up resistor, R1, with a
value of 3.3 to 10 kΩ, should be externally connected, even if the
SD1 terminal is not used. In addition, a capacitor, C1, of 0.01 μF
or less should be connected for eliminating noise.
The recommended constant ranges of RL and Cf are:
RL = 1 to 10 kΩ
Cf = 0.001 to 0.01 μF
OCL This is the output terminal of current limiter signal. The
internal circuit composition is shown in figure 9.
When the current limiter function is not used, the OCL terminal
should be left floating.
When the LS1 terminal voltage continuously exceeds 0.53 V
typical for 2 μs or longer, the transistor of the open collector
circuit connected to the OCL terminal is turned on.
Protection Functions
This section describes in detail the various device protection
features provided with the SLA6860M and SMA6860M.
In the case where the OCL signal is connected to the SD1
terminal and the SD2 terminal, each one of those connections
Undervoltage Lockout (UVLO) on Control Power Supply
When the gate-driving voltages on the output MOSFETs become
too low, the losses of the power MOSFETs increase, and in the
worst case the circuits may be damaged. In order to prevent this,
undervoltage protection circuits are built into the control power
supply.
50 Ω
+5V
On in OCP
R1
To Shutdown
SD1
Filter
3.3 μs
The high-side driver IC monitors the voltage between VCC1 and
COM1, the voltage between VB1 and U, VB2 and V, and VB3
and W1. As shown in the timing chart (figure 11), when the VBx
voltage exceeds the UVHH voltage (10.5 V typical), that enables
the HO output (gate of MOSFET) pulses on each subsequent
HINx rising edge (edge operation). When the VBx voltage is
below the UVHL value (10 V typical), the high-side MOSFETs
are shut down.
C1
COM1
Figure 8. SD1 Terminal Internal Equivalent Circuit
+5V
RL
+5V
RL
0.53 V
50 Ω
OCL
OCL
–
+
Filter
2μs(typ)
2 kΩ
SD1 [SD2]
LS1
Cf
Cf
400 kΩ
COM2
COM1
COM2
Figure 9. OCL Terminal Internal Circuit
Figure 10. OCL Function Terminal Connections
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When the output of the power MOSFETs is shut down by UVLO
operation due to falling boot voltage, the transistor on the open
collector SD1 terminal does not turn on. At UVLO operation due
to VCC voltage fall, however, the SD1 terminal does turn on.
Overtemperature Protection (TSD) A thermal shut-
down (TSD) protection circuit is built in for the SLA6860M-
SMA6860M Series. In the event of overheating, such as due
to increased power consumption or an increase in the ambient
temperature at the device, the power MOSFETs are shut down.
The determination of a overtemperature condition is made by the
driver circuit ICs on the high side and low side, in accordance
with table 1. When the operating temperature rises above 135°
typical, thermal shutdown enables. When the temperature subse-
quently falls below 115°, thermal shutdown is released, and the
device can continue operation again in accordance with the xINx
signals.
The high-side UVLO detection circuit and the internal equivalent
circuit are shown in figure 12. As shown there, a filter is inserted
to prevent line noise from affecting the control power supply
voltage.
When the voltage between VCC1 and COM1 falls below the
UVLL voltage of 11 V typical, the high-side MOSFETs are shut
down. When the power supply voltage rises above the UVLH
voltage level of 11.5 V typical, that enables the HO output (gate
of MOSFET) pulses on each subsequent HINx rising edge
(referred to as edge operation).
Temperature monitoring occurs both on the high side and the low
side. When TSD operates on the high side, those MOSFETs are
turned off, and transistor of the open collector circuit to the SD1
terminal is turned on.
The low-side driver IC monitors the voltage between VCC2 and
COM2. As shown in the low-side timing diagram (figure 13),
when the voltage between VCC2 and COM2 falls below the
UVLL voltage of 11 V typical, the low-side MOSFETs are shut
down and the transistor of the open collector circuit connected to
the SD2 terminal is turned on.
Note: Because the temperatures of the power MOSFETs them-
selves are not monitored for overtemperature condition, the
internal protection function on its own may not be sufficient to
prevent damage to the device due to overheating. It also should
be noted that in a case where the temperature of the MOSFETs
rise very rapidly, the overtemperature detection may lag.
When the VCC2 voltage rises above the UVLH voltage of 11.5 V
typical, the shutdown of the low-side MOSFETs is released and
the transistor of the SD2 terminal is turned off, allowing the
device to operate in accordance with the command signal input
on the LINx pins (steady state operation).
Overcurrent Protection (OCP) The SLA6860M-SMA6860M
Series has a built-in overcurrent protection circuit. If the voltage
between LS1 and COM2 (1.0 V or higher) continues for longer
than the blanking time, tBLANK (2 μs typical), then overcurrent
protection starts operation (see figure 15).
At the start of OCP operation, the transistor connected to the SD2
terminal (through a 50 Ω resistor) turns on, and simultaneously
the MOSFET connected to the RC terminal (through a 50 Ω
resistor) turns on (see figure 16).
As shown in figure 14, a filter is inserted to prevent line noise
from affecting the control power supply voltage, as in the high-
side UVLO circuits, described above. The filter protects against
the sharp fall of VBx, VCC1 , and VCC2. However, in case of: over-
voltage, filter time constants being exceeded, or only VCC1 falling
while VBx voltage is sustained, malfunction or damage to the
device might be caused. To protect against these faults, a ceramic
capacitor (0.01 to 0.1 μF) and a Zener diode (VZ = 18 to 22 V)
should be provided near the power supply terminal.
The voltages of the SD2 terminal and the RC terminal fall in
accordance with the time constants determined by external capac-
itors C2 and CC. When the SD2 terminal voltage falls below Vth
(2. 1 V), a shutdown operation is performed on the MOSFET
gate. With the gate shut down, current decreases. As the voltage
falls below the VTRIP level, the MOSFET connected to the RC
terminal turns off, in 5 μs, and the RC terminal voltage rises with
the time constant determined by RR and CC.
Table 1. Overtemperature Protection Characteristics
When the RC terminal voltage rises to 3.5 V, the OCP reset
operation starts, releasing the gate shutdown of the MOSFETs
and turning off the transistor on the SD2 terminal, allowing the
device to operate in accordance with the command signal input
on the LINx pins (steady state operation).
Characteristic Symbol
Min.
120
100
–
Typ.
135
115
20
Max.
150
130
–
Units
TSD Enable
TDH
TDL
Hys
°C
TSD Release
TSD Hysteresis
°C
°C
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HIN
UVLH
VCC1
VB- HS
UVLL
UVHH
UVHH
UVHL
HO
Figure 11. High-Side MOSFET Output Timing
FF
SET
RESET
To MOSFET
S
Q
VREF
R
+
–
Filter
VBx
Figure 12. High-Side VCC1 UVLO Internal Equivalent Circuit
LIN
UVLH
VCC2
UVLH
UVLL
LO
SD2
Figure 13. Low-Side MOSFET Output Timing
LIN
VREF
To MOSFET
Gate Drive Circuit
–
Filter
+
VCC2
To SD2 Output
Figure 14. Low-Side VCC2 UVLO Internal Equivalent Circuit
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LIN
LO
VTRIP
(1 V)
LS1
2μs
㧨2 μs
OCP
Release
Vth (2.9 V)
SD
2
Slope set by
R2, C2
3.5 V
RC
Slope set by
RC, CC
5 μs
A. The LOx signal is described, including delay imposed in accordance with the
RC time constant by the input capacitance of the gate resistor and MOSFET.
B. Waveforms when both the SD2 and the RC signals are off, and include delay
due to the time constants of the internal resistor (50 Ω) and the external capacitors
C2, CC, and RC.
Figure 15. Overcurrent Protection Circuit Timing
3.5 V
+5 V
RR
OCP
–
+
MOSFET
Shutdown
+5 V
50 Ω
RC
CC
R2
Pulse
Expansion
SD2
50 Ω
5 μs
FF
R
Vref
Q
C2
(1 V)
S
OCP
–
+
Filter
2 μs
LS1
Figure 16. Overcurrent Protection Circuit
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Current Limiting by PWM Control This application imple-
ments current limiting by connecting the OCL and SD1 pins (fig-
ure 17). Current limiting occurs by turning off and on the power
supplied to the high side of the MOSFET bridge. The timing is
illustrated in figure 18.
Typical Applications
This section examines typical application circuit designs using
these devices, with and without output current limiting, and the
timing effects that result.
1
2
3
SLA6860M/SMA6860M
10
VB1 VB2 VB3
4
VCC1
HO1
24
5 V
R1
HS1
High-side
Logic Circuit
ZD
C1
HO2
5
SD1
12
HS2
M
9
8
7
HIN1
HIN2
HIN3
HO3
HS3
6
11
COM1
13
CSB
23
VCC2
Low-side
Logic Circuit
ZD
LO1
17
System
Logic
OCL
20
19
18
LIN 1
LIN 2
LIN 3
LO2
RS
16
14
RR
5V
LO3
15
RC
5V
R2
CC
22
21
SD2
C2
COM2
15V
Figure 17. Typical Application. Current limiting by controlling power to high-side MOSFETs.
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Enables high-side turn-on at next rising edge on HIN signal
Enables low-side turn-on at
next rising edge on LIN signal
HIN
LIN
HO
High-side shutdown
3.3μs
3.3μs
Low-side shutdown
LO
(1V)
VTRIP
VOCL
(0.5V)
LS1
2μs
2μs
2μs
,
OCL
SD1
Vth
Vth
(2.9V)
Vth
(2.9V)
Vth
(2.1V)
(2.1V)
T = RLCf
T = RLCf
T = 50 Cf
T = R2C2
SD2
RC
Vth
(2.9V)
T = 50 C2
T = 50 CC
3.5V
T = RRCC
5μs
Figure 18. Output Timing Effects. Using typical application shown in figure 17.
HIN and LIN must not be in phase.
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turning off and on the power supplied to the high side of the
MOSFET bridge, according to a fault signal on the OCL-SD2
output. The effect on timing is shown in figure 20.
Current Limiting Using External Diode This application
implements current limiting by connecting the OCL and SD1
pins as in the first application example, and also inserting a diode
between OCL and SD2 (figure 19). Current limiting occurs by
1
2
3
SLA6860M/SMA6860M
10
VB1 VB2 VB3
4
VCC1
HO1
24
5 V
R1
HS1
High-side
Logic Circuit
ZD
C1
HO2
5
SD1
12
HS2
M
9
8
7
HIN1
HIN2
HIN3
HO3
HS3
6
11
COM1
13
CSB
23
VCC2
Low-side
Logic Circuit
ZD
LO1
17
System
Logic
OCL
20
19
18
LIN 1
LIN 2
LIN 3
LO2
RS
16
14
RR
5V
LO3
DT
15
RC
5V
R2
CC
22
21
SD2
C2
COM2
15V
Figure 19. Typical Application. Current limiting by controlling power to high-side MOSFETs, with an external diode,
DT, affecting the timing.
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Enables high-side turn-on at next rising edge on HIN signal
HIN
LIN
HO
High-side shutdown
Enables low-side turn-on at
next rising edge on LIN signal
3.3μs
3.3μs
Low-side shutdown
LO
(1V)
VTRIP
VOCL
(0.5V)
LS1
2μs
2μs
2μs
T = RLCf
Vf
,
OCL
SD1
Vth
Vth
(2.9V)
Vth
(2.9V)
Vth
(2.1V)
(2.1V)
T = RLCf
T = 50 Cf
T = RLCf
SD2
RC
Vth
(2.9V)
3.5V
T = 50 CC
T = RRCC
5μs
Figure 20. Output Timing Effects. Using typical application shown in figure 19.
HIN and LIN must not be in phase.
For the DT diode, use a diode for which Vf is less than 1.2 V at 5 mA (TA = –20°C to 125°C).
Observe the following conditions:
RL = 1.0 kΩ to 10 kΩ,
R2 = 3.3 kΩ to 10 kΩ, and
Cf and C2 = 0.001 μF to 0.01 μF
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nals and the pull-up resistor on SD2 are not required. The effect
on timing is shown in figure 22.
No Current Limiting This application does not use the device
itself to limit output current. This is implemented by connecting
the SD1 and SD2 pins (figure 21). The capacitors on the SD sig-
1
2
3
SLA6860M/SMA6860M
10
VB1 VB2 VB3
4
VCC1
HO1
24
5 V
R1
HS1
High-side
Logic Circuit
ZD
HO2
5
SD1
12
HS2
M
9
8
7
HIN1
HIN2
HIN3
HO3
HS3
6
11
COM1
13
CSB
23
VCC2
Low-side
Logic Circuit
ZD
LO1
17
System
Logic
OCL
20
19
18
LIN 1
LIN 2
LIN 3
LO2
RS
16
14
RR
LO3
VRC
15
RC
CC
22
21
SD2
COM2
15V
Figure 21. Typical Application. No output current limiting.
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HIN
LIN
tBLANK
tBLANK
VTRIP
VLIM
LS 1
Slope of
RC, CC
OCL
RC
OCP
Release
3.5 V
5 μs
tp
SD2
SD1
delay
HO
LO
Figure 22. Output Timing Effects. Using typical application shown in figure 21 (no current limiting).
HIN and LIN must not be in phase.
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Protection Function Timing
This section provides information about the timing of fault events
handled by these devices.
HIN
LIN
tDH
tDL
tJH
tDH
tDL
tJL
SD1
SD2
HO
LO
Figure 23. Overtemperature Protection Thermal Shutdown (TSD) Timing.
HIN and LIN must not be in phase.
HIN
LIN
VUVHL
VUVHH
tf
VBx to
HSx
VUVLL
VUVLH
tf
VCC
SD1
SD2
HO
LO
Figure 24. Undervoltage Lockout (UVLO) Protection.
HIN and LIN must not be in phase.
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Surge Protection Each terminal should be protected against
power surges by isolation using an external component such as a
ceramic capacitor or Zener diode. Power surges that impinge on
the device may cause critical damage to the IC as well as faulty
operation.
Application Circuit Recommendations
When designing application circuits using these devices, the fol-
lowing should be taken into consideration:
Supply Sequence The load power supply does not have to be
provided in any particular sequence. However, commands should
not be transmitted on the sequencing signal input terminals, HIN
and LIN, until after the logic control power supply, VCC, has
reached steady state.
Input Blanking Time In order to avoid a high-side to low-side
short-circuit, the HIN and LIN signals must never be in phase.
The blanking time, tBLANK, or dead-time, is the delay between
rising edges on the HIN and LIN signals. It must be controlled
externally by the application system logic, as it is not set inter-
nally. A tBLANK of more than 1.5 μs is recommended.
Short Circuit Protection There is no built-in protection circuit
against short circuits through the outputs to ground. The applica-
tion circuit logic should be designed to monitor outputs to detect
a short circuit condition.
Pin to Pin Distance The device packages in the SLA6860M-
SMA6860M Series have 24 pins, and a 1.27 mm pin pitch. At
operating voltage levels, there may be insufficient creepage and
clearance distance, and conformal coating or encapsulation of the
application printed board assembly is recommended.
Electrical Characteristics Data
The following pages contain characteristic performance data.
The information shown applies to all models of the SLA6860M-
SMA6860M Series, unless otherwise specified.
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ICC versus VCC
ICC versus TJ
CC = 15 V, Input Off
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
7
6
5
4
3
2
1
0
V
Input Off
MAX
TYP
TJ =125°C
TJ = 25°C
MIN
12
13
14
15
16
17
18
19
20
-25
0
25
50
75
100
125
150
VCC (V)
TJ (°C)
IBOOT versus TJ
VBx to HSx = 15 V, Input Off
IBOOT versus TJ
VBx to HSx = 15 V, Input On
300
250
200
150
100
50
400
350
300
250
200
150
100
50
MAX
MAX
TYP
TYP
MIN
MIN
0
0
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ (°C)
TJ (°C)
IIN versus TJ
IBOOT versus VBx
250
200
150
100
50
Input Off
700
600
500
400
300
200
100
0
IIN = 5 V
TJ = 125°C
TJ = 25°C
MAX
TYP
MIN
0
-25
0
25
50
75
100
125
150
12
13
14
15
16
17
18
19
20
TJ (°C)
VBx (V)
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VIL versus TJ
VIH versus TJ
4.0
3.0
2.0
1.0
0.0
4.0
3.0
2.0
1.0
0.0
TYP
MAX
MIN
TYP
MAX
MIN
-25
0
25
50
75
J (°C)
100
125
150
-25
0
25
50
75
J (°C)
100
125
150
T
T
Minimum On Width versus TJ, High Side
Minimum On Width versus TJ, Low Side
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
MAX
TYP
MAX
TYP
-25
0
25
50
TJ (°C)
75
100
125
150
-25
0
25
50
TJ (°C)
75
100
125
150
High-Side Release versus TJ
Gate Output Pulse Width versus Input Pulse Width
Typical, TJ = 25°C, VCC =15 V
1200
1000
800
600
400
200
0
12.0
11.5
11.0
10.5
10.0
9.5
TYP
MAX
MIN
High Side
Low Side
9.0
8.5
8.0
0
200
400
600
800
1000
1200
-25
0
25
50
75
100
125
150
Input Pulse Width (ns)
TJ (°C)
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High-Side Operation versus TJ
Low-Side Release versus TJ
12.0
11.5
11.0
10.5
10.0
9.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
MAX
MAX
TYP
MIN
TYP
MIN
9.0
8.5
8.0
9.0
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ (°C)
TJ (°C)
UVLO Filter Delay (High Side) versus TJ
Low-Side Operation versus TJ
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
25
20
15
10
5
MAX
TYP
MIN
MAX
TYP
MIN
9.0
-25
0
-25
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TJ (°C)
TJ (°C)
VLIM versus TJ
UVLO Filter Delay (Low Side) versus TJ
0.60
0.55
0.50
0.45
0.40
12
10
8
MAX
TYP
MIN
MAX
6
TYP
MIN
4
2
0
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ (°C)
TJ (°C)
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VTRIP versus TJ
Blanking Time versus TJ (OCP,OCL)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.10
1.05
1.00
0.95
0.90
0.85
0.80
MAX
MAX
TYP
MIN
TYP
MIN
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ (°C)
TJ (°C)
Pulse Expansion versus TJ (OCP,OCL)
OCP Hold Time versusTJ
VRC = 5 V, RR= 360 kꢀ,CC= 0.0047μF
9
8
7
6
5
4
3
2
1
0
3.5
3.0
2.5
2.0
1.5
1.0
TYP
MAX
MIN
MAX
TYP
MIN
0
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ (°C)
TJ (°C)
VSDL versus TJ
VSDH versus TJ
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
3.4
MAX
3.2
3.0
2.8
2.6
2.4
2.2
2.0
TYP
MIN
MAX
TYP
MIN
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ (°C)
TJ (°C)
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SD Filter versus TJ
Saturation Voltage versus TJ (SD, OCL)
8
7
6
5
4
3
2
1
0
700
600
500
400
300
200
100
0
V
μP = 5 V, R = 1 kꢀ, C = 0.01μF
MAX
TYP
MIN
MAX
TYP
MIN
-25
0
25
50
75
100
125
150
-25
0
25
50
75
100
125
150
TJ(°C)
TJ(°C)
Saturation Voltage versus TJ (RC)
500
VRC = 5 V,RR= 330 kꢀ,CC= 0.01μF MAX
450
400
350
300
250
200
150
100
50
TYP
MIN
0
-25
0
25
50
75
100
125
150
TJ(°C)
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SMA6861M MOSFET Characteristics
2.0
RD(on) versus ID
ISD versus VSD
4
3
2
1
0
VGS =15 V
VSD = 0 V
1.5
125°C
75°C
25°C
125°C
75°C
25°C
1.0
0.5
0
0
0.5
1.0
D (A)
1.5
2.0
0
0.2
0.4
0.6
0.8
1.0
V
SD (V)
I
SMA6862M MOSFET Characteristics
RD(on) versus ID
125°C
ISD versus VSD
8
1.5
VGS =15 V
VSD = 0 V
7
6
5
4
3
2
1
0
125°C
1.0
0.5
0
75°C
25°C
75°C
25°C
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.5
1.0
1.5
ID (A)
VSD (V)
SMA6863M MOSFET Characteristics
RD(on) versus ID
125°C
ISD versus VSD
125°C
5
2.5
VGS =15 V
VSD = 0 V
4
3
2
1
0
2.0
1.5
1.0
0.5
0
75°C
25°C
75°C
25°C
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
ID (A)
VSD (V)
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All performance characteristics given are typical values for
circuit or system baseline design only and are at the nominal
operating voltage and an ambient temperature of 25°C,
unless otherwise stated.
The products described herein are manufactured in Japan by Sanken Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken and Allegro reserve the right to make, from time to time, such departures from the detail specifications as may be required to permit im-
provements in the performance, reliability, or manufacturability of its products. Therefore, the user is cautioned to verify that the information in this
publication is current before placing any order.
When using the products described herein, the applicability and suitability of such products for the intended purpose shall be reviewed at the users
responsibility.
Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products
at a certain rate is inevitable.
Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to society due to device failure or malfunction.
Sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equipment or apparatus
(home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Their use in any application requiring radiation
hardness assurance (e.g., aerospace equipment) is not supported.
When considering the use of Sanken products in applications where higher reliability is required (transportation equipment and its control systems
or equipment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written
confirmation of your specifications.
The use of Sanken products without the written consent of Sanken in applications where extremely high reliability is required (aerospace equip-
ment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited.
The information included herein is believed to be accurate and reliable. Application and operation examples described in this publication are
given for reference only and Sanken and Allegro assume no responsibility for any infringement of industrial property rights, intellectual property
rights, or any other rights of Sanken or Allegro or any third party that may result from its use.
The contents in this document must not be transcribed or copied without Sanken’s written consent.
Copyright © 2008-2010 Allegro MicroSystems, Inc.
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Worldwide Contacts
Asia-Pacific
China
Korea
Sanken Electric Korea Co., Ltd.
Samsung Life Yeouido Building 16F
23-10, Yeouido-Dong, Yeongdeungpo-gu
Seoul 150-734, Korea
Sanken Electric Hong Kong Co., Ltd.
Suite 1026, Ocean Centre
Canton Road, Tsimshatsui
Tel: 82-2-714-3700, Fax: 82-2-3272-2145
Kowloon, Hong Kong
Tel: 852-2735-5262, Fax: 852-2735-5494
Singapore
Sanken Electric (Shanghai) Co., Ltd.
Room 3202, Maxdo Centre
Xingyi Road 8, Changning District
Shanghai, China
Sanken Electric Singapore Pte. Ltd.
152 Beach Road, #10-06 The Gateway East
Singapore 189721
Tel: 65-6291-4755, Fax: 65-6297-1744
Tel: 86-21-5208-1177, Fax: 86-21-5208-1757
Europe
Sanken Electric (Shanghai) Co., Ltd.
Shenzhen Office
Sanken Power Systems (UK) Limited
Pencoed Technology Park
Pencoed, Bridgend CF35 5HY, United Kingdom
Tel: 44-1656-869-100, Fax: 44-1656-869-162
Room 1013, Xinhua Insurance Building
Mintian Road, Futian District
Shenzhen City, Guangdong, China
Tel: 86-755-3391-9356/9358, Fax: 86-755-3391-9368
Taiwan Sanken Electric Co., Ltd.
Room 1801, 18th Floor
88 Jung Shiau East Road, Sec. 2
Taipei 100, Taiwan R.O.C.
North America
United States
Tel: 886-2-2356-8161, Fax: 886-2-2356-8261
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01606, U.S.A.
Tel: 1-508-853-5000, Fax: 1-508-853-7895
Japan
Sanken Electric Co., Ltd.
Overseas Sales Headquarters
Metropolitan Plaza Building
1-11-1 Nishi-Ikebukuro, Toshima-ku
Tokyo 171-0021, Japan
Allegro MicroSystems, Inc.
14 Hughes Street, Suite B105
Irvine, California 92618, U.S.A.
Tel: 1-949-460-2003, Fax: 1-949-460-7837
Tel: 81-3-3986-6164, Fax: 81-3-3986-8637
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