UCN5890A [ALLEGRO]
BIMOS II 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS; BIMOS II 8位串行输入，锁存源极驱动器
| 型号： | UCN5890A |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | BIMOS II 8-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS |
| 文件： | 总8页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5890
5891 AND
BIMOS II 8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Frequently applied in non-impact printer systems, the UCN5890A,
UCN5890LW, UCN5891A, and UCN5891LW are BiMOS II serial-input,
latched source (high-side) drivers. The octal, high-current smart-power ICs
merge an 8-bit CMOS shift register, associated CMOS latches, and CMOS
control logic (strobe and output enable) with sourcing power Darlington
outputs. Typical applications include multiplexed LED and incandescent
displays, relays, solenoids, and similar peripheral loads to a maximum of
-500 mA per output.
SERIAL
DATA OUT
16
15
GROUND
CLOCK
1
2
3
4
LOGIC
SUPPLY
V
CLK
ST
DD
SHIFT
REGISTER
OUTPUT
ENABLE
SERIAL
DATA IN
OE 14
LOAD
SUPPLY
V
13
STROBE
BB
LATCHES
12 OUT
11 OUT
OUT
1
5
6
8
7
6
5
Except for output voltage ratings, these smart high-side driver ICs are
equivalent. The UCN5890A/LW are rated for operation with load supply
voltages of 20 V to 80 V and a minimum output sustaining voltage of 50 V.
The UCN5891A/LW are optimized for operation with supply voltages of 5 V
to 50 V (35 V sustaining).
OUT
2
OUT
OUT
OUT
3
10
9
7
8
OUT
4
BiMOS II devices have higher data-input rates than the original BiMOS
circuits. With a 5 V supply, they will operate to at least 3.3 MHz. At 12 V,
higher speeds are possible. The CMOS inputs are compatible with standard
CMOS and NMOS logic levels. TTL circuits may require the use of appropri-
ate pull-up resistors to ensure a proper input-logic high. A CMOS serial data
output, allows cascading these devices in multiple drive-line applications
required by many dot matrix, alphanumeric, and bar graph displays.
Dwg. PP-026-2A
Note the suffix ‘A’ devices (DIP) and the suffix
‘LW’ devices (SOIC) are electrically identical and
share a common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Output Voltage, VOUT
Suffix ‘A’ devices are supplied in a standard dual in-line plastic package
with copper lead frame for enhanced package power dissipation characteris-
tics. Suffix ‘LW’ devices are supplied in a standard wide-body SOIC package
for surface-mount applications. Similar driver, featuring reduced output
saturation voltage, are the UCN5895A and A5895SLW. Complementary,
8-bit serial-input, latched sink drivers are the Series UCN5820A.
(UCN5890A & UCN5890LW) .........80 V
(UCN5891A & UCN5891LW) .........50 V
Logic Supply Voltage Range,
VDD ....................................4.5 V to 15 V
Driver Supply Voltage Range, VBB
(UCN5890A/LW)................20 V to 80 V
(UCN5891A/LW)...............5.0 V to 50 V
FEATURES
Input Voltage Range,
I
I
I
I
I
50 V or 80 V Source Outputs
V
IN ........................ -0.3 V to VDD + 0.3 V
Continuous Output Current,
OUT ........................................... -500 mA
Output Current to -500 mA
I
Output Transient-Suppression Diodes
To 3.3 MHz Data-lnput Rate
Allowable Package Power Dissipation,
PD ......................................... See Graph
Low-Power CMOS Logic and Latches
Operating Temperature Range,
TA .................................. -20°C to +85°C
Storage Temperature Range,
TS ................................ -55°C to +150°C
Caution: CMOS devices have input static
protection, but are susceptible to damage when
exposed to extremely high static electrical
charges.
Always order by complete part number, e.g., UCN5891LW .
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
FUNCTIONAL BLOCK DIAGRAM
2.5
2.0
CLOCK
SUFFIX 'A', R
= 60°C/W
θJA
SERIAL
DATA OUT
SERIAL
DATA IN
8-BIT SERIAL-PARALLEL SHIFT REGISTER
LATCHES
1.5
1.0
0.5
0
V
STROBE
GROUND
DD
OUTPUT
ENABLE
MOS
BIPOLAR
SUFFIX 'LW', R
= 80°C/W
θJA
V
BB
25
50
75
100
125
150
OUT OUT OUT OUT OUT OUT OUT OUT
8
Dwg. No. A-12,654
1
2
3
4
5
6
7
AMBIENT TEMPERATURE IN °C
Dwg. GP-018B
TYPICAL INPUT CIRCUIT
Number of
Outputs On at
UCN5890/91A Max. Allowable Duty Cycle
at TA of
V
DD
IOUT = -200 mA
50°C
60°C
70°C
8
7
6
5
4
3
2
1
53%
60%
70%
47%
54%
64%
75%
94%
100%
100%
100%
41%
48%
56%
67%
84%
100%
100%
100%
IN
83%
100%
100%
100%
100%
Dwg. EP-010-4A
TYPICAL OUTPUT DRIVER
V
BB
Number of
Outputs On at
UCN5890/91LW Max. Allowable Duty Cycle
at TA of
IOUT = -200 mA
50°C
60°C
70°C
8
7
6
5
4
3
2
1
40%
45%
53%
62%
80%
100%
100%
100%
35%
41%
48%
56%
71%
96%
100%
100%
31%
36%
42%
50%
62%
84%
100%
100%
OUT
Dwg. No. A-12,648
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 80 V (UCN5890A/LW) or 50 V
(UCN5891A/LW), VDD = 5 V and 12 V (unless otherwise noted).
Limits
Max.
Characteristic
Symbol
VBB
Test Conditions
Min.
—
Units
µA
µA
V
Output Leakage Current
I
Max.
T = +25°C
-50
-100
1.8
1.9
2.0
—
CEX
A
T = +70°C
—
A
Output Saturation Voltage
V
50 V
I
I
I
I
I
= -100 mA
—
CE(SAT)
OUT
OUT
OUT
OUT
OUT
= -225 mA
—
V
= -350 mA
—
V
Output Sustaining Voltage
Input Voltage
V
Max.
50 V
= -350 mA, L = 2 mH, UCN5891A/LW
35
50
3.5
10.5
-0.3
—
V
CE(sus)
= -350 mA, L = 2 mH, UCN5890A/LW
—
V
V
V
V
V
V
V
V
V
= 5.0 V
5.3
12.3
+0.8
50
V
IN(1)
DD
DD
DD
DD
DD
DD
DD
= 12 V
V
V
50 V
50 V
= 5 V to 12 V
V
IN(0)
IN(1)
Input Current
I
= V = 5.0 V
µA
µA
kΩ
kΩ
MHz
kΩ
kΩ
µs
µs
mA
µA
µA
µA
mA
mA
µA
µA
V
IN
= V = 12 V
IN
—
240
—
Input lmpedance
Max. Clock Frequency
Z
50 V
= 5.0 V
= 12 V
100
50
3.3*
—
IN
—
f
50 V
50 V
—
c
Serial Data Output
Resistance
R
V
V
= 5.0 V
= 12 V
20
OUT
DD
—
6.0
2.0
10
DD
Turn-On Delay
Turn-Off Delay
Supply Current
t
t
50 V
50 V
50 V
Output Enable to Output, I
Output Enable to Output, I
= -350 mA
= -350 mA
—
PLH
PHL
OUT
OUT
—
I
All outputs on, All outputs open
All outputs off
—
10
BB
—
200
100
200
1.0
3.0
50
l
50 V
V
V
V
V
= 5 V, All outputs off, Inputs = 0 V
—
DD
DD
DD
DD
DD
= 12 V, All outputs off, Inputs = 0 V
= 5 V, One output on, All Inputs = 0 V
= 12 V, One output on, All Inputs = 0 V
—
—
—
Diode Leakage Current
Diode Forward Voltage
I
Max.
T = +25°C
—
R
A
T = +70°C
—
100
2.0
A
V
Open
I = 350 mA
—
F
F
NOTES: Turn-off delay is influenced by load conditions. Systems applications well below the specified output loading may require
timing considerations for some designs, i.e., multiplexed displays or when used in combination with sink drivers in a totem
pole configuration.
Positive (negative) current is defined as going into (coming out of) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
CLOCK
A
D
B
DATA IN
STROBE
BLANKING
OUTN
E
F
C
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the OUTPUT ENABLE input be high
during serial data entry.
G
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
When the OUTPUT ENABLE input is high,
all of the output buffers are disabled (off) without
affecting the information stored in the latches or
shift register. With the OUTPUT ENABLE input
low, the outputs are controlled by the state of
their respective latches.
(Data Set-Up Time).......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
...
Output Contents
... I
Output
Enable
I
I
...
I
I
I
I
I
I
I
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R1 R2 ... RN-2 RN-1
R1 R2 ... RN-2 RN-1
RN-1
RN-1
RN
X
R1 R2 R3 ... RN-1 RN
...
P1 P2 P3 ... PN-1 PN
X
X
X
X
X
X
X
L
R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
X
H
X
L
L
P1 P2 P3 ... PN-1 PN
... L
...
X
X
H
L
L
L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
TYPICAL APPLICATION
SOLENOID OR RELAY DRIVER
+5V
+48V
UCN5890A
1
16
DATA OUT
2
3
15
14
CLOCK
DATA IN
SHIFT
VDD
OE
REGISTER
OUTPUT ENABLE
(ACTIVE LOW)
LATCHES
13
4
5
STROBE
VBB
12
11
10
9
6
7
8
Dwg. No. A-12,548
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
www.allegromicro.com
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5890A and UCN5891A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
9
16
0.430
MAX
0.280
0.240
0.300
BSC
1
8
0.100
BSC
0.070
0.005
MIN
0.045
0.775
0.735
0.210
MAX
0.015
MIN
0.150
0.115
0.022
0.014
Dwg. MA-001-16A in
Dimensions in Millimeters
(for reference only)
0.355
0.204
9
16
10.92
MAX
7.11
6.10
7.62
BSC
1
8
2.54
BSC
1.77
0.13
MIN
1.15
19.68
18.67
5.33
MAX
0.39
MIN
3.81
2.93
0.558
0.356
Dwg. MA-001-16A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 25 devices.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
UCN5890LW and UCN5891LW
Dimensions in Inches
(for reference only)
16
9
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
BSC
3
0° TO 8°
0.4133
0.3977
0.0926
0.1043
Dwg. MA-008-16A in
0.0040 MIN.
16
Dimensions in Millimeters
(controlling dimensions)
9
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
BSC
3
0° TO 8°
10.50
10.10
2.65
2.35
Dwg. MA-008-16A mm
0.10 MIN.
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 47 devices or add “TR” to part number for tape and reel.
www.allegromicro.com
5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
POWER
INTERFACE DRIVERS
†
Function
Output Ratings*
SERIAL-INPUT LATCHED DRIVERS
Part Number
8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
-120 mA
350 mA
350 mA
350 mA
350 mA
75 mA
250 mA
350 mA
100 mA
50 V‡
50 V
80 V
50 V‡
80 V‡
17 V
50 V
50 V‡
50 V
5895
5821
5822
5841
5842
6275
6595
6A595
6B595
8-Bit
8-Bit (constant-current LED driver)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
10-Bit (active pull-downs)
-25 mA
-25 mA
75 mA
-25 mA
60 V
60 V
17 V
60 V
5810-F and 6809/10
5811 and 6811
6276
12-Bit (active pull-downs)
16-Bit (constant-current LED driver)
20-Bit (active pull-downs)
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
32-Bit (saturated drivers)
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
-25 mA
350 mA
100 mA
250 mA
60 V
50 V‡
50 V
50 V
5815
5801
6B273
6273
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 28-Line Decoder/Driver
1.25 A
250 mA
350 mA
100 mA
450 mA
50 V‡
5804
6259
6A259
6B259
6817
50 V
50 V‡
50 V
30 V
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
‡
Complete part number includes additional characters to indicate operating temperature range and package style.
Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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