UCQ5832A [ALLEGRO]
SIPO Based Peripheral Driver, 0.15A, BIMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40;
| 型号： | UCQ5832A |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | SIPO Based Peripheral Driver, 0.15A, BIMOS, PDIP40, 0.600 INCH, PLASTIC, DIP-40 驱动 光电二极管 接口集成电路 |
| 文件： | 总8页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
5832
BiMOS II 32-BIT SERIAL-INPUT,
LATCHED DRIVERS
Intended originally to drive thermal printheads, the UCN5832A
and UCN5832EP have been optimized for low output-saturation
voltage, high-speed operation, and pin configurations most convenient
for the tight space requirements of high-resolution printheads. These
integrated circuits can also be used to drive multiplexed LED displays
or incandescent lamps at up to 150 mA peak current. The combination
of bipolar and MOS technologies gives BiMOS II arrays an interface
flexibility beyond the reach of standard buffers and power driver
circuits.
UCN5832A
LOGIC
CLOCK
1
40
VDD
SUPPLY
SERIAL
DATA IN
SERIAL
DATA OUT
39
38
2
3
OUTPUT
ENABLE
GROUND
STROBE
OUT
32
4
5
37
36
OUT
31
OUT
1
OUT
30
OUT
2
35
34
6
7
The devices each have 32 bipolar NPN open-collector saturated
drivers, a CMOS data latch for each of the drivers, two 16-bit CMOS
shift registers, and CMOS control circuitry. The high-speed CMOS
shift registers and latches allow operation with most microprocessor
based systems. Use of these drivers with TTL may require input
pull-up resistors to ensure an input logic high. MOS serial data
outputs permit cascading for interface applications requiring additional
drive lines.
OUT
29
OUT
3
OUT
4
8
33 OUT
28
9
32
31
OUT
5
OUT
OUT
27
26
10
OUT
6
OUT
7
11
12
12
30 OUT
25
24
OUT
8
OUT
OUT
29
28
OUT
9
23
OUT
10
OUT
OUT
14
15
16
27
26
25
22
21
OUT
11
The UCN5832A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. Under normal operating condi-
tions, this device will allow all outputs to sustain 100 mA continuously
without derating. The UCN5832EP is supplied in a 44-lead plastic
leaded chip carrier for minimum area, surface-mount applications.
Both devices are also available for operation from -40°C to +85°C.
To order, change the prefix from ‘UCN’ to ‘UCQ’.
OUT
12
OUT
OUT
20
19
OUT
13
17
18
19
20
24
23
22
21
OUT
14
OUT
OUT
18
OUT
15
17
OUT
16
INTERNAL
CONNECTION
Dwg. No. A-12,377A
Similar 32-bit serial-input latched source drivers are available as
the UCN5818AF/EPF. Other high-voltage, high-current 8-bit devices
are available as the UCN5821A, UCN5841A/LW, and UCN5842A.
ABSOLUTE MAXIMUM RATINGS
at +25°C Free-Air Temperature
FEATURES
Output Voltage, VOUT ...................... 40 V
Logic Supply Voltage, VDD ................ 15 V
■ To 3.3 MHz Data Input Rate
■ Low-Power CMOS Logic and Latches
■ 40 V Current Sink Outputs
■ Low Saturation Voltage
Input Voltage Range,
V ...................-0.3 V to V + 0.3 V
IN
DD
Continuous Output Current,
l
OUT .................................. 150 mA
Package Power Dissipation,
■ Automotive Capable
P ................................ See Graph
D
Operating Temperature Range,
T ........................... -20°C to +85°C
Storage Temperature Range,
A
Always order by complete part number:
T .......................... -55°C to +150°C
S
Part Number
UCN5832A
UCN5832EP
Package
Caution: CMOS devices have input-static
protection but are susceptible to damage when
exposed to extremely high static electrical charges.
40-Pin DIP
44-Lead PLCC
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
3.0
FUNCTIONAL BLOCK DIAGRAM
2.5
SUFFIX 'A', R
= 36°C/W
θJA
VDD
CLOCK
32-BIT SHIFT REGISTER
LATCHES
2.0
SERIAL
DATA IN
SERIAL DATA
OUT
STROBE
1.5
1.0
SUFFIX 'EP', R
= 46°C/W
OUTPUT
ENABLE
θJA
MOS
BIPOLAR
0.5
0
OUT OUT2 OUT
GROUND OUT30 OUT OUT
31
32
1
3
25
50
75
100
125
150
AMBIENT TEMPERATURE IN °C
Dwg. GP-025A
UCN5832EP
OUT
39
38
37
36
31
7
8
OUT2
9
10
35
34
33
11
12
13
14
32
31
30
29
15
16
17
OUT21
OUT
12
Dwg. No. A-14,360
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1984, 1998, Allegro MicroSystems, Inc.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic
Symbol
ICEX
Test Conditions
VOUT = 40 V, TA = 70°C
lOUT = 50 mA
Min.
—
Max.
Units
µA
mV
mV
mV
V
Output Leakage Current
10
Collector-Emitter
Saturation Voltage
VCE(SAT)
—
275
550
550
5.3
+0.8
1.0
-1.0
—
lOUT = 100 mA, “A” package
lOUT = 100 mA, “EP” package
150
—
Input Voltage
Input Current
VIN(1)
VIN(0)
lIN(1)
lIN(0)
ZIN
3.5
-0.3
—
V
VIN = 3.5 V
VIN = 0.8 V
VIN = 3.5 V
µA
µA
MΩ
kΩ
mA
µA
µs
—
Input lmpedance
3.5
—
Serial Data Output Resistance
Supply Current
ROUT
lDD
20
One output ON, lOUT = 100 mA
All outputs OFF
—
5.0
50
—
Output Rise Time
Output Fall Time
tr
tf
lOUT = 100 mA, 10% to 90%
lOUT = 100 mA, 90% to 10%
—
1.0
1.0
—
µs
NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
V
DD
V
DD
IN
OUT
675Ω
Dwg. No. A-12,380A
Dwg. No. A-12,379A
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
Serial Data present at the input is trans-
ferred to the shift register on the logic “0” to
logic “1” transition of the CLOCK input pulse.
On succeeding CLOCK pulses, the registers
shift data information towards the SERIAL
DATA OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge of
the CLOCK input waveform.
CLOCK
A
D
B
DATA IN
STROBE
E
F
C
OUTPUT
ENABLE
Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel conver-
sion). The latches will continue to accept
new data as long as the STROBE is held
high. Applications where the latches are
bypassed (STROBE tied high) will require
that the OUTPUT ENABLE input be low
during serial data entry.
G
OUTN
Dwg. No. A-12,276A
TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
When the OUTPUT ENABLE input is low,
all of the output buffers are disabled (OFF)
without affecting the information stored in the
latches or shift register. With the OUTPUT
ENABLE input high, the outputs are con-
trolled by the state of the latches.
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time)..........................................................................75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ........................................................................... 500 ns
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
Output
Enable
Input
Output Contents
... I
I
2
I
3
...
I
I
N
I
I
2
I
3
...
I
I
N
I
1
I
2
I
3
I
N-1 N
1
N-1
1
N-1
H
L
H
L
R1 R2 ... RN-2 RN-1
R1 R2 ... RN-2 RN-1
RN-1
RN-1
RN
X
R1 R2 R3 ... RN-1 RN
...
P1 P2 P3 ... PN-1 PN
X
X
X
X
X
X
L
R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
H
H
L
P1 P2 P3 ... PN-1 PN
... H
X
X
X
...
X
X
H
H
H
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
UCN5832A
Dimensions in Inches
(controlling dimensions)
0.015
0.008
40
21
0.700
MAX
0.580
0.485
0.600
BSC
1
2
20
0.100
3
4
0.070
0.030
0.005
MIN
BSC
2.095
1.980
0.250
MAX
0.015
0.200
0.115
MIN
0.022
0.014
Dwg. MA-003-40 in
Dimensions in Millimeters
(for reference only)
0.381
0.204
40
21
17.78
MAX
14.73
12.32
15.24
BSC
1
2
1.77
0.77
20
3
4
0.13
2.54
MIN
BSC
53.2
50.3
6.35
MAX
0.39
5.08
2.93
MIN
0.558
0.356
Dwg. MA-003-40 mm
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
UCN5832EP
Dimensions in Inches
(controlling dimensions)
18
28
29
17
0.032
0.026
0.319
0.291
0.695
0.685
0.021
0.013
0.656
0.650
0.319
0.291
INDEX AREA
0.050
BSC
39
7
44
1
2
40
6
0.020
0.656
0.650
MIN
0.695
0.685
0.180
0.165
Dwg. MA-005-44A in
Dimensions in Millimeters
(for reference only)
28
18
29
17
0.812
0.661
8.10
7.39
17.65
17.40
0.533
0.331
16.662
16.510
8.10
7.39
INDEX AREA
1.27
BSC
39
7
44
1
2
40
6
16.662
16.510
0.51
MIN
4.57
4.20
17.65
17.40
Dwg. MA-005-44A mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
5832
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVERS
BiMOS II (Series 5800) & DABiC IV (Series 6800)
INTELLIGENT POWER INTERFACE DRIVERS
SELECTION GUIDE
Function
Output Ratings *
Part Number †
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
-120 mA
350 mA
350 mA
350 mA
350 mA
50 V‡
50 V
5895
5821
5822
5841
5842
8-Bit
8-Bit
8-Bit
8-Bit
80 V
50 V‡
80 V‡
9-Bit
1.6 A
-25 mA
-25 mA
-25 mA
50 V
60 V
60 V
60 V
5829
10-Bit (active pull-downs)
12-Bit (active pull-downs)
20-Bit (active pull-downs)
5810-F and 6809/10
5811 and 6811
5812-F and 6812
32-Bit (active pull-downs)
32-Bit
-25 mA
100 mA
100 mA
60 V
30 V
40 V
5818-F and 6818
5833
32-Bit (saturated drivers)
5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
8-Bit
-25 mA
350 mA
60 V
5815
5801
50 V‡
SPECIAL-PURPOSE FUNCTIONS
Unipolar Stepper Motor Translator/Driver
Addressable 28-Line Decoder/Driver
1.25 A
50 V‡
30 V
5804
6817
450 mA
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
‡
Complete part number includes additional characters to indicate operating temperature range and package style.
Internal transient-suppression diodes included for inductive-load protection.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the design of its products.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibil-
ity for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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