AS4C14400 [ALSC]
1M-bit × 4 CMOS DRAM (Fast page mode or EDO); 1M位× 4 CMOS DRAM（快速页面模式或EDO ）
| 型号： | AS4C14400 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 1M-bit × 4 CMOS DRAM (Fast page mode or EDO) |
| 文件： | 总16页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance
1M×4
AS4C14400
AS4C14405
®
CMOS DRAM
1M-bit × 4 CMOS DRAM (Fast page mode or EDO)
Preliminary information
Features
• 1024 refresh cycles, 16 ms refresh interval
• Organization: 1,048,576 words × 4 bits
- RAS-only or CAS-before-RAS refresh
• Read-modify-write
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 300 mil, 20/26-pin SOJ
• High speed
- 40/50/60/70 ns RAS access time
- 20/25/30/35 ns column address access time
- 10/13/15/18 ns CAS access time
• Low power consumption
- Active: 385 mW max (-60)
- Standby: 5.5 mW max, CMOS I/O
• Fast page mode (AS4C14400) or EDO (AS4C14405)
- 300 mil, 20/26-pin TSOP
• Single 5V power supply
• ESD protection ≥ 2001V
• Latch-up current ≥ 200 mA
Pin arrangement
Pin designation
Pin(s)
Description
SOJ
TSOP
A0 to A9
RAS
Address inputs
Row address strobe
Input/output
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
GND
I/O3
I/O2
CAS
OE
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
GND
I/O3
I/O2
CAS
OE
I/O0 to I/O3
OE
Output enable
Column address strobe
Read/write control
Power (5.0 ± 0.5V)
Ground
9
10
11
12
13
9
10
11
12
18
17
16
15
14
A8
A7
A6
A5
A4
A0
A1
A2
A3
VCC
A0
A1
A2
A3
VCC
18
A8
A7
A6
A5
A4
CAS
17
16
15
14
WE
13
V
CC
GND
Selection guide
Symbol
4C14400-40 4C14400-50 4C14400-60 4C14400-70
Unit
ns
Maximum RAS access time
t
t
t
t
t
t
I
I
40
20
10
10
70
30
90
1.0
50
25
13
13
90
35
80
1.0
60
30
70
35
RAC
CAA
CAC
OEA
RC
Maximum column address access time
Maximum CAS access time
ns
15
18
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
15
18
ns
110
40
130
45
ns
ns
PC
70
60
mA
mA
CC1
CC5
Maximum CMOS standby current
Shaded areas contain advance information.
1.0
1.0
ALLIANCE SEMICONDUCTOR
AS4C14400
®
Functional description
The AS4C14400 is a high performance CMOS Dynamic Random Access Memory organized as 1,048,576 words × 4 bits. The AS4C14400 is
fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power
and wide operating margins at component and system levels.
The AS4C14400 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the
1024 × 4 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease
the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe (CAS) which acts
as an output enable independent of RAS. Very fast CAS to output access time eases system design.
Refresh on the 1024 address combinations of A0 to A9 during a 16 ms period is accomplished by performing any of the following:
• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
The AS4C14400 is available in JEDEC standard 20/26-pin plastic SOJ and 20/26-pin plastic TSOP packages. System level features include
single power supply of 5.0 ± 0.5V tolerance and direct interface with TTL logic families.
Logic block diagram
I/O3
Vcc
Column decoder
Sense amp
Data
I/O
I/O2
I/O1
I/O0
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
OE
RAS clock
generator
1024 × 1024 × 4
Array
RAS
(4,194,304)
CAS clock
generator
CAS
WE
WE clock
generator
Recommended operating conditions
Parameter
Symbol
Minimum
Nominal
Maximum
Unit
V
V
4.5
0.0
2.4
–1.0
0
5.0
0.0
–
5.5
0.0
CC
Supply voltage
GND
V
V
V
V
+ 1
CC
V
IH
IL
Input voltage
–
0.8
70
V
Operating temperature
TA
°C
Recommended operating conditions apply to all specifications unless otherwise noted.
2
AS4C14400
®
Absolute maximum ratings
Parameter
Symbol
Minimum
-1.0
-1.0
-1.0
-55
–
Maximum
+7.0
+7.0
+7.0
+150
260 × 10
1
Unit
V
Input voltage
V
V
V
T
T
in
Output voltage
V
out
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
V
CC
°C
STG
SOLDER
D
o
C × sec
P
–
W
DC output current
I
–
50
mA
out
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
DC electrical characteristics
-40
-50
-60
-70
Parameter
Symbol Test Conditions
Min Max Min Max Min Max Min Max Unit Notes
0V ≤ V ≤ +5.5V
Pins not under test = 0V
in
Input leakage current
I
I
I
I
I
-2
+2 -2
+2 -2
+2 -2
+2 µA
I
Outputs disabled,
Output leakage current
-10 +10 -10 +10 -10 +10 -10 +10 µA
OZ
CC1
CC2
CC3
0V ≤ V ≤ +5.5V
out
Operating power
supply current
RAS, CAS, Address
–
–
–
90
2.0
90
–
–
–
80
2.0
80
–
–
–
70
2.0
70
–
–
–
60 mA 1,2
2.0 mA
cycling: t =min
RC
TTL standby power
supply current
RAS = CAS = V
IH
Average power supply
current, RAS refresh mode
RAS cycling, CAS = VIH,
= min
60 mA
1
t
RC
RAS = V , CAS cycling,
Address cycling:
IL
Fast page mode average
power supply current
I
–
80
–
70
–
60
–
50 mA 1,2
1.0 mA
CC4
t
= min
PC
CMOS standby power
supply current
I
I
RAS = CAS = V - 0.2V –
1.0
90
–
–
1.0
80
–
–
1.0
70
–
–
CC5
CC6
CC
CAS-before-RAS refresh
power supply current
RAS, CAS cycling:
–
60 mA
1
t
I
I
= min
RC
V
V
= -5.0 mA
= 4.2 mA
2.4
–
–
2.4
–
–
2.4
–
–
2.4
–
–
V
V
OH
OL
OUT
OUT
Output voltage
0.4
0.4
0.4
0.4
Shaded areas contain advance information.
3
AS4C14400
®
AC parameters common to all waveforms
-40
-50
-60
-70
Symbol Parameter
Min
70
20
40
10
18
13
10
40
0
Max
–
Min
Max
–
Min
110
40
60
15
20
15
15
60
0
Max
–
Min
130
50
70
18
20
15
18
70
0
Max Unit Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Random read or write cycle time
RAS precharge time
90
30
50
13
20
15
13
50
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RC
–
–
–
RP
RAS pulse width
10K
–
10K
–
10K
–
10K
–
RAS
CAS
RCD
RAD
RSH(R)
CSH
CRP
ASR
RAH
T
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time (read)
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
30
20
–
37
25
–
45
30
–
52
35
–
6
7
–
–
–
–
–
–
–
–
0
–
0
–
0
–
0
–
8
–
10
2
–
10
2
–
10
2
–
2
50
16
–
50
16
–
50
16
–
50
16
–
4,5
3
–
–
–
–
REF
CLZ
CAS to output in low Z
0
0
0
0
8
Shaded areas contain advance information.
Read cycle
-40
-50
-60
-70
Symbol
Parameter
Min
–
Max
40
10
20
–
Min
–
Max
50
13
25
–
Min
–
Max
Min
Max
Unit Notes
t
Access time from RAS
60
15
30
–
–
–
70
18
35
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
RAC
CAC
AA
t
t
t
t
t
t
t
t
t
t
Access time from CAS
–
–
–
6,13
7,13
Access time from address
Column add hold from RAS
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS lead time
CAS precharge time
–
–
–
–
30
0
40
0
45
0
55
0
AR(R)
RCS
–
–
–
–
0
–
0
–
0
–
0
–
9
9
RCH
RRH
RAL
CPN
ODS
OFF
0
–
0
–
0
–
0
–
20
5
–
25
10
0
–
30
10
0
–
35
10
0
–
–
–
–
–
Output disable setup time
Output buffer turn-off time
0
–
–
–
–
0
10
0
13
0
15
0
18
8,10
Shaded areas contain advance information.
4
AS4C14400
®
Write cycle
-40
-50
-60
-70
Symbol
Parameter
Min
0
Max
–
Min
0
Max
–
Min
0
Max
–
Min
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
Column address setup time
Column address hold time
Column address hold time to RAS
Write command setup time
Write command hold time
Write command hold time to RAS
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-In setup time
ASC
t
t
t
t
t
t
t
t
t
t
t
8
–
10
40
0
–
10
45
0
–
15
55
0
–
CAH
AWR
WCS
WCH
WCR
WP
30
0
–
–
–
–
–
–
–
–
11
11
5
–
10
40
10
13
13
0
–
10
45
10
15
15
0
–
15
55
15
18
18
0
–
30
8
–
–
–
–
–
–
–
–
10
10
0
–
–
–
–
RWL
CWL
DS
–
–
–
–
–
–
–
–
12
12
Data-In hold time
8
–
10
40
–
10
45
–
15
55
–
DH
Data-In hold time to RAS
30
–
–
–
–
DHR
Shaded areas contain advance information.
Read-modify-write cycle
-40
-50
-60
-70
Symbol
Parameter
Min
105
60
Max
–
Min
131
73
Max
–
Min
155
85
Max
–
Min
181
98
Max
–
Unit Notes
t
t
t
t
t
t
Read-write cycle time
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
CAS to RAS hold time (write)
CAS pulse width (write)
ns
RWC
–
–
–
–
ns
ns
ns
ns
ns
11
11
11
RWD
30
–
36
–
40
–
46
–
CWD
40
–
48
–
55
–
63
–
AWD
10
–
13
–
15
–
18
–
RSH(W)
CAS(W)
10
–
13
–
15
–
18
–
Shaded areas contain advance information.
5
AS4C14400
®
Fast page mode cycle
-40
-50
-60
-70
Symbol
Parameter
Min
30
–
Max
–
Min
Max
–
Min
40
–
Max
–
Min
45
–
Max
–
Unit
ns
Notes
14
Read-write cycle time
(fast page)
t
t
t
t
t
t
35
–
PC
Access time from CAS precharge
25
–
30
–
35
–
40
–
ns
13
CAP
CP
CAS precharge time
(fast page)
5
10
76
54
50
10
85
60
60
10
96
69
70
ns
Fast page mode RMW cycle
65
45
40
–
–
–
–
ns
PCM
CRW
RASP
Page mode CAS pulse width
(RMW)
–
–
–
–
ns
RAS pulse width
100K
100K
100K
100K
ns
Shaded areas contain advance information.
Refresh cycle
-40
-50
-60
-70
Symbol
Parameter
Min
10
10
0
Max
–
Min
10
10
0
Max
–
Min
10
15
0
Max
–
Min
10
15
0
Max
–
Unit
ns
Notes
3
t
t
t
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
CSR
CHR
RPC
–
–
–
–
ns
3
–
–
–
–
ns
CAS precharge time
(CAS-before-RAS counter test)
t
5
–
10
–
10
–
10
–
ns
CPT
Shaded areas contain advance information.
Output enable
-40
-50
-60
-70
Std
Symbol
Parameter
Min
5
Max
–
Min
10
–
Max
–
Min
10
–
Max
–
Min
10
–
Max
–
Unit
ns
Notes
t
t
t
RAS hold time referenced to OE
OE access time
ROH
OEA
OED
–
10
–
13
–
15
–
18
–
ns
OE to data delay
10
13
15
18
ns
Output buffer turnoff delay
from OE
t
t
–
10
–
–
13
–
–
15
–
–
18
–
ns
ns
8, 10
OEZ
OE command hold time
10
13
15
18
OEH
Shaded areas contain advance information.
6
AS4C14400
®
Notes
1
2
3
ICC1, ICC3, ICC4, and ICC6 depend on cycle rate.
ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 16 ms).
4
AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH
(max) ≤ VCC. See AC test conditions for more information.
5
6
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by tCAC
.
7
Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the
specified tRAD (max) limit, then access time is controlled exclusively by tAA
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either tRCH or tRRH must be satisfied for a read cycle.
.
8
9
10 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
11 tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWCS
≥
tWCS (min) and tWCH ≥ tWCH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.
If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of tCAA or tCAC or tCAP
14 tASC ≥ tCP to achieve tPC (min) and tCAP (max) values.
15 These parameters are sampled and not 100% tested.
.
AC test conditions
- Access times are measured with output reference
+5V
levels of V = 2V and V = 0.8 V
OH
OL
- Input rise and fall times: 5 ns
R1 = 828W
D
out
+3.0V
90%
90%
10%
100 pF*
R2 = 295W
GND
*including scope
and jig capacitance
10%
Figure A: Input waveform
Figure B: Equivalent output load
Key to switching waveforms
Don’t care input
Rising input
Falling input
Undefined output
7
AS4C14400
®
Timing waveform of read cycle
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tRCS
tCAH
tCRP
tASC
tCAS
CAS
tAR
tRAD
tRAL
tRAH
tASR
Row
Address
Column
tRRH
tRCH
WE
OE
tROH
tOEZ
tRAC
tAA
tOEA
tCAC
tOFF
tCLZ
I/O
Data Out
Timing waveform of early write cycle
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
CAS
tAWR
tRAD
tRAL
tCAH
tASC
tASR
tRAH
Row
Column
tWCR
Address
tCWL
tRWL
tWP
tWCS
tWCH
WE
OE
tDHR
tDS
tDH
Data In
I/O
8
AS4C14400
®
Timing waveform of write cycle
(OE controlled)
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CAS
tRAL
tAWR
tRAD
tRAH
tASC
tASR
tCAH
Row
Column
tWCR
Address
tRWL
tCWL
tWP
WE
OE
tOEH
tDHR
tOED
tDS
tDH
Data In
I/O
Timing waveform of read-write cycle
tRWC
tRAS
tRP
RAS
tCAS
tRSH
tCRP
tRCD
tCSH
CAS
tAR
tRAL
tRAD
tASC
tRAH
tCAH
tASR
Row
Column
tRWD
Address
tRWL
tAWD
tCWL
tWP
tRCS
tCWD
WE
OE
tOEA
tOEZ
tOED
tRAC
tAA
tCAC
tCLZ
tDS
tDH
Data Out
Data In
I/O
9
AS4C14400
®
Timing waveform of fast page mode read cycle
tRASP
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
tCP
tPC
CAS
tAR
tRAD
tRAL
tCAH
Column
tASC
tASR
tRAH
Row
Column
tRCS
Column
tRCS
Address
tRRH
tRCH
tRCH
tOEA
WE
OE
tOEA
tRAC
tOEZ
tOFF
tCLZ
tCAP
tAA
Data Out
tCAC
Data Out
Data Out
I/O
Timing waveform of fast page mode early write cycle
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCAH
tCSH
tASC
tWCS
tCAS
tCP
tRSH
CAS
tRAL
tAR
tASR
tRAD
Address
Row
Column
Column
Column
tCWL
tWP
tWCH
tOEH
WE
OE
tHDR
tOED
tDH
tDS
I/O
Data In
Data In
Data In
10
AS4C14400
®
Timing waveform of fast page mode read-write cycle
tRASP
tRP
RAS
tPCM
tCAS
tCSH
tRCD
tRAD
tCP
tCRP
CAS
tRAL
tCAH
tASR
tRAH
tCAH
tCAH
Row
tRCS
Column
tRWD
Column
tCWL
Column
Address
tRWL
tCWL
tWP
tCWD
tAWD
tCWD
tCWD
tAWD
WE
OE
tOEA
tOEZ
tOED
tOEA
tAA
tDH
tRAC
tCAP
tCLZ
tCAC
tDS
tCLZ
tCAC
tDS
tCLZ
tCAC
Data In
Data Out
Data In
Data Out
Data In
I/O
Data Out
Timing waveform of RAS only refresh cycle
(WE = OE = V or V )
IH IL
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tARS
tRAH
Address
Row
Timing waveform of CAS-before-RAS refresh cycle
(WE = OE = V or V )
IH IL
tRC
tRP
tRAS
RAS
tRPC
tCPN
tCSR
tCHR
CAS
tOFF
I/O
11
AS4C14400
®
Timing waveform of hidden refresh cycle (read)
tRC
tRC
tRAS
tPR
tRAS
tPR
RAS
tCRP
tCHR
tRCD
tRSH
tCRP
CAS
tAR
tRAD
tRAH
tASC
Column
tASR
Row
Address
tRCS
tRRH
WE
OE
tOEA
tRAC
tAA
tCAC
tCLZ
tOFF
tOEZ
Data Out
I/O
Timing waveform of hidden refresh cycle (write)
tRC
tRAS
tRP
RAS
CAS
tCRP
tRCD
tRSH
tAR
tRAD
tASC
tRAH
tRAL
tASR
tCAH
Row
Column
tWP
Address
WE
tRWL
tWCR
tWCS
tWCH
tDS
tDH
tDHR
Data In
I/O
OE
12
AS4C14400
®
Timing waveform of CAS before RAS refresh counter test cycle
tRAS
tRP
tRSH
RAS
CAS
tCSR
tCPT
tCAS
tCHR
tRAL
tCAH
Address
Column
tAA
tCAC
tCLZ
tOFF
I/O
WE
OE
Data Out
tRRH
tRCH
tRCS
tROH
tOEA
tRWL
tCWL
tWP
tWCH
tWCS
WE
tDH
tDS
I/O
OE
Data In
tRCS
tWP
tCWD
tAWD
tCWL
WE
OE
tOEA
tOED
t AA
tDH
tCLZ
tCAC
tOEZ
tDS
I/O
Data Out
Data In
13
AS4C14400
®
Typical DC and AC characteristics
Normalized access time t
Normalized access time t
Typical access time t
RAC
vs. load capacitance C
L
RAC
RAC
a
vs. supply voltage V
vs. ambient temperature T
CC
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
90
80
70
60
50
40
30
20
T = 25°C
a
-60
-50
-40
4.1
4.5
5.0
5.5
–55
–10
35
80
50
100
150
200
250
6.0
125
Supply voltage (V)
Ambient temperature (°C)
Load capacitance (pF)
Typical supply current I
Typical supply current I
Typical power-on current I
PO
CC
CC
a
vs. supply voltage V
vs. ambient temperature T
vs. cycle rate 1/t
RC
CC
70
60
50
40
30
20
10
0.0
70
60
50
40
30
20
10
0.0
70
60
50
40
30
20
10
0.0
4.0
4.5
5.0
5.5
–55
–10
35
80
2
4
6
8
6.0
125
10
Supply voltage (V)
Ambient temperature (°C)
Cycle rate (MHz)
Typical refresh current I
Typical refresh current I
Typical TTL stand-by current I
CC2
CC3
CC3
a
vs. supply voltage V
vs. ambient temperature T
vs. supply voltage V
CC
CC
70
60
50
40
30
20
10
0.0
70
60
50
40
30
20
10
0.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
4.0
4.5
5.0
5.5
–55
–10
35
80
2
4
6
8
6.0
125
10
Supply voltage (V)
Ambient temperature (°C)
Supply voltage (V)
14
AS4C14400
®
Typical TTL stand-by current I
Typical fast page mode current I
Typical fast page mode current I
CC4
CC2
CC4
vs. ambient temperature T
vs. ambient temperature T
vs. supply voltage V
CC
a
a
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
70
60
50
40
30
20
10
0.0
70
60
50
40
30
20
10
0.0
0
20
40
60
80
0
20
40
60
80
4.0
4.5
5.0
5.5
6.0
Ambient temperature (°C)
Ambient temperature (°C)
Supply voltage (V)
Capacitance
(f = 1 MHz, T = Room Temperature)
a
Parameter
Symbol
Signals
Test Conditions
Max
5
Unit
pF
C
C
C
A0 to A8
V
= 0V
= 0V
IN1
IN2
I/O
in
in
Input capacitance
I/O capacitance
RAS, CAS, WE, OE
I/O0 to I/O3
V
7
pF
V = V = 0V
7
pF
in
out
15
AS4C14400
®
Ordering codes
Package \ RAS Access Time
40 ns
50 ns
60 ns
70 ns
AS4C14400-40JC
AS4C14405-40JC
AS4C14400-50JC
AS4C14405-50JC
AS4C14400-60JC
AS4C14405-60JC
AS4C14400-70JC
AS4C14405-70JC
Plastic SOJ, 300 mil, 20/26-pin
AS4C14400-40TC
AS4C14405-40TC
AS4C14400-50TC
AS4C14405-50TC
AS4C14400-60TC
AS4C14405-60TC
AS4C14400-70TC
AS4C14405-70TC
Plastic TSOP, 300 mil, 20/26-pin
Shaded areas contain advance information.
Part numbering system
AS4C
14400
–XX
RAS access time
X
C
Package:
J
T
= SOJ 300 mil,
= TSOP 300 mil
DRAM Prefix
Device number
Commercial temperature range, 0°C to 70 °C
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Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a
committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not
authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks
of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.
ALLIANCE SEMICONDUCTOR
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Printed in U.S.A.he
Copyright © 1996 All rights reserved.
June 1996
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