AS4C16M32MS-7BCN [ALSC]
Multiple Burst Read with Single Write Operation;
| 型号： | AS4C16M32MS-7BCN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Multiple Burst Read with Single Write Operation |
| 文件： | 总48页 (文件大小：3864K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
512M Low Power Mobile SDRAM (MSDR)
Revision History
512M AS4C32M16MS-7BCN/AS4C32M16MS-6BIN - 54 ball FBGA PACKAGE
512M AS4C16M32MS-7BCN/AS4C16M32MS-6BIN - 90 ball FBGA PACKAGE
Revision Details
Rev 1.0 Preliminary datasheet
Date
Jun 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
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Rev.1.0 June 2016
AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
- Drive Strength (DS) Option: Full, 1/2, 1/4 and 3/4
- Auto Temperature Compensated Self Refresh
(Auto TCSR)
Features
- 4 banks x 8Mbit x 16 organization
- 4 banks x 4Mbit x 32 organization
- High speed data transfer rates up to 166 MHz
- Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
- Partial Array Self Refresh (PASR) option: Full, 1/
2, 1/4, 1/8 and 1/16
- Deep Power Down (DPD) mode
- Programmable Power Reduction Feature by patial
array activation during Self-Refresh
- Operating Temperature Range
Commercial (-25°C to 85°C)
- Single Pulsed RAS Interface
- Data Mask for Read/Write Control
- Four Banks controlled by BA0 & BA1
- Programmable CAS Latency: 2, 3
- Programmable Wrap Sequence:
Sequential or Interleave
Industrial (-40°C to +85°C)
- Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
- Multiple Burst Read with Single Write Operation
- Automatic and Controlled Precharge Command
- Random Column Address every CLK (1-N Rule)
- Power Down Mode and Clock Suspend Mode
- Auto Refresh and Self Refresh
- Refresh Interval:
8192 cycles/64 ms
- Available in 54-ball (32M x16) and 90-ball (16M x32)FBGA
- VDD=1.8V, VDDQ=1.8V
- LVTTL Interface
Table 1. Key Specifications
AS4C32M16MS/AS4C16M32MS
-6/7
tCK(3)
tAC(3)
tRAS
Clock Cycle time(min.)
Access time from CLK (max.)
Row Active time(min.)
6/7.5 ns
5/5.4 ns
42/45 ns
60/67.5 ns
Row Cycle time(min.)
tRC
Tableꢀ2.ꢀOrderingꢀInformationꢀ
PartꢀNumberꢀ
AS4C32M16MS-7BCNꢀ
AS4C32M16MS-6BINꢀ
AS4C16M32MS-7BCNꢀ
AS4C16M32MS-6BINꢀ
Orgꢀ
Temperatureꢀ
MaxClockꢀ(MHz)ꢀ
Packageꢀ
133
54-ballꢀFBGA
54-ballꢀFBGA
90-ballꢀFBGA
90-ballꢀFBGA
32Mx16ꢀ
32Mx16ꢀ
16Mx32
16Mx32ꢀ
Commercial ꢀꢀ-25°Cꢀtoꢀ+85°Cꢀ
Industrial ꢀ-40°Cꢀtoꢀ+85°Cꢀ
Commercial ꢀꢀ-25°Cꢀtoꢀ+85°Cꢀ
Industrial ꢀ-40°Cꢀtoꢀ+85°Cꢀ
166ꢀ
133
166ꢀ
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Rev.1.0 June 2016
AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
512Mb Mobile SDRAM Addressing
Configuration
32MX16
16MX32
16MX32
(Reduced page size)
# of Bank
4
4
4
Bank Address
Auto precharge
Row Address
Column Address
BA0 ~ BA1
A10/AP
BA0 ~ BA1
A10/AP
BA0 ~ BA1
A10/AP
A0 ~ A12
A0 ~ A9
A0 ~ A12
A0 ~ A8
A0 ~ A13
A0 ~ A7
54 Pin (X16) BGA PIN CONFIGURATION
Top View
9
8
7
6
5
ꢀꢁꢁꢁꢁꢁꢂꢁꢁꢁꢁꢁꢃ
1
65C bmm!)7Y :*!D T Q
A
B
C
D
E
F
2
3
4
8
9
:
B
C
D
E
F
G
H
I
K
W T T
E R 26
E R 24
E R 22
E R :
W T T R
W E E R
W T T R
W E E R
W T T
W E E R
W T T R
W E E R
W T T R
W E E
E R 1
E R 3
E R 4
E R 7
ME R N
W E E
E R 2
E R 4
E R 6
E R 8
E R 25
E R 23
E R 21
E R 9
V E R N
B 23
E O V 2
D L
D L F
B :
D B T
C B 1
S B T
C B 2
X F
D T
G
H
J
B 22
B 8
B 9
B 7
B 5
B 1
B 4
B 2
B 3
B 210B Q
W T T
B 6
W E E
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
90 Pin (X32) BGA PIN CONFIGURATION
Top View
9
8
7
6
5
ꢀꢁꢁꢁꢁꢁꢂꢁꢁꢁꢁꢁꢃ
ꢄ
:1C bmm!)7Y 26*!D T Q
A
B
C
D
E
F
2
3
4
8
9
:
B
C
D
E
F
G
H
I
K
L
M
N
O
Q
S
E R 37
E R 39
W T T R
W T T R
W E E R
W T T
E R 35
W E E R
E R 38
E R 3:
E R 42
E R N 4
B 6
W T T
W T T R
E R 36
E R 41
O D
W E E
W E E R
E R 33
E R 28
O D
E R 34
W T T R
E R 31
E R 29
E R 27
E R N 3
B 1
E R 32
E R 2:
W E E R
W E E R
W T T R
W E E
B 4
B 3
B 5
B 7
B 210B Q
B 242
B 2
G
H
B 8
B 9
B 23
B :
C B 2
B 22
D L
D L F
E O V 3
C B 1
D T
S B T
E R N 2
W E E R
W T T R
W T T R
E R 22
E R 24
O D
D B T
W E E
X F
E R N 1
W T T R
W E E R
W E E R
E R 5
J
K
/
E R 9
W T T
E R :
E R 25
W T T R
W T T
E R 8
E R 6
E R 4
W T T R
E R 1
E R 21
E R 23
W E E R
E R 26
E R 7
E R 2
W E E R
W E E
0
1
3
E R 3
O p uf !2 ;!B 2 4 !jt!pomz!bwbjmbcmf!gps!sfevdfe!qbhf.tj{f!dpogjhvsbujpo/
O p uf !3 ;!U i f !E O V !q jo!n vtu!cf!dpoofdufe!up!W T T -!W T T R -!ps!mf gu!gmpbujoh/
5
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Description
The AS4C32M16MS / AS4C16M32MS is a four bank Synchronous DRAM organized as 4 banks x
8Mbit x 16 and 4 banks x 4Mbit x 32. The AS4C32M16MS / AS4C16M32MS achieves high speed data
transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. All of the control, address, data input and output circuits
are synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Signal Pin Description
Pin
Type
Signal Polarity
Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
CKE
CS
Input
Input
Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Pulse Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
RAS, CAS Input
WE
Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
A0 - A13
Input
Level
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
and A0-A13 defines the row address (RA0-RA13) for 16Mx32 reduced page size when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
for 32Mx16, A0-A8 defines the column address (CA0-CA8) for 16Mx32 and A0-A7 de-
fines tthe column address (CA0-CA7) for 16Mx32 reduced page size when sampled at
the rising clock edge.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
BA0,
BA1
Input
Level
Level
—
—
Selects which bank is to be active.
DQx
Input
Data Input/Output pins operate in the same manner as on conventional DRAMs.
Output
LDQM
UDQM
Input
Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high. If it’s high, LDM corresponds to DQ0-DQ7, and UDM corresponds to data
on DQ8-DQ15 in 32Mx16. DM0 corresponds to DQ0-DQ7, DM1 corresponds to data on
DQ8-DQ15, DM2 corresponds to DQ16-DQ23, and DM3 corresponds to data on DQ24-
DQ31 in 16Mx32.
(DM0~3)
VDD, VSS Supply
Power and ground for the input buffers and the core logic.
VDDQ
VSSQ
Supply
—
—
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
NC
Input
No connect.
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the
positive edge of the clock. The following list shows the thruth table for the operation commands.
Device CKE CKE
A0-9,
BA0
BA1
Operation
State
n-1
n
X
X
X
X
X
X
X
X
X
X
H
L
CS
L
RAS CAS WE DQM A11,12 A10
Row Activate
Idle3
H
L
H
H
H
H
L
H
L
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
X
X
V
X
X
X
X
V
L
V
V
V
V
V
V
X
V
X
X
X
X
Read
Active3
Active3
Active3
Active3
Any
H
L
Read w/Autoprecharge
Write
H
L
L
H
L
H
L
L
Write with Autoprecharge
Row Precharge
Precharge All
H
L
L
L
H
L
H
L
H
H
L
L
Any
H
L
L
L
H
V
X
X
X
X
Mode Register Set
No Operation
Idle
H
L
L
L
Any
H
L
H
X
L
H
X
L
H
X
H
H
X
X
X
X
X
L
Device Deselect
Auto Refresh
Any
H
H
L
Idle
H
Self Refresh Entry 6
Self Refresh Exit 6
Idle
H
L
L
L
Idle
H
L
X
H
X
H
X
H
X
H
X
H
X
H
(Self Refr.)
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
Power Down Entry
Power Down Exit
Idle
Active4
H
L
Any
H
L
(Power
Down)
H
Data Write/Output Enable
Data Write/Output Disable
Deep Power Down Entry
Deep Power Down Exit
Active
Active
Idle
H
H
H
L
X
X
L
X
X
L
X
X
H
X
X
X
H
X
X
X
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Deep power-
Down
H
X
X
Notes:
1. V = Valid , x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.
3. These are state of bank designated by BA0, BA1 signals.
4. Power Down Mode can not entry in the burst cycle.
5. After Deep Power Down mode exit a full new initialization of memory device is mandatory
6. Extended grade does not guarantee self-refresh function
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following power
on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a
conventional DRAM, the Synchronous DRAM must be powered up and initialized in a pre-defined manner. During
power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals
are held in the “NOP” state. The CLK signal must be started at the same time. After power on, the device requires
a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point
during this 100us period and continuing at least through the end of this period, COMMAND INHIBIT or NOP
commands should be applied. After the 100us delay is satisfied by issuing at least one COMMAND INHIBIT or
NOP command, a PRECHARGE command must be issued. All banks must then be pre-charged, which places
the device in the all banks idle state. Once all banks have been pre-charged, the Mode Register and Extended
Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh
cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to
follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
The Mode register designates the operation mode at the read or write cycle. This register is divided into 4
fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column
access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock
cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a
special Burst Read and Single Write mode. The mode set operation must be done before any activate com-
mand after the initial power up. Any content of the mode register can be altered by re-executing the mode set
command. All banks must be in pre-charged state and CKE must be high at least one clock before the mode
set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS,
CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing
defines parameters to be set as shown in the previous table.
Extended Mode Register
The extended Mode Register controls functions beyond those controlled by the Mode Register. These
additional functions are unique to the mobile SDRAM and includes the selection of drive strength (DS). The device
has four drive strength options: Full, 12, 1/4 or 3/4. And a Partial-Array Self-Refresh field (PASR). The PASR
field is used to specify whether partial bank 1/2, 1/4, 1/8, 1/16 or all banks of the SDRAM array are enabled.
Disabled banks will not be refreshed in Self-Refresh mode and written data will be lost. When only bank 0 is
selected, it’s possible to partially select only half or more quarter of bank 0. The default setting for DS is full-
strength, while PASR is full memory. Both DS and PASR can be set during the initialization sequence and can be
modified when the part is idle. Additionally, the device has internal temperature sensor control self refresh
cycle automatically. This is the device internal Temperature Compensated Self Refresh (TCSR).
Read and Write Operation
When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According
to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline
are set. A CAS cycle is triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, t
or a write (WE = L) at this stage.
, from the RAS timing. WE is used to define either a read (WE = H)
RCD
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write
operations are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length
programmed at the mode set operation, i.e., one of 1, 2, 4, 8. Column addresses are segmented by the burst
length and serial data accesses are done within this boundary. The first column address to be accessed is supplied
at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length
and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the
rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Address Input for Mode Set (Mode Register Operation)
BA1 BA0 An~ A10 A9
Operation Mode
Address Bus (Ax)
Mode Register
A8 A7 A6 A5 A4 A3 A2 A1 A0
CAS Latency BT Burst Length
Burst Type
Operation Mode
A3
0
Type
BA1 BA0 An~A10 A9 A8 A7
Mode
Sequential
Interleave
Burst Read/Burst
Write
0
0
0
0
0
0
0
0
0
1
Burst Read/Single
Write
1
0
0
Burst Length
CAS Latency
Length
A6
0
A5
0
A4
0
Latency
Reserve
Reserve
2
A2
A1
A0
Sequential Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
1
2
0
0
1
0
1
0
4
4
0
1
1
3
8
8
1
0
0
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Full page
Reserve
Reserve
Reserve
Reserve
1
0
1
1
1
0
1
1
1
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum t or the refresh
RAS
interval time limits the number of random column accesses. A new burst access can be done even before the
previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is
interrupted, the remaining addresses are overridden by the new address with the full burst length. An
interrupt which accompanies with an operation change from a read to a write is possible by exploiting
DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and pre-charge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or more
banks are activated, column to column interleave operation can be done between different pages.
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Extended Mode Register Table
BA1 BA0 An~ A10 A9
Address Bus (Ax)
Mode Register
A8 A7 A6 A5 A4 A3 A2 A1 A0
all have to be set to "0"
1*)
DS
0*)
TCSR**
PASR
Drive Strength
A6
0
A5
0
Drive Strength
Full
1/2
1/4
3/4
0
1
Partial-Array Self Refresh:
1
0
banks to be self-refreshed
A1 A0
A2
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
all banks
1/2 array (BA1=0)
1/4 array (BA1=0, BA0=0)
Reserved
0
0
0
1
Reserved
1
1/8 array (BA1=BA0=0,
RA11=0)
1
1
1
1
0
1
1/16 array (BA1=BA0=0,
RA11=RA10=0)
Reserved
* *On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
*)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register)
The extended Mode Register can be set during the initialization sequence. Once the device is operational, the
extended Mode Register set can be issued anytime when the part is idle.
Extended grade does not guarantee self-refresh function.
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Burst Length and Sequence:
Burst Starting Address Sequential Burst Addressing
Interleave Burst Addressing
(decimal)
Length
(A2 A1 A0)
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4
8
x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full Page
nnn
Cn, Cn+1, Cn+2
Not supported
Data Disable Latency t
). It also provides a data
Refresh Mode
DQZ
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited
(DQM Write Mask Latency t
= zero clocks).
DQW
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(t ) must occur before the SDRAM can enter the
RP
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device can’t remain in Power
command is necessary. A minimum t time is re-
RC
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
Down mode longer than the Refresh period (t
) of
REF
the device. Exit from this mode is performed by tak-
ing CKE “high”. One clock delay is required for
mode entry and exit.
Auto Precharge
Two methods are available to precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command
is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the
precharge operation one clock before the last data
out for CAS latencies 2, and two clocks for CAS la-
tencies 3. If CA10 is high when a Write Command is
tion. After the exit command, at least one t delay
RC
is required prior to any access command. Extended
grade does not guarantee self-refresh function.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after delay (DQM
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
issued, the Write with Auto-Precharge function is
initiated. The SDRAM automatically enters the pre-
Once a burst read or write operation has been ini-
tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Pre-charge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.
charge operation a time delay equal to t
recovery time) after the last data in.
(Write
WR
Precharge Command
There is also a separate precharge command
available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharge command.
Bank Selection by Address Bits:
A10 BA0 BA1
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Bank 0
Bank 1
Bank 2
Bank 3
all Banks
Deep Power Down Mode
The Deep Power Down mode is an unique
with very low standby currents. All internal voltage
generators inside the Mobile SDRAM are stopped; all
memory data is lost in this mode. To enter the Deep
Power Down mode all banks must be precharged
Burst Termination
Recommended Operation and Characteristics
T = -25 to 85 °C(Commercial); -40 to 125°C(Extended) V = 0 V; V = 1.8 V,V
= 1.8V
A
SS
DD
DDQ
Limit Values
Parameter
Symbol
VDD
min.
max.
Unit Notes
Supply voltage
1.7
1.7
1.95
1.95
VDD+0.3
0.3
V
I/O Supply Voltage
VDDQ
VIH
V
V
1, 2
1, 2
1, 2
Input high voltage (AC)
Input low voltage (AC)
Output high voltage (IOUT = – 0.1 mA)
Output low voltage (IOUT = 0.1 mA)
0.8xVDDQ
– 0.3
0.9*VCCQ
–
VIL
V
VOH
VOL
–
V
0.2
V
Input leakage current, any input
II(L)
– 1
1
μA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output leakage current
IO(L)
– 1.5
1.5
μA
(DQ is disabled, 0 V < VOUT < VCC
)
Note:
1. All voltages are referenced to VSS
.
2. VIH may overshoot to VCC + 2 V for pulse width of < 3ns with 1.8V. VIL may undershoot to -2 V for pulse width < 3ns with 1.8V. Pulse
width measured at 50% points with amplitude measured peak to DC reference.
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Absolute Maximum Ratings*
Operating temperature range (commercial)-25 to 85 °C
Operating temperature range (industrial) -40 to 85 °C
Storage temperature range ............... -55 to 150 °C
Input/output voltage.............................-0.5 to 2.4 V
Power supply voltage ..........................-0.5 to 2.4 V
*Note:
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Operating Currents T =-25 to 85 °C(Commercial)/-40 to 85 °C(Industrial);
A
V
= 0 V; V = 1.8 V,V = 1.8V(Recommended Operating Conditions unless otherwise noted)
DDQ
SS
DD
Max.
Symbol Parameter & Test Condition
-6
-7
Unit
Note
ICC1
Operating Current
1 bank operation
50
45
mA
7
tRC = tRCMIN., tRC = tCKMIN
.
Active-precharge command cycling,
without Burst Operation
ICC2P
ICC2N
Precharge Standby Current
in Power Down Mode
tCK = min.
0.3
10
0.3
10
mA
mA
7
CS =VIH, CKE≤ VIL(max)
Precharge Standby Current
in Non-Power Down Mode
CS =VIH, CKE≥ VIL(max)
tCK = min.
ICC3N
ICC3P
ICC4
No Operating Current
CKE ≥ VIH(MIN.)
20
5
20
5
mA
mA
mA
t
CK = min, CS = VIH(min)
bank ; active state ( 4 banks)
CKE ≤ VIL(MAX.)
(Power down mode)
Burst Operating Current
75
70
7,8
7
t
CK = min
Read/Write command cycling
ICC5
IZZ
Auto Refresh Current
95
10
95
10
mA
uA
t
CK = min
Auto Refresh command cycling
Deep Power Down Current
Notes:
7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and
tRC. Input signals are changed one time during tCK
8. These parameter depend on output loading. Specified values are obtained with output open.
.
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Temperature Compensated/Partial Array Self-Refresh Currents
Extended Mode
Register A[2:0]
Tcase [oC]
Parameter & Test Condition
Symb.
max.
Unit
Note
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
85oC max.
45oC max.
85oC max.
45oC max.
85oC max.
45oC max.
85oC max.
45oC max.
85oC max.
45oC max.
ICC6
ICC6
ICC6
ICC6
ICC6
ICC6
ICC6
ICC6
ICC6
ICC6
600
300
480
260
420
250
420
250
400
250
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
full array activations, all banks
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
1/2 array activations
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
1/4 array activation
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
1/8 array activation
Self Refresh Current
Self Refresh Mode
CKE=Low, tck=min,
1/16 array activation
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
AC Characteristics
T = -25 to 85 °C(Commercial)/-40 to 85 °C(Industrial) V = 0 V; V = 1.8 V,V = 1.8V, tT=1 ns
A
SS
DD
DDQ
Limit Values
-7
-6
#
Symbol Parameter
Min.
Max.
Min.
Max.
Unit
Note
Clock and Clock Enable
1
2
3
tCK
fCK
tAC
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
6
9
–
–
7.5
9
–
–
ns
ns
6
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
–
166
110
–
–
133
110
MHz
MHz
Access Time from Clock
CAS Latency = 3
–
_
5
8
–
_
5.4
8
ns
ns
CAS Latency = 2
4
5
6
tCH
tCL
tT
Clock High Pulse Width
Clock Low Pulse Width
Transition Tim
2.5
2.5
0.3
–
–
2.5
2.5
0.3
–
–
ns
ns
ns
1.2
1.2
9
Setup and Hold Times
7
tCKH
tCKS
tDH
CKE hold time
1
1.5
1
–
–
–
–
–
–
1
1.5
1
–
–
–
–
–
–
–
–
–
ns
ns
8
CKE setup time
9
Data-in hold time
ns
10
11
12
13
14
15
tDS
Data-in setup time
1.5
1
1.5
1
ns
tAH
Address hold time
ns
tAS
Address setup time
1.5
1.5
0.5
2
1.5
1.5
0.5
2
ns
tCMH
tCMS
tMRD
/CS, /RAS, /CAS, /WE, DQM hold time
/CS, /RAS, /CAS, /WE, DQM setup time
Mode Register Set to Command delay
ns
–
–
ns
CLK
Common Parameters
16
17
18
19
tRCD
tRP
tRAS
tRC
Row to Column Delay Time
Row Precharge Time
Row Active Time
18
18
42
60
–
–
19.2
19.2
45
–
–
ns
ns
ns
ns
100K
–
100k
–
ActivetoActive/Auto Refreshcommand
period
67.5
20
tRRD
Activate(a) to Activate(b) Command
Period
2
–
2
–
CLK
21
22
23
tBDL
tCCD
tCDL
Last data-in to burst STOP command
CAS(a) to CAS(b) Command Period
1
1
1
–
–
–
1
1
1
–
–
–
CLK
CLK
CLK
12
12
13
Last data-in to new READ/WRITE com-
mand
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
AC Characteristics (Cont’d)
Limit Values
-7
-6
#
Symbol Parameter
Min.
Max.
Min.
Max.
Unit
Note
24
tCKED
CKE to clock disable or power-down
1
–
1
–
CLK
13
entry mode
25
tPED
CKE to clock enable or power-down
exit mode
1
–
1
–
CLK
13
Refresh Cycle
—
64
—
–
—
64
—
–
ms
ns
ns
8
26
27
tREF
tXSR
Refresh Period (8192 cycles)
Exit SELF REFRESH to first valid
command
112
97.5
112.5
97.5
11
28
tRFC
Row Refresh Cycle Time
Read Cycle
29
30
31
32
tOH
tOHN
tLZ
Data Out Hold Time(load)
2.5
1.8
1
–
–
–
2.5
1.8
1
–
–
–
ns
ns
ns
Data Out Hold Time(no load)
Data Out to Low Impedance Time
7
tHZ
Data Out to High Impedance Time
CAS Latency = 3
–
_
5
8
–
_
5.4
8
ns
ns
CAS Latency = 2
33
tROH
Data-out High-Z from PRECHARGE
command
CAS Latency = 3
3
2
–
_
3
2
–
_
CLK
CLK
12
CAS Latency = 2
Write Cycle
34
35
36
37
38
39
40
41
tWR
tDAL
tDPL
tDQD
tDQM
tDQZ
tDWD
tRDL
Write Recovery Time
15
5
–
–
–
–
–
–
–
–
15
5
–
–
–
–
–
–
–
–
ns
10
14,16
15,16
12
Data-in to ACTIVE command
Data-in to PRECHARGE command
DQM to input data delay
CLK
CLK
CLK
CLK
CLK
CLK
CLK
2
2
0
0
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Last data-in to PRECHARGE command
0
0
12
2
2
12
0
0
12
2
2
15,16
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Note:
1. A full initialization sequence is required before proper device operation is ensured.
2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature
range (0oC< TA <+70oC standard temperature and -40oC < TA <+85oC industrial temperature) is ensured.
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
4. Outputs measured for 1.8V at 0.9V with equivalent load:
Test loads with full DQ driver strength. Performance will vary with actual system DQ bus capacitive loading, termination,
and programmed drive strength.
5. AC timing tests have VIL and Vih with timing referenced to VIH/2 = crossover point. If the input transition time is
longer than tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover
point.
6. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints
specified for the clock ball) during access or pre-charge states (READ, WRITE, including tWR, and PRE-CHARGE
commands). CKE may be used to reduce the data rate.
7. tHZ defines the time at which the output achieves the open circuit condition, it is not a reference to VOH or VOL. The
last valid data element will meet tOH before going High-Z.
8. The 512M Mobile SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO
REFRESH command every 7.8125gs meets the refresh requirement and ensures that each row is refreshed. Alterna-
tively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms.
9. AC characteristics assume tT = 1ns.
10. Auto pre-charge mode only. The pre-charge timing budget (tRP) begins at x ns for -7 after the first clock delay
and after the last WRITE is executed. May not exceed the limit set for pre-charge mode.
11. CLK must be toggled a minimum of two times during this period.
12. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
13. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate.
14. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cycle rate.
15. Timing is specified by tWR. 16. Based on tCK (MIN), CL = 3.
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AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Timing Diagrams
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. Burst Termination
8.1 Termination of a Burst Write Operation
8.2 Termination of a Burst Write Operation
9. AC- Parameters
9.1 AC Parameters for a Write Timing
9.2 AC Parameters for a Read Timing
10. Mode Register Set
11. Power on Sequence and Auto Refresh (CBR)
12. Power Down Mode
13. Self Refresh (Entry and Exit)
14. Auto Refresh (CBR)
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AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Timing Diagrams (Cont’d)
15. Random Column Read ( Page within same Bank)
15.1 CAS Latency = 2
15.2 CAS Latency = 3
16. Random Column Write ( Page within same Bank)
16.1 CAS Latency = 2
16.2 CAS Latency = 3
17. Random Row Read ( Interleaving Banks) with Precharge
17.1 CAS Latency = 2
17.2 CAS Latency = 3
18. Random Row Write ( Interleaving Banks) with Precharge
18.1 CAS Latency = 2
18.2 CAS Latency = 3
19. Precharge Termination of a Burst
19.1 CAS Latency = 2
19.2 CAS Latency = 3
20. Deep Power Down Entry/Exit
20.1 Deep Power Down Entry
20.2 Deep Power Down Exit
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AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
1. Bank Activate Command Cycle
(CAS latency = 3)
T0
T1
T
T
T
T
T
CLK
. . . . . . . . . .
Bank A
Row Addr.
Bank A
Col. Addr.
Bank A
Row Addr.
Bank B
Row Addr.
. . . . . . . . . .
ADDRESS
tRCD
tRRD
Write A
with Auto
Precharge
Bank B
Activate
Bank A
Activate
Bank A
Activate
. . . . . . . . . .
NOP
NOP
NOP
COMMAND
: “H” or “L”
tRC
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
tCK2, I/O’s
CAS latency = 3
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
tCK3, I/O’s
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3. Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT B
0
DOUT B
DOUT B
DOUT B
3
0
1
2
tCK2, I/O’s
CAS latency = 3
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
3
0
0
1
2
tCK3, I/O’s
4.1 Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0 T1 T2
T3
T4
T5
T6
T7
T8
CLK
Minimum delay between the Read and Write Commands = 4+1 = 5 cycles
tDQW
DQM
tDQZ
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
COMMAND
I/O’s
DIN B
DIN B
DIN B
2
DOUT A
0
1
0
Must be Hi-Z before
the Write Command
: “H” or “L”
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AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
4.2 Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
1 Clk Interval
READ A
BANK A
ACTIVATE
NOP
NOP
WRITE A
NOP
NOP
NOP
NOP
COMMAND
Must be Hi-Z before
the Write Command
CAS latency = 2
DIN A
DIN A
DIN A
DIN A
3
0
1
2
tCK2, I/O’s
: “H” or “L”
4.3 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
tDQW
DQM
tDQZ
NOP
READ A
NOP
NOP
READ A
NOP
WRITE B
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT A
DOUT A
DIN B
DIN B
DIN B
DIN B
DIN B
DIN B
0
1
0
1
2
tCK1, I/O’s
Must be Hi-Z before
the Write Command
CAS latency = 3
0
0
1
2
tCK2, I/O’s
: “H” or “L”
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5. Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
I/O’s
DIN A
0
don’t care
DIN A
DIN A
DIN A
3
1
2
The first data element and the Write
are registered on the same clock edge.
Extra data is ignored after
termination of a Burst.
6.1 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
I/O’s
1 Clk Interval
DIN A
0
DIN B
0
DIN B
DIN B
DIN B
3
1
2
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6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
don’t care
don’t care
DIN A
0
DOUT B
0
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
1
2
3
t
CK2, I/O’s
CAS latency = 3
DIN A
0
don’t care
DOUT B
3
0
1
2
tCK3, I/O’s
Input data must be removed from the I/O’s at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
T2
T3
T7
T8
T0
T1
T5
T6
T4
CLK
Bank
Activate
WRITEA
NOP
NOP
NOP
NOP
NOP
NOP
Command
NOP
Auto-Precharge
tWR
tRP
CAS latency = 2
DIN A
DIN A
DIN A
0
1
t
CK2, I/O’s
*
tRP
tWR
CAS latency = 3
DIN A
1
0
t
CK2, I/O’s
Begin Autoprecharge
*
Bank can be reactivated after t
RP
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7.2 Burst Read with Auto-Precharge
Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ A
COMMAND
t
RP
CAS latency = 2
*
DOUT A
DOUT A
DOUT A
DOUT A
t
0
1
2
3
t
CK2, I/O’s
RP
CAS latency = 3
*
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
tCK3, I/O’s
Begin Autoprecharge
*
Bank can be reactivated after t
RP
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8.1 Termination of a Burst Read Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
t
CK2, I/O’s
CAS latency = 3
DOUT A
DOUT A
DOUT A
DOUT A
3
0
1
2
t
CK3, I/O’s
8.2 Termination of a Burst Write Operation
(CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2,3
don’t care
DIN A
0
DIN A
DIN A
2
1
I/O’s
Input data for the Write is masked.
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\
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\
11. Power on Sequence and Auto Refresh (CBR)
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20.1 Deep Power Down Mode Entry
CLK
CKE
CS
WE
CAS
RAS
Addr.
DQM
DQ
input
DQ
output
High-Z
t RP
Precharge Command
Deep Power Down Entry
Deep Power Down Mode
Normal Mode
The deep power down mode has to be maintained for a minimum of 100μs
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20.2 Deep Power Down Exit
The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to
enter a new command:
1. Maintain NOP input conditions for a minimum of 200 μs
2. Issue precharge commands for all banks of the device
3. Issue eight or more autorefresh commands
4. Issue a mode register set command to initialize the mode register
5. Issue an extended mode register set command to initialize the extende mode register
CLK
CK E
CS
RAS
CAS
WE
t
t
RC
t
200 us
RFC
RP
Deep Power Down
exit
All banks
precharge
Auto
refresh
Auto
refresh
Mode
Register Mode
Set
Extended
New
Command
Register Accepted
Set
Here
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Mobile SDRAM State Diagram
Power
Applied
Deep
Power
Down
DPDSX
Power
On
Precharge
PREALL
DPDS
Self
Refresh
REFS
REFSX
MRS
Auto
MRS
REFA
Idle
EMRS
Refresh
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Write
Burst Stop
Row
Active
Read
Write
Read
Write A
Read A
Read
Read
Write
Read A
Write A
Read
A
PRE
Write
A
Read
A
PRE
PRE
Precharge
PREALL
PRE
Automatic Sequence
Command Sequence
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Package Diagram
32Mx16 54-BALL 0.8mm pitch BGA
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Package Diagram
16Mx32 90-BALL 0.8mm pitch BGA
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PART NUMBERING SYSTEM
B
AS4Cꢀ 32M16MS or 16M32MS
6/7ꢀ
C / Iꢀ
Nꢀ
C=Commercialꢀ
(-25°ꢀC~+85°ꢀC)
I = Industrial
Bꢀ=ꢀFBGA
6=166MHz
7=133MHzꢀ
32M16=32Mx16
DRAMꢀ
IndicatesꢀPbꢀandꢀ
HalogenꢀFreeꢀ
16M32=16Mx32
MS=Mobile SDRAM
(-40° C~+85° C)
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names
may be the trademarks of their respective companies. Alliance reserves the right to make changes
to this document and its products at any time without notice. Alliance assumes no responsibility for
any errors that may appear in this document. The data contained herein represents Alliance's best
data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant
changes to these specifications are possible. The information in this product data sheet is intended
to be general descriptive information for potential customers and users, and is not intended to
operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not
assume any responsibility or liability arising out of the application or use of any product described
herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance
products including liability or warranties related to fitness for a particular purpose, merchantability,
or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made
exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from
Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not
authorize its products for use as critical components in life-supporting systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such
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