AS4C256K16E0 [ALSC]
5V 256Kx16 CMOS DRAM (EDO); 5V 256Kx16 CMOS DRAM （ EDO ）
| 型号： | AS4C256K16E0 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 5V 256Kx16 CMOS DRAM (EDO) |
| 文件： | 总24页 (文件大小：632K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C256K16E0
®
5V 256K×16 CMOS DRAM (EDO)
Features
• Refresh
• Organization: 262,144 words × 16 bits
- 512 refresh cycles, 8 ms refresh interval
• High speed
- RAS-only or CAS-before-RAS refresh or self-refresh
- Self-refresh option is available for new generation device
only. Contact Alliance for more information.
• Read-modify-write
- 30/35/50 ns RAS access time
- 16/18/25 ns column address access time
- 7/10/10/10 ns CAS access time
• Low power consumption
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil, 40-pin SOJ
- Active: 500 mW max (AS4C256K16E0-25)
- Standby: 3.6 mW max, CMOS I/O (AS4C256K16E0-25)
• EDO page mode
- 400 mil, 40/44-pin TSOP II
• 5V power supply
• Latch-up current > 200 mA
Pin arrangement
Pin designation
Pin(s)
A0 to A8
RAS
Description
TSOP II
44
SOJ
VCC
I/O0
I/O1
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
I/O15
I/O14
I/O13
I/O12
GND
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
Address inputs
Row address strobe
43
42
41
40
39
38
37
36
35
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
I/O0 to I/O15 Input/output
OE
Output enable
UCAS
LCAS
WE
Column address strobe, upper byte
Column address strobe, lower byte
Read/write control
NC
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
NC
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
WE
RAS
NC
A0
A1
A2
A3
Vcc
LCAS
UCAS
OE
A8
A7
A6
A5
A4
GND
VCC
GND
Power (5V ± 0.5V)
A6
A5
A4
GND
Ground
Selection guide
Symbol
AS4C256K16E0-30
AS4C256K16E0-35
AS4C256K16E0-50
Unit
ns
tRAC
tCAA
tCAC
tOEA
tRC
30
16
35
18
50
25
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
ns
10
10
10
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum EDO page mode cycle time
Maximum operating current
10
10
10
ns
65
70
85
ns
tPC
12
14
25
ns
ICC1
ICC2
180
2.0
160
2.0
140
2.0
mA
mA
Maximum CMOS standby current
Shaded areas contain advance information.
4/11/01; v.1.1
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Copyright © Alliance Semiconductor. All rights reserved.
AS4C256K16E0
®
Functional description
The AS4C256K16E0 is a high performance 4 megabit CMOS Dynamic Random Access Memory (DRAM) organized as 262,144 words by 16
bits. The AS4C256K16E0 is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels.
The AS4C256K16E0 features a high speed page mode operation in which high speed read, write and read-write are performed on any of the
512 × 16 bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease
the system level timing constraints associated with multiplexed addressing. Very fast CAS to output access time eases system design.
Refresh on the 512 address combinations of A0 to A8 during an 8 ms period is accomplished by performing any of the following:
• RAS-only refresh cycles
• Hidden refresh cycles
• CAS-before-RAS refresh cycles
• Normal read or write cycles
• Self-refresh cycles*
The AS4C256K16E0 is available in standard 40-pin plastic SOJ and 40/44-pin TSOP II packages compatible with widely available automated
testing and insertion equipment. System level features include single power supply of 5V ± 0.5V tolerance and direct interface with TTL logic
families.
Logic block diagram
VCC
DATA
I/O
BUFFER
COLUMN DECODER
SENSE AMP
I/O0 to I/O15
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
512×512×16
ARRAY
RAS CLOCK
GENERATOR
RAS
(4,194,304)
CAS CLOCK
GENERATOR
UCAS
LCAS
SUBSTRATE
BIAS
GENERATOR
WE CLOCK
GENERATOR
WE
Recommended operating conditions
(Ta = 0°C to +70°C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
0.0
–
Max
5.5
Unit
V
Supply voltage
Input voltage
GND
VIH
0.0
0.0
V
2.4
VCC + 1
0.8
V
VIL
–1.0
–
V
*Self-refresh option is available for new generation device only. Contact Alliance for more information.
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AS4C256K16E0
®
Absolute maximum ratings
Parameter
Symbol
Vin
Min
-1.0
-1.0
-1.0
0
Max
+7.0
+7.0
+7.0
+70
+150
260 × 10
1
Unit
V
Input voltage
Output voltage
Vout
V
Power supply voltage
Operating temperature
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
VCC
V
TOPR
TSTG
°C
-55
–
°C
oC × sec
TSOLDER
PD
–
W
Short circuit output current
Latch-up current
Iout
–
50
mA
mA
200
–
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
DC electrical characteristics
-30
-35
-50
Parameter
Symbol Test conditions
Min Max Min Max Min Max Unit Note
Input leakage
current
0V ≤ Vin ≤ +5.5V
pins not under test = 0V
IIL
-10
-10
–
10
10
-10
-10
–
10
10
-10
-10
–
10 µA
10 µA
140 mA
2.0 mA
Output leakage
current
DOUT disabled,
0V ≤ Vout ≤ +5.5V
IOL
Operating power
supply current
RAS, UCAS, LCAS, address cycling;
tRC=min
ICC1
180
2.0
160
2.0
1,2
TTL standby power
supply current
ICC2
RAS = UCAS = LCAS = VIH
–
–
–
Average power
supply current,
RAS refresh mode
RAS cycling,
UCAS = LCAS = VIH,
tRC = min
ICC3
ICC4
ICC5
ICC6
–
–
–
–
200
190
1.0
–
–
–
–
190
180
1.0
–
–
–
–
140 mA
70 mA
1.0 mA
140 mA
1
EDO page mode
average power
supply current
RAS=UCAS=LCAS=VIL,
address cycling: tSC = min
1,2
CMOS standby
power supply
current
RAS=UCAS=LCAS= VCC - 0.2V
CAS-before-RAS
refresh power
supply current
RAS, UCAS, LCAS, cycling;
tRC = min
200
190
1
VOH
VOL
IOUT = -5.0 mA
IOUT = 4.2 mA
2.4
–
–
2.4
–
–
2.4
–
–
V
V
Output Voltage
0.4
0.4
0.4
RAS = UCAS = LCAS=VIL,
WE = OE = A0-A8 = VCC-0.2V,
DQ0-DQ15 = VCC-0.2V,
0.2V are open
Self refresh
current
ICC7
–
2.0
–
2.0
–
2.0 mA
Shaded areas contain advance information.
4/11/01; v.1.1
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AS4C256K16E0
®
AC parameters common to all waveforms
-30
-35
-50
Std
Symbol
Parameter
Min
65
25
30
5
Max
–
Min
70
25
35
6
Max
–
Min
85
25
50
10
15
15
10
50
5
Max Unit
Notes
tRC
Random read or write cycle time
RAS precharge time
–
–
ns
ns
tRP
–
–
tRAS
tCAS
tRCD
tRAD
tRSH(R)
tCSH
tCRP
tASR
tRAH
tT
RAS pulse width
75K
–
75K
–
75K ns
CAS pulse width
–
35
25
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time (read cycle)
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
15
10
10
30
5
20
14
–
16
11
10
35
5
24
17
–
6
7
–
–
–
–
–
–
0
–
0
–
0
–
5
–
6
–
9
–
1.5
–
50
8
1.5
–
50
8
3
50
8
4,5
3
tREF
–
tCLZ
CAS to output in low Z
0
–
0
–
3
–
8
Shaded areas contain advance information.
Read cycle
-30
-35
-50
Std
Symbol
Parameter
Min
–
Max
30
10
16
–
Min
–
Max
35
10
18
–
Min
–
Max
50
10
25
–
Unit Notes
tRAC
Access time from RAS
ns
6
tCAC
Access time from CAS
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
6,13
7,13
tAA
Access time from address
Column add hold from RAS
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
Column address to RAS Lead time
CAS precharge time
–
–
–
tAR(R)
tRCS
26
0
28
0
30
0
–
–
–
tRCH
0
–
0
–
0
–
9
9
0
–
0
–
0
–
tRRH
tRAL
16
3
–
18
4
–
25
5
–
tCPN
tOFF
–
–
–
Output buffer turn-off time
0
8
0
8
0
8
8,10
Shaded areas contain advance information.
4/11/01; v.1.1
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AS4C256K16E0
®
Write cycle
-30
-35
-50
Std
Symbol
Parameter
Min
0
Max
Min
0
Max
–
Min
0
Max Unit
Notes
tASC
Column address setup time
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCAH
tAWR
tWCS
tWCH
tWCR
tWP
Column address hold time
Column address hold time to RAS
Write command setup time
Write command hold time
Write command hold time to RAS
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
5
5
–
9
26
0
28
0
–
30
0
–
11
11
5
5
–
9
26
5
28
5
–
30
9
–
tRWL
tCWL
tDS
10
10
0
11
11
0
–
12
12
0
–
–
12
12
tDH
Data-in hold time
5
5
–
9
tDHR
Data-in hold time to RAS
26
28
–
30
Shaded areas contain advance information.
Read-modify-write cycle
-30
-35
-50
Std
Symbol
Parameter
Min
100
50
Max
–
Min
105
54
Max
–
Min
120
60
Max Unit
Notes
tRWC
Read-write cycle time
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tRWD
RAS to WE delay time
CAS to WE delay time
Column address to WE delay time
CAS to RAS hold time (write)
CAS pulse width (write)
–
–
11
11
11
tCWD
26
–
28
–
30
tAWD
32
–
35
–
40
tRSH(W)
tCAS(W)
10
–
10
–
12
15
–
15
–
15
Shaded areas contain advance information.
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AS4C256K16E0
®
EDO page mode cycle
-30
-35
-50
Std
Symbol
Parameter
Min
12
–
Max
–
Min
14
–
Max
–
Min
25
–
Max Unit
ns
23 ns
Notes
14
tPC
Read or write cycle time
Access time from CAS precharge
CAS precharge time
–
tCAP
19
–
21
–
13
tCP
3
4
5
–
–
–
ns
ns
ns
tPCM
tCRW
tRASP
EDO page mode RMW cycle
Page mode CAS pulse width (RMW)
RAS pulse width
56
44
30
–
58
46
35
–
60
50
50
–
–
75K
75K
75K ns
Shaded areas contain advance information.
Refresh cycle
-30
-35
-50
Std
Symbol
Parameter
Min
Max
–
Min
10
8
Max
–
Min
10
10
0
Max Unit
Notes
tCSR
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
10
7
–
–
–
ns
ns
ns
3
3
tCHR
–
–
tRPC
0
–
0
–
CAS precharge time
(CAS-before-RAS counter test)
tCPT
8
–
8
–
8
–
ns
Shaded areas contain advance information.
Output enable
-30
-35
-50
Min Max Unit
Std
Symbol
tROH
tOEA
Parameter
Min
5
Max
–
Min
5
Max
–
Notes
RAS hold time referenced to OE
OE access time
5
–
8
–
8
–
ns
–
10
–
–
10
–
10 ns
tOED
OE to data delay
5
5
–
8
–
ns
ns
ns
tOEZ
Output buffer turnoff delay from OE
OE command hold time
–
8
–
8
8
tOEH
8
–
8
–
Shaded areas contain advance information.
Self refresh cycle
-30
-35
-50
Std
Symbol
Parameter
Min
Max
–
Min
Max
–
Min
Max Unit
Notes
RAS pulse width
(CBR self refresh)
tRASS
100K
100K
85
100K
85
–
–
–
ns
ns
ns
RAS precharge time
(CBR self refresh)
tRPS
85
30
–
–
–
–
CAS hold time
(CBR self refresh)
tCHS
30
30
Shaded areas contain advance information.
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AS4C256K16E0
®
Notes
1
2
3
I
, I , I , and I
depend on cycle rate.
CC6
CC1 CC3 CC4
I
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume t = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, V (min) ≥ GND and V (max)
T
IL
IH
≤ V
.
CC
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
IH
IL
IH
IL
Operation within the t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
is greater than the
RCD
RAC
RCD
RCD
specified t
(max) limit, then access time is controlled exclusively by t
.
CAC
RCD
7
Operation within the t
(max) limit insures that t
(max) can be met. t (max) is specified as a reference point only. If t
RAD
is greater than the
RAD
RAC
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
11
t
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.
OFF
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ t
AWD WS
WCS WCH RWD CWD
(min) and t ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If t
≥ t
WH
WH
RWD
(min), tCWD ≥ t
(min) and tAWD ≥ t (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.
RWD
CWD
AWD
If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t or t or t
.
CAP
CAA
CAC
14
t
ASC ≥ t to achieve t (min) and t
(max) values.
CP
PC
CAP
15 These parameters are sampled and not 100% tested.
Key to switching waveform
Undefined/don’t care
Rising input
Falling input
Read cycle waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tASC
tRCS
tCAH
tCRP
tCAS
UCAS,
tAR
LCAS
tRAD
tRAL
tASR
tRAH
Row Address
Address
Col Address
tRRH
tRCH
WE
OE
tROH
tOEZ
tRAC
tAA
tOFF
tOEA
tCAC
tCLZ
Data Out
I/O
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AS4C256K16E0
®
Upper byte read cycle waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCAS
tCSH
tCRP
tCRP
UCAS
tCRP
LCAS
tRAH
tRAD
tRAL
tASC
tASR
tCAH
Row
Column
Address
tRCH
tRRH
tRCS
WE
OE
tROH
tOEA
tRAC
tOEZ
tAA
tCAC
tCLZ
tOFF
Upper I/O
Lower I/O
Data Out
Lower byte read cycle waveform
tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
LCAS
tCRP
UCAS
tRAH
tASC
tRAD
tRAL
tASR
tCAH
Row
Column
Address
WE
tRCH
tRCS
tRRH
tROH
OE
Upper I/O
tOEA
tRAC
tOEZ
tAA
tCAC
tOFF
tCLZ
Data Out
Lower I/O
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AS4C256K16E0
®
Early write cycle waveform
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
UCAS,
tAWR
LCAS
tRAD
tRAL
tASC
tASR
tRAH
tCAH
Row Address
Col Address
Address
tWCR
tCWL
tRWL
tWP
tWCS
tWCH
WE
OE
tDHR
tDS
tDH
Data In
I/O
Upper byte early write cycle waveform
tRC
tRAS
tRP
RAS
tAWR
tASR
tRAH
tRAD
tRAL
Row Address
Column Address
Address
tCAH
tRSH
tASC
tRCD
tCSH
tCAS
tCRP
tCRP
tCRP
UCAS
LCAS
tRPC
tCWL
tRWL
tWP
tWCH
tWCS
tWCR
WE
OE
tDHR
tDS
tDH
Data In
Upper I/O
Lower I/O
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AS4C256K16E0
®
Lower byte early write cycle waveform
tRC
tRAS
tRP
RAS
tAWR
tRAD
tRAL
tASR
tRAH
Address
UCAS
Row Address
tCRP
Column Address
tRPC
tASC
tCSH
tCAH
tRCD
tCAS
tRSH
tCRP
tCRP
LCAS
tWCR
tRWL
tCWL
tWCH
tWCS
tWP
WE
OE
Upper I/O
tDHR
tDS
tDH
Data In
Lower I/O
Write cycle waveform
(OE controlled)
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
UCAS,
LCAS
tRAL
tAWR
tASC
tRAD
tASR
Row Address
tRAH
tCAH
Col Address
tWCR
Address
tRWL
tCWL
tWP
WE
OE
tOEH
tDHR
tOED
tDS
tDH
Data In
I/O
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AS4C256K16E0
®
Upper byte write cycle waveform
(OE controlled)
tRC
tRAS
tRP
RAS
tRAD
tRAL
tAWR
tASR
tRAH
Row Address
Column Address
tCSH
Address
tRCD
tRSH
tCAH
tCAS
tCRP
tASC
tCRP
UCAS
LCAS
tCRP
tRPC
tCWL
tRWL
tWP
WE
OE
tOEH
tDS
tDH
Upper I/O
Lower I/O
Data In
tOED
Lower byte write cycle waveform
(OE controlled)
tRC
tRAS
tRP
RAS
tRAD
tASR
tAWR
tRAH
tRAL
Address
Row Address
Column Address
tCAH
tCAS
tRCD
tCSH
tACS
tCRP
tRSH
tCRP
LCAS
UCAS
tCRP
tRPC
tCWL
tRWL
tWP
WE
tOEH
OE
Upper I/O
tDH
tDS
Lower I/O
Data In
4/11/01; v.1.1
Alliance Semiconductor
11 of 24
AS4C256K16E0
®
Read-modify-write cycle waveform
tRWC
tRAS
tRP
RAS
tCAS
tRSH
tCRP
tRCD
tCSH
UCAS,
LCAS
tAR
tRAL
tRAD
tASC
tRAH
tCAH
tASR
Row Address
Col Address
Address
tRWD
tAWD
tRWL
tCWL
tWP
tRCS
tCWD
tOED
WE
OE
tOEA
tOEZ
tRAC
tAA
tCAC
tCLZ
tDS
tDH
Data Out
Data In
I/O
4/11/01; v.1.1
Alliance Semiconductor
12 of 24
AS4C256K16E0
®
Upper byte read-modify-write cycle waveform
tRWC
tRAS
tRP
RAS
tCSH
tRCD
tCAS
tRSH
tCRP
tCRP
UCAS
LCAS
tCRP
tRAD
tRAH
tRPC
tACS
tASR
tRAL
tCAH
Column Address
tRWD
Address
Row
tCWL
tRWL
tWP
tAWD
tCWD
tOEA
tRCS
WE
OE
tDS
tOED
Upper Input
tCLZ
tCAC
Data In
tAA
tOEZ
tRAC
Upper Output
Data Out
Data Out
tOED
Lower Input
Lower Output
4/11/01; v.1.1
Alliance Semiconductor
13 of 24
AS4C256K16E0
®
Lower byte read-modify-write cycle waveform
tRWC
tRAS
tRP
RAS
tRPC
tCRP
UCAS
tCSH
tCAS
tRCD
tCRP
tRSH
tCRP
LCAS
tRAD
tRAL
tCAH
tASR
tACS
tRAH
Row
Column Address
Address
tCWL
tRWL
tRWD
tAWD
tRCS
tCWD
tWP
WE
OE
tOEA
Upper Input
Upper Output
Data Out
tDS
tOED
Lower Input
tRAC
Data In
tAA
tCAC
tOEZ
tCLZ
Lower Output
Data Out
4/11/01; v.1.1
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AS4C256K16E0
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EDO page mode read cycle waveform
tRASP
tRP
RAS
tCSH
tRSH
tPC
tCRP
tRCD
tCAS
tCP
UCAS,
LCAS
tAR
tCAH
tRAD
tRAH
Row
tRAL
t
tASR
ASC
Col Address
tRCS
Col Address
tRCS
Address
Col Address
tRRH
tRCH
tRCH
tOEA
WE
OE
tOEA
tRAC
tCAP
tCLZ
tCAC
tAA
t
CAC
Data Out
Data Out
I/O
EDO page mode byte read cycle waveform
tRP
tRASP
RAS
tCSH
tRSH
tCAS
tCRP
tCRP
tCAS
tRCD
UCAS
LCAS
tCP
tPC
tPC
tCAS
tCRP
tRPC
tCP
tRAL
tCAH
tRAH
tRAD
tCAH
tASC
tCAH
Column 2
tASR
tASC
tASC
Column n
tRCS
Row
Column 1
Address
tRCS
tRCS
tRCH
tRCH
WE
OE
tOEA
tOEA
tOEA
tCAC
tCLZ
tAA
tOFF
tOEZ
tCAP
Data Out 2
Lower I/O
Upper I/O
tAA
tRAC
tCAC
tCLZ
tAA
tCAP
tOFF
tOEZ
tOFF
tOEZ
tCAC
tCLZ
Data Out 1
Data Out n
4/11/01; v.1.1
Alliance Semiconductor
15 of 24
AS4C256K16E0
®
EDO page mode early write cycle waveform
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCSH
tCAH
tRSH
tASC
tWCS
tCAS
tCP
UCAS,
LCAS
tRAL
tAR
tASR
tRAD
Row address
Address
Col address
Col Address
Col Address
tCWL
tWP
tWCH
tOEH
WE
OE
tHDR
tDS
tDH
I/O
Data In
Data In
Data In
EDO page mode byte early write cycle waveform
tRASP
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tCRP
tRCD
tCAS
UCAS
LCAS
tCP
tCP
tPC
tPC
tCAS
tCRP
tRPC
tRAD
tRAH
tRAL
tCAH
tASC
Column n
tCAH
tCAH
tASC
Column 2
tASR
tASC
Column 1
Address
Row
tRWL
tWCH
tWP
tWCH
tWCH
tWCS
tWP
tWCS
tCWL
tWCS
tWP
tCWL
tCWL
WE
OE
tDS
tDH
Data In 2
Lower I/O
Upper I/O
tDH
Data In n
tDS
tDH
Data In 1
tDS
4/11/01; v.1.1
Alliance Semiconductor
16 of 24
AS4C256K16E0
®
EDO page mode read-modify-write cycle waveform
tRASP
tRP
RAS
tPCM
tCAS
tCSH
tRCD
tCP
tCRP
UCAS,
LCAS
tRAD
tRAH
tRAL
tCAH
tASR
tCAH
tCAH
Row Ad
tRCS
Col Ad
tRWD
Col Ad
tCWL
Col Address
Address
tRWL
tCWL
tCWD
tAWD
tCWD
tCWD
tAWD
tWP
WE
OE
tOEA
tOEZ
tOED
tOEA
tAA
tDH
tRAC
tCLZ
tCAC
tCAP
tCLZ
tCAC
tDS
tCLZ
tCAC
tDS
Data In
Data Out
Data In
Data Out
Data In
I/O
Data Out
CAS-before-RAS refresh cycle waveform
(WE = VIH )
tRC
tRP
tRAS
RAS
tRPC
tCPN
tCSR
tCHR
UCAS,
LCAS
tOFF
I/O
RAS only refresh cycle waveform
(WE = OE = VIH or VIL)
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS,
LCAS
tARS
tRAH
Address
Row Address
4/11/01; v.1.1
Alliance Semiconductor
17 of 24
AS4C256K16E0
®
EDO page mode byte read-modify-write cycle
tRASP
tRP
RAS
tCSH
tRCD
tRSH
tCAS
tCRP
tCRP
tCAS
UCAS
LCAS
tPCM
tCAS
tCP
tCP
tRAL
tCAH
tAWD
tASC
tRAD
tRAH
tASR
tCAH
tCAH
tAWD
tASC
tASC
C 1
Address
C n
R
C 2
tRWL
tAWD
tCWD
tRWD
tRCS
tCWD
tCWD
tCWL
tCWL
tCWL
tWP
tWP
tWP
WE
OE
tOEA
tOEA
tOEA
tDH
tDH
tOED
tDS
tOED
tDS
Upper Input
Data In 1
Data In n
tCAP
tRAC
tAA
tCAC
tAA
tCAC
tOEZ
tOEZ
tCLZ
tCLZ
Upper Output
Lower Input
tOED
Data Out n
Data Out 1
tDH
Data In 2
tDS
tOEZ
tAA
tCAC
tCLZ
Lower Output
Data Out 2
4/11/01; v.1.1
Alliance Semiconductor
18 of 24
AS4C256K16E0
®
Hidden refresh cycle (read) waveform
tRC
tRC
tRAS
tPR
tRAS
tPR
RAS
CAS
tCRP
tCHR
tRCD
tRSH
tCRP
tAR
tRAD
tRAH
tASC
Col Address
tASR
Row
Address
tRCS
tRRH
WE
OE
tOEA
tRAC
tAA
tCAC
tCLZ
tOFF
tOEZ
Data Out
I/O
Hidden refresh cycle (write) waveform
tRC
tRAS
tRP
RAS
tCRP
tRCD
tRSH
UCAS,
LCAS
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Row Address
Col Address
tRWL
Address
WE
tWCR
tWP
tWCS
tWCH
tDS
tDHR
Data In
tDH
I/O
OE
4/11/01; v.1.1
Alliance Semiconductor
19 of 24
AS4C256K16E0
®
CAS-before-RAS refresh counter test cycle waveform
tRAS
tRSH
tRP
RAS
tCPT
tCSR
tCAS
tCHR
UCAS,
LCAS
tRAL
tCAH
Address
Col Address
tAA
tCAC
tCLZ
tOFF
I/O
WE
OE
Data Out
tRRH
tRCH
tRCS
tOEA
t
ROH
tRWL
tCWL
tWP
tWCH
tWCS
WE
tDH
tDS
I/O
OE
Data In
tRCS
tWP
tCWD
tAWD
tCWL
WE
OE
tOEA
tOED
t AA
tCLZ
tDH
tOEZ
tCAC
Data Out
tDS
Data In
I/O
4/11/01; v.1.1
Alliance Semiconductor
20 of 24
AS4C256K16E0
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CAS-before-RAS self refresh cycle
tRP
tRASS
tRPS
RAS
tRPC
tCP
tRPC
tCSR
tCHS
UCAS,
LCAS
tCEZ
DQ
Typical DC and AC characteristics
Normalized access time tRAC
vs. supply voltage VCC
1.5
Normalized access time tRAC
vs. ambient temperature Ta
Typical access time tRAC
vs. load capacitance CL
1.5
100
1.4
1.4
1.3
1.2
1.1
1.0
0.9
0.8
90
80
70
60
50
40
30
Ta = 25°C
1.3
1.2
1.1
1.0
0.9
0.8
4.0
4.5
5.0
5.5
–55
–10
35
80
50
100
150
200
250
6.0
125
Supply voltage (V)
Ambient temperature (°C)
Load capacitance (pF)
Typical supply current ICC
vs. supply voltage VCC
Typical supply current ICC
vs. ambient temperature Ta
Typical power-on current IPO
vs. cycle rate 1/tRC
70
60
50
40
30
20
10
70
60
50
40
30
20
10
0.0
35
30
25
20
15
10
5
0.0
4.0
0.0
4.5
5.0
5.5
–55
–10
35
80
2
4
6
8
6.0
125
10
Supply voltage (V)
Ambient temperature (°C)
Cycle rate (MHz)
4/11/01; v.1.1
Alliance Semiconductor
21 of 24
AS4C256K16E0
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Typical refresh current ICC3
vs. supply voltage VCC
Typical refresh current ICC3
vs. Ambient temperature Ta
Typical TTL stand-by current ICC2
vs. supply voltage VCC
35
30
25
20
15
10
5
35
30
25
20
15
10
5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
4.0
0
0.0
4.5
5.0
5.5
20
40
60
4.0
4.5
5.0
5.5
6.0
6.0
80
Supply voltage (V)
Ambient temperature (°C)
Supply voltage (V)
Typical TTL stand-by current ICC2
vs. ambient temperature Ta
Typical output sink current IOL
vs. output voltage VOL
Typical output source current IOH
vs. output voltage VOH
3.5
70
70
60
50
40
30
20
10
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
60
50
40
30
20
10
0.0
0
20
40
60
0.0
0.5
1.0
1.5
0.0
1.0
2.0
3.0
80
2.0
4.0
Ambient temperature (°C)
Output voltage (V)
Output voltage (V)
Typical EDO page mode current ICC4
vs. ambient temperature Ta
35
Typical EDO page mode current ICC4
vs. supply voltage VCC
35
30
25
20
15
10
5
30
25
20
15
10
5
0.0
0.0
4.0
0
20
40
60
4.5
5.0
5.5
6.0
80
Ambient temperature (°C)
Supply voltage (V)
4/11/01; v.1.1
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AS4C256K16E0
®
Package dimensions
44-pin TSOP II
c
44 43 42 41 40 39 38 37 36 35
32 31 30 29 28 27 26 25 24 23
Min
Max
(mm)
(mm)
A
A1
A2
b
1.2
0.05
0.95
0.30
He
E
44-pin TSOP II
1.05
0.45
c
0.127 (typical)
1
2
3
4
5
6
7
8
9
10
13 14 15 16 17 18 19 20 21 22
d
18.28
10.03
11.56
18.54
10.29
11.96
d
E
He
e
0.80 (typical)
0.40 0.60
l
A2
A
l
0–5°
A1
b
e
40-pin SOJ
400 mil
D
Min
Max
0.148
-
1.115
0.032
0.020
0.013
1.035
e
A
A1
A2
B
b
c
0.128
0.025
1.105
0.026
0.015
0.007
1.020
E1 E2
40-pin SOJ
Pin 1
A1
B
c
A2
D
A
E
0.370 (typical)
E
Seating
Plane
b
E1
E2
e
0.390
0.435
0.410
0.445
0.050 (typical)
Capacitance
ƒ = 1 MHz, Ta = room temperature, VCC = 5V ± 0.5V
Parameter
Symbol
Signals
Test conditions
Vin = 0V
Max
5
Unit
pF
CIN1
CIN2
CI/O
A0 to A8
Input capacitance
I/O capacitance
RAS, UCAS, LCAS, WE, OE
I/O0 to I/O15
Vin = 0V
7
pF
Vin = Vout = 0V
7
pF
Ordering codes
Package \ Access time
30 ns
AS4C256K16E0-30JC
35 ns
AS4C256K16E0-35JC
50 ns
Plastic SOJ, 400 mil, 40-pin
TSOP II, 400 mil, 40/44-pin
AS4C256K16E0-50JC
AS4C256K16E0-50TC
Shaded areas contain advance information.
Part numbering system
AS4C
256K16E0
–XX
X
C
Package: J = SOJ
Commercial temperature range,
0°C to 70 °C
DRAM prefix
Device number
RAS access time
T = TSOP II
4/11/01; v.1.1
Alliance Semiconductor
23 of 24
AS4C256K16E0
®
4/11/01; v.1.1
Alliance Semiconductor
24 of 24
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their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
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