AS4C4M4F1 概述
5V 4M×4 CMOS DRAM (Fast Page mode) 5V 4M × 4 CMOS DRAM(快页模式)
AS4C4M4F1 数据手册
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AS4C4M4F1
®
5V 4M×4 CMOS DRAM (Fast Page mode)
Features
• Organization: 4,194,304 words × 4 bits
• High speed
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
- 300 mil, 24/26-pin TSOP
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 mV
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 908 mW max
- Standby: 5.5 mW max, CMOS I/O
• Fast page mode
• Industrial and commercial temperature available
• Refresh
- 4096 refresh cycles, 64 ms refresh interval for
AS4C4M4F0
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4F1
- RAS-only or CAS-before-RAS refresh or self-refresh
Pin arrangement
Pin designation
Pin(s)
A0 to A11
RAS
Description
SOJ
TSOP
Address inputs
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
VCC
GND
I/O3
I/O2
CAS
OE
VCC
GND
I/O3
I/O2
CAS
OE
1
2
3
4
5
6
26
25
24
23
22
21
1
2
3
4
5
6
26
25
24
23
22
21
I/O0
I/O1
WE
I/O0
I/O1
WE
CAS
RAS
RAS
*NC/A11
A9
*NC/A11
A9
WE
A10
A8
A7
A6
A5
A4
A10
8
9
10
11
12
13
A8
A7
A6
A5
A4
GND
I/O0 to I/O3
OE
8
9
10
11
12
13
19
18
17
16
15
14
19
18
17
16
15
14
A0
A1
A2
A3
VCC
A0
A1
A2
A3
VCC
VCC
GND
GND
Ground
*NC on 2K refresh version; A11 on 4K refresh version
Selection guide
AS4C4M4F0-50
AS4C4M4F1-50
AS4C4M4F0-60
AS4C4M4F1-60
Symbol
Unit
ns
Maximum RAS access time
tRAC
tCAA
tCAC
tOEA
tRC
50
25
12
13
85
25
135
1.0
60
Maximum column address access time
Maximum CAS access time
30
ns
15
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
15
ns
100
30
ns
tPC
ns
ICC1
ICC5
120
1.0
mA
mA
Maximum CMOS standby current
4/11/01; v.0.9
Alliance Semiconductor
P. 1 of 18
Copyright © Alliance Semiconductor. All rights reserved.
AS4C4M4F0
AS4C4M4F1
®
Functional description
The AS4C4M4F0 and AS4C4M4F1 are high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) devices organized as
4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high
speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for
use as main memory in PC, workstation, router and switch applications.
These devices feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The AS4C4M4F0 and AS4C4M4F1 are available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The
AS4C4M4F0 and AS4C4M4F1 operate with a single power supply of 5V 0.5V and provide TTL compatible inputs and outputs.
Logic block diagram for 4K refresh
Data
I/O
buffers
VCC
Column decoder
Sense amp
GND
I/O0 to I/O3
RAS clock
generator
RAS
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
4096 × 1024 × 4
Array
CAS clock
generator
(16,777,216)
A9
A10
A11
WE clock
generator
WE
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AS4C4M4F0
AS4C4M4F1
®
Logic block diagram for 2K refresh
Data
I/O
buffers
VCC
Column decoder
Sense amp
GND
I/O0 to I/O3
RAS clock
generator
RAS
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
2048 × 2048 × 4
Array
CAS clock
generator
(16,777,216)
A9
A10
Substrate bias
generator
WE clock
generator
WE
Recommended operating conditions
Parameter
Symbol
VCC
Min
4.5
0.0
2.4
–0.5†
0
Nominal
Max
Unit
V
5.0
0.0
–
5.5
0.0
VCC
0.8
70
Supply voltage
Input voltage
GND
VIH
V
V
VIL
–
V
Commercial
Industrial
–
Ambient operating temperature
TA
°C
-40
–
85
†
V
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
IL
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AS4C4M4F0
AS4C4M4F1
®
Absolute maximum ratings
Parameter
Symbol
Vin
Min
-1.0
-1.0
-1.0
-55
–
Max
Unit
Input voltage
+7.0
VCC + 0.5
+7.0
+150
260 × 10
1
V
Input voltage (DQs)
VDQ
V
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
VCC
V
TSTG
TSOLDER
PD
°C
oC × sec
–
W
Short circuit output current
Iout
–
50
mA
DC electrical characteristics
-50
-60
Parameter
Symbol Test conditions
0V ≤ Vin ≤ +5.5V,
Pins not under test = 0V
Min Max Min Max Unit Notes
Input leakage current
IIL
-5
-5
–
+5
+5
-5
-5
–
+5
+5
µA
µA
Output leakage current IOL
DOUT disabled, 0V ≤ Vout ≤ +5.5V
Operating power
ICC1
RAS, CAS Address cycling; tRC=min
135
120
mA
1,2
supply current
TTL standby power
ICC2
RAS = CAS ≥ VIH
–
–
2.0
–
–
2.0
mA
mA
supply current
Average power supply
RAS cycling, CAS ≥ VIH,
current, RAS refresh
mode or CBR
ICC3
120
110
1
tRC = min of RAS low after XCAS low.
Fast page mode average
power supply current
RAS = VIL, CAS,
address cycling: tHPC = min
ICC4
ICC5
–
–
130
1.0
–
–
120
1.0
mA
mA
1, 2
CMOS standby power
supply current
RAS = CAS = VCC - 0.2V
VOH
VOL
IOUT = -5.0 mA
IOUT = 4.2 mA
2.4
–
–
2.4
–
–
V
V
Output voltage
0.4
0.4
CAS before RAS refresh
current
ICC6
RAS, CAS cycling, tRC = min
–
120
0.6
–
110
0.6
mA
RAS = UCAS = LCAS ≤ 0.2V,
WE = OE ≥ VCC - 0.2V,
all other inputs at 0.2V or
Self refresh current
ICC7
–
–
mA
VCC - 0.2V
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AS4C4M4F0
AS4C4M4F1
®
AC parameters common to all waveforms
-50
-60
Symbol
tRC
Parameter
Min
80
30
50
8
Max
–
Min
100
40
60
10
15
12
10
50
5
Max
–
Unit
Notes
Random read or write cycle time
RAS precharge time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
tRP
–
–
tRAS
tCAS
tRCD
tRAD
tRSH
tCSH
tCRP
tASR
tRAH
tT
RAS pulse width
10K
10K
35
25
–
10K
10K
43
30
–
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
15
12
10
40
5
6
7
–
–
–
–
0
–
0
–
8
–
10
1
–
1
50
64
–
50
64
–
4,5
3
tREF
tCP
–
–
CAS precharge time
8
10
30
0
tRAL
tASC
tCAH
Column address to RAS lead time
Column address setup time
Column address hold time
25
0
–
–
–
–
8
10
–
Read cycle
-50
-60
Symbol Parameter
Min
–
Max
50
12
25
–
Min
–
Max
60
15
30
–
Unit
ns
Notes
6
tRAC
tCAC
tAA
Access time from RAS
Access time from CAS
–
–
ns
6,13
7,13
Access time from address
–
–
ns
tRCS
tRCH
tRRH
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
0
0
ns
0
–
0
–
ns
9
9
0
–
0
–
ns
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AS4C4M4F0
AS4C4M4F1
®
Write cycle
-50
-60
Symbol Parameter
Min
0
Max
–
Min
0
Max
–
Unit
Notes
11
tWCS
tWCH
tWP
Write command setup time
ns
ns
ns
ns
ns
ns
ns
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
10
10
10
8
–
10
10
10
10
0
–
11
–
–
tRWL
tCWL
tDS
–
–
–
–
0
–
–
12
12
tDH
Data-in hold time
8
–
10
–
Read-modify-write cycle
-50
-60
Symbol Parameter
Min
113
67
Max
–
Min
135
77
Max
–
Unit
ns
Notes
tRWC
tRWD
tCWD
tAWD
Read-write cycle time
RAS to WE delay time
–
–
ns
11
11
11
CAS to WE delay time
32
–
35
–
ns
Column address to WE delay time
42
–
47
–
ns
Refresh cycle
-50
-60
Symbol
tCSR
Parameter
Min
5
Max
–
Min
5
Max
–
Unit
ns
Notes
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
3
3
tCHR
8
–
10
0
–
ns
tRPC
0
–
–
ns
CAS precharge time
(CBR counter test)
tCPT
10
10
–
ns
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AS4C4M4F0
AS4C4M4F1
®
Fast page mode cycle
-50
-60
Symbol
tCPA
Parameter
Min
–
Max
Min
–
Max
Unit
Notes
13
Access time from CAS precharge
RAS pulse width
28
35
tRASP
tPC
50
30
10
80
12
100K
60
35
10
85
15
100K
Read-write cycle time
–
–
–
–
–
–
–
–
tCP
CAS precharge time (fast page)
Fast page mode RMW cycle
Page mode CAS pulse width (RMW)
tPCM
tCRW
Output enable
-50
-60
Symbol
tCLZ
Parameter
Min
0
Max
–
Min
0
Max
–
Unit
ns
Notes
8
CAS to output in Low Z
RAS hold time referenced to OE
OE access time
tROH
tOEA
tOED
tOEZ
8
–
10
–
–
ns
–
13
–
15
–
ns
OE to data delay
13
0
15
0
ns
Output buffer turnoff delay from OE
OE command hold time
OE to output in Low Z
Output buffer turn-off time
13
–
15
–
ns
8
tOEH
tOLZ
10
0
10
0
ns
–
–
ns
tOFF
0
13
0
15
ns
8,10
Self refresh cycle
-50
-60
Std
Symbol
Parameter
Min
100
Max
–
Min
100
Max
–
Unit
µs
Notes
RAS pulse width
(CBR self refresh)
tRASS
RAS precharge time
(CBR self refresh)
tRPS
90
8
–
–
105
10
–
–
ns
ns
CAS hold time
(CBR self refresh)
tCHS
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P. 7 of 18
AS4C4M4F0
AS4C4M4F1
®
Notes
1
2
3
I
, I , I , and I
are dependent on frequency.
CC6
CC1 CC3 CC4
I
and I
depend on output loading. Specified values are obtained with the output open.
CC4
CC1
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) ≥ GND and V
IH
T
IL
(max) ≤ V
.
CC
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
I
H
I
L
I
H
I
L
Operation within the t
specified t
(max) limit insures that t
(max) limit, then access time is controlled exclusively by t
(max) can be met. t
(max) is specified as a reference point only. If t
(max) is specified as a reference point only. If t
is greater than the
is greater than the
RCD
RAC
RCD
.
RCD
RCD
CAC
7
Operation within the t
(max) limit insures that t
(max) can be met. t
RAC RAD
RAD
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
is referenced from
OFF
OFF
rising edge of RAS or CAS, whichever occurs last.
t , t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
WCS WCH RWD CWD
11
AWD
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
WS
WH
cycle. If tRWD ≥ t
(min), t
≥ t
(min) and tAWD ≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the
RWD
CWD
CWD
AWD
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t or t or t
CAA
CAC
CPA
14
t
ASC ≥ t to achieve t (min) and t
(max) values.
CPA
CP
PC
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C4M4F0 5V devices.
AC test conditions
- Access times are measured with output reference levels of V
=
OH
2.4V and V = 0.4V,
OL
V
= 2.4V and V = 0.8V
IH
IL
- Input rise and fall times: 2 ns
+5V
+3.3V
R1 = 828Ω
R1 = 828Ω
Dout
Dout
100 pF*
R2 = 295Ω
50 pF*
R2 = 295Ω
*including scope
and jig capacitance
*including scope
and jig capacitance
GND
GND
Figure A: Equivalent output load
(AS4C4M4E0)
Figure B: Equivalent output load
(AS4LC4M4E0)
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
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AS4C4M4F0
AS4C4M4F1
®
Read waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tRCS
tCAH
tCAS
tCRP
tASC
CAS
tRAD
tRAL
tRAH
tASR
Row address
Address
Column address
tRRH
tRCH
tWEZ
WE
OE
tROH
tROH
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC
tREZ
tCLZ
Data out
DQ
tOLZ
Early write waveform
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
CAS
tRAD
tRAL
tASC
tASR
tRAH
tCAH
Row address
Column address
Address
tCWL
tRW L
tWP
tWCS
tWCH
WE
OE
tDH
Data in
tDS
DQ
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AS4C4M4F0
AS4C4M4F1
®
Write waveform
OE controlled
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CAS
tRAL
tRAD
tRAH
tASC
tASR
Row address
tCAH
Column address
Address
tRWL
tCWL
tWP
WE
OE
tOEH
tDS
tOED
tDH
Data in
DQ
Read-modify-write waveform
tRWC
tRAS
tRP
RAS
tCAS
tRSH
tCRP
tRCD
tCSH
CAS
tAR
tRAL
tRAD
tRAH
tASC
tCAH
tASR
Row address
Column address
tRWD
Address
tRWL
tAWD
tCWL
tWP
tRCS
tCWD
WE
OE
tOEA
tOED
tOEZ
tRAC
tAA
tCAC
tCLZ
tDS
tDH
Data out
Data in
DQ
tOLZ
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AS4C4M4F0
AS4C4M4F1
®
Fast page mode read waveform
tRASP
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
tCP
tPC
CAS
tAR
tRAD
tRAL
tCAH
Column
tASC
tASR
tRAH
Row
Column
tRCS
Column
tRCS
Address
tRRH
tRCH
tRCH
tOEA
WE
OE
tOEA
tRAC
tOEZ
tOFF
tCLZ
tCAP
tAA
Data out
tCAC
Data out
Data out
I/O
Fast page mode byte write waveform
tRASP
tRP
RAS
tPCM
tCAS
tCSH
tRCD
tRAD
tCP
tCRP
CAS
tRAL
tCAH
tASR
tRAH
tCAH
tCAH
Row
tRCS
Column
tRWD
Column
tCWL
Column
Address
tRWL
tCWL
tWP
tCWD
tAWD
tCWD
tCWD
tAWD
WE
OE
tOEA
tOEZ
tOED
tOEA
tAA
tDH
tRAC
tCAP
tCLZ
tCAC
tDS
tCLZ
tCAC
tDS
tCLZ
tCAC
Data in
Data out
Data in
Data out
Data in
I/O
Data out
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AS4C4M4F0
AS4C4M4F1
®
Fast page mode early write waveform
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCAH
tCSH
tASC
tWCS
tCAS
tCP
tRSH
CAS
tRAL
tAR
tASR
tRAD
Address
Row
Column
Column
Column
tCWL
tWP
tWCH
tOEH
WE
OE
tHDR
tOED
tDH
tDS
I/O
Data In
Data in
Data in
CAS before RAS refresh waveform
WE = VIH
tRC
tRP
tRAS
RAS
tRPC
tCHR
tCP
tCSR
CAS
DQ
OPEN
RAS only refresh waveform
WE = OE = VIH or VIL
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tASR
tRAH
Address
Row address
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AS4C4M4F0
AS4C4M4F1
®
Hidden refresh waveform (read)
tRC
tRC
tRAS
tRP
tRAS
tRP
RAS
tCRP
tCHR
tRCD
tRSH
tCRP
CAS
tAR
tRAD
tCAH
tRAH
tASC
Col address
tASR
Row
Address
tRCS
tRRH
WE
OE
tOEA
tRAC
tOFF
tAA
tCAC
tCLZ
tOEZ
Data out
DQ
Hidden refresh waveform (write)
tRC
tRAS
tRP
RAS
tCHR
tCRP
tRCD
tRSH
CAS
Address
WE
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Row address
Col address
tRWL
tWCR
tWP
tWCS
tWCH
tDS
tDH
tDHR
Data in
DQ
OE
4/11/01; v.0.9
Alliance Semiconductor
P. 13 of 18
AS4C4M4F0
AS4C4M4F1
®
CAS before RAS refresh counter test waveform
tRAS
tRSH
tRP
RAS
tCSR
tCHR
tCPT
tCAS
CAS
tRAL
tASC
tCAH
Col address
tAA
Address
tCAC
tCLZ
tOFF
tOEZ
DQ
WE
OE
Data out
tRRH
tRCH
tRCS
tROH
tOEA
tRWL
tCWL
tWP
tWCH
tWCS
WE
tDH
tDS
DQ
OE
Data in
tRWL
tWP
tRCS
tCWD
tAWD
tCWL
WE
OE
tOEA
tOED
t AA
tDH
tCLZ
tCAC
tOEZ
tDS
Data in
DQ
Data out
4/11/01; v.0.9
Alliance Semiconductor
P. 14 of 18
AS4C4M4F0
AS4C4M4F1
®
CAS-before-RAS self refresh cycle
tRP
tRASS
tRPS
RAS
tRPC
tCP
tRPC
tCSR
tCHS
UCAS,
LCAS
tCEZ
DQ
Typical DC and AC characteristics
Normalized access time tRAC
vs. supply voltage VCC
1.5
Normalized access time tRAC
vs. ambient temperature Ta
Typical access time tRAC
vs. load capacitance CL
1.5
100
1.4
1.4
1.3
1.2
1.1
1.0
0.9
0.8
90
80
70
60
50
40
30
Ta = 25°C
1.3
-70
1.2
1.1
1.0
0.9
0.8
-60
-50
4.0
4.5
5.0
5.5
–55
–10
35
80
50
100
150
200 250
6.0
125
Supply voltage (V)
Ambient temperature (°C)
Load capacitance (pF)
Typical supply current ICC
vs. supply voltage VCC
Typical supply current ICC
vs. ambient temperature Ta
Typical power-on current I
vs. cycle rate 1/tRC
PO
170
160
150
140
130
120
110
100
170
160
150
140
130
120
110
100
35
30
25
20
15
10
5
-50
-50
-60
-70
-60
-70
0.0
4.0
4.5
5.0
5.5
–55
–10
35
80
2
4
6
8
6.0
125
10
Supply voltage (V)
Ambient temperature (°C)
Cycle rate (MHz)
4/11/01; v.0.9
Alliance Semiconductor
P. 15 of 18
AS4C4M4F0
AS4C4M4F1
®
Typical refresh current ICC3
vs. supply voltage VCC
Typical refresh current ICC3
vs. Ambient temperature Ta
Typical TTL stand-by current ICC2
vs. supply voltage VCC
160
140
120
100
80
160
140
120
100
80
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-50
-60
-70
-50
-60
-70
60
60
40
40
20
4.0
20
0.0
4.5
5.0
5.5
20
40
60
4.0
4.5
5.0
5.5
6.0
6.0
80
Supply voltage (V)
Ambient temperature (°C)
Supply voltage (V)
Typical TTL stand-by current ICC2
vs. ambient temperature Ta
Typical output sink current IOL
vs. output voltage VOL
Typical output source current IOH
vs. output voltage VOH
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
70
60
50
40
30
20
10
0.0
70
60
50
40
30
20
10
0.0
0
20
40
60
0.0
0.5
1.0
1.5
0.0
1.0
2.0
3.0
80
2.0
4.0
Ambient temperature (°C)
Output voltage (V)
Output voltage (V)
Typical fast page mode current ICC4
vs. ambient temperature Ta
Typical fast page mode current ICC4
vs. supply voltage VCC
140
120
100
80
140
120
100
80
-50
-50
-60
-70
-60
-70
60
60
40
40
20
20
0.0
0.0
4.0
0
20
40
60
4.5
5.0
5.5
6.0
80
Ambient temperature (°C)
Supply voltage (V)
4/11/01; v.0.9
Alliance Semiconductor
P. 16 of 18
AS4C4M4F0
AS4C4M4F1
®
Capacitance 15
ƒ = 1 MHz, Ta = Room temperature
Parameter
Symbol
CIN1
Signals
Test conditions
Vin = 0V
Max
5
Unit
pF
A0 to A9
Input capacitance
DQ capacitance
CIN2
RAS, UCAS, LCAS, WE, OE
DQ0 to DQ15
Vin = 0V
7
pF
CDQ
Vin = Vout = 0V
7
pF
AS4C4M4F0 ordering information
Package \ RAS access time
50 ns
60 ns
AS4C4M4F0-50JC
AS4C4M4F0-50JI
AS4C4M4F0-60JC
AS4C4M4F0-60JI
Plastic SOJ, 300 mil, 24/26-pin
Plastic TSOP, 300 mil, 24/26-pin
5V
5V
AS4C4M4F0-50TC
AS4C4M4F0-50TI
AS4C4M4F0-60TC
AS4C4M4F0-60TI
AS4C4M4F1 ordering information
Package \ RAS access time
50 ns
60 ns
AS4C4M4F1-50JC
AS4C4M4F1-50JI
AS4C4M4F1-60JC
AS4C4M4F1-60JI
Plastic SOJ, 300 mil, 24/26-pin
Plastic TSOP, 300 mil, 24/26-pin
5V
5V
AS4C4M4F1-50TC
AS4C4M4F1-50TI
AS4C4M4F1-60TC
AS4C4M4F1-60TI
AS4C4M4F0/F1 family part numbering system
AS4
C
4M4
F0/F1
–XX
X
X
Package:
J = SOJ 300 mil, 24/26
T = TSOP 300 mil, 24/26 I=Industrial, -40°C to 85°C
Temperature range
C=Commercial, 0°C to 70 °C
DRAM
prefix
F0=4K refresh RAS access
F1=2K refresh time
C = 5V CMOS
4M×4
4/11/01; v.0.9
Alliance Semiconductor
P. 17 of 18
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in
this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and
users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or
infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to
Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the
user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
AS4C4M4F0
AS4C4M4F1
®
4/11/01; v.0.9
Alliance Semiconductor
P. 18 of 18
AS4C4M4F1 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
AS4C4M4F1-50 | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-50JC | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-50JI | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-50TC | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-50TI | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-60 | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-60JC | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-60JI | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-60TC | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 | |
AS4C4M4F1-60TI | ALSC | 5V 4M×4 CMOS DRAM (Fast Page mode) | 获取价格 |
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