AS4C64M8D2-25BIN_技术文档

AS4C64M8D2

512M – (64M x 8 bit) DDRII Synchronous DRAM (SDRAM)

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Features

(Rev. 1.0, Feb. /2014)

Overview

JEDEC Standard Compliant

JEDEC standard 1.8V I/O (SSTL_18-compatible)

Power supplies: V_DD& V_DDQ= +1.8V  0.1V

The 512Mb DDR2 SDRAM is a high-speed CMOS

Double-Data-Rate-Two (DDR2), synchronous dynamic

random - access memory (SDRAM) containing 512

Mbits in an 8-bit wide data I/Os. It is internally

configured as a quad bank DRAM, 4 banks x 16Mb

addresses x 8 I/Os.

The device is designed to comply with DDR2 DRAM

key features such as posted CAS# with additive latency,

Write latency = Read latency -1 and On Die

Termination(ODT).



Operating temperature: 0 – 95 C

°

Supports JEDEC clock jitter specification

Fully synchronous operation

Fast clock rate: 400 MHz

Differential Clock, CK & CK#

Bidirectional single/differential data strobe

4 internal banks for concurrent operation

4-bit prefetch architecture

Internal pipeline architecture

Precharge & active power down

Programmable Mode & Extended Mode registers

Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5

WRITE latency = READ latency - 1 t

Burst lengths: 4 or 8

Burst type: Sequential / Interleave

DLL enable/disable

On-die termination (ODT)

RoHS compliant

Auto Refresh and Self Refresh

8192 refresh cycles / 64ms

-Average refresh period

All of the control and address inputs are

synchronized with a pair of externally supplied

differential clocks. Inputs are latched at the cross point

of differential clocks (CK rising and CK# falling)

All I/Os are synchronized with a pair of bidirectional

strobes (DQS and DQS#) in a source synchronous

fashion. The address bus is used to convey row,

column, and bank address information in RAS #, CAS#

multiplexing style. Accesses begin with the registration

of a Bank Activate command, and then it is followed by

a Read or Write command. Read and write accesses to

the DDR2 SDRAM are 4 or 8-bit burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed

sequence.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. An

auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst sequence. A sequential and gapless data rate

is possible depending on burst length, CAS latency, and

speed grade of the device

CK

℃ ≦

7.8s @ 0

≦

℃

TC +85

℃ ＜

3.9s @ +85

≦ ℃

TC +95

60-ball 8 x 10 x 1.2mm (max) FBGA package

- All parts are ROHS Compliant



Table 1. Ordering Information

Part Number

AS4C64M8D2-25BCN

AS4C64M8D2-25BIN

Clock Frequency

400MHz

Data Rate

800Mbps/pin

Power Supply

VDD 1.8V, VDDQ 1.8V

Package

60 ball FBGA

400MHz

B: indicates 60-ball 8 x 10 x 1.2mm (max) FBGA package

C: indicates commercial temperature

I: indicates industrial temperature

N: indicates Pb and Halogen Free - ROHS Compliant

Table 2. Speed Grade Information

Speed Grade

Clock Frequency

CAS Latency

t_RCD(ns)

t_RP(ns)

12.5

DDR2-800

400 MHz

5

12.5

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Figure 1. Ball Assignment (FBGA Top View)

…

1

2

3

7

8

9

VDD

NC

VSS

VSSQ

DQS#

VDDQ

A

B

C

D

E

F

DQ6

VDDQ

DQ4

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

DM

VDDQ

DQ3

VSS

WE#

BA1

A1

DQS

VDDQ

DQ2

VSSDL

RAS#

CAS#

A2

VSSQ

DQ0

VSSQ

CK

DQ7

VDDQ

DQ5

VDDL

VDD

CK#

CS#

A0

ODT

NC

G

H

J

VDD

VSS

VDD

A3

A5

A6

A4

A7

A9

A11

A8

K

L

A12

NC

A13

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Figure 2. Block Diagram

DLL

CLOCK

BUFFER

CK

CK#

CKE

16M x 8

CELL ARRAY

(BANK #0)

CONTROL

SIGNAL

GENERATOR

CS#

RAS#

CAS#

WE#

COMMAND

DECODER

Column Decoder

A10/AP

COLUMN

COUNTER

16M x 8

CELL ARRAY

(BANK #1)

MODE

REGISTER

Column Decoder

A0~A9

A11~A13

BA0~BA1

ADDRESS

BUFFER

16M x 8

CELL ARRAY

(BANK #2)

REFRESH

COUNTER

Column Decoder

DATA

STROBE

BUFFER

DQS

DQS#

DQ

Buffer

DQ0

DQ7

16M x 8

CELL ARRAY

(BANK #3)

Column Decoder

DM

ODT

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Figure 3. State Diagram

CKEL

OCD

calibration

Initialization

Sequence

Self

Refreshing

PR

Setting

MR,

EMR(1)

EMR(2)

EMR(3)

Idle

All banks

precharged

(E)MRS

REF

Refreshing

ACT

Precharge

Power

Down

Automatic Sequence

Cammand Sequence

Activating

CKEL

Active

Power

Down

Bank

Active

R

D

RD

WR

Reading

RD

Writing

WR

CKEL = CKE LOW, enter Power Down

CKEH = CKE HIGH, exit Power Down,exit Self Refresh

ACT = Activate

RDA

WRA

WR(A) = Write (with Autoprecharge)

RD(A) = Read (with Autoprecharge)

PR(A) = Precharge (All)

Reading

With

Autoprecharge

PR, PRA

Writing

With

Autoprecharge

PR, PRA

(E)MRS = (Extended) Mode Register Set

SRF = Enter Self Refresh

Precharging

REF = Refresh

Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the

commands to control them, not all details. In particular situations involving more than one bank,

enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among

other things, are not captured in full detail.

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Ball Descriptions

Table 3. Ball Descriptions

Symbol

Type

Description

CK, CK#

Input

Differential Clock:

CK, CK# are driven by the system clock. All SDRAM input signals are sampled on the

crossing of positive edge of CK and negative edge of CK#. Output (Read) data is

referenced to the crossings of CK and CK# (both directions of crossing).

CKE

Input

Clock Enable:

CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes LOW

synchronously with clock, the internal clock is suspended from the next clock cycle

and the state of output and burst address is frozen as long as the CKE remains LOW.

When all banks are in the idle state, deactivating the clock controls the entry to the

Power Down and Self Refresh modes.

BA0-BA1

A0-A13

Input

Bank Address:

BA0-BA1 defines to which bank the BankActivate, Read, Write, or BankPrecharge

command is being applied.

Address Inputs:

A0-A13 are sampled during the BankActivate command (row address A0-A13) and

Read/Write command (column address A0-A9 with A10 defining Auto Precharge). A13

row address use on x8 components only.

CS#

Input

Chip Select:

CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder.

All commands are masked when CS# is sampled HIGH. CS# provides for external

bank selection on systems with multiple banks. It is considered part of the command

code.

RAS#

Row Address Strobe:

The RAS# signal defines the operation commands in conjunction with the CAS# and

WE# signals and is latched at the crossing of positive edges of CK and negative edge

of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"

either the BankActivate command or the Precharge command is selected by the WE#

signal. When the WE# is asserted "HIGH," the BankActivate command is selected and

the bank designated by BA is turned on to the active state. When the WE# is asserted

"LOW," the Precharge command is selected and the bank designated by BA is

switched to the idle state after the precharge operation.

CAS#

WE#

Input

Column Address Strobe:

The CAS# signal defines the operation commands in conjunction with the RAS# and

WE# signals and is latched at the crossing of positive edges of CK and negative edge

of CK#. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is

started by asserting CAS# "LOW." Then, the Read or Write command is selected by

asserting WE# “HIGH " or “LOW".

Write Enable:

The WE# signal defines the operation commands in conjunction with the RAS# and

CAS# signals and is latched at the crossing of positive edges of CK and negative edge

of CK#. The WE# input is used to select the BankActivate or Precharge command and

Read or Write command.

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Bidirectional Data Strobe:

DQS,

Input /

Output

Output with read data, input with write data for source synchronous operation. Edge-

aligned with read data, center-aligned with write data. DQS# is only used when

differential data strobe mode is enabled via the LOAD MODE command.

DQS#

Data Input Mask:

DM

Input

DM is an input mask signal for write data. Input data is masked when DM is sampled

HIGH along with that input data during a WRITE access.

DQ0 – DQ7 Input /

Data I/O:

Output

Bi-directional data bus.

On Die Termination:

ODT

Input

ODT enables internal termination resistance. It is applied to each DQ, DQS/DQS# and

DM signal. The ODT pin is ignored if the EMR (1) is programmed to disable ODT.

V_DD

V_SS

Supply

-

Power Supply: +1.8V 0.1V

Ground

V_DDL

V_SSDL

V_DDQ

V_SSQ

V_REF

NC

DLL Power Supply: +1.8V 0.1V

DLL Ground

DQ Power: +1.8V 0.1V.

DQ Ground

Reference Voltage for Inputs: +0.5*V_DDQ

No Connect: These pins should be left unconnected.

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Operation Mode

Table 4 shows the truth table for the operation commands.

Table 4. Truth Table (Note (1), (2))

Command

BankActivate

State CKE_n-1CKE_nDM BA0-2 A10 A0-9, 11-13 CS# RAS# CAS# WE#

Idle⁽³⁾

Any

H

X

V

X

V

Row address

L

H

L

H

L

Single Bank Precharge

All Banks Precharge

Write

L

H

L

X

Any

L

Active⁽³⁾

H

Column

address

Write with AutoPrecharge

H

L

(A0 – A9)

Active⁽³⁾

H

X

V

L

H

L

H

Column

address

Read

Read and Autoprecharge

H

(A0 – A9)

(Extended) Mode Register Set

No-Operation

Idle

Any

H

X

H

L

X

V

X

OP code

L

H

X

L

H

X

L

H

L

X

Burst Stop

Active⁽⁴⁾

L

Device Deselect

Refresh

Any

H

L

X

H

X

H

X

H

X

H

X

Idle

SelfRefresh Entry

Idle

L

H

L

X

H

X

H

X

H

X

H

X

H

X

H

X

SelfRefresh Exit

Idle

Any

L

H

L

H

L

X

H

L

Power Down Mode Entry

Power Down Mode Exit

H

L

H

Data Input Mask Disable

Data Input Mask Enable(5)

Active

H

X

L

X

H

NOTE 1: V=Valid data, X=Don't Care, L=Low level, H=High level

NOTE 2: CKEn signal is input level when commands are provided.

NOTE 3: CKEn_-1signal is input level one clock cycle before the commands are provided.

NOTE 4: These are states of bank designated by BA signal.

NOTE 5: Device state is 4, and 8 burst operation.

NOTE 6: LDM and UDM can be enabled respectively.

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Functional Description

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and

continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an

Active command, which is then followed by a Read or Write command. The address bits registered coincident with

the active command are used to select the bank and row to be accessed (BA0-BA1 select the bank; A0-A13 select

the row). The address bits registered coincident with the Read or Write command are used to select the starting

column location for the burst access and to determine if the auto precharge command is to be issued.

Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information

covering device initialization, register definition, command descriptions, and device operation.

 Power-up and Initialization

DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation.

The following sequence is required for POWER UP and Initialization.

1. Apply power and attempt to maintain CKE below 0.2*V_DDQand ODT ^*1at a low state (all other inputs may be

undefined.) The V_DDvoltage ramp time must be no greater than 200ms from when V_DDramps from 300mV to

V_DDmin; and during the V_DDvoltage ramp, |V_DD-V_DDQ| ≦ 0.3V

-

V_DD, V_DDLand V_DDQare driven from a single power converter output, AND

V_TTis limited to 0.95 V max, AND

-

V_REFtracks V_DDQ/2.

or

-

Apply V_DDbefore or at the same time as V_DDL

Apply V_DDLbefore or at the same time as V_DDQ

Apply V_DDQbefore or at the same time as V_TT& V_REF

At least one of these two sets of conditions must be met.

.

2. Start clock and maintain stable condition.

3. For the minimum of 200s after stable power and clock (CK, CK#), then apply NOP or deselect and take CK

HIGH.

4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.

5. Issue EMRS(2) command. (To issue EMRS (2) command, provide “LOW” to BA0, “HIGH” to BA1.)

6. Issue EMRS (3) command. (To issue EMRS (3) command, provide “HIGH” to BA0 and BA1.)

7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and "LOW"

to BA1.)

8. Issue a Mode Register Set command for “DLL reset”. (To issue DLL reset command, provide "HIGH" to A8 and

"LOW" to BA0-BA1)

9. Issue precharge all command.

10.Issue 2 or more auto-refresh commands.

11.Issue a mode register set command with LOW to A8 to initialize device operation.

(i.e. to program operating parameters without resetting the DLL.)

12.At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).If OCD

calibration is not used, EMRS OCD Default command (A9=A8=A7=HIGH) followed by EMRS OCD calibration

Mode Exit command (A9=A8=A7=LOW) must be issued with other operating parameters of EMRS.

13.The DDR2 SDRAM is now ready for normal operation.

NOTE 1: To guarantee ODT off, V_REFmust be valid and a LOW level must be applied to the ODT pin.

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 Mode Register Set(MRS)

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS

latency, burst length, burst sequence, test mode, DLL reset, WR, and various vendor specific options to make

DDR2 SDRAM useful for various applications. The default value of the mode register is not defined, therefore the

mode register must be programmed during initialization for proper operation. The mode register is written by

asserting LOW on CS#, RAS#, CAS#, WE#, BA0 and BA1, while controlling the state of address pins A0 - A13.

The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode

register.The mode register set command cycle time (t_MRD) is required to complete the write operation to the mode

register. The mode register contents can be changed using the same command and clock cycle requirements

during normal operation as long as all bank are in the precharge state.The mode register is divided into various

fields depending on functionality.

- Burst Length Field (A2, A1, A0)

This field specifies the data length of column access and selects the Burst Length.

- Addressing Mode Select Field (A3)

The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential Mode and Interleave Mode

support burst length of 4 and 8.

- CAS Latency Field (A6, A5, A4)

This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The

minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the

following formula must be programmed into this field. (t_CAC(min)≦ CAS Latency X t_CK)

- Test Mode Field (A7); DLL Reset Mode Field (A8)

These two bits must be programmed to "00" in normal operation.

- Write recovery Field (A11, A10, A9)

The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. The WR register is

used by the DDR2 SDRAM during WRITE with auto precharge operation.

- Active Power down Field (A12)

PD mode enables the user to determine the active power-down mode, which determines performance versus

power savings. does not apply to precharge PD mode.

- (BA0-BA1): Bank addresses to define MRS selection.

Table 5. Mode Register Bitmap

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field

0

0^*2PD

WR

DLL TM CAS Latency BT Burst Length Mode Register

A8 DLL Reset

A7 Mode

A3

0

Burst Type

Sequential

Interleave

A2 A1 A0 BL

0

1

No

0

1

Normal

Test

0

1

0

1

4

8

Yes

1

A12 Active power down exit time Write recovery for autoprecharge^*1

0

1

Fast exit (use t_XARD

)

A11

0

A10

0

A9

0

WR(cycles)

A6 A5 A4

CAS Latency

Slow exit (use t_XARDS

)

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

0

1

2

3

Reserved

BA1 BA0

MRS Mode

0

1

0

Reserved

0

1

0

1

0

1

MR

0

1

4

3

EMR(1)

EMR(2)

EMR(3)

1

0

5

4

1

0

1

6

5

6

Reserved

1

0

1

Reserved

NOTE 1: For DDR2-667/800, WR min is determined by t_CK(avg) max and WR max is determined by t_CK(avg) min. WR [cycles]

= RU {t_WR[ns]/t_CK(avg)[ns]}, where RU stands for round up. The mode register must be programmed to this

value.This is also used with t_RPto determine t_DAL

.

NOTE 2: A13 are reserved for future use and must be set to 0 when programming the MR.

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 Extended Mode Register Set (EMRS)

-

EMR(1)

The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT

value selection and additive latency. The default value of the extended mode register is not defined, therefore the

extended mode register must be written after power-up for proper operation. The extended mode register is

written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1 and HIGH on BA0, while controlling the states of

address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to

writing into the extended mode register. The mode register set command cycle time (t_MRD) must be satisfied to

complete the write operation to the extended mode register. Mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharge

state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver. A3~A5

determine the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for OCD control,

A10 is used for DQS# disable.

-

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon

returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self

refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled

(and subsequently reset), 200 clock cycles must occur before a Read command can be issued to allow time for

the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may

result in a violation of the t_ACor t_DQSCKparameters.

Table 6. Extended Mode Register EMR (1) Bitmap

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field

0^*3Qoff 0^*3

OCD program Rtt

Rtt

DQS#

Additive Latency

D.I.C Extended Mode Register

DLL

0

1

BA1 BA0

MRS mode

A6 A2

Rtt

(NOMINAL)

0

1

0

1

0

1

MR

0

1

0

1

0

1

ODT Disable

Ω

A0

DLL Enable

Enable

EMR(1)

EMR(2)

EMR(3)

75

0

1

Ω

150

Disable

Ω

50

A9

0

A8

0

A7 OCD Calibration Program

Output Driver

Impedance Control

A1

OCD Calibration mode exit; maintain setting

Reserved

0

1

0

1

0

1

Full strength

Reserved

0

1

Reduced strength

Reserved

1

0

OCD Calibration default^*1

1

A5 A4 A3

Additive Latency

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A12

0

Qoff ^*2

1

Output buffer enabled

Output buffer disabled

2

A10

0

DQS#

1

3

Enable

4

1

Disable

5

Reserved

NOTE 1: After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.

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NOTE 2: Output disabled – DQs, DQSs, DQSs#. This feature is intended to be used during I_DDcharacterization of read

current.

NOTE 3: A11, A13 are reserved for future use and must be set to 0 when programming the MR.

-

EMR(2)

The extended mode register (2) controls refresh related features. The default value of the extended mode

register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper

operation. The extended mode register(2) is written by asserting LOW on CS#, RAS#, CAS#, WE#, HIGH on

BA1 and LOW on BA0, while controlling the states of address pins A0 ~ A13. The DDR2 SDRAM should be in all

bank precharge with CKE already HIGH prior to writing into the extended mode register (2). The mode register

set command cycle time (t_MRD) must be satisfied to complete the write operation to the extended mode register

(2). Mode register contents can be changed using the same command and clock cycle requirements during

normal operation as long as all banks are in the precharge state.

Table 7. Extended Mode Register EMR(2) Bitmap

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field

0^*1

SRF

Extended Mode Register(2)

1

0

A7

0

High Temperature Self-Refresh Rate Enable

Disable

Enable ^*2

1

NOTE 1: The rest bits in EMRS(2) are reserved for future use and all bits in EMRS(2) except A7, BA0 and BA1 must be

programmed to 0 when setting the extended mode register(2) during initialization.

NOTE 2: Due to the migration nature, user needs to ensure the DRAM part supports higher than 85℃ Tcase temperature

self-refresh entry. If the high temperature self-refresh mode is supported then controller can set the EMRS2[A7] bit

to enable the self-refresh rate in case of higher than 85℃ temperature self-refresh operation.

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-

EMR(3)

No function is defined in extended mode register(3).The default value of the extended mode register(3) is not

defined, therefore the extended mode register(3) must be programmed during initialization for proper operation.

Table 8. Extended Mode Register EMR (3) Bitmap

BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field

0^*1

Extended Mode Register(3)

1

NOTE 1: All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming the

EMR (3).

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 ODT (On Die Termination)

On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ,

DQS/DQS#, DM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the

memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all

DRAM devices.

The ODT function is supported for ACTIVE and STANDBY modes. It is turned off and not supported in SELF

REFRESH mode.

Figure 4. Functional representation of ODT

V_DDQ

SW1

SW2

SW3

Rval1

Rval2

Rval3

DRAM

Input

Buffer

Input

Rval1

SW1

Rval2

SW2

Rval3

SW3

V_SSQ

Switch (sw1, sw2, sw3) is enabled by ODT pin.

Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR.

Termination included on all DQs, DM, DQS, DQS# pins

Table 9. ODT DC Electrical Characteristics

Parameter/Condition

Symbol

Min.

Nom.

Max.

Unit Note

Rtt effective impedance value for EMRS(A6,A2)=0,1;75Ω

Rtt effective impedance value for EMRS(A6,A2)=1,0;150Ω

Rtt effective impedance value for EMRS(A6,A2)=1,1;50Ω

Ω

%

Rtt1(eff)

Rtt2(eff)

Rtt3(eff)

60

120

40

75

150

50

-

90

180

60

6

1

2

Rtt mismatch tolerance between any pull-up/pull-down pair Rtt(mis)

-6

NOTE 1: Measurement Definition for Rtt(eff):

Apply V_IH(ac) and V_IL(ac) to test pin separately, then measure current I(V_IH(ac)) and I(V_IL(ac)) respectively.

V (ac)  V (ac)

IH

IL

Rtt(eff)=

I(V (ac))-I(V (ac))

IH

IL

NOTE 2: Measurement Definition for Rtt (mis): Measure voltage (VM) at test pin (midpoint) with no load.









2xVM

V_DDQ

Rtt(mis)=

1 100%





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 Bank activate command

The Bank Activate command is issued by holding CAS# and WE# HIGH with CS# and RAS# LOW at the rising

edge of the clock. The bank addresses BA0-BA1 are used to select the desired bank. The row addresses A0

through A13 are used to determine which row to activate in the selected bank. The Bank Activate command must

be applied before any Read or Write operation can be executed. Immediately after the bank active command, the

DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If

a R/W command is issued to a bank that has not satisfied the t_RCDmin specification, then additive latency must be

programmed into the device to delay the R/W command which is internally issued to the device. The additive

latency value must be chosen to assure t_RCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported.

Once a bank has been activated it must be precharged before another Bank Activate command can be applied to

the same bank. The bank active and precharge times are defined as t_RASand t_RP, respectively. The minimum time

interval between successive Bank Activate commands to the same bank is determined (t_RC). The minimum time

interval between Bank Active commands is t_RRD

 Read and Write access modes

After a bank has been activated, a Read or Write cycle can be executed. This is accomplished by setting RAS#

HIGH, CS# and CAS# LOW at the clock’s rising edge. WE# must also be defined at this time to determine whether

the access cycle is a Read operation (WE# HIGH) or a Write operation (WE# LOW). The DDR2 SDRAM provides a

fast column access operation. A single Read or Write Command will initiate a serial Read or Write operation on

successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length.

Any system or application incorporating random access memory products should be properly designed, tested, and

qualified to ensure proper use or access of such memory products. Disproportionate, excessive, and/or repeated

access to a particular address or addresses may result in reduction of product life.

 Posted CAS#

Posted CAS# operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2

SDRAM. In this operation, the DDR2 SDRAM allows a CAS# Read or Write command to be issued immediately

after the RAS bank activate command (or any time during the RAS# -CAS#-delay time, t_RCD, period). The command

is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is

controlled by the sum of AL and the CAS latency (CL). Therefore if a user chooses to issue a R/W command before

the t_RCDmin, then AL (greater than 0) must be written into the EMR(1). The Write Latency (WL) is always defined as

RL - 1 (Read Latency -1) where Read Latency is defined as the sum of additive latency plus CAS latency

(RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to seamless operation timing diagram

examples in Read burst and Write burst section)

 Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory

locations (Read cycle). The parameters that define how the burst mode will operate are burst sequence and burst

length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address

ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst

length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or

interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst Read or Write

operations are supported. Interruption of a burst Read or Write operation is prohibited, when burst length = 4 is

programmed. For burst interruption of a Read or Write burst when burst length = 8 is used, see the “Burst

Interruption“ section of this datasheet. A Burst Stop command is not supported on DDR2 SDRAM devices.

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Table 10. Burst Definition, Addressing Sequence of Sequential and Interleave Mode

Start Address

Burst Length

Sequential

Interleave

A2

X

0

A1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

4

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

0

1

8

 Burst read command

The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the

rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from

the start of the command to when the data from the first cell appears on the outputs is equal to the value of the

Read Latency (RL). The data strobe output (DQS) is driven LOW 1 clock cycle before valid data (DQ) is driven

onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each

subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The

RL is equal to an additive latency (AL) plus CAS Latency (CL). The CL is defined by the Mode Register Set

(MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set (1)

(EMRS (1)).

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the

setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design.

The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode,

timing relationships are measured relative to the rising or falling edges of DQS crossing at V_REF. In differential

mode, these timing relationships are measured relative to the cross point of DQS and its complement, DQS#.

This distinction in timing methods is guaranteed by design and characterization. Note that when differential data

strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to V_SSthrough a

20 Ω to 10 KΩ resistor to insure proper operation.

 Burst write operation

The Burst Write command is initiated by having CS#, CAS# and WE# LOW while holding RAS# HIGH at the

rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined

by a Read latency (RL) minus one and is equal to (AL + CL -1);and is the number of clocks of delay that are

required from the time the Write command is registered to the clock edge associated to the first DQS strobe. A

data strobe signal (DQS) should be driven LOW (preamble) one clock prior to the WL. The first data bit of the

burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The t_DQSS

specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles.

The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed,

which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored.

The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst

Write to bank precharge is the write recovery time (WR). DDR2 SDRAM pin timings are specified for either single

ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing

advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin

timings are measured is mode dependent.

In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at

the specified AC/DC levels. In differential mode, these timing relationships are measured relative to the cross

point of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and

characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin,

DQS#, must be tied externally to V_SSthrough a 20Ω to 10KΩ resistor to insure proper operation.

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 Write data mask

One Write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with

the implementation on DDR SDRAMs. It has identical timings on Write operations as the data bits, and though

used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM

is not used during read cycles.

 Precharge operation

The Precharge command is used to precharge or close a bank that has been activated. The Precharge Command

is triggered when CS#, RAS# and WE# are LOW and CAS# is HIGH at the rising edge of the clock. The

Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three

address bits A10, BA1, and BA0 are used to define which bank to precharge when the command is issued.

Table 11. Bank Selection for Precharge by address bits

A10

LOW

HIGH

BA1

LOW

HIGH

BA0

LOW

HIGH

LOW

HIGH

Precharged Bank(s)

Bank 0 only

Bank 1 only

Bank 2 only

Bank 3 only

DON’T CARE DON’T CARE

ALL Banks

 Burst read operation followed by precharge

Minimum Read to precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks. For the

earliest possible precharge, the precharge command may be issued on the rising edge which “Additive latency

(AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after

the RAS# precharge time (t_RP). A precharge command cannot be issued until t_RASis satisfied.

The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge

that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called t_RTP(Read to Precharge).

For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8

this is the time from AL + 2 clocks after the Read to the Precharge command.

 Burst Write operation followed by precharge

Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + t_WR. For write cycles, a delay

must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued.

This delay is known as a write recovery time (t_WR) referenced from the completion of the burst write to the

Precharge command. No Precharge command should be issued prior to the t_WRdelay, as DDR2 SDRAM does

not support any burst interrupt by a Precharge command. t_WRis an analog timing parameter and is not the

programmed value for t_WRin the MRS.

 Auto precharge operation

Before a new row in an active bank can be opened, the active bank must be precharged using either the

Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the DDR2

SDRAM, the CAS# timing accepts one extra address, column address A10, to allow the active bank to

automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is LOW

when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and the

bank remains active at the completion of the burst sequence. If A10 is HIGH when the Read or Write Command

is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as

normal with the exception that the active bank will begin to precharge on the rising edge which is CAS latency (CL)

clock cycles before the end of the read burst. Auto-precharge also be implemented during Write commands. The

precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write

sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or

completely hidden during burst Read cycles (dependent upon CAS latency) thus improving system performance

for random data access. The RAS# lockout circuit internally delays the Precharge operation until the array restore

operation has been completed (t_RASsatisfied) so that the auto precharge command may be issued with any Read

or Write command.

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 Burst read with auto precharge

If A10 is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2

SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read

with AP command if t_RAS(min) and t_RTPare satisfied. If t_RAS(min) is not satisfied at the edge, the start point of Auto-

Precharge operation will be delayed until t_RAS(min) is satisfied. If t_RTP(min) is not satisfied at the edge, the start

point of Auto-precharge operation will be delayed until t_RTP(min) is satisfied.

In case the internal precharge is pushed out by t_RTP, t_RPstarts at the point where the internal precharge happens

(not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-

Precharge to the next Activate command becomes AL + t_RTP+ t_RP. For BL = 8 the time from Read with Auto-

Precharge to the next Activate command is AL + 2 + t_RTP+ t_RP. Note that both parameters t_RTPand t_RPhave to be

rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after

the last 4-bit prefetch.

A new bank active (command) may be issued to the same bank if the following two conditions are satisfied

simultaneously:

(1) The RAS# precharge time (t_RP) has been satisfied from the clock at which the Auto-Precharge begins.

(2) The RAS# cycle time (t_RC) from the previous bank activation has been satisfied.

 Burst write with auto precharge

If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2

SDRAM automatically begins precharge operation after the completion of the burst write plus Write recovery time

(t_WR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the

following two conditions are satisfied.

(1) The data-in to bank activate delay time (WR + t_RP) has been satisfied.

(2) The RAS# cycle time (t_RC) from the previous bank activation has been satisfied.

Table 12. Precharge & Auto Precharge Clarification

Minimum Delay between “From

Command” to “To Command”

From Command

Read

To Command

Unit Note

t_CK1,2

Precharge (to same Bank as Read)

Precharge All

Precharge (to same Bank as Read w/AP)

Precharge All

Precharge (to same Bank as Write)

Precharge All

Precharge (to same Bank as Write w/AP)

Precharge All

AL+BL/2+max(RTP,2)-2

Read w/AP

Write

WL+BL/2+t_WR

t_CK

2

Write w/AP

Precharge

Precharge All

Precharge (to same Bank as Precharge)

Precharge All

1

Precharge

Precharge All

NOTE 1: RTP [cycles] =RU {t_RTP[ns]/t_CK(avg) [ns]}, where RU stands for round up.

NOTE 2: For a given bank, the precharge period should be counted from the latest precharge command, either

one bank precharge or precharge all, issued to that bank.The precharge period is satisfied after t_RPor t_RPall(=t_RP

for 4 bank device) depending on the latest precharge command issued to that bank.

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 Refresh command

When CS#, RAS# and CAS# are held LOW and WE# HIGH at the rising edge of the clock, the chip enters the

Refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the

Precharge time (t_RP) before the Refresh command (REF) can be applied. An address counter, internal to the

device, supplies the bank address during the refresh cycle. No control of the external address bus is required

once this cycle has started.

When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A

delay between the Refresh command (REF) and the next Activate command or subsequent Refresh command

must be greater than or equal to the Refresh cycle time (t_RFC).To allow for improved efficiency in scheduling and

switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh

commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any

Refresh command and the next Refresh command is 9 * t_REFI

.

 Self refresh operation

The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is

powered down. When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The

DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is

defined by having CS#, RAS#, CAS# and CKE# held LOW with WE# HIGH at the rising edge of the clock. ODT

must be turned off before issuing Self Refresh command, by either driving ODT pin LOW or using EMRS

command. Once the Command is registered, CKE must be held LOW to keep the device in Self Refresh mode.

The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self

Refresh. When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are

“don’t care”. For proper Self Refresh operation all power supply pins (V_DD, V_DDQ, V_DDLand V_REF) must be at valid

levels. The DRAM initiates a minimum of one refresh command internally within t_CKEperiod once it enters Self

Refresh mode. The clock is internally disabled during Self Refresh Operation to save power. The minimum time

that the DDR2 SDRAM must remain in Self Refresh mode is t_CKE. The user may change the external clock

frequency or halt the external clock one clock after Self Refresh entry is registered, however, the clock must be

restarted and stable before the device can exit Self Refresh operation.

The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to

CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least t_XSNRmust be satisfied before a

valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH

for the entire Self Refresh exit period t_XSRDfor proper operation except for Self Refresh re-entry. Upon exit from

Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting at least t_XSNRperiod and

issuing one refresh command(refresh period of t_RFC). NOP or Deselect commands must be registered on each

positive clock edge during the Self Refresh exit interval t_XSNR. ODT should be turned off during t_XSRD. The use of

Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is

raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of

one extra auto refresh command before it is put back into Self Refresh mode.

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 Power-Down

Power-down is synchronously entered when CKE is registered LOW along with NOP or Deselect command. No

read or write operation may be in progress when CKE goes LOW. These operations are any of the following: read

burst or write burst and recovery. CKE is allowed to go LOW while any of other operations such as row activation,

precharge or autoprecharge, mode register or extended mode register command time, or auto refresh is in

progress.

The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting

power-down mode for proper read operation.

If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if

power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For

Active Power-down two different power saving modes can be selected within the MRS register, address bit A12.

When A12 is set to “LOW” this mode is referred as “standard active power-down mode” and a fast power-down

exit timing defined by the t_XARDtiming parameter can be used. When A12 is set to “HIGH” this mode is referred as

a power saving “LOW power active power-down mode”. This mode takes longer to exit from the power-down

mode and the t_XARDStiming parameter has to be satisfied. Entering power-down deactivates the input and output

buffers, excluding CK, CK#, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or

slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down

mode, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR2 SDRAM, and all other

input signals are “Don’t Care”. Power-down duration is limited by 9 times t_REFIof the device.

The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect

command). A valid, executable command can be applied with power-down exit latency, t_XP, t_XARDor t_XARDS, after

CKE goes HIGH. Power-down exit latencies are defined in the AC spec table of this data sheet.

 Asynchronous CKE LOW Event

DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this datasheet. If CKE

asynchronously drops “LOW” during any valid operation DRAM is not guaranteed to preserve the contents of

array. If this event occurs, memory controller must satisfy DRAM timing specification tDelay before turning off the

clocks. Stable clocks must exist at the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-

initialized. DRAM is ready for normal operation after the initialization sequence.

 Input clock frequency change during precharge power down

DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged

power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must

be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to

change only within minimum and maximum operating frequency specified for the particular speed grade. During

input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is

changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL

must be RESET via EMRS after precharge power down exit. Depending on new clock frequency an additional

MRS command may need to be issued to appropriately set the WR, CL etc. During DLL re-lock period, ODT

must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency.

 No operation command

The No Operation Command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The

purpose of the No Operation Command (NOP) is to prevent the DDR2 SDRAM from registering any unwanted

commands between operations. A No Operation Command is registered when CS# is LOW with RAS#, CAS#,

and WE# held HIGH at the rising edge of the clock. A No Operation Command will not terminate a previous

operation that is still executing, such as a burst read or write cycle.

 Deselect command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs

when CS# is brought HIGH at the rising edge of the clock, the RAS#, CAS#, and WE# signals become don’t

cares.

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Table 13. Absolute Maximum DC Ratings

Symbol

Parameter

Rating

-1.0 ~ 2.3

-0.5 ~ 2.3

- 0.5 ~ 2.3

- 55~100

Unit Note

V_DD

Voltage on V_DDpin relative to Vss

V

1,3

1,4

1,2

V_DDQVoltage on V_DDQpin relative to Vss

V_DDLVoltage on V_DDLpin relative to Vss

V_IN, V_OUTVoltage on any pin relative to Vss

T_STGStorage temperature

C

°

NOTE1: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

devices. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

NOTE2: Storage temperature is the case temperature on the center/top side of the DRAM.

NOTE3: When V_DDand V_DDQand V_DDLare less than 500mV, Vref may be equal to or less than 300mV.

NOTE4: Voltage on any input or I/O may not exceed voltage on V_DDQ

.

Table 14. Operating Temperature Condition

Symbol

Parameter

Rating

0~85

Unit Note

Normal operating temperature

C

°

1

T_OPER

Extended operating temperature

85~95

C

1,2

NOTE1: Operating temperature is the case surface temperature on center/top of the DRAM.

NOTE2: If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh. It is required to set tREFI=3.9μs

in auto refresh mode and to set ‘1’ for EMRS (2) bit A7 in self refresh mode.

Table 15. Recommended DC Operating Conditions (SSTL_1.8)

Symbol

Parameter

Min.

1.7

Typ.

1.8

Max.

1.9

Unit Note

V_DD

Power supply voltage

V

1

5

V_DDLPower supply voltage for DLL

1.7

1.8

1.9

V_DDQPower supply voltage for I/O Buffer

1.7

1.8

1.9

1,5

V_REFInput reference voltage

0.49 x V_DDQ

0.5 x V_DDQ

0.51 x V_DDQ

mV 2,3

V_TT

Termination voltage

V_REF- 0.04

V_REF

V_REF+ 0.04

V

4

NOTE1: There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all

conditions V_DDQmust be less than or equal to V_DD.

NOTE2: The value of V_REFmay be selected by the user to provide optimum noise margin in the system. Typically the

value of V_REFis expected to be about 0.5 x V_DDQof the transmitting device and V_REFis expected to track

variations in V_DDQ

.

±

NOTE3: Peak to peak ac noise on V_REFmay not exceed 2 % V_REF(dc).

NOTE4: V_TTof transmitting device must track V_REFof receiving device.

NOTE5: V_DDQtracks with V_DD, V_DDLtracks with V_DD. AC parameters are measured with V_DD, V_DDQand V_DDLtied

together

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Table 16. Input logic level (

V_DD= 1.8V  0.1V, T_OPER= 0~95 C)

-25/3

Unit

Symbol

Parameter

Min.

V_REF+ 0.125

- 0.3

Max.

VIH (DC)

VIL (DC)

VIH (AC)

VIL (AC)

VID (AC)

VIX (AC)

DC Input logic High Voltage

DC Input Low Voltage

V_DDQ+ 0.3

V_REF- 0.125

V_DDQ+ V_peak

V_REF- 0.2

V_DDQ

V

AC Input High Voltage

V_REF+ 0.2

V_SSQ- V_peak

0.5

AC Input Low Voltage

AC Differential Voltage

AC Differential cross point Voltage

0.5 x V_DDQ- 0.175 0.5 x V_DDQ+ 0.175

NOTE1: Refer to Overshoot/undershoot specification for V_peakvalue: maximum peak amplitude allowed for

overshoot and undershoot.

Table 17. AC Input test conditions

(V_DD= 1.8V  0.1V, T_OPER= 0~95 C)

Value

Symbol

Parameter

Input reference voltage

Unit Note

V_REF

0.5 x V_DDQ

1.0

V

1

V_SWING(max)Input signal maximum peak to peak swing

Slew Rate Input signal minimum slew rate

1.0

V/ns 2, 3

NOTE1: Input waveform timing is referenced to the input signal crossing through the V_IH/_IL(ac) level applied to the

device under test.

NOTE2: The input signal minimum slew rate is to be maintained over the range from V_REFto V_IH(ac) min for rising

edges and the range from V_REFto V_IL(ac) max for falling edges .

NOTE3: AC timings are referenced with input waveforms switching from V_IL(ac) to V_IH(ac) on the positive

transitions and V_IH(ac) to V_IL(ac) on the negative transitions.

Table 18. Differential AC output parameters

(V_DD= 1.8V  0.1V, T_OPER= 0~95 C)

Value

Symbol

Parameter

Unit Note

Min.

Max.

0.5xV_DDQ+0.125

V_ox(ac)

AC Differential Cross Point Voltage

0.5xV_DDQ-0.125

V

1

NOTE1: The typical value of V_OX(ac) is expected to be about 0.5 x V_DDQof the transmitting device and V_OX(ac) is

expected to track variations in V_DDQ. V_OX(ac) indicates the voltage at which differential output signals must

cross.

Table 19. AC overshoot/undershoot specification for address and control pins

(A0-A12, BA0-BA1, CS#, RAS#, CAS#, WE#, CKE, ODT)

-25

0.5

-3

Parameter

Unit

V

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area above V_DD

0.5

0.8

0.5

V

0.66

V-ns

Maximum undershoot area below V_SS

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Table 20. AC overshoot/undershoot specification for clock, data, strobe, and mask pins

(DQ, DQS, DQS#, DM, CK, CK#)

Parameter

-25

0.5

-3

Unit

V

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area

Maximum overshoot area above V_DD

0.5

V

0.23

V-ns

Maximum undershoot area below V_SS

Table 21. Output AC test conditions (

V_DD= 1.8V  0.1V, T_OPER= 0~95 C)

Symbol

Parameter

Output timing measurement reference level

Value

Unit Note

V_OTR

0.5xV_DDQ

V

1

NOTE1: The V_DDQof the device under test is referenced.

Table 22. Output DC current drive

(V_DD= 1.8V  0.1V, T_OPER= 0~95 C)

Symbol

I_OH(dc)

I_OL(dc)

Parameter

Value

-13.4

13.4

Unit Note

mA 1, 3, 4

mA 2, 3, 4

Output minimum source DC current

Output minimum sink DC current

NOTE1: V_DDQ= 1.7 V; V_OUT= 1420 mV. (V_OUT- V_DDQ) /I_OHmust be less than 21 Ω for values of V_OUTbetween V_DDQ

and V_DDQ- 280 mV.

NOTE2: V_DDQ= 1.7 V; V_OUT= 280 mV. V_OUT/I_OLmust be less than 21 Ω for values of V_OUTbetween 0 V and 280 mV.

NOTE3: The dc value of V_REFapplied to the receiving device is set to V_TT

NOTE4: The values of I_OH(dc) and I_OL(dc) are based on the conditions given in Notes 1 and 2. They are used to test

device drive current capability to ensure V_IHmin plus a noise margin and VIL max minus a noise margin are

delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver

operating point (see JEDEC standard: Section 3.3 of JESD8-15A) along a 21 Ω load line to define a

convenient driver current for measurement.

Table 23. Capacitance

(V_DD= 1.8V, f = 1MHz, T_OPER= 25 C)

Value

Symbol

Parameter

Unit

Min.

1.0

2.5

-

Max.

1.75

2.0

C_IN

C_CK

Input Capacitance : Command and Address

Input Capacitance (CK, CK#)

pF

C_I/O

DM, DQ, DQS Input/Output Capacitance

Delta Input Capacitance: Command and Address

Delta Input Capacitance: CK, CK#

3.5

DC_IN

DC_CK

DC_IO

0.25

0.5

-

Delta Input/Output Capacitance: DM, DQ, DQS

-

NOTE: These parameters are periodically sampled and are not 100% tested.

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Table 24. IDD specification parameters and test conditions

(V_DD= 1.8V  0.1V, T_OPER= 0~95 C)

-25

-3

Parameter & Test Condition

Symbol

Unit

Max.

Operating one bank active-precharge current:

t_CK=t_CK(min), t_RC= t_RC(min), t_RAS= t_RAS(min); CKE is HIGH, CS# is

HIGH between valid commands; Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

I_DD0

75

70

mA

Operating one bank active-read-precharge current:

I_OUT= 0mA; BL = 4, CL = CL (min), AL = 0; t_CK= t_CK(min),t_RC= t_RC(min),

t_RAS= t_RAS(min), t_RCD= t_RCD(min);CKE is HIGH, CS# is HIGH between

valid commands; Address bus inputs are switching; Data pattern is same

as I_DD4W

I_DD1

85

80

mA

Precharge power-down current:

I_DD2P

8

mA

All banks idle;t_CK=t_CK(min); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

Precharge quiet standby current:

All banks idle; t_CK=t_CK(min); CKE is HIGH, CS# is HIGH; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current:

I_DD2Q

35

All banks idle; t_CK= t_CK(min); CKE is HIGH, CS# is HIGH; Other control

and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

I_DD2N

I_DD3P

I_DD3N

40

mA

Active power-down current:

All banks open; t_CK=t_CK(min); CKE is LOW; Other control

20

14

MRS(A12)=0

20

14

mA

and address bus inputs are STABLE; Data bus inputs are

MRS(A12)=1

FLOATING

Active standby current:

All banks open; t_CK= t_CK(min), t_RAS= t_RAS(max), t_RP= t_RP(min); CKE is

HIGH, CS# is HIGH between valid commands; Other control and address

bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current:

All banks open, continuous burst writes; BL = 4, CL = CL (min), AL = 0;

t_CK= t_CK(min), t_RAS= t_RAS(max), t_RP= t_RP(min); CKE is HIGH, CS# is

HIGH between valid commands; Address bus inputs are switching; Data

bus inputs are switching

55

mA

I_DD4W

120

110

Operating burst read current:

All banks open, continuous burst reads, I_OUT= 0mA; BL = 4, CL = CL

(min), AL = 0; t_CK= t_CK(min), t_RAS= t_RAS(max), t_RP= t_RP(min); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

I_DD4R

130

120

mA

Burst refresh current:

t_CK= t_CK(min); refresh command at every t_RFC(min) interval; CKE is

HIGH, CS# is HIGH between valid commands; Other control and address

bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current:

CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

I_DD5

95

6

90

6

mA

I_DD6

Operating bank interleave read current:

All bank interleaving reads, I_OUT= 0mA; BL = 4, CL = CL (min), AL =t_RCD

(min) - 1 x t_CK(min); t_CK= t_CK(min), t_RC= t_RC(min), t_RRD= t_RRD(min), t_RCD

= t_RCD(min); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs. Data pattern is

same as IDD4R

I_DD7

200

180

mA

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Table 25. Electrical Characteristics and Recommended A.C. Operating Conditions

(V_DD= 1.8V  0.1V, T_OPER= 0~95C)

-25

-3

Specific

Notes

Symbol

Parameter

Unit

Min.

Max.

Min.

Max.

CL=3

5

8

5

3.75

3

8

15, 33, 34

34, 35

ns

t_CK

CL=4

CL=5

CL=6

3.75

2.5

Average clock period

t_CK(avg)

8

2.5

8

-

Average clock HIGH pulse width

0.48

0.52

0.48

0.52

t_CH(avg)

t_CL(avg)

WL

Average Clock LOW pulse width

0.52

34, 35

Write command to DQS associated clock edge

RL-1

DQS latching rising transitions to associated clock

edges

-0.25

0.25

-0.25

0.25

28

t_DQSS

t_CK

DQS falling edge to CK setup time

DQS falling edge hold time from CK

0.2

-

0.2

-

t_DSS

t_DSH

t_CK

-

DQS input HIGH pulse width

0.35

-

0.35

-

t_DQSH

t_CK

DQS input LOW pulse width

Write preamble

0.35

0.4

-

0.35

0.4

-

t_DQSL

t_WPRE

t_WPST

t_CK

Write postamble

0.6

10

5, 7, 9, 22,

27

Address and Control input setup time

0.175

-

0.2

-

t_IS(base)

ns

5, 7, 9, 23,

27

Address and Control input hold time

Control & Address input pulse width for each input

DQ & DM input setup time

0.25

0.6

-

0.275

0.6

-

t_IH(base)

t_IPW

ns

t_CK

ns

6, 7, 8, 20,

26, 29

0.05

0.1

t_DS(base)

6, 7, 8, 21,

26, 29

DQ & DM input hold time

0.125

-

0.175

-

t_DH(base)

ns

DQ and DM input pulse width for each input

DQ output access time from CK, CK#

DQS output access time from CK, CK#

Data-out high-impedance time from CK, CK#

DQS(DQS#) low-impedance time from CK, CK#

DQ low-impedance time from CK, CK#

DQS-DQ skew for DQS and associated DQ signals

CK half pulse width

0.35

-

0.35

-0.45

-0.4

-

t_DIPW

t_AC

t_DQSCK

t_HZ

t_LZ(DQS)

t_LZ(DQ)

t_DQSQ

t_CK

ns

t_CK

ns

t_CK

ns

t_CK

ns

t_CK

-0.4

0.4

0.35

0.45

0.4

38

-0.35

-

18, 38

13

t_AC(max)

t_AC(min)

t_AC(max)

t_AC(min)

t_AC(max)

2t_AC(min)

t_AC(max)

0.2

t_AC(max)

-

0.24

min(t_CL,t_CH

)

-

min(t_CL,t_CH

)

11, 12, 35

12, 36

37

t_HP

t_QHS

-

DQ hold skew factor

-

t_HP-t_QHS

0.9

0.3

-

0.34

DQ/DQS output hold time from DQS

Read preamble

-

0.9

t_HP-t_QHS

t_QH

1.1

19, 39

19, 40

4, 30

t_RPRE

t_RPST

t_RRD

t_CCD

t_WR

Read postamble

0.4

0.6

0.4

0.6

Active to active command period

CAS# to CAS# command delay

10

-

10

-

2

Write recovery time

15

30

14, 31

3, 24, 30

3, 30

25

Auto Power write recovery + precharge time

Internal Write to Read Command Delay

Internal read to precharge command delay

CKE minimum pulse width

WR + t_RP

7.5

WR + t_RP

7.5

t_DAL

t_WTR

t_RTP

t_CKE

t_XSNR

t_XSRD

t_XP

7.5

3

t_RFC+10

200

2

-

3

Exit self refresh to non-read command delay

Exit self refresh to a read command

Exit precharge power down to any command

30

t

_RFC+10

200

2

-

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Exit active power down to read command

2

-

2

-

1

t_XARD

t_CK

Exit active power down to read command(slow exit,

lower power)

8-AL

7-AL

1, 2

t_XARDS

ODT turn-on delay

ODT turn-on

2

16

t_AOND

t_AON

t_CK

ns

t_AC(max)+0.7

6, 16, 38

t_AC(min)

2 t_CK

+t_AC(max)+1

2 t_CK

+t_AC(max)+1

ODT turn-on (Power-Down mode)

t_AC(min)+2

t_AONPD

ns

ODT turn-off delay

ODT turn-off

2.5

17, 42

t_AOFD

t_AOF

t_CK

ns

17, 41, 42

t_AC(min)

t

t_AC(min)

t

_AC(max)+0.6

2.5 t_CK

+t_AC(max)+1

2.5 t_CK

+t_AC(max)+1

ODT turn-off (Power-Down mode)

t_AC(min)+2

t_AOFPD

ns

ODT to power down entry latency

ODT power down exit latency

3

8

2

0

-

3

8

2

0

-

t_ANPD

t_AXPD

t_MRD

t_MOD

t_OIT

t_CK

ns

Mode register set command cycle time

MRS command to ODT update delay

OCD drive mode output delay

-

12

30

Minimum time clocks remains ON after CKE

asynchronously drops LOW

t_IS+ t_CK+t_IH

-

t_IS+ t_CK+t_IH

-

15

t_Delay

t_RFC

ns

Refresh to active/Refresh command time

105

-

105

7.8

3.9

15

-

43

ns

s

ns

℃≦

@ 0

≦

℃

TC +85

-

Average periodic refresh

interval

t_REFI

@ +85℃＜TC≦ +95℃

-

RAS# to CAS# Delay time

Row precharge Delay time

Row cycle Delay time

12.5

57.5

45

-

t_RCD

t_RP

-

15

-

60

t_RC

Row active Delay time

70k

45

70k

t_RAS

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General notes, which may apply for all AC parameters:

NOTE 1: DDR2 SDRAM AC timing reference load

The below figure represents the timing reference load used in defining the relevant timing parameters of the part.

It is not intended to be either a precise representation of the typical system environment or a depiction of the actual

load presented by a production tester.

Figure 5. AC timing reference load

VDDQ

DQ

DQS

Ouput

V_TT=V_DDQ/2

DUT

DQS#

25Ω

Timing reference

point

The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing

reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g.

DQS#) signal.

NOTE 2: Slew Rate Measurement Levels

a) Output slew rate for falling and rising edges is measured between V_TT- 250 mV and V_TT+ 250 mV for single

ended signals. For differential signals (e.g. DQS – DQS#) output slew rate is measured between DQS – DQS#

= - 500 mV and DQS – DQS# = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily

tested on each device.

b) Input slew rate for single ended signals is measured from V_REF(dc) to V_IH(ac), min for rising edges and from

V_REF(dc) to V_IL(ac),max for falling edges. For differential signals (e.g. CK – CK#) slew rate for rising edges is

measured from CK – CK# = - 250 mV to CK -CK# = + 500 mV (+ 250 mV to - 500 mV for falling edges).

c) V_IDis the magnitude of the difference between the input voltage on CK and the input voltage on CK#, or

between DQS and DQS# for differential strobe.

NOTE 3: DDR2 SDRAM output slew rate test load

Output slew rate is characterized under the test conditions as bellow

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Figure 6. Slew rate test load

VDDQ

DQ

DQS

Ouput

V_TT=V_DDQ/2

DUT

DQS#

25Ω

Test point

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NOTE 4: Differential data strobe

DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the

setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design.

The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode,

timing relationships are measured relative to the rising or falling edges of DQS crossing at V_REF. In differential

mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This

distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe

mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to V_SSthrough a 20 Ω to

10 kΩ resistor to insure proper operation

NOTE 5: AC timings are for linear signal transitions.

NOTE 6:All voltages are referenced to V_SS.

NOTE 7:These parameters guarantee device behavior, but they are not necessarily tested on each device. They

may be guaranteed by device design or tester correlation

NOTE 8: Tests for AC timing, I_DD, and electrical (AC and DC) characteristics, may be conducted at nominal

reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full

voltage range specified.

Specific notes for dedicated AC parameters

NOTE 1:User can choose which active power down exit timing to use via MRS (bit 12). t_XARDis expected to be used

for fast active power down exit timing. t_XARDSis expected to be used for slow active power down exit timing

where a lower power value is defined by each vendor data sheet.

NOTE 2: AL=Additive Latency.

NOTE 3:This is a minimum requirement. Minimum read to precharge timing is AL+BL/2 provided that the t_RTPand

t_RAS(min) have been satisfied.

NOTE 4: A minimum of two clocks (2* t_CK) is required irrespective of operating frequency.

NOTE 5: Timings are specified with command/address input slew rate of 1.0 V/ns.

NOTE 6:Timings are specified with DQs, DM, and DQS’s (DQS in single ended mode) input slew rate of 1.0V/ns.

NOTE 7:Timings are specified with CK/CK# differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS

signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single

ended mode.

NOTE 8:Data setup and hold time derating.

For all input signals the total t_DS(setup time) and t_DH(hold time) required is calculated by adding the data sheet.

t_DS(base)and t_DH(base)value to the Δt_DSand Δt_DHderating value respectively.

Example: t_DS(total setup time) =t_{DS (base)}+ Δt_DS.For slew rates in between the values listed in Tables 26, the

derating values may obtained by linear interpolation.These values are typically not subject to production test.

They are verified by design and characterization.

Table 26. DDR2-667/800 tDS/tDH derating with differential data strobe

△tDS, △tDH derating values for DDR2-667, DD2-800 (All units in ‘ps’; the note applies to the entire table)

DQS,DQS# Differential Slew Rate

2.8 V/ns

2.4 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

0.8 V/ns

△tDS

△tDH

△tDS

△tDH

△tDS

△tDH

△tDS

△tDH

△tDS

△tDH

△tDS

△tDH

△tDS

△tDH

△tDS

△tDH

△tDS

△tDH

DQ

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

100

63

42

0

-

100

63

100

67

0

63

42

0

-

Slew

Rate

V/ns

67

0

-

67

0

-5

-

42

79

12

7

54

12

-2

-19

-42

-

24

19

11

2

-

24

10

-7

-30

-59

-

0

-

-14

-5

-13

-

-14

-31

-

31

23

14

2

22

5

-

-1

-10

-

35

26

14

-12

-52

17

-6

-

-18

-47

-89

-

38

26

0

6

-

-10

-

-35

-77

-140

-23

-65

-128

38

12

-28

-11

-53

-116

-

-24

-

-40

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NOTE 9:t_ISand t_IH(input setup and hold) derating

For all input signals the total t_IS(setup time) and t_IH(hold time) required is calculated by adding the data sheet

t_IS(base)and t_IH(base)value to the Δt_ISand Δ_tIHderating value respectively. Example: t_IS(total setup time) =

t_IS(base) + Δt_IS

For slew rates in between the values listed in Tables 27, the derating values may obtained by linear

interpolation.These values are typically not subject to production test. They are verified by design and

characterization

Table 27. Derating values for DDR2-667, DDR2-800

△tIS and △tIH Derating Values for DDR2-667, DDR2-800

CK,CK# Differential Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

△tIS

△tIH

△tIS

△tIH

△tIS

△tIH

Units

Notes

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.25

0.2

0.15

0.1

+150

+143

+133

+120

+100

+67

0

-5

-13

-22

-34

+94

+89

+83

+75

+45

+21

0

-14

-31

-54

-83

-125

-188

-292

-375

-500

-708

-1125

+180

+173

+163

+150

+130

+97

+30

+25

+17

+8

-4

-30

-70

-138

-170

-295

-487

-970

+124

+119

+113

+105

+75

+51

+30

+16

-1

-24

-53

-95

-158

-262

-345

-470

-678

-1095

+210

+203

+193

+180

+160

+127

+60

+55

+47

+38

+26

+154

+149

+143

+135

+105

+81

+60

+46

+29

+6

ps

1

Command/

Address Slew rate

(V/ns)

-23

-65

-60

0

-40

-100

-168

-200

-325

-517

-1000

-128

-232

-315

-440

-648

-1065

-108

-140

-265

-457

-940

NOTE 10: The maximum limit for this parameter is not a device limit. The device will operate with a greater value

for this parameter, but system performance (bus turnaround) will degrade accordingly.

NOTE 11: MIN (t_CL, t_CH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as

provided to the device (i.e. this value can be greater than the minimum specification limits for t_CLand t_CH).

NOTE 12:t_QH= t_HP– t_QHS, where:

t_HP= minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (t_CH, t_CL). t_QHS

accounts for:

1) The pulse duration distortion of on-chip clock circuits; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-

channel variation of the output drivers.

NOTE 13: t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the

output drivers as well as output slew rate mismatch between DQS / DQS# and associated DQ in any given

cycle.

NOTE 14: t_DAL= WR + RU{ t_RP[ns] / t_CK[ns] }, where RU stands for round up.WR refers to the t_WRparameter stored

in the MRS. For t_RP, if the result of the division is not already an integer, round up to the next highest integer.

t_CKrefers to the application clock period.

NOTE 15: The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In

case of clock frequency change during precharge power-down.

NOTE 16: ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on.

ODT turn on time max is when the ODT resistance is fully on. Both are measured from t_AOND, which is interpreted

as 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.

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NOTE 17: ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is

when the bus is in high impedance. Both are measured from t_AOFD, which is interpreted differently per speed

bin. For DDR2-667/800, if t_CK(avg) = 3 ns is assumed, t_AOFDis 1.5 ns (= 0.5 x 3 ns) after the second trailing

clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input

clock edges.

NOTE 18: t_HZand t_LZtransitions occur in the same access time as valid data transitions. These parameters are

referenced to a specific voltage level which specifies when the device output is no longer driving (t_HZ), or

begins driving (t_LZ).

NOTE 19: t_RPSTend point and t_RPREbegin point are not referenced to a specific voltage level but specify when the

device output is no longer driving (t_RPST), or begins driving (t_RPRE). The actual voltage measurement points are

not critical as long as the calculation is consistent.

NOTE 20: Input waveform timing t_DSwith differential data strobe enabled MR[bit10]=0, is referenced from the input

signal crossing at the V_IH(ac) level to the differential data strobe crosspoint for a rising signal, and from the

input signal crossing at the V_IL(ac) level to the differential data strobe crosspoint for a falling signal applied to

the device under test. DQS, DQS# signals must be monotonic between V_IL(dc)max and V_IH(dc)min.

NOTE 21: Input waveform timing t_DHwith differential data strobe enabled MR[bit10]=0, is referenced from the

differential data strobe crosspoint to the input signal crossing at the V_IH(dc) level for a falling signal and from

the differential data strobe crosspoint to the input signal crossing at the V_IL(dc) level for a rising signal applied

to the device under test. DQS, DQS# signals must be monotonic between V_IL(dc)max and V_IH(dc)min.

NOTE 22: Input waveform timing is referenced from the input signal crossing at the V_IH(ac) level for a rising signal

and V_IL(ac) for a falling signal applied to the device under test.

NOTE 23: Input waveform timing is referenced from the input signal crossing at the V_IL(dc) level for a rising signal

and V_IH(dc) for a falling signal applied to the device under test.

NOTE 24: t_WTRis at lease two clocks (2 x t_CK) independent of operation frequency.

NOTE 25: t_CKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must

remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any

CKE transition, CKE may not transition from its valid level during the time period of t_IS+ 2 x t_CK+ t_IH.

NOTE 26: If t_DSor t_DHis violated, data corruption may occur and the data must be re-written with valid data before a

valid READ can be executed.

NOTE 27: These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT,

BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are not

affected by the amount of clock jitter applied (i.e. t_JIT(per), t_JIT(cc), etc.), as the setup and hold are relative to

the clock signal crossing that latches the command/address. That is, these parameters should be met whether

clock jitter is present or not.

NOTE 28: These parameters are measured from a data strobe signal (DQS/DQS#) crossing to its respective clock

signal (CK/CK#) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t_JIT(per),

t_JIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met

whether clock jitter is present or not.

NOTE 29: These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its

respective data strobe signal (DQS/DQS#) crossing.

NOTE 30: For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM =

RU{tPARAM / t_CK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.

NOTE 31: t_DAL[t_CK] = WR [t_CK] + tRP [t_CK] = WR + RU {t_RP[ps] / t_CK(avg) [ps] }, where WR is the value programmed

in the mode register set.

NOTE 32: New units, ‘t_CK(avg)’ is introduced in DDR2-667 and DDR2-800. Unit ‘t_CK(avg)’ represents the actual

t_CK(avg) of the input clock under operation.

NOTE 33: Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as

'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter

specified is a random jitter meeting a Gaussian distribution.

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Table 28. Input clock jitter spec parameter

-25

-3

Parameter

Clock period jitter

Symbol

Units Notes

Min.

-100

-80

Max.

100

80

Min.

-125

-100

-250

-200

-175

-225

-250

-350

-450

-125

Max.

125

100

250

200

175

225

250

350

450

125

t_{JIT (}per)

t_JIT(per,lck)

t_JIT(cc)

ps

33

Clock period jitter during DLL locking

period

Cycle to cycle clock period jitter

-200

-160

-150

-175

-200

-300

-450

-100

200

160

150

175

200

300

450

100

Cycle to cycle clock period jitter during

DLL locking period

Cumulative error across 2 cycles

t_JIT(cc,lck)

t_ERR(2per)

t_ERR(3per)

t_ERR(4per)

t_ERR(5per)

t_ERR(6-10per)

t_ERR(11-50per)

t_JIT(duty)

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across n cycles,

n=6...10, inclusive

Cumulative error across n cycles,

n=11...50, inclusive

Duty cycle jitter

NOTE 34: These parameters are specified per their average values, however it is understood that the following

relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and

max of SPEC values are to be used for calculations in the table below.)

Table 29. Absolute clock period average values

Parameter

Symbol

Min.

Max.

Unit

Absolute clock period

t_CK(abs)

t_CK(avg),min + t_JIT(per),min

t_CK(avg),max + t_JIT(per),max

ps

Absolute clock HIGH pulse width

Absolute clock LOW pulse width

t_CH(abs)

t_CL(abs)

t_CH(avg),min * t_CK(avg),min + t_CH(avg),max * t_CK(avg),max + ps

t_JIT(duty),min t_JIT(duty),max

t_CL(avg),min * t_CK(avg),min + t_CL(avg), max * t_CK(avg),max + ps

t_JIT(duty),min t_JIT(duty), max

NOTE 35: t_HPis the minimum of the absolute half period of the actual input clock. t_HPis an input parameter but not

an input specification parameter. It is used in conjunction with t_QHSto derive the DRAM output timing t_QH. The

value to be used for tQH calculation is determined by the following equation;

t_HP= Min ( t_CH(abs), t_CL(abs) ),

where,

t_CH(abs) is the minimum of the actual instantaneous clock HIGH time;

t_CL(abs) is the minimum of the actual instantaneous clock LOW time;

NOTE 36: t_QHSaccounts for:

1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t_HPat the input is

transferred to the output; and

2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next

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transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-

channel to n-channel variation of the output drivers

NOTE 37: t_QH= t_HP– t_QHS, where: t_HPis the minimum of the absolute half period of the actual input clock; and t_QHSis

the specification value under the max column. {The less half-pulse width distortion present, the larger the t_QH

value is; and the larger the valid data eye will be.}

NOTE 38: When the device is operated with input clock jitter, this parameter needs to be derated by the actual

t_ERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)

NOTE 39: When the device is operated with input clock jitter, this parameter needs to be derated by the actual

tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)

NOTE 40: When the device is operated with input clock jitter, this parameter needs to be derated by the actual

t_JIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)

NOTE 41: When the device is operated with input clock jitter, this parameter needs to be derated by { -

t_JIT(duty),max - t_ERR(6-10per),max } and { - t_JIT(duty),min - t_ERR(6-10per),min } of the actual input clock. (output

deratings are relative to the SDRAM input clock.)

NOTE 42: For t_AOFDof DDR2-667/800, the 1/2 clock of t_CKin the 2.5 x t_CKassumes a t_CH(avg), average input clock

HIGH pulse width of 0.5 relative to t_CK(avg). t_AOF,min and t_AOF,max should each be derated by the same

amount as the actual amount of t_CH(avg) offset present at the DRAM input with respect to 0.5.

NOTE 43: If refresh timing is violated, data corruption may occur and the data must be re-written with valid data

before a valid READ can be executed.

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Timing Waveforms

Figure 7. Initialization sequence after power-up

t_CHt_CL

CK

CK#

t_IS

CKE

ODT

t_IS

EMR

S

ANY

CMD

EMR

S

EMR

S

PRE

ALL

PRE

ALL

REF

MRS

NOP

MRS

Command

Follow OCD Flowchart

t_RFC

400ns

t_RP

t_MRD

t_RP

t_RFC

t_MRD

t_OIT

OCD

DLL

ENABLE

DLL

CAL.MOD

E EXIT

Default

min 200 Cycle

RESET

NOTE 1: To guarantee ODT off, V_REFmust be valid and a LOW level must be applied to the ODT pin.

Figure 8. ODT update delay timing-tMOD

EMRS

NOP

CMD

CK#

CK

ODT

t_IS

t_{MOD, max}

Updating

t_AOFD

t_{MOD, min}

Rtt

Old setting

New setting

NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:

- t_AOFDmust be met before issuing the EMRS command.

- ODT must remain LOW for the entire duration of t_MODwindow, until t_MOD, max is met.

then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned

on the ODT.

NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).

NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.

Figure 9. ODT update delay timing-t_MOD, as measured from outside

CK#

CK

EMRS

NOP

CMD

ODT

t_IS

t_AOND

t_AOFD

t_{MOD, max}

Rtt

Old setting

New setting

NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).

NOTE 2: "setting" in this diagram is measured from outside.

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Figure 10. ODT timing for active standby mode

T0 T1

T2

T3

T4

T5

T6

CK#

CK

t_IS

CKE

t_IS

V_IH(ac)

V_IL(ac)

ODT

t_AOND

t_AOFD

RTT

Internal

Term Res.

t_AON,min

t_AOF,min

t_AON,max

t_AOF,max

Figure 11. ODT timing for power-down mode

T0 T1

T2

T3

T4

T5

T6

CK#

CK

CKE

ODT

t_IS

V_IH(AC)

V_IL(AC)

t_AOFPD,max

t_AOFPD,min

Internal

Term Res.

RTT

t_AONPD,min

t_AONPD,max

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Figure 12. ODT timing mode switch at entering power-down mode

T-5

T-4

T-3

T-2

T-1

T0

T1

T2

T3

T4

CK#

CK

t_ANPD

t_IS

CKE

Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode.

t_IS

ODT

V_IL(ac)

t_AOFD

Active & Standby mode

timings to be applied.

Internal

Term Res.

RTT

t_IS

ODT

V_IL(ac)

Power Down mode

timings to be applied.

t_{AOFPD max}

Internal

Term Res.

RTT

t_IS

V_IH(ac)

ODT

t_AOND

Active & Standby mode

timings to be applied.

RTT

Internal

Term Res.

t_IS

V_IH(ac)

ODT

t_{AONPD max}

Power Down mode

timings to be applied.

Internal

Term Res.

RTT

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Figure 13.ODT timing mode switch at exit power-down mode

T0

T1

T4

T5

T6

T7

T8

T9

T10

T11

CK#

CK

t_IS

t_AXPD

V_IH(ac)

CKE

Exiting from Slow Active Power Down Mode or Precharge power Down Mode.

t_IS

ODT

V_IL(ac)

Active & Standby mode

t_AOFD

timings to be applied.

Internal

Term Res.

RTT

t_IS

ODT

Power Down mode

V_IL(ac)

timings to be applied.

t_{AOFPD max}

Internal

Term Res.

RTT

t_IS

V_IH(ac)

Active & Standby mode

ODT

timings to be applied.

t_AOND

RTT

Internal

Term Res.

t_IS

V_IH(ac)

Power Down mode

ODT

timings to be applied.

t_{AONPD max}

Internal

Term Res.

RTT

Figure 14. Bank activate command cycle (t_RCD=3, AL=2, t_RP=3, t_RRD=2, t_CCD=2)

T0

T1

T2

T3

Tn

Tn+1

Tn+2

Tn+3

CK#

CK

Internal RAS# - CAS# delay (>=t_{RCD min}

)

Bank A

Row Addr.

Bank A

Col. Addr.

Bank B

Row Addr.

Bank B

Col. Addr

Bank A

Addr.

Bank B

Addr.

Bank A

Row Addr.

ADDRESS

CAS# - CAS# delay time (t_CCD

)

Additive latency delay (AL)

t_RCD= 1

Read Begins

RAS# - RAS# delay time (>=t_RRD

)

Bank A

Post CAS#

Read

Bank B

Post CAS#

Read

Bank A

Activate

Bank B

Activate

Bank A

Precharge

Bank B

Precharge

Bank A

Activate

COMMAND

Bank precharge time (>=t_RP

)

Bank Active (>=t_RAS

)

RAS# Cycle time (>=t_RC

)

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Figure 15. Posted CAS# operation: AL=2

Read followed by a write to the same bank

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

CK#

CK

Active

A-Bank

Read

A-Bank

Write

A-Bank

CMD

WL=RL-1=4

AL=2

CL=3

DQS

DQS#

>=t_RCD

RL=AL+CL=5

Dout 0 Dout 1 Dout 2 Dout 3

Din 0 Din 1 Din 2 Din 3

DQ

[ AL=2 and CL=3, RL= (AL+CL)=5, WL= (RL-1)=4, BL=4]

Figure 16. Posted CAS# operation: AL=0

Read followed by a write to the same bank

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

CK#

CK

AL=0

Active

A-Bank

Read

A-Bank

Write

A-Bank

CMD

WL=RL-1=2

CL=3

DQS

DQS#

>=t_RCD

RL=AL+CL=3

Dout 0 Dout 1 Dout 2 Dout 3

Din 0 Din 1 Din 2 Din 3

DQ

[ AL=0 and CL=3, RL= (AL+CL)=3, WL= (RL-1)=2, BL=4]

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Figure 17. Data output (read) timing

t_CH

t_CL

CK#

CK

DQS#

DQS

DQS#

t_RPRE

t_{DQSQ max}

t_RPST

Q

DQ

t_{DQSQ max}

t_QH

Figure 18. Data input (write) timing

t_DQSH

t_DQSL

DQS#

DQS

DQS#

t_WPRE

t_WPSL

V_IH(ac)

V_IH(dc)

D

DQ

D

V_IL(dc)

V_IL(ac)

t_DS

t_DH

t_DS

t_DH

V_IH(dc)

V_IH(ac)

DMin

V_IL(dc)

DMin

V_IL(ac)

DM

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Figure 19. Burst read operation: RL=5 (AL=2, CL=3, BL=4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Posted CAS#

READ A

NOP

CMD

=< t_DQSCK

DQS

DQS#

AL=2

CL=3

RL=5

Dout A0 Dout A1 Dout A2

Dout A3

DQs

Figure 20. Burst read operation: RL=3 (AL=0, CL=3, BL=8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

READ A

NOP

CMD

=< t_DQSCK

DQS

DQS#

CL=3

RL=3

Dout A0 Dout A1 Dout A2

Dout A3 Dout A4 Dout A5 Dout A6

Dout A7

DQs

Figure 21. Burst read followed by burst write: RL=5, WL= (RL-1) =4, BL=4

T0

T1

Tn-1

Tn

Tn+1

Tn+2

Tn+3

Tn+4

Tn+5

CK#

CK

Post CAS#

READ A

Post CAS#

WRITE A

NOP

CMD

t_RTW(Read to Write turn around time)

DQS

DQS#

RL=5

WL = RL-1 = 4

Dout A₀Dout A₁Dout A₂Dout A₃

Din A₀

Din A₁

Din A₂

Din A₃

DQs

NOTE : The minimum time from the burst read command to the burst write command is defined by a read-to-write-

turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.

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Figure 22. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Post CAS#

READ A

Post CAS#

READ B

NOP

CMD

DQS

DQS#

AL=2

CL=3

RL=5

Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2

DQs

NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL =

4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks

as long as the banks are activated.

Figure 23. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)

CK#

CK

Read A

Read B

NOP

CMD

DQS

DQS#

A0

A1

A2

A3

B0

B1

B2

B3

B4

B5

B6

B7

DQs

NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write

command or Precharge command is prohibited.

NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst

interrupt timings are prohibited.

NOTE 4: Read burst interruption is allowed to any bank inside DRAM.

NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt.

NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command.

NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to

actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the

mode register and not the actual burst (which is shorter because of interrupt).

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Figure 24. Burst write operation: RL=5 (AL=2, CL=3), WL=4, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

Tn

CK#

CK

Posted CAS#

WRITE A

Precharge

NOP

t_DQSS

NOP

t_DSSt_DQSS

NOP

CMD

Completion of the

Burst Write

Case 1: with t_{DQSS (max)}

t_DSS

DQS

WL = RL-1 =4

>=t_WR

DQS#

DNA₀DNA₁DNA₂DNA₃

DQs

Case 2: with t_{DQSS (min)}

t_DQSSt_DSH

DQS

DQS#

>=t_WR

WL = RL-1 =4

DNA₀DNA₁DNA₂DNA₃

DQs

Figure 25. Burst write operation: RL=3 (AL=0, CL=3), WL=2, BL=4

T0

T1

T2

T3

T4

T5

Tm

Tm+1

Tn

CK#

CK

Bank A

Activate

Precharge

WRITE A

NOP

<=t_DQSS

NOP

CMD

Completion of the

Burst Write

DQS

DQS#

>=t_WR

>=t_RP

WL = RL-1 =2

DNA₀DNA₁DNA₂DNA₃

DQs

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Figure 26. Burst write followed by burst read:

RL=5 (AL=2, CL=3, WL=4, t_WTR=2, BL=4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK#

CK

Write to Read = CL-1+BL/2+t_WTR

NOP NOP NOP

Post CAS#

READ A

NOP

CKE

DQS#

DQS

DQS#

WL = RL-1 = 4

AL=2

CL=3

RL=5

>=t_WTR

DQ

DOUT A₀

DNA₀DNA₁DNA₂DNA₃

NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + t_WTR].

This t_WTRis not a write recovery time (t_WR) but the time required to transfer the 4 bit write data from the input buffer into

sense amplifiers in the array. t_WTRis defined in the timing parameter table of this standard.

Figure 27. Seamless burst write operation RL=5, WL=4, BL=4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Post CAS#

Write A

Post CAS#

Write B

NOP

CMD

DQS#

DQS

DQS#

WL = RL-1 = 4

DQ

DNA₀DNA₁DNA₂DNA₃DNB₀DNB₁DNB₂DNB₃

NOTE : The seamless burst write operation is supported by enabling a write command every other clock for

BL= 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or

different banks as long as the banks are activated.

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Figure 28. Write burst interrupt timing: (CL=3, AL=0, RL=3, WL=2, BL=8)

CK#

CK

NOP

Write A

NOP

Write B

NOP

CMD

DQS

DQS#

A0

A1

A2

A3

B0

B1

B2

B3

B4

B5

B6

B7

DQs

NOTE 1: Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.

NOTE 2: Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or

Precharge command is prohibited.

NOTE 3: Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt

timings are prohibited.

NOTE 4: Write burst interruption is allowed to any bank inside DRAM.

NOTE 5: Write burst with Auto Precharge enabled is not allowed to interrupt.

NOTE 6: Write burst interruption is allowed by another Write with Auto Precharge command.

NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual

burst. For example, minimum Write to Precharge timing is WL + BL/2 + tWR where tWR starts with the rising clock after the

uninterrupted burst end and not from the end of actual burst end.

Confidential

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AS4C64M8D2

Figure 29. Write data mask

Data Mask Timing

DQS

DQS#

DQ

V_IH(acV_{) IH(dc)}

V_IL(ac)V_IL(dc)

V_IH(acV_{) IH(dc)}

V_IL(ac)V_IL(dc)

DM

t_DSt_DH

Data Mask Function, WL=3, AL=0, BL=4 shown

Case 1: min t_DQSS

CK#

CK

t_WR

Write

COMMAND

WL

t_DQSS

DQS

DQS#

DQ

DM

Case 2: max t_DQSS

DQS

t_DQSS

DQS#

DQ

DM

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AS4C64M8D2

Figure 30. Burst read operation followed by precharge:

(RL=4, AL=1, CL=3, BL=4, t_RTP≦2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Bank A

Active

Post CAS#

Read A

Precharge

NOP

AL+BL'/2 clks

NOP

CMD

DQS

DQS#

AL=1

CL=3

>=t_RP

RL=4

DQ

DOUTA₀DOUTA₁DOUTA₂DOUTA₃

>=t_RAS

>=t_RTP

CL=3

Figure 31. Burst read operation followed by precharge:

(RL=4, AL=1, CL=3, BL=8, t_RTP≦2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Post CAS#

READ A

Precharge A

NOP

AL + BL/2 clks

NOP

CMD

DQS

DQS#

AL = 1

CL = 3

RL= 4

DQ's

DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT

A₀

A₁

A₂

A₃

A₄

A₅

A₆

A₇

>=t_RTP

First 4-bit prefetch

Second 4-bit prefetch

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AS4C64M8D2

Figure 32. Burst read operation followed by precharge:

(RL=5, AL=2, CL=3, BL=4, t_RTP≦2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Bank A

Activate

Post CAS#

READ A

Precharge A

NOP

AL + BL/2 clks

NOP

CMD

DQS

AL = 2

CL = 3

DQS#

>=t_RP

RL= 5

DOUT DOUT DOUT DOUT

DQ's

A₀

A₁

A₂

A₃

>=t_RAS

CL = 3

>=t_RTP

Figure 33. Burst read operation followed by precharge:

(RL=6, AL=2, CL=4, BL=4, t_RTP≦2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Bank A

Activate

Post CAS#

READ A

Precharge A

NOP

AL + BL/2 clks

NOP

CMD

DQS

AL = 2

CL = 4

DQS#

>=t_RP

RL= 6

DOUT DOUT DOUT DOUT

A₀A₁A₂A₃

DQ's

>=t_RAS

CL = 4

>=t_RTP

Confidential

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AS4C64M8D2

Figure 34. Burst read operation followed by precharge:

(RL=4, AL=0, CL=4, BL=8, t_RTP>2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Bank A

Activate

Post CAS#

READ A

Precharge A

NOP

CMD

AL + 2 + max( t_RTP, 2 t_CK)*

DQS

DQS#

CL = 4

RL= 4

AL = 0

>=t_RP

DQ's

DOUT

A₇

DOUT DOUT DOUT DOUT DOUT DOUT DOUT

A₀

A₁

A₂

A₃

A₄

A₅

A₆

>=t_RAS

>=t_RTP

First 4-bit prefetch

Second 4-bit prefetch

*: rounded to next integer.

Figure 35. Burst write operation followed by precharge: WL= (RL-1) =3

T0 T1 T2 T3 T4 T5 T6

T7

T8

CK#

CK

Post CAS#

Write A

Precharge A

NOP

CMD

Completion of the Burst Write

>=t_WR

DQS

DQS#

WL= 3

DNA₀DNA₁DNA₂DNA₃

DQ's

Confidential

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AS4C64M8D2

Figure 36. Burst write followed by precharge: WL= (RL-1) =4

T0 T1 T2 T3 T4 T5

T6

T7

T9

CK#

CK

Post CAS#

Write A

Precharge A

NOP

CMD

Completion of the Burst Write

>=t_WR

DQS

DQS#

WL= 4

DNA₀DNA₁DNA₂DNA₃

DQ's

Figure 37. Burst read operation with auto precharge:

(RL=4,AL=1, CL=3, BL=8, t_RTP≦2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Bank A

Activate

Post CAS#

READ A

NOP

>= t_RP

NOP

CMD

Autoprecharge

AL + BL/2 clks

DQS

DQS#

CL = 3

AL = 1

RL= 4

DOUT

A₇

DOUT DOUT DOUT DOUT DOUT DOUT DOUT

A₀A₁A₂A₃A₄A₅A₆

DQ's

>=t_RTP

t_RTP

First 4-bit prefetch

Second 4-bit prefetch

Precharge begins here

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AS4C64M8D2

Figure 38. Burst read operation with auto precharge:

(RL=4, AL=1, CL=3, BL=4, t_RTP>2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Bank A

Activate

Post CAS#

READ A

NOP

CMD

>= AL+t_RTP+t_RP

Autoprecharge

DQS

DQS#

AL= 1

CL= 3

RL= 4

DoutA₀DoutA₁DoutA₂DoutA₃

DQ's

t_RTP

t_RP

First 4-bit prefetch

Precharge begins here

Figure 39. Burst read operation with auto precharge followed by activation to the same

bank (t_RCLimit): RL=5(AL=2, CL=3, internal t_RCD=3, BL=4, t_RTP≦2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

A10= 1

Bank A

Activate

Post CAS#

READ A

NOP

CMD

>=t_RAS(min)

Auto Precharge Begins

DQS

DQS#

AL= 2

CL= 3

RL= 5

>=t_RP

DoutA₀DoutA₁DoutA₂DoutA₃

DQ's

CL=3

>= t_RC

Confidential

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AS4C64M8D2

Figure 40. Burst read operation with auto precharge followed by an activation to the same

bank (t_RPLimit): (RL=5 (AL=2, CL=3, internal t_RCD=3, BL=4, t_RTP≦2 clocks)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

A10= 1

Bank A

Activate

Post CAS#

READ A

NOP

>=t_RAS(min)

NOP

CMD

Auto Precharge Begins

DQS

DQS#

>= t_RP

AL= 2

CL= 3

RL= 5

DoutA₀DoutA₁DoutA₂DoutA₃

DQ's

CL=3

>= t_RC

Figure 41. Burst write with auto-precharge (t_RCLimit): WL=2, WR=2, BL=4, t_RP=3

T0

T1

T2

T3

T4

T5

T6

T7

Tm

CK#

CK

A10 = 1

Bank A

Active

Post CAS#

WRA Bank A

NOP

CMD

Completion of the Burst Write

Auto Precharge Begins

DQS

DQS#

WL= RL-1=2

>=WR

>=t_RP

DNA₀DNA₁DNA₂DNA₃

DQ's

>=t_RC

Confidential

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AS4C64M8D2

Figure 42. Burst write with auto-precharge (WR+t_RP): WL=4, WR=2, BL=4, t_RP=3

T0 T3 T4 T5 T6 T7 T8 T9

T12

CK#

CK

A10=1

Bank A

Active

Post CAS#

WRA Bank A

NOP

CMD

Completion of the Burst Write

Auto Precharge Begins

DQS

DQS#

>=WR

>=t_RP

WL= RL-1=4

DNA₀DNA₁DNA₂DNA₃

DQ's

>=t_RC

Figure 43. Refresh command

T0 T1 T2

T3

Tm

Tn

Tn+1

CK#

CK

HIGH

CKE

>=t_RP

>=t_RFC

CMD

Precharge

NOP

REF

NOP

ANY

Confidential

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Rev. 1.0

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AS4C64M8D2

Figure 44. Self refresh operation

T0

T1

T2

T3

T4

T5

T6

Tm

Tn

t_CK

t_CH

t_CL

CK#

CK

>=t_XSNR

t_RP*

>=t_XSRD

CKE

V_IH(ac)

V_IL(ac)

t_IS

t_AOFD

t_IS

V_IL(ac)

ODT

CMD

t_IS

t_IH

t_IS

NOP

t_IH

Valid

t_ISt_IH

V_IH(ac)

V_IL(ac)

V_IH(dc)

V_IL(dc)

Self

NOP

Refresh

NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode.

NOTE 2 ODT must be turned off t_AOFDbefore entering Self Refresh mode, and can be

turned on again when t_XSRDtiming is satisfied.

NOTE 3 t_XSRDis applied for Read or a Read with autoprecharge command.

t_XSNRis applied for any command except a Read or a Read with autoprecharge command.

Figure 45. Basic power down entry and exit timing diagram

CK

CK#

t_IH

t_IS

t_ISt_IH

t_IH

t_IS

t_IH

CKE

VALID

or NOP

VALID

NOP

VALID

Command

t_{CKE min}

t_XP,t_XARD

t_CKE(min)

t_XARDS

Exit Power-Down mode

Enter Power-Down mode

Don't Care

Figure 46. CKE intensive environment

CK#

CK

t_CKE

CKE

t_CKE

NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation

Confidential

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AS4C64M8D2

Figure 47. CKE intensive environment

CK#

CK

CKE

t_CKE

t_XP

CMD

REF

t_REFI

NOTE: The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all AC and DC timing & voltage

specifications and DLL operation with temperature and voltage drift

Figure 48. Read to power-down entry

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

Tx+7

Tx+8

Tx+9

CK#

CK

Read operation starts with a read command and

CMD

CKE

RD

CKE should be kept HIGH until the end of burst operation

BL=4

AL+CL

t_IS

Q

DQ

DQS

DQS#

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

Tx+7

Tx+8

Tx+9

CK#

CK

CMD

CKE

RD

CKE should be kept HIGH until the end of burst operation

BL=8

AL+CL

t_IS

Q

DQ

DQS

DQS#

Confidential

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Rev. 1.0

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AS4C64M8D2

Figure 49. Read with autoprecharge to power-down entry

T0

T1

T2

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

Tx+7

Tx+8

Tx+9

CK#

CK

CMD

CKE

RDA

PRE

CKE should be kept HIGH until the end of burst operation

BL=4

AL+BL/2 with t_RTP= 7.5ns

& t_RASmin satisfied

AL+CL

Q

t_IS

Q

DQ

DQS

DQS#

T0

T1

RD

T2

Tx

Tx+1

Tx+2

PRE

Tx+3

Tx+4

Tx+5

Tx+6

Tx+7

Tx+8

Tx+9

CK#

CK

Start internal precharge

CMD

CKE

CKE should be kept HIGH until the end of burst operation

BL=8

AL+BL/2 with t_RTP= 7.5ns

& t_RASmin satisfied

AL+CL

t_IS

Q

DQ

DQS

DQS#

Figure 50. Write to power-down entry

T0

T1

Tm

Tm+1

Tm+2

Tm+3

Tx

Tx+1

Tx+2

Ty

Ty+1

Ty+2

Ty+3

CK#

CK

CMD

CKE

WR

BL=4

WL

t_IS

Q

DQ

t_WTR

DQS

DQS#

T0

T1

Tm

Tm+1

Tm+2

Tm+3

Tm+4

Tm+5

Tx

Tx+1

Tx+2

Tx+3

Tx+4

CK#

CK

CMD

CKE

WR

BL=8

WL

t_IS

Q

DQ

t_WTR

DQS

DQS#

Confidential

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AS4C64M8D2

Figure 51. Write with autoprecharge to power-down entry

T0

T1

Tm

Tm+1

Tm+2

Tm+3

Tx

Tx+1

Tx+2

Tx+3

Tx+4

Tx+5

Tx+6

CK#

CK

CMD

CKE

WRA

PRE

BL=4

WL

t_IS

Q

DQ

WR*1

DQS

DQS#

T0

T1

Tm

Tm+1

Tm+2

Tm+3

Tm+4

Tm+5

Tx

Tx+1

PRE

Tx+2

Tx+3

Tx+4

CK#

CK

Start internal Precharge

CMD

CKE

WRA

BL=8

WL

t_IS

Q

DQ

WR*1

DQS

DQS#

*1: WR is programmed through MRS

Confidential

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AS4C64M8D2

Figure 52. Refresh command to power-down entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK#

CK

REF

CMD

CKE

CKE can go to LOW one clock after an Auto-refresh command

t_IS

Figure 53. Active command to power-down entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CMD

CKE

ACT

CKE can go to LOW one clock after an Active command

t_IS

Figure 54. Precharge/precharge-all command to power-down entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

PR or PRA

CMD

CKE

CKE can go to LOW one clock after a Precharge or Precharge all command

t_IS

Figure 55. MRS/EMRS command to power-down entry

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

MRS or

EMRS

CMD

CKE

t_MRD

t_IS

Confidential

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Rev. 1.0

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AS4C64M8D2

Figure 56. Asynchronous CKE LOW event

Stable clocks

t_CK

CK#

CK

CKE

t_Delay

t_IS

CKE asynchronously drops LOW

Clocks can be turned off after this point

Figure 57. Clock frequency change in precharge power down mode

T0

T1

T2

T4

Tx

Tx+1

Ty

Ty+1

Ty+2

Ty+3

Ty+4

Tz

CK#

CK

DLL

RESET

CMD

CKE

ODT

NOP

Valid

Frequency Change Occurs here

200 Clocks

t_IS

t_XP

t_RP

t_AOFD

t_IH

ODT is off during DLL RESET

Minimum 2 clocks required before

changing frequency

Stable new clock before power

down exit

Confidential

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AS4C64M8D2

Figure 58. 60-Ball FBGA Package Outline Drawing Information

PIN A1 INDEX

Top View

Side View

Bottom View

DETAIL : "A"

Dimension in inch

Dimension in mm

Symbol

Min

--

Nom Max

Min

--

Nom Max

--

0.047

0.016

0.319

0.0.398

--

1.20

0.40

8.10

10.10

--

A

A1

D

0.010

0.311

0.340

--

0.25

7.90

9.90

--

0.315

0.394

0.252

0.315

0.126

0.031

0.018

--

8.00

10.00

6.40

8.00

3.20

0.80

0.45

--

E

D1

E1

F

e

b

--

0.016

--

0.020

0.081

0.40

--

0.50

2.05

D2

Confidential

58

Rev. 1.0

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AS4C64M8D2

Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070

TEL: (650) 610-6800 FAX: (650) 620-9211

Alliance Memory Inc. reserves the right to change products or specification without notice.

Confidential

59

Rev. 1.0

Feb. /2014


型号：	AS4C64M8D2-25BIN
厂家：	ALLIANCE SEMICONDUCTOR CORPORATION
描述：	Fully synchronous operation
文件：	总59页 (文件大小：1530K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AS4C64M8D2-25BIN [ALSC]

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