AS4CM4E1Q-50 [ALSC]
4M X 4 CMOS Quad CAS DRAM (EDO) family; 4M X 4 CMOS四路CAS DRAM （ EDO ）系列
| 型号： | AS4CM4E1Q-50 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 4M X 4 CMOS Quad CAS DRAM (EDO) family |
| 文件： | 总16页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2001
AS4C4M4EOQ
AS4C4M4E1Q
®
4M ✕ 4 CMOS QuadCAS DRAM (EDO) family
Features
• Organization: 4,194,304 words × 4 bits
AS4C4M4E1Q
• High speed
- RAS-only and hidden refresh or CAS-before-RAS refresh
or self-refresh
• TTL-compatible
• 4 separate CAS pins allow for separate I/O operation
• JEDEC standard package
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 495 mW max
- 300 mil, 28-pin SOJ
- Standby: 5.5 mW max, CMOS I/O
• Extended data out
- 300 mil, 28-pin TSOP
• 5V power supply
• Refresh
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 mV
- 4096 refresh cycles, 64 ms refresh interval for
4C4M4EOQ
- 2048 refresh cycles, 32 ms refresh interval for
Pin arrangement
Pin designation
Pin(s)
A0 to A11
RAS
Description
SOJ
TSOP
Address inputs
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
VCC
GND
I/O3
I/O2
CAS3
OE
A9
CAS2
NC
A8
A7
A6
A5
VCC
GND
I/O3
I/O2
CAS3
OE
1
2
3
4
5
6
28
27
26
25
24
23
22
21
1
2
3
4
5
6
28
27
26
25
24
23
I/O0
I/O1
WE
I/O0
I/O1
WE
CAS
RAS
RAS
*NC/A11
CAS0
*NC/A11
CAS0
A9
WE
CAS2
NC
A8
A7
A6
A5
A4
GND
7
8
9
10
11
12
13
14
7
8
22
21
CAS1
A10
CAS1
A10
I/O0 to I/O3
OE
9
20
19
18
17
16
15
20
19
18
17
16
15
10
11
12
13
14
A0
A1
A2
A3
VCC
A0
A1
A2
A3
VCC
VCC
A4
GND
GND
Ground
NC
No Connection
* NC on 2K refresh version; A11 on 4K refresh version
Selection guide
Symbol
tRAC
tCAA
tCAC
tOEA
tRC
4C4M4EOQ/E1Q-50
4C4M4EOQ/E1-60
Unit
ns
Maximum RAS access time
50
25
12
13
85
20
110
1.0
60
Maximum column address access time
Maximum CAS access time
30
ns
15
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum hyper page mode cycle time
Maximum operating current
15
ns
100
24
ns
tPC
ns
ICC1
ICC5
100
1.0
mA
mA
Maximum CMOS standby current
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AS4C4M4EOQ
AS4C4M4E1Q
®
Functional description
The 4C4M4EOQ, and AS4C4M4E1Q are high performance 16-megabit CMOS Quad CAS Dynamic Random Access Memories (DRAM)
organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques
resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family
is optimized for use as main memory in PC, workstation, router and switch applications.
These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Extended data out (EDO) read mode enables 50 MHz operation using 50 ns devices. Four individual CAS pins allow for separate I/O
operation which enables the device to operate in parity mode. In contrast to 'fast page mode' devices, data remains active on outputs after
CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus
contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and CAS
going high.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The 4C4M4EOQ and AS4C4M4E1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4EOQ and
AS4C4M4E1Q operate with a single power supply of 5V 0.5V. All provide TTL compatible inputs and outputs.
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Logic block diagram for 4K refresh
Data
I/O
buffers
VCC
Column decoder
Sense amp
GND
I/O0 to I/O3
RAS clock
generator
RAS
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
4,194,304 × 4
Array
CAS clock
generator
(16,777,216)
A9
A10
A11
WE clock
generator
WE
Logic block diagram for 2K refresh
Data
I/O
buffers
VCC
Column decoder
Sense amp
GND
I/O0 to I/O3
RAS clock
generator
RAS
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
4,194,304 × 4
Array
CAS clock
generator
(16,777,216)
A9
A10
Substrate bias
generator
WE clock
generator
WE
Recommended operating conditions
Parameter
Symbol
VCC
Min
Nominal
Max
5.5
Unit
V
4C4M4EOQ
AS4C4M4E1Q
4.5
0.0
2.4
5.0
0.0
–
Supply voltage
GND
VIH
0.0
V
4C4M4EOQ
AS4C4M4E1Q
VCC
V
Input voltage
VIL
TA
–0.5†
0
–
0.8
70
V
Ambient operating temperature
°C
†
V
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
IL
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AS4C4M4EOQ
AS4C4M4E1Q
®
Absolute maximum ratings
Parameter
Symbol
Vin
Min
-1.0
-1.0
-1.0
-55
–
Max
Unit
Input voltage
+7.0
VCC + 0.5
+7.0
+150
260 × 10
1
V
Input voltage (DQs)
VDQ
V
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
VCC
V
TSTG
°C
oC × sec
TSOLDER
PD
–
W
Short circuit output current
Iout
–
50
mA
DC electrical characteristics (AS4C4M4E0/E1)
-50
-60
Parameter
Symbol Test conditions
Min
Max
+5
Min
-5
-5
–
Max
Unit
µA
Notes
1,2
0V ≤ Vin ≤ +5.5V,
Pins not under test = 0V
Input leakage current IIL
Output leakage current IOL
-5
-5
–
+5
+5
DOUT disabled, 0V ≤ Vout ≤ +5.5V
+5
µA
Operating power
ICC1
RAS, UCAS, LCAS, Address cycling;
tRC=min
110
100
mA
supply current
TTL standby power
ICC2
RAS = UCAS = LCAS ≥ VIH
–
–
2.0
–
–
2.0
mA
mA
supply current
Average power supply
current, RAS refresh ICC3
mode or CBR
RAS cycling, UCAS = LCAS ≥ VIH,
t
RC = min of RAS low after XCAS
110
100
1
low.
EDO page mode
average power supply ICC4
current
RAS = VIL, UCAS or LCAS,
address cycling: tHPC = min
–
–
90
–
–
80
mA
mA
1, 2
CMOS standby power
ICC5
RAS = UCAS = LCAS = VCC - 0.2V
1.0
1.0
supply current
VOH
Output voltage
VOL
IOUT = -5.0 mA
IOUT = 4.2 mA
2.4
–
–
2.4
–
–
V
V
0.4
0.4
CAS before RAS refresh
current
RAS, UCAS or LCAS cycling, tRC
min
=
ICC6
–
110
0.6
–
100
0.6
mA
RAS = UCAS = LCAS ≤ 0.2V,
WE = OE ≥ VCC - 0.2V,
all other inputs at 0.2V or
Self refresh current
ICC7
–
–
mA
V
CC - 0.2V
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®
DC electrical characteristics (AS4LC4M4E0/E1)
-50
-60
Parameter
Symbol Test conditions
0V ≤ Vin ≤ VCC (max)
Min
-5
Max
+5
Min
-5
Max
+5
Unit
µA
Notes
Input leakage current
IIL
Pins not under test = 0V
DOUT disabled, 0V ≤ Vout ≤ VCC
(max)
Output leakage current IOL
-5
–
+5
85
-5
–
+5
75
µA
mA
mA
Operating power
ICC1
RAS, UCAS, LCAS, Address cycling;
RC=min
4,5
supply current
t
TTL standby power
ICC2
RAS = UCAS = LCAS ≥ VIH,
all other inputs at VIH or VIL
–
2.0
–
2.0
supply current
Average power supply
current, RAS refresh
mode or CBR
RAS cycling, UCAS = LCAS ≥ VIH,
ICC3
–
80
–
70
mA
4
t
RC = min of RAS low after XCAS low.
EDO page mode
average power supply ICC4
current
RAS = VIL, UCAS or LCAS,
address cycling: tHPC = min
–
–
85
–
–
75
mA
µA
4, 5
CMOS standby power
ICC5
RAS = UCAS = LCAS = VCC - 0.2V,
F = 0
200
200
supply current
VOH
IOUT = -2.0 mA
IOUT = 2 mA
2.4
–
–
2.4
–
–
V
V
Output voltage
VOL
0.4
0.4
CAS before RAS refresh
current
RAS, UCAS or LCAS cycling, tRC
min
=
mA
ICC6
–
80
–
70
RAS = UCAS = LCAS ≤ 0.2V,
WE = OE = VCC - 0.2V,
all other inputs at 0.2V or VCC
0.2V
Self refresh current
ICC7
–
0.3
–
0.3
mA
-
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AS4C4M4E1Q
®
AC parameters common to all waveforms
-50
-60
Symbol Parameter
Min
Max
Min
100
40
60
10
15
12
10
50
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
Notes
tRC
Random read or write cycle time
80
30
50
8
–
–
–
–
tRP
RAS precharge time
tRAS
tCAS
tRCD
tRAD
tRSH
tCSH
tCRP
tASR
tRAH
tT
RAS pulse width
10K
10K
35
25
–
10K
10K
43
30
–
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
15
12
10
40
5
6
7
–
–
–
–
0
–
0
–
8
–
10
1
–
1
50
32/64
–
50
32/64
–
4,5
tREF
tCP
–
–
17/16
CAS precharge time
8
10
30
0
tRAL
tASC
tCAH
Column address to RAS lead time
Column address setup time
Column address hold time
25
0
–
–
–
–
8
10
–
Read cycle
-50
-60
Symbol Parameter
Min
–
Max
50
12
25
–
Min
–
Max
60
15
30
–
Unit
ns
Notes
6
tRAC
tCAC
tAA
Access time from RAS
Access time from CAS
–
–
ns
6,13
7,13
Access time from address
–
–
ns
tRCS
tRCH
tRRH
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
0
0
ns
0
–
0
–
ns
9
9
0
–
0
–
ns
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AS4C4M4E1Q
®
Write cycle
-50
-60
Symbol Parameter
Min
0
Max
Min
0
Max
–
Unit
ns
Notes
11
tWCS
tWCH
tWP
Write command setup time
–
–
–
–
–
–
–
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
10
10
10
8
10
10
10
10
0
–
ns
11
–
ns
tRWL
tCWL
tDS
–
ns
–
ns
0
–
ns
12
12
tDH
Data-in hold time
8
10
–
ns
Read-modify-write cycle
-50
-60
Symbol Parameter
Min
113
67
Max
–
Min
135
77
Max
–
Unit
ns
Notes
tRWC
tRWD
tCWD
tAWD
Read-write cycle time
RAS to WE delay time
–
–
ns
11
11
11
CAS to WE delay time
32
–
35
–
ns
Column address to WE delay time
42
–
47
–
ns
Refresh cycle
-50
-60
Symbol Parameter
Min
5
Max
–
Min
5
Max
–
Unit
ns
Notes
tCSR
tCHR
tRPC
CAS setup time (CAS-before-RAS)
3
3
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
8
–
10
0
–
ns
0
–
–
ns
CAS precharge time
(CBR counter test)
tCPT
10
10
–
ns
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AS4C4M4EOQ
AS4C4M4E1Q
®
Hyper page mode cycle
-50
-60
Symbol Parameter
Min
45
–
Max
–
Min
52
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
13
tCPWD
tCPA
CAS precharge to WE delay time
Access time from CAS precharge
RAS pulse width
28
100K
–
35
100K
–
tRASP
tDOH
tREZ
50
5
60
5
Previous data hold time from CAS
Output buffer turn off delay from RAS
Output buffer turn off delay from WE
Output buffer turn off delay from OE
Hyper page mode cycle time
0
13
13
13
–
0
15
15
15
–
tWEZ
tOEZ
tHPC
0
0
0
0
20
47
30
25
56
35
tHPRWC Hyper page mode RMW cycle
tRHCP RAS hold time from CAS
–
–
–
–
Output enable
-50
-60
Symbol Parameter
Min
0
Max
–
Min
0
Max
–
Unit
ns
Notes
8
tCLZ
tROH
tOEA
tOED
tOEZ
tOEH
tOLZ
tOFF
CAS to output in Low Z
RAS hold time referenced to OE
OE access time
8
–
10
–
–
ns
–
13
–
15
–
ns
OE to data delay
13
0
15
0
ns
Output buffer turnoff delay from OE
OE command hold time
OE to output in Low Z
13
–
15
–
ns
8
10
0
10
0
ns
–
–
ns
Output buffer turn-off time
0
13
0
15
ns
8,10
Self-refresh cycle
-50
-60
Std
Symbol
Parameter
Min
Max
Min
Max
–
Unit
µs
Notes
RAS pulse width
(CBR self refresh)
tRASS
100
90
–
–
–
100
105
-50
RAS precharge time
(CBR self refresh)
tRPS
–
–
ns
ns
CAS hold time
(CBR self refresh)
tCHS
-50
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®
Notes
1
2
3
I
, I , I , and I
are dependent on frequency.
CC6
CC1 CC3 CC4
I
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) ≥ GND and V
IH
T
IL
(max) ≤ V
.
CC
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
IH
IL
IH
IL
Operation within the t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
is greater than the
RCD
RAC
RCD
RCD
specified t
(max) limit, then access time is controlled exclusively by t
.
CAC
RCD
7
Operation within the t
(max) limit insures that t
(max) can be met. t (max) is specified as a reference point only. If t
RAD
is greater than the
RAD
RAC
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
is referenced from
OFF
OFF
rising edge of RAS or CAS, whichever occurs last.
t , t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
WCS WCH RWD CWD
11
AWD
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
WS
WH
cycle. If tRWD ≥ t
(min), t
≥ t
(min) and tAWD ≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the
RWD
CWD
CWD
AWD
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t or t or t
CAA
CAC
CPA
14
tASC ≥ t to achieve t (min) and t (max) values.
CP PC CPA
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C4M4EOQ 5V devices.
17 These characteristics apply to AS4C4M4E1Q 5V devices.
AC test conditions
- Access times are measured with output reference levels of V
=
OH
2.4V and V = 0.4V,
OL
V
= 2.4V and V = 0.8V
IL
IH
- Input rise and fall times: 2 ns
+5V
+3.3V
R1 = 828Ω
R1 = 828Ω
Dout
Dout
100 pF*
R2 = 295Ω
50 pF*
R2 = 295Ω
*including scope
and jig capacitance
*including scope
and jig capacitance
GND
GND
Figure A: Equivalent output load
(AS4C4M4E0/AS4C4M4E1)
Figure B: Equivalent output load
(AS4C4M4E0/AS4C4M4E1)
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
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AS4C4M4EOQ
AS4C4M4E1Q
®
Read waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tRCS
tCAH
tCAS
tCRP
tASC
CAS
tRAD
tRAL
tRAH
tASR
Row address
Address
Column address
tRRH
tRCH
tWEZ
WE
OE
tROH
tROH
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC
tREZ
tCLZ
Data out
DQ
tOLZ
Early write waveform
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
CAS
tRAD
tRAL
tASC
tASR
tRAH
tCAH
Row address
Column address
Address
tCWL
tRW L
tWP
tWCS
tWCH
WE
OE
tDH
Data in
tDS
DQ
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Write waveform
OE controlled
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CAS
tRAL
tRAD
tRAH
tASC
tASR
Row address
tCAH
Column address
Address
tRWL
tCWL
tWP
WE
OE
tOEH
tDS
tOED
tDH
Data in
DQ
Read-modify-write waveform
tRWC
tRAS
tRP
RAS
tCAS
tRSH
tCRP
tRCD
tCSH
CAS
tAR
tRAL
tRAD
tRAH
tASC
tCAH
tASR
Row address
Column address
tRWD
Address
tRWL
tAWD
tCWL
tWP
tRCS
tCWD
WE
OE
tOEA
tOED
tOEZ
tRAC
tAA
tCAC
tCLZ
tDS
tDH
Data out
Data in
DQ
tOLZ
3/22/01; v.1.0
Alliance Semiconductor
P. 11 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
EDO page mode read waveform
tRASP
tRP
RAS
tRHCP
tHPC
tCSH
tRSH
tCRP
tRCD
tCAS
tCP
CAS
tAR
tRAD
tRAL
tRAH
Row
tASC
Col address
tCAH
tASR
Col address
tRCS
Address
Col address
tRRH
tRCH
WE
OE
tOEA
tOEA
tRAC
tCPA
tOEZ
tOFF
tCLZ
tCAC
tAA
tOEZ
tCPA
Data out
tCLZ
Data out
Data out
tCLZ
DQ
tOLZ
EDO page mode early write waveform
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCSH
tCAH
tASC
tWCS
tCAS
tCP
tRSH
CAS
tRAL
tAR
tASR
tRAD
Row address
Col address
Address
Col address
Col address
tCWL
tWP
tOEH
tWCH
WE
OE
tHDR
tOED
tDH
tDS
DQ
Data in
Data In
Data in
3/22/01; v.1.0
Alliance Semiconductor
P. 12 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
EDO page mode read-modify-write waveform
tRASP
tRP
RAS
tHPRWC
tCAS
tCSH
tRCD
tCP
tCRP
CAS
tRAD
tRAL
tCAH
tASR
tRAH
tASC
tASC
tASC
tCAH
tCAH
Row ad
Col ad
tRWD
Col ad
Col address
tCPWD
Address
tCWL
tRWL
tCWL
tRCS
tCWD
tCWD
tCWD
tAWD
tAWD
tWP
WE
OE
tOEA
tOEZ
tOED
tOEA
tAA
tRAC
tCLZ
tCAC
tDH
tCPA
tCLZ
tCAC
tDS
tDS
tCLZ
tCAC
Data in
Data in
Data out
Data in
DQ
Data out
Data out
CAS before RAS refresh waveform
WE = A = VIH or VIL
tRC
tRP
tRAS
RAS
tRPC
tCHR
tCP
tCSR
CAS
DQ
OPEN
RAS only refresh waveform
WE = OE = VIH or VIL
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tASR
tRAH
Address
Row address
3/22/01; v.1.0
Alliance Semiconductor
P. 13 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
Hidden refresh waveform (read)
tRC
tRC
tRAS
tRP
tRAS
tRP
RAS
tCRP
tCHR
tRCD
tRSH
tCRP
CAS
tAR
tRAD
tCAH
tRAH
tASC
Col address
tASR
Row
Address
tRCS
tRRH
WE
OE
tOEA
tRAC
tOFF
tAA
tCAC
tCLZ
tOEZ
Data out
DQ
Hidden refresh waveform (write)
tRC
tRAS
tRP
RAS
tCHR
tCRP
tRCD
tRSH
CAS
Address
WE
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Row address
Col address
tRWL
tWCR
tWP
tWCS
tWCH
tDS
tDH
tDHR
Data in
DQ
OE
3/22/01; v.1.0
Alliance Semiconductor
P. 14 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
CAS before RAS refresh counter test waveform
tRAS
tRSH
tRP
RAS
tCSR
tCHR
tCPT
tCAS
CAS
tRAL
tASC
tCAH
Address
Col address
tAA
tCAC
tCLZ
tOFF
tOEZ
DQ
WE
OE
Data out
tRRH
tRCH
tRCS
tROH
tOEA
tRWL
tCWL
tWP
tWCH
tWCS
WE
tDH
tDS
DQ
OE
Data in
tRWL
tWP
tRCS
tCWD
tAWD
tCWL
WE
OE
tOEA
tOED
t AA
tDH
tCLZ
tCAC
tOEZ
tDS
Data in
DQ
Data out
3/22/01; v.1.0
Alliance Semiconductor
P. 15 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
CAS-before-RAS self refresh cycle
tRP
tRASS
tRPS
RAS
tRPC
tCP
tRPC
tCSR
tCHS
UCAS,
LCAS
tCEZ
DQ
Capacitance 15
ƒ = 1 MHz, Ta = Room temperature
Parameter
Symbol
CIN1
Signals
Test conditions
Vin = 0V
Max
5
Unit
pF
A0 to A9
Input capacitance
DQ capacitance
CIN2
RAS, UCAS, LCAS, WE, OE
DQ0 to DQ15
Vin = 0V
7
pF
CDQ
Vin = Vout = 0V
7
pF
4C4M4EOQ ordering information
Package \ RAS access time
50 ns
60 ns
Plastic SOJ, 300 mil, 24/26-pin
Plastic TSOP, 300 mil, 24/26-pin
5V
5V
4C4M4EOQ-50JC
4C4M4EOQ-50TC
4C4M4EOQ-60JC
4C4M4EOQ-60TC
AS4C4M4E1Q ordering information
Package \ RAS access time
50 ns
60 ns
Plastic SOJ, 300 mil, 24/26-pin
Plastic TSOP, 300 mil, 24/26-pin
5V
5V
AS4C4M4E1Q-50JC
AS4C4M4E1Q-50TC
AS4C4M4E1Q-60JC
AS4C4M4E1Q-60TC
4C4M4EOQ family part numbering system
AS4
C
4M4
E0
–XX
X
C
Package:
J = SOJ 300 mil, 24/26
T = TSOP 300 mil, 24/26
DRAM
prefix
C = 5V CMOS
LC = 3.3V CMOS
E0=4K refresh RAS access
E1=2K refresh time
Commercial temperature
range, 0°C to 70 °C
4M×4
3/22/01; v.1.0
Alliance Semiconductor
P. 16 of 16
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