AS4LC4M4F1 [ALSC]
4M×4 CMOS DRAM (Fast Page) 3.3V Family; 4M × 4 CMOS DRAM（快速页面）， 3.3V系列
| 型号： | AS4LC4M4F1 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 4M×4 CMOS DRAM (Fast Page) 3.3V Family |
| 文件： | 总14页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2001
AS4LC4M4F1
®
4M×4 CMOS DRAM (Fast Page) 3.3V Family
Features
• Refresh
• Organization: 4,194,304 words × 4 bits
- 2048 refresh cycles, 32 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
• 3.3V power supply
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 500 mW max
- Standby: 3.6 mW max, CMOS I/O
• Fast page mode
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 volts
• Industrial and commercial temperature available
Pin arrangement
Pin designation
Pin(s)
A0 to A10
RAS
Description
SOJ
TSOP*
Address inputs
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
VCC
GND
I/O3
I/O2
CAS
OE
VCC
GND
I/O3
I/O2
CAS
OE
1
2
3
4
5
6
26
25
24
23
22
21
1
2
3
4
5
6
19
18
17
16
15
14
I/O0
I/O1
WE
RAS
NC
I/O0
I/O1
WE
RAS
NC
CAS
A9
A9
WE
A10
A8
A7
A6
A5
A4
A10
A8
A7
A6
A5
A4
GND
8
9
I/O0 to I/O3
OE
8
9
10
11
12
13
19
18
17
16
15
14
26
25
24
23
22
21
A0
A1
A2
A3
VCC
A0
A1
A2
A3
VCC
10
11
12
13
VCC
GND
GND
Ground
*TSOP availability to be determined
Selection guide
Symbol
AS4LC4M4F1-50
AS4LC4M4F1-60
Unit
ns
Maximum RAS access time
tRAC
tCAA
tCAC
tOEA
tRC
50
25
60
30
Maximum column address access time
Maximum CAS access time
ns
12
15
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum fast page mode cycle time
Maximum operating current
13
15
ns
80
100
30
ns
tPC
25
ns
ICC1
ICC5
120
1.0
110
1.0
mA
mA
Maximum CMOS standby current
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Copyright © Alliance Semiconductor. All rights reserved.
AS4LC4M4F1
®
Functional description
The AS4LC4M4F1 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) device organized as 4,194,304
words × 4 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed,
extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as
main memory in PC, workstation, router and switch applications.
This device features a high speed page-mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The AS4LC4M4F1 is available in the standard 24/26-pin plastic SOJ. TSOP 24/26-pin availability is to be determined. The AS4LC4M4F1
operates with a single power supply of 3.3V 0.3V and provides TTL compatible inputs and outputs.
Logic block diagram for 2K refresh
Data
I/O
buffers
VCC
Column decoder
Sense amp
GND
I/O0 to I/O3
RAS clock
generator
RAS
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
2048 × 2048 × 4
Array
CAS clock
generator
(16,777,216)
A9
A10
Substrate bias
generator
WE clock
generator
WE
Recommended operating conditions
Parameter
Symbol
VCC
Min
3.0
0.0
2.0
–0.5†
0
Nominal
Max
Unit
V
3.3
0.0
–
3.6
0.0
Supply voltage
Input voltage
GND
VIH
V
VCC+0.5V
0.8
V
VIL
–
V
Commercial
Industrial
–
70
Ambient operating temperature
TA
°C
-40
–
85
†
V
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
IL
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Absolute maximum ratings
Parameter
Symbol
Vin
Min
Max
Unit
V
Input voltage
-1.0
-1.0
-1.0
-55
–
4.6
4.6
4.6
150
Input voltage (DQs)
VDQ
VCC
V
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
V
TSTG
TSOLDER
PD
°C
oC × sec
260 × 10
0.432
50
–
W
Short circuit output current
Iout
–
mA
DC electrical characteristics
-50
-60
Parameter
Symbol Test conditions
Min Max Min Max Unit Notes
0V ≤ Vin ≤ +Vcc(max)
Input leakage current
IIL
-5
+5
+5
-5
-5
–
+5
+5
µA
µA
Pins not under test = 0V
Output leakage current IOL
DOUT disabled, 0V ≤ Vout ≤ + Vcc(max) -5
Operating power
ICC1
CAS, Address cycling; tRC=min
RAS = CAS ≥ VIH
–
–
120
110
mA
1,2
supply current
TTL standby power
ICC2
2.0
–
–
2.0
mA
mA
supply current
Average power supply
current, RAS refresh
mode or CBR
RAS cycling, CAS ≥ VIH,
ICC3
–
120
110
1
t
RC = min of RAS low after CAS low.
Fast page mode average
power supply current
RAS = VIL, CAS,
address cycling: tHPC = min
ICC4
ICC5
–
–
90
–
–
80
mA
mA
1, 2
CMOS standby power
supply current
RAS = CAS = VCC - 0.2V
2.0
2.0
VOH
VOL
IOUT = -2.0 mA
IOUT = 2.0 mA
2.4
–
–
2.4
–
–
V
V
Output voltage
0.4
0.4
CAS before RAS refresh
current
ICC6
RAS, CAS cycling, tRC = min
–
120
–
110
mA
RAS = CAS ≤ 0.2v,
Self refresh current
ICC7
WE - OE ≥ VCC - 0.2V,
-
0.6
-
0.6
mA
all other inputs at 0.2V or VCC - 0.2V
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AC parameters common to all waveforms
-50
-60
Symbol
tRC
Parameter
Min
80
30
50
8
Max
–
Min
100
40
60
10
15
12
10
50
5
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
Notes
Random read or write cycle time
RAS precharge time
tRP
–
–
tRAS
tCAS
tRCD
tRAD
tRSH
tCSH
tCRP
tASR
tRAH
tT
RAS pulse width
10K
10K
35
25
–
10K
10K
43
30
–
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS hold time
RAS to CAS hold time
CAS to RAS precharge time
Row address setup time
Row address hold time
Transition time (rise and fall)
Refresh period
15
12
10
40
5
6
7
–
–
–
–
0
–
0
–
8
–
10
1
–
1
50
64
–
50
64
–
4,5
3
tREF
tCP
–
–
CAS precharge time
8
10
30
0
tRAL
tASC
tCAH
Column address to RAS lead time
Column address setup time
Column address hold time
25
0
–
–
–
–
8
10
–
Read cycle
-50
-60
Symbol Parameter
Min
–
Max
50
12
25
–
Min
–
Max
60
15
30
–
Unit
ns
Notes
6
tRAC
tCAC
tAA
Access time from RAS
Access time from CAS
–
–
ns
6,13
7,13
Access time from address
–
–
ns
tRCS
tRCH
tRRH
Read command setup time
Read command hold time to CAS
Read command hold time to RAS
0
0
ns
0
–
0
–
ns
9
9
0
–
0
–
ns
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Write cycle
-50
-60
Symbol Parameter
Min
0
Max
–
Min
0
Max
–
Unit
ns
Notes
11
tWCS
tWCH
tWP
Write command setup time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
10
10
10
8
–
10
10
10
10
0
–
ns
11
–
–
ns
tRWL
tCWL
tDS
–
–
ns
–
–
ns
0
–
–
ns
12
12
tDH
Data-in hold time
8
–
10
–
ns
Read-modify-write cycle
-50
-60
Symbol Parameter
Min
113
67
Max
–
Min
135
77
Max
–
Unit
ns
Notes
tRWC
tRWD
tCWD
tAWD
Read-write cycle time
RAS to WE delay time
–
–
ns
11
11
11
CAS to WE delay time
32
–
35
–
ns
Column address to WE delay time
42
–
47
–
ns
Refresh cycle
-50
-60
Symbol
tCSR
Parameter
Min
5
Max
–
Min
5
Max
–
Unit
ns
Notes
CAS setup time (CAS-before-RAS)
CAS hold time (CAS-before-RAS)
RAS precharge to CAS hold time
3
3
tCHR
8
–
10
0
–
ns
tRPC
0
–
–
ns
CAS precharge time
(CBR counter test)
tCPT
10
10
–
ns
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Fast page mode cycle
-50
-60
Symbol
tCPA
Parameter
Min
–
Max
Min
–
Max
Unit
Notes
13
Access time from CAS precharge
RAS pulse width
28
35
tRASP
tPC
50
30
10
80
12
100K
60
35
10
85
15
100K
Read-write cycle time
–
–
–
–
–
–
–
–
tCP
CAS precharge time (fast page)
Fast page mode RMW cycle
Page mode CAS pulse width (RMW)
tPCM
tCRW
Output enable
-50
-60
Symbol
tCLZ
Parameter
Min
0
Max
–
Min
0
Max
–
Unit
ns
Notes
8
CAS to output in Low Z
RAS hold time referenced to OE
OE access time
tROH
tOEA
tOED
tOEZ
8
–
10
–
–
ns
–
13
–
15
–
ns
OE to data delay
13
0
15
0
ns
Output buffer turnoff delay from OE
OE command hold time
OE to output in Low Z
Output buffer turn-off time
13
–
15
–
ns
8
tOEH
tOLZ
10
0
10
0
ns
–
–
ns
tOFF
0
13
0
15
ns
8,10
Self-refresh cycle
-50
-60
Std Symbol
Parameter
Min
Max
Min
100
105
10
Max
Unit
µs
Notes
15
tRASS
tRPS
RAS pulse width (CBR self refresh)
RAS precharge time (CBR self refresh)
CAS hold time (CBR self refresh)
100
90
8
-
-
-
-
-
-
ns
tCHS
nx
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Notes
1
2
3
I
, I , I , and I
are dependent on frequency.
CC6
CC1 CC3 CC4
I
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V (min) ≥ GND and V
T
IL
IH
(max) ≤ V
.
CC
5
6
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
IH
IL
IH
IL
Operation within the t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
is greater than the
RCD
RAC
RCD
RCD
specified t
(max) limit, then access time is controlled exclusively by t
.
CAC
RCD
7
Operation within the t
(max) limit insures that t
(max) can be met. t (max) is specified as a reference point only. If t
RAD
is greater than the
RAD
RAC
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
8
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either t or t must be satisfied for a read cycle.
9
RCH
RRH
10
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
is referenced from
OFF
OFF
rising edge of RAS or CAS, whichever occurs last.
t , t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
WCS WCH RWD CWD
11
AWD
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
WS
WH
cycle. If t
≥ t
(min), t
≥ t
(min) and tAWD ≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the
AWD
RWD
RWD
CWD
CWD
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of t
or t
or t
CAC CPA
CAA
14
t
ASC ≥ t to achieve t (min) and t (max) values.
CP
PC
CPA
15 These parameters are sampled and not 100% tested.
AC test conditions
- Access times are measured with output reference levels of
V
V
= 2.4V and V = 0.4V,
OH
OL
= 2.0V and V = 0.8V
IH
IL
- Input rise and fall times: 2 ns
+3.3V
R1 = 828Ω
Dout
*including scope
and jig capacitance
50 pF*
R2 = 295Ω
GND
Figure A: Equivalent output load
(AS4LC4M4F1)
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
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Read waveform
tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tRCS
tCAH
tCAS
tCRP
tASC
CAS
tRAD
tRAL
tRAH
tASR
Row address
Address
Column address
tRRH
tRCH
tWEZ
WE
OE
tROH
tROH
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC
tREZ
tCLZ
Data out
DQ
tOLZ
Early write waveform
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
CAS
tRAD
tRAL
tASC
tASR
tRAH
tCAH
Row address
Column address
Address
tCWL
tRW L
tWP
tWCS
tWCH
WE
OE
tDH
Data in
tDS
DQ
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Write waveform
OE controlled
tRC
tRAS
tRP
RAS
tCSH
tRSH
tCAS
tCRP
tRCD
CAS
tRAL
tRAD
tRAH
tASC
tASR
Row address
tCAH
Column address
Address
tRWL
tCWL
tWP
WE
OE
tOEH
tDS
tOED
tDH
Data in
DQ
Read-modify-write waveform
tRWC
tRAS
tRP
RAS
tCAS
tRSH
tCRP
tRCD
tCSH
CAS
tAR
tRAL
tRAD
tRAH
tASC
tCAH
tASR
Row address
Column address
tRWD
Address
tRWL
tAWD
tCWL
tWP
tRCS
tCWD
WE
OE
tOEA
tOED
tOEZ
tRAC
tAA
tCAC
tCLZ
tDS
tDH
Data out
Data in
DQ
tOLZ
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Fast page mode read waveform
tRASP
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
tCP
tPC
CAS
tAR
tRAD
tRAL
tCAH
Column
tASC
tASR
tRAH
Row
Column
tRCS
Column
tRCS
Address
tRRH
tRCH
tRCH
tOEA
WE
OE
tOEA
tRAC
tOEZ
tOFF
tCLZ
tCAP
tAA
Data out
tCAC
Data out
Data out
I/O
Fast page mode byte write waveform
tRASP
tRP
RAS
tPCM
tCAS
tCSH
tRCD
tRAD
tCP
tCRP
CAS
tRAL
tCAH
tASR
tRAH
tCAH
tCAH
Row
tRCS
Column
tRWD
Column
tCWL
Column
Address
tRWL
tCWL
tWP
tCWD
tAWD
tCWD
tCWD
tAWD
WE
OE
tOEA
tOEZ
tOED
tOEA
tAA
tDH
tRAC
tCAP
tCLZ
tCAC
tDS
tCLZ
tCAC
tDS
tCLZ
tCAC
Data in
Data out
Data in
Data out
Data in
I/O
Data out
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Fast page mode early write waveform
tRASP
tRAH
tRWL
RAS
tCRP
tRCD
tPC
tCAH
tCSH
tASC
tWCS
tCAS
tCP
tRSH
CAS
tRAL
tAR
tASR
tRAD
Address
Row
Column
Column
Column
tCWL
tWP
tWCH
tOEH
WE
OE
tHDR
tOED
tDH
tDS
I/O
Data In
Data in
Data in
CAS before RAS refresh waveform
WE = VIH
tRC
tRP
tRAS
RAS
tRPC
tCHR
tCP
tCSR
CAS
DQ
OPEN
RAS only refresh waveform
WE = OE = VIH or VIL
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tASR
tRAH
Address
Row address
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Hidden refresh waveform (read)
tRC
tRC
tRAS
tRP
tRAS
tRP
RAS
tCRP
tCHR
tRCD
tRSH
tCRP
CAS
tAR
tRAD
tCAH
tRAH
tASC
Col address
tASR
Row
Address
tRCS
tRRH
WE
OE
tOEA
tRAC
tOFF
tAA
tCAC
tCLZ
tOEZ
Data out
DQ
Hidden refresh waveform (write)
tRC
tRAS
tRP
RAS
tCHR
tCRP
tRCD
tRSH
CAS
Address
WE
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
Row address
Col address
tRWL
tWCR
tWP
tWCS
tWCH
tDS
tDH
tDHR
Data in
DQ
OE
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CAS before RAS refresh counter test waveform
tRAS
tRSH
tRP
RAS
tCSR
tCPT
tCAS
tCHR
CAS
tRAL
tASC
tCAH
Address
Col address
tAA
tCAC
tCLZ
tOFF
tOEZ
DQ
WE
OE
Data out
tRRH
tRCH
tRCS
tROH
tOEA
tRWL
tCWL
tWP
tWCH
tWCS
WE
tDH
tDS
DQ
OE
Data in
tRWL
tWP
tRCS
tCWD
tAWD
tCWL
WE
OE
tOEA
tOED
t AA
tDH
tCLZ
tCAC
tOEZ
tDS
Data in
DQ
Data out
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CAS-before-RAS self refresh cycle
tRP
tRASS
tRPS
RAS
tRPC
tCP
tRPC
tCSR
tCHS
CAS
CAS
tCEZ
DQ
Capacitance 15
ƒ = 1 MHz, Ta = Room temperature
Parameter
Symbol
CIN1
Signals
Test conditions
Vin = 0V
Max
5
Unit
pF
A0 to A10
Input capacitance
DQ capacitance
CIN2
RAS, CAS, WE, OE
DQ0 to DQ03
Vin = 0V
7
pF
CDQ
Vin = Vout = 0V
7
pF
AS4LC4M4F1 ordering information
Package \ RAS access time
50 ns
60 ns
AS4LC4M4F1-50JC
AS4LC4M4F1-50JI
AS4LC4M4F1-60JC
AS4LC4M4F1-60JI
Plastic SOJ, 300 mil, 24/26-pin
3.3V
3.3V
AS4LC4M4F1-50TC
AS4LC4M4F1-50TI
AS4LC4M4F1-60TC
AS4LC4M4F1-60TI
Plastic TSOP, 300 mil, 24/26-pin*
* Shading indicates availability is TBD.
AS4LC4M4F1 family part numbering system
AS4
LC
4M4
F1
–XX
X
X
Package:
J = SOJ 300 mil, 24/26
T = TSOP 300 mil, 24/26* I=Industrial, -40°C to 85°C
Temperature range
C=Commercial, 0°C to 70 °C
DRAM
prefix
LC = 3.3V
CMOS
4M×4 F1=2K refresh RAS access time
5/16/01; v.1.0 Restored
Alliance Semiconductor
P. 14 of 14
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