AS6UA25617-100BI [ALSC]
Standard SRAM, 256KX16, 100ns, CMOS, PBGA48, FBGA-48;
| 型号： | AS6UA25617-100BI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 256KX16, 100ns, CMOS, PBGA48, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary information
June 2000
AS6UA25617
1.65V to 3.6V 256K×16 Intelliwatt™ low power CMOS SRAM with two chip enables
• Low power consumption: STANDBY
- 72 µW max at 3.6V
Features
• AS6UA25617
- 41 µW max at 2.7V
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 2.7V to 3.6V at 55 ns
• 2.3V to 2.7V at 70 ns
• 1.65V to 2.3V at 100 ns
- 28 µW max at 2.3V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS1, CS2, OE inputs
• Smallest footprint package
- 400-mil 44-pin TSOP II
- 48-ball FBGA
• CS1 and CS2 for chip selection
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
- 28 mW at 2.3 V and 100 ns
Pin arrangement (top view)
400-pin 400-mil TSOP II
Logic block diagram
A0
A1
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A0
2
A16
V
A1
A2
A2
3
A15
DD
A3
4
OE
1024 × 256 × 16
Array
(4,194,304)
A4
5
UB
V
A3
SS
CS1
I/ O1
6
LB
A4
I/ O16
I/ O15
I/ O14
7
A6
I/ O
2
8
A7
I/ O3
I/ O4
9
A8
I/ O
13
10
11
12
13
14
15
16
17
18
19
20
21
22
A12
A13
V
V
SS
CC
V
V
CC
SS
I/ O12
I/ O5
I/ O6
I/ O7
I/ O8
WE
A5
I/ O1–I/ O8
I/ O
Control circuit
I/ O11
I/ O10
I/ O9
CS2
buffer
I/ O9–I/ O16
Column decoder
WE
A14
A6
A13
A7
A12
A8
A11
A9
A10
UB
OE
LB
CS1
CS2
48-CSP Ball-Grid-Array Package
1
2
3
4
5
6
A
B
C
D
E
LB
OE
A
A
A
2
CS2
0
1
I/ O9 UB
A
A
CS1 I/ O1
I/ O2 I/ O3
I/ O4 VCC
3
4
I/ O10 I/ O11
A
A
6
5
V
I/ O12
A
A
7
SS
17
VCC I/ O13 NC
A
I/ O5
V
SS
16
F
I/ O15 I/ O14
I/ O16 NC
A
A
I/ O6 I/ O7
WE I/ O8
14
15
G
H
A
A
13
12
NC
A
A
A
A
11
NC
8
9
10
Selection guide
VCC Range
Power Dissipation
Typ2
(V)
Max
(V)
Speed
(ns)
Operating (ICC1
)
Standby (ISB2)
Min
(V)
Product
Max (mA)
Max (µA)
AS6UA25617
AS6UA25617
2.7
2.3
3.0
2.5
2.0
3.6
2.7
2.3
55
70
2
1
1
20
15
12
AS6UA25617*
1.65
100
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS6UA25617
Functional description
The AS6UA25617 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144
words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/ 70/ 100 ns are ideal for low-power applications. Active high and
low chip selects (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems.
When CS1 is high, or UB and LB are high or CS2 is low, the device enters standby mode: the AS6UA25617 is guaranteed not
to exceed 72 µW power consumption at 3.6V and 55 ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device
also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS1) low, UB and/ or LB low, and CS2 high. Data
on the input pins I/ O1–I/ O16 is written on the rising edge of WE (write cycle 1) or CS1, CS2 (write cycle 2). To avoid bus
contention, external devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write
enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS1) low, UB and/ or LB low, with write enable
(WE) and CS2 high. The chip drives I/ O pins with the data word referenced by the input address. When either chip select or
output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode.
This device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/ O1–I/ O8, and UB controls the higher bits, I/ O9–I/ O16.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. The device is
available in the JEDEC standard 48-ball FBGA and 44-pin TSOPII packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.5
–0.5
–
Max
Unit
V
Voltage on VCC relative to V
V
VCC + 0.5
SS
tIN
Voltage on any I/ O pin relative to GND
Power dissipation
V
V
tI/ O
PD
1.0
+150
+125
20
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
Tbias
IOUT
–65
–55
–
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS1
H
X
X
L
CS2
X
L
OE
X
X
X
H
H
L
WE
X
X
X
H
H
H
H
H
L
LB
X
X
H
L
UB
X
X
H
X
L
I/ O1–8
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
I/ O9–16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
Mode
Power
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Deselected
Deselected
X
H
H
H
H
H
H
H
H
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
X
L
L
H
L
L
L
H
L
High-Z
DOUT
L
L
L
DOUT
L
X
X
X
L
H
L
D
High-Z
Lower Byte Write
Upper Byte Write
Word Write
IN
L
L
H
L
High-Z
D
IN
L
L
L
D
D
IN
IN
Key: X = Don’t care, L = Low, H = High.
2
AS6UA25617
Recommended operating condition (over the operating range)
Parameter
Description
Test Conditions
Min
2.4
2.0
1.5
Max
Unit
V
IOH = 2.1mA
OH = 1.5mA
IOH = 1.65mA
OL = 2.1mA
VCC = 2.7V
V
Output HIGH Voltage
I
VCC = 2.3V
VCC = 1.65V
VCC = 2.7V
VCC = 2.3V
VCC = 1.65V
OH
I
0.4
V
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
IOL = 0.5mA
IOL = 0.1mA
0.4
V
V
V
OL
0.2
VCC = 2.7V
2.2
2.0
VCC + 0.5
V
VCC = 2.3V
VCC + 0.3
IH
VCC = 1.65V
1.4
VCC + 0.3
VCC = 2.7V
–0.5
–0.3
–0.3
–1
0.8
V
VCC = 2.3V
0.6
IL
VCC = 1.65V
0.4
IIX
Input Load Current
Output Load Current
GND < VIN < VCC
GND < V < VCC; Outputs High Z
+1
µA
µA
IOZ
–1
+1
O
VCC = 3.6V
VCC = 2.7V
2
CS1 = V , VIN = V
IL
IL
VCC Operating Supply
Current
ICC
or V , IOUT = 0mA,
1
mA
mA
mA
IH
f = 0
VCC = 2.3V
1
VCC = 3.6V
2
CS1 ≤ 0.2V, V
≤
IN
ICC1
@
Average VCC Operating
Supply Current at 1 MHz
0.2V or V ≥ VCC
–
VCC = 2.7V
1
IN
1 MHz
0.2V, f = 1mS
VCC = 2.3V
1
VCC = 3.6V (55/ 70/ 100 ns)
VCC = 2.7V (55/ 70/ 100 ns)
40/ 30/ 20
30/ 25/ 15
25/ 20/ 12
Average VCC Operating
Supply Current
CS1 ≤ V , VIN = V ,
IL IL
ICC2
or V , f = fMax
IH
V
CC = 2.3V (55/ 70/ 100 ns)
CC = 3.6V
VCC = 2.7V
CC = 2.3V
CS1 ≥ V , CS2 = V ,
V
IH
IH
CS1, CS2 Power Down
Current; TTL inputs
or UB = LB ≥ V ,
IH
ISB
100
µA
other inputs = V or
IL
V
V , f = 0
IH
CS1 > VCC – 0.2V, CS2
= + 0.2V, or UB = LB
> VCC – 0.2V, other
20
15
VCC = 3.6V
VCC = 2.7V
CS1, CS2 Power Down
Current; CMOS Inputs
ISB1
µA
µA
input = 0V – V ,
CC
VCC = 2.3V
12
2
f = fMax
CS1 > VCC – 0.1V, CS2
< + 0.1V, or UB =
ISBDR
Data Retention
VCC = 1.2V
LB = VCC – 0.1V, f = 0
Capacitance (f = 1 MHz, T = Room temperature, V = NOMINAL)2
a
CC
Signals
Parameter
Input capacitance
I/ O capacitance
Symbol
Test conditions
IN = 0V
IN = VOUT = 0V
Max
5
7
Unit
pF
pF
C
A, CS1, CS2, WE, OE, LB, UB
I/ O
V
IN
C
V
I/ O
3
AS6UA25617
Read cycle (over the operating range)
–55
–70
–100
Parameter
Read cycle time
Symbol Min
Max
–
Min
70
–
Max
–
Min
100
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
tRC
tAA
tACS1,2
tOE
55
–
Address access time
55
55
25
–
70
70
35
–
100
100
50
–
3
3
Chip selects access time
Output enable (OE) access time
Output hold from address change
Chip selects low to output in low Z
Chip selects high to output in high Z
OE low to output in low Z
UB/ LB access time
–
–
–
–
–
–
tOH
10
10
0
10
10
0
15
10
0
5
tCLZ
tCHZ
tOLZ
tBA
–
–
–
4, 5
4, 5
4, 5
20
–
20
–
20
–
5
5
5
–
55
–
–
70
–
–
100
–
UB/ LB low to low Z
tBLZ
tBHZ
tOHZ
tPU
10
0
10
0
10
0
4, 5
4, 5
4, 5
4, 5
4, 5
UB/ LB high to high Z
20
20
–
20
20
–
20
20
–
OE high to output in high Z
Power up time
0
0
0
0
0
0
Power down time
tPD
–
55
–
70
–
100
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
Read waveform 1 (address controlled)
t
RC
Address
t
AA
t
t
OH
OH
D
Previous data valid
Data valid
OUT
Read waveform 2 (chip selects, OE, UB, LB controlled)
t
RC
Address
t
AA
OE
t
OE
t
t
t
OH
OLZ
OLZ
CS1
t
t
t
OHZ
LZ
t
t
t
t
HZ
OHZ
ACS1
ACS1
LZ
CS2
t
OH
t
t
HZ
OE
LB, UB
t
t
BHZ
BA
t
BLZ
D
Data valid
OUT
4
AS6UA25617
Write cycle (over the operating range)
–55
–70
–100
Parameter
Write cycle time
Symbol
tWC
tCW
tAW
Min
55
40
40
0
Max
–
Min
70
60
60
0
Max
–
Min
100
80
80
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
Chip selects to write end
Address setup to write end
Address setup time
–
–
–
–
–
–
tAS
–
–
–
12
Write pulse width
tWP
tAH
tDW
tDH
35
0
–
55
0
–
70
0
–
Address hold from end of write
Data valid to write end
Data hold time
–
–
–
25
0
–
30
0
–
40
0
–
–
–
–
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
tWZ
tOW
tBW
0
20
–
0
20
–
0
20
–
5
5
5
UB/ LB low to end of write
35
–
55
–
70
–
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
t
t
WC
CW
Address
t
AH
CS1
CS2
t
CW
t
AH
t
BW
LB, UB
WE
t
AW
t
t
AS
WP
t
t
DH
DW
D
IN
Data valid
t
WZ
t
OW
D
OUT
Data undefined
High Z
Write waveform 2 (chip selects controlled)
t
WC
Address
t
t
AS
AH
AH
t
CW
CS1
CS2
t
t
AW
AW
t
CW
t
t
AS
t
BW
LB, UB
WE
t
WP
t
t
DH
DW
Data valid
High Z
D
IN
t
t
CLZ
WZ
t
OW
D
Data undefined
OUT
High Z
5
AS6UA25617
Data retention characteristics (over the operating range)
Parameter
VCC for data retention
Data retention current
Sym
Test conditions
Min
1.2V
–
Max
3.6
2
Unit
V
VDR
VCC = 1.2V
CS1 ≥ VCC – 0.1V or
UB = LB > VCC – 0.1V
ICCDR
mA
ns
Chip deselect to data retention time tCDR
0
–
V
≥ VCC – 0.1V or
IN
Operation recovery time
tR
V
≤ 0.1V
tRC
–
ns
IN
Data retention waveform
Data retention mode
1.2V
V
V
V
CC
V
≥
CC
CC
DR
t
t
R
CDR
V
DR
V
V
IH
IH
CS1
CS2
V
V
IH
IH
V
DR
t
t
R
CDR
AC test loads and waveforms
R1
Thevenin equivalent:
R1
V
R
CC
V
TH
CC
V
OUTPUT
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
V
Typ
R2
CC
R2
90%
10%
90%
10%
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
< 5 ns
(c)
GND
(a)
(b)
Parameters
3.0V
1105
1550
645
2.5V
2.0V
15294
11300
6500
Unit
R1
R2
RTH
16670
15380
8000
Ohms
Ohms
Ohms
Volts
V
1.75V
1.2V
0.85V
TH
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS1 is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t are specified with C = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WEis HIGH for read cycle.
CS1 and OE are LOW and CS2 is HIGH for read cycle.
Address valid prior to or coincident with CS1 transition LOW and CS2 HIGH.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS1 or WE must be HIGH or CS2 LOW during address transitions. Either CS1 or WE asserting HIGH terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at HIGH Z and LOW Z parameters, where C = 5pF.
6
AS6UA25617
Typical DC and AC characteristics
Normalized supply current
vs. supply voltage
1.4
Normalized access time
vs. supply voltage
Normalized standby current
vs. ambient temperature
1.0
3.0
2.5
2.0
1.2
1.0
V
= V typ
CC
CC
0.75
0.5
V
= V typ
IN
CC
V
= V typ
CC
IN
1.5
1.0
0.5
0.8
0.6
0.4
0.2
0.0
TA = 25 °C
T = 25 °C
A
0.0
0.25
0.0
–0.5
1.7
2.2
2.7
3.2
3.7
1.7
2.2
2.7
3.2
3.7
–55
25
105
Supply voltage (V)
Supply Voltage (V)
Ambient temperature (°C)
Normalized standby current
vs. supply voltage
Normalized I
CC
vs. Cycle Time
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.5
1.0
I
SB2
V
= V typ
CC
IN
T = 25 °C
A
0.50
0.10
V
= V typ
CC
IN
T = 25 °C
A
1
5
10
15
2.8
1
1.9
3.7
Supply voltage (V)
Supply voltage (V)
Package diagrams and dimensions
44-pin TSOP II
c
2423
4443424140393837363534333231302928272625
Min (mm)
Max (mm)
1.2
A
A
0.05
0.95
0.25
1
A
1.05
0.45
2
H
e
44-pin TSOP II
e
b
c
0.15 (typical)
d
e
He
E
l
20.85
10.06
11.56
0.80 (typical)
0.40
21.05
10.26
11.96
1 2 3 4 5 6 7 8 9 10111213141516171819202122
d
0.60
l
A
2
A
0–5
°
A
1
b
E
7
AS6UA25617
48-ball FBGA
Bottom View
Top View
Ball # A1 index
Ball # A1
6
5
4
3
2
1
A
B
C
D
E
SRAM Die
C
C1
F
A
G
H
Elastomer
A
B
B1
Detail View
Side View
A
E2
D
E
E2
Y
E
Die
Die
E1
0.3/ Typ
Minimum
Typical
0.75
7.00
3.75
11.00
5.25
0.35
–
Maximum
–
7.10
–
11.10
–
A
B
B1
C
C1
D
E
E1
E2
Y
–
6.90
–
10.90
–
0.30
–
–
Notes
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
0.40
1.20
–
0.27
0.08
4. All tolerances are ±0.050 unless otherwise specified.
5. Typ: typical.
0.68
0.25
–
0.22
–
6. Y is coplanarity: 0.08 (max).
8
AS6UA25617
Ordering codes
Speed (ns)
Ordering Code
AS6UA25617-BC
AS6UA25617-TC
AS6UA25617-BI
A6UA25617-TI
Package Type
48-ball fine pitch BGA
44-pin TSOP II
Operating Range
Commercial
Industrial
55/ 70/ 100
48-ball fine pitch BGA
44-pin TSOP II
Part numbering system
AS6UA
25617
B, T
C, I
Package:
Temperature range:
SRAM Intelliwatt™ prefix
Device number
B: CSP BGA
T: TSOP II
C: Commercial: 0° C to 70° C
I: Industrial: -40° C to 85° C
9
Copyright ©2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or r egistered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this web site
and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not assume any
responsibility or liability arising out of the application or use of any product described herein, and disclaims any express orimplied warranties related to fitness
相关型号：
©2020 ICPDF网 联系我们和版权申明